arch/arm64/boot/dts/renesas/r8a779g0.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Device Tree Source for the R-Car V4H (R8A779G0) SoC
   4  *
   5  * Copyright (C) 2022 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a779g0-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a779g0";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 a76_0: cpu@0 {
  22                         compatible = "arm,cortex-a76";
  23                         reg = <0>;
  24                         device_type = "cpu";
  25                         power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
  26                 };
  27         };
  28
  29         extal_clk: extal {
  30                 compatible = "fixed-clock";
  31                 #clock-cells = <0>;
  32                 /* This value must be overridden by the board */
  33                 clock-frequency = <0>;
  34         };
  35
  36         extalr_clk: extalr {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 /* This value must be overridden by the board */
  40                 clock-frequency = <0>;
  41         };
  42
  43         pmu_a76 {
  44                 compatible = "arm,cortex-a76-pmu";
  45                 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  46         };
  47
  48         /* External SCIF clock - to be overridden by boards that provide it */
  49         scif_clk: scif {
  50                 compatible = "fixed-clock";
  51                 #clock-cells = <0>;
  52                 clock-frequency = <0>;
  53         };
  54
  55         soc: soc {
  56                 compatible = "simple-bus";
  57                 interrupt-parent = <&gic>;
  58                 #address-cells = <2>;
  59                 #size-cells = <2>;
  60                 ranges;
  61
  62                 rwdt: watchdog@e6020000 {
  63                         compatible = "renesas,r8a779g0-wdt",
  64                                      "renesas,rcar-gen4-wdt";
  65                         reg = <0 0xe6020000 0 0x0c>;
  66                         interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
  67                         clocks = <&cpg CPG_MOD 907>;
  68                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  69                         resets = <&cpg 907>;
  70                         status = "disabled";
  71                 };
  72
  73                 pfc: pinctrl@e6050000 {
  74                         compatible = "renesas,pfc-r8a779g0";
  75                         reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
  76                               <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
  77                               <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
  78                               <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
  79                               <0 0xe6068000 0 0x16c>;
  80                 };
  81
  82                 gpio0: gpio@e6050180 {
  83                         compatible = "renesas,gpio-r8a779g0",
  84                                      "renesas,rcar-gen4-gpio";
  85                         reg = <0 0xe6050180 0 0x54>;
  86                         interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
  87                         clocks = <&cpg CPG_MOD 915>;
  88                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
  89                         resets = <&cpg 915>;
  90                         gpio-controller;
  91                         #gpio-cells = <2>;
  92                         gpio-ranges = <&pfc 0 0 19>;
  93                         interrupt-controller;
  94                         #interrupt-cells = <2>;
  95                 };
  96
  97                 gpio1: gpio@e6050980 {
  98                         compatible = "renesas,gpio-r8a779g0",
  99                                      "renesas,rcar-gen4-gpio";
 100                         reg = <0 0xe6050980 0 0x54>;
 101                         interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&cpg CPG_MOD 915>;
 103                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 104                         resets = <&cpg 915>;
 105                         gpio-controller;
 106                         #gpio-cells = <2>;
 107                         gpio-ranges = <&pfc 0 32 29>;
 108                         interrupt-controller;
 109                         #interrupt-cells = <2>;
 110                 };
 111
 112                 gpio2: gpio@e6058180 {
 113                         compatible = "renesas,gpio-r8a779g0",
 114                                      "renesas,rcar-gen4-gpio";
 115                         reg = <0 0xe6058180 0 0x54>;
 116                         interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
 117                         clocks = <&cpg CPG_MOD 916>;
 118                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 119                         resets = <&cpg 916>;
 120                         gpio-controller;
 121                         #gpio-cells = <2>;
 122                         gpio-ranges = <&pfc 0 64 20>;
 123                         interrupt-controller;
 124                         #interrupt-cells = <2>;
 125                 };
 126
 127                 gpio3: gpio@e6058980 {
 128                         compatible = "renesas,gpio-r8a779g0",
 129                                      "renesas,rcar-gen4-gpio";
 130                         reg = <0 0xe6058980 0 0x54>;
 131                         interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&cpg CPG_MOD 916>;
 133                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 134                         resets = <&cpg 916>;
 135                         gpio-controller;
 136                         #gpio-cells = <2>;
 137                         gpio-ranges = <&pfc 0 96 30>;
 138                         interrupt-controller;
 139                         #interrupt-cells = <2>;
 140                 };
 141
 142                 gpio4: gpio@e6060180 {
 143                         compatible = "renesas,gpio-r8a779g0",
 144                                      "renesas,rcar-gen4-gpio";
 145                         reg = <0 0xe6060180 0 0x54>;
 146                         interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&cpg CPG_MOD 917>;
 148                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 149                         resets = <&cpg 917>;
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                         gpio-ranges = <&pfc 0 128 25>;
 153                         interrupt-controller;
 154                         #interrupt-cells = <2>;
 155                 };
 156
 157                 gpio5: gpio@e6060980 {
 158                         compatible = "renesas,gpio-r8a779g0",
 159                                      "renesas,rcar-gen4-gpio";
 160                         reg = <0 0xe6060980 0 0x54>;
 161                         interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
 162                         clocks = <&cpg CPG_MOD 917>;
 163                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 164                         resets = <&cpg 917>;
 165                         gpio-controller;
 166                         #gpio-cells = <2>;
 167                         gpio-ranges = <&pfc 0 160 21>;
 168                         interrupt-controller;
 169                         #interrupt-cells = <2>;
 170                 };
 171
 172                 gpio6: gpio@e6061180 {
 173                         compatible = "renesas,gpio-r8a779g0",
 174                                      "renesas,rcar-gen4-gpio";
 175                         reg = <0 0xe6061180 0 0x54>;
 176                         interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
 177                         clocks = <&cpg CPG_MOD 917>;
 178                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 179                         resets = <&cpg 917>;
 180                         gpio-controller;
 181                         #gpio-cells = <2>;
 182                         gpio-ranges = <&pfc 0 192 21>;
 183                         interrupt-controller;
 184                         #interrupt-cells = <2>;
 185                 };
 186
 187                 gpio7: gpio@e6061980 {
 188                         compatible = "renesas,gpio-r8a779g0",
 189                                      "renesas,rcar-gen4-gpio";
 190                         reg = <0 0xe6061980 0 0x54>;
 191                         interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
 192                         clocks = <&cpg CPG_MOD 917>;
 193                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 194                         resets = <&cpg 917>;
 195                         gpio-controller;
 196                         #gpio-cells = <2>;
 197                         gpio-ranges = <&pfc 0 224 21>;
 198                         interrupt-controller;
 199                         #interrupt-cells = <2>;
 200                 };
 201
 202                 gpio8: gpio@e6068180 {
 203                         compatible = "renesas,gpio-r8a779g0",
 204                                      "renesas,rcar-gen4-gpio";
 205                         reg = <0 0xe6068180 0 0x54>;
 206                         interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&cpg CPG_MOD 918>;
 208                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 209                         resets = <&cpg 918>;
 210                         gpio-controller;
 211                         #gpio-cells = <2>;
 212                         gpio-ranges = <&pfc 0 256 14>;
 213                         interrupt-controller;
 214                         #interrupt-cells = <2>;
 215                 };
 216
 217                 cpg: clock-controller@e6150000 {
 218                         compatible = "renesas,r8a779g0-cpg-mssr";
 219                         reg = <0 0xe6150000 0 0x4000>;
 220                         clocks = <&extal_clk>, <&extalr_clk>;
 221                         clock-names = "extal", "extalr";
 222                         #clock-cells = <2>;
 223                         #power-domain-cells = <0>;
 224                         #reset-cells = <1>;
 225                 };
 226
 227                 rst: reset-controller@e6160000 {
 228                         compatible = "renesas,r8a779g0-rst";
 229                         reg = <0 0xe6160000 0 0x4000>;
 230                 };
 231
 232                 sysc: system-controller@e6180000 {
 233                         compatible = "renesas,r8a779g0-sysc";
 234                         reg = <0 0xe6180000 0 0x4000>;
 235                         #power-domain-cells = <1>;
 236                 };
 237
 238                 i2c0: i2c@e6500000 {
 239                         compatible = "renesas,i2c-r8a779g0",
 240                                      "renesas,rcar-gen4-i2c";
 241                         reg = <0 0xe6500000 0 0x40>;
 242                         interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&cpg CPG_MOD 518>;
 244                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 245                         resets = <&cpg 518>;
 246                         i2c-scl-internal-delay-ns = <110>;
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         status = "disabled";
 250                 };
 251
 252                 i2c1: i2c@e6508000 {
 253                         compatible = "renesas,i2c-r8a779g0",
 254                                      "renesas,rcar-gen4-i2c";
 255                         reg = <0 0xe6508000 0 0x40>;
 256                         interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&cpg CPG_MOD 519>;
 258                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 259                         resets = <&cpg 519>;
 260                         i2c-scl-internal-delay-ns = <110>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         status = "disabled";
 264                 };
 265
 266                 i2c2: i2c@e6510000 {
 267                         compatible = "renesas,i2c-r8a779g0",
 268                                      "renesas,rcar-gen4-i2c";
 269                         reg = <0 0xe6510000 0 0x40>;
 270                         interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
 271                         clocks = <&cpg CPG_MOD 520>;
 272                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 273                         resets = <&cpg 520>;
 274                         i2c-scl-internal-delay-ns = <110>;
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         status = "disabled";
 278                 };
 279
 280                 i2c3: i2c@e66d0000 {
 281                         compatible = "renesas,i2c-r8a779g0",
 282                                      "renesas,rcar-gen4-i2c";
 283                         reg = <0 0xe66d0000 0 0x40>;
 284                         interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&cpg CPG_MOD 521>;
 286                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 287                         resets = <&cpg 521>;
 288                         i2c-scl-internal-delay-ns = <110>;
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         status = "disabled";
 292                 };
 293
 294                 i2c4: i2c@e66d8000 {
 295                         compatible = "renesas,i2c-r8a779g0",
 296                                      "renesas,rcar-gen4-i2c";
 297                         reg = <0 0xe66d8000 0 0x40>;
 298                         interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&cpg CPG_MOD 522>;
 300                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 301                         resets = <&cpg 522>;
 302                         i2c-scl-internal-delay-ns = <110>;
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         status = "disabled";
 306                 };
 307
 308                 i2c5: i2c@e66e0000 {
 309                         compatible = "renesas,i2c-r8a779g0",
 310                                      "renesas,rcar-gen4-i2c";
 311                         reg = <0 0xe66e0000 0 0x40>;
 312                         interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&cpg CPG_MOD 523>;
 314                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 315                         resets = <&cpg 523>;
 316                         i2c-scl-internal-delay-ns = <110>;
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         status = "disabled";
 320                 };
 321
 322                 hscif0: serial@e6540000 {
 323                         compatible = "renesas,hscif-r8a779g0",
 324                                      "renesas,rcar-gen4-hscif",
 325                                      "renesas,hscif";
 326                         reg = <0 0xe6540000 0 96>;
 327                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&cpg CPG_MOD 514>,
 329                                  <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
 330                                  <&scif_clk>;
 331                         clock-names = "fck", "brg_int", "scif_clk";
 332                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 333                         resets = <&cpg 514>;
 334                         status = "disabled";
 335                 };
 336
 337                 avb0: ethernet@e6800000 {
 338                         compatible = "renesas,etheravb-r8a779g0",
 339                                      "renesas,etheravb-rcar-gen4";
 340                         reg = <0 0xe6800000 0 0x1000>;
 341                         interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 344                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 349                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 353                                      <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
 356                                      <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 357                                      <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 366                         interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
 367                                           "ch5", "ch6", "ch7", "ch8", "ch9",
 368                                           "ch10", "ch11", "ch12", "ch13",
 369                                           "ch14", "ch15", "ch16", "ch17",
 370                                           "ch18", "ch19", "ch20", "ch21",
 371                                           "ch22", "ch23", "ch24";
 372                         clocks = <&cpg CPG_MOD 211>;
 373                         clock-names = "fck";
 374                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 375                         resets = <&cpg 211>;
 376                         phy-mode = "rgmii";
 377                         rx-internal-delay-ps = <0>;
 378                         tx-internal-delay-ps = <0>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         status = "disabled";
 382                 };
 383
 384                 avb1: ethernet@e6810000 {
 385                         compatible = "renesas,etheravb-r8a779g0",
 386                                      "renesas,etheravb-rcar-gen4";
 387                         reg = <0 0xe6810000 0 0x1000>;
 388                         interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
 391                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
 392                                      <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
 393                                      <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
 394                                      <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
 395                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
 396                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
 397                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
 398                                      <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
 399                                      <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
 400                                      <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
 401                                      <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
 402                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
 403                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
 404                                      <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
 405                                      <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
 406                                      <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
 407                                      <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 408                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 409                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 410                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
 411                                      <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
 412                                      <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
 413                         interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
 414                                           "ch5", "ch6", "ch7", "ch8", "ch9",
 415                                           "ch10", "ch11", "ch12", "ch13",
 416                                           "ch14", "ch15", "ch16", "ch17",
 417                                           "ch18", "ch19", "ch20", "ch21",
 418                                           "ch22", "ch23", "ch24";
 419                         clocks = <&cpg CPG_MOD 212>;
 420                         clock-names = "fck";
 421                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 422                         resets = <&cpg 212>;
 423                         phy-mode = "rgmii";
 424                         rx-internal-delay-ps = <0>;
 425                         tx-internal-delay-ps = <0>;
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         status = "disabled";
 429                 };
 430
 431                 avb2: ethernet@e6820000 {
 432                         compatible = "renesas,etheravb-r8a779g0",
 433                                      "renesas,etheravb-rcar-gen4";
 434                         reg = <0 0xe6820000 0 0x1000>;
 435                         interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
 436                                      <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
 437                                      <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
 438                                      <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
 440                                      <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
 441                                      <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
 442                                      <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
 443                                      <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 444                                      <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 445                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 446                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 447                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 448                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 449                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 450                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 451                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 452                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 453                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 454                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 455                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 456                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 457                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 458                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
 459                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
 460                         interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
 461                                           "ch5", "ch6", "ch7", "ch8", "ch9",
 462                                           "ch10", "ch11", "ch12", "ch13",
 463                                           "ch14", "ch15", "ch16", "ch17",
 464                                           "ch18", "ch19", "ch20", "ch21",
 465                                           "ch22", "ch23", "ch24";
 466                         clocks = <&cpg CPG_MOD 213>;
 467                         clock-names = "fck";
 468                         power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
 469                         resets = <&cpg 213>;
 470                         phy-mode = "rgmii";
 471                         rx-internal-delay-ps = <0>;
 472                         tx-internal-delay-ps = <0>;
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         status = "disabled";
 476                 };
 477
 478                 gic: interrupt-controller@f1000000 {
 479                         compatible = "arm,gic-v3";
 480                         #interrupt-cells = <3>;
 481                         #address-cells = <0>;
 482                         interrupt-controller;
 483                         reg = <0x0 0xf1000000 0 0x20000>,
 484                               <0x0 0xf1060000 0 0x110000>;
 485                         interrupts = <GIC_PPI 9
 486                                       (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 487                 };
 488
 489                 prr: chipid@fff00044 {
 490                         compatible = "renesas,prr";
 491                         reg = <0 0xfff00044 0 4>;
 492                 };
 493         };
 494
 495         timer {
 496                 compatible = "arm,armv8-timer";
 497                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 498                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 499                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 500                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 501         };
 502 };