arch/arm64/boot/dts/renesas/r8a779f0.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a779f0-sysc.h>
  11
  12 / {
  13         compatible = "renesas,r8a779f0";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cluster01_opp: opp-table-0 {
  18                 compatible = "operating-points-v2";
  19                 opp-shared;
  20
  21                 opp-500000000 {
  22                         opp-hz = /bits/ 64 <500000000>;
  23                         opp-microvolt = <880000>;
  24                         clock-latency-ns = <500000>;
  25                 };
  26                 opp-800000000 {
  27                         opp-hz = /bits/ 64 <800000000>;
  28                         opp-microvolt = <880000>;
  29                         clock-latency-ns = <500000>;
  30                 };
  31                 opp-1000000000 {
  32                         opp-hz = /bits/ 64 <1000000000>;
  33                         opp-microvolt = <880000>;
  34                         clock-latency-ns = <500000>;
  35                 };
  36                 opp-1200000000 {
  37                         opp-hz = /bits/ 64 <1200000000>;
  38                         opp-microvolt = <880000>;
  39                         clock-latency-ns = <500000>;
  40                         opp-suspend;
  41                 };
  42         };
  43
  44         cluster23_opp: opp-table-1 {
  45                 compatible = "operating-points-v2";
  46                 opp-shared;
  47
  48                 opp-500000000 {
  49                         opp-hz = /bits/ 64 <500000000>;
  50                         opp-microvolt = <880000>;
  51                         clock-latency-ns = <500000>;
  52                 };
  53                 opp-800000000 {
  54                         opp-hz = /bits/ 64 <800000000>;
  55                         opp-microvolt = <880000>;
  56                         clock-latency-ns = <500000>;
  57                 };
  58                 opp-1000000000 {
  59                         opp-hz = /bits/ 64 <1000000000>;
  60                         opp-microvolt = <880000>;
  61                         clock-latency-ns = <500000>;
  62                 };
  63                 opp-1200000000 {
  64                         opp-hz = /bits/ 64 <1200000000>;
  65                         opp-microvolt = <880000>;
  66                         clock-latency-ns = <500000>;
  67                         opp-suspend;
  68                 };
  69         };
  70
  71         cpus {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74
  75                 cpu-map {
  76                         cluster0 {
  77                                 core0 {
  78                                         cpu = <&a55_0>;
  79                                 };
  80                                 core1 {
  81                                         cpu = <&a55_1>;
  82                                 };
  83                         };
  84
  85                         cluster1 {
  86                                 core0 {
  87                                         cpu = <&a55_2>;
  88                                 };
  89                                 core1 {
  90                                         cpu = <&a55_3>;
  91                                 };
  92                         };
  93
  94                         cluster2 {
  95                                 core0 {
  96                                         cpu = <&a55_4>;
  97                                 };
  98                                 core1 {
  99                                         cpu = <&a55_5>;
 100                                 };
 101                         };
 102
 103                         cluster3 {
 104                                 core0 {
 105                                         cpu = <&a55_6>;
 106                                 };
 107                                 core1 {
 108                                         cpu = <&a55_7>;
 109                                 };
 110                         };
 111                 };
 112
 113                 a55_0: cpu@0 {
 114                         compatible = "arm,cortex-a55";
 115                         reg = <0>;
 116                         device_type = "cpu";
 117                         power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
 118                         next-level-cache = <&L3_CA55_0>;
 119                         enable-method = "psci";
 120                         cpu-idle-states = <&CPU_SLEEP_0>;
 121                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
 122                         operating-points-v2 = <&cluster01_opp>;
 123                 };
 124
 125                 a55_1: cpu@100 {
 126                         compatible = "arm,cortex-a55";
 127                         reg = <0x100>;
 128                         device_type = "cpu";
 129                         power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
 130                         next-level-cache = <&L3_CA55_0>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&CPU_SLEEP_0>;
 133                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
 134                         operating-points-v2 = <&cluster01_opp>;
 135                 };
 136
 137                 a55_2: cpu@10000 {
 138                         compatible = "arm,cortex-a55";
 139                         reg = <0x10000>;
 140                         device_type = "cpu";
 141                         power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
 142                         next-level-cache = <&L3_CA55_1>;
 143                         enable-method = "psci";
 144                         cpu-idle-states = <&CPU_SLEEP_0>;
 145                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
 146                         operating-points-v2 = <&cluster01_opp>;
 147                 };
 148
 149                 a55_3: cpu@10100 {
 150                         compatible = "arm,cortex-a55";
 151                         reg = <0x10100>;
 152                         device_type = "cpu";
 153                         power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
 154                         next-level-cache = <&L3_CA55_1>;
 155                         enable-method = "psci";
 156                         cpu-idle-states = <&CPU_SLEEP_0>;
 157                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
 158                         operating-points-v2 = <&cluster01_opp>;
 159                 };
 160
 161                 a55_4: cpu@20000 {
 162                         compatible = "arm,cortex-a55";
 163                         reg = <0x20000>;
 164                         device_type = "cpu";
 165                         power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
 166                         next-level-cache = <&L3_CA55_2>;
 167                         enable-method = "psci";
 168                         cpu-idle-states = <&CPU_SLEEP_0>;
 169                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
 170                         operating-points-v2 = <&cluster23_opp>;
 171                 };
 172
 173                 a55_5: cpu@20100 {
 174                         compatible = "arm,cortex-a55";
 175                         reg = <0x20100>;
 176                         device_type = "cpu";
 177                         power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
 178                         next-level-cache = <&L3_CA55_2>;
 179                         enable-method = "psci";
 180                         cpu-idle-states = <&CPU_SLEEP_0>;
 181                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
 182                         operating-points-v2 = <&cluster23_opp>;
 183                 };
 184
 185                 a55_6: cpu@30000 {
 186                         compatible = "arm,cortex-a55";
 187                         reg = <0x30000>;
 188                         device_type = "cpu";
 189                         power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
 190                         next-level-cache = <&L3_CA55_3>;
 191                         enable-method = "psci";
 192                         cpu-idle-states = <&CPU_SLEEP_0>;
 193                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
 194                         operating-points-v2 = <&cluster23_opp>;
 195                 };
 196
 197                 a55_7: cpu@30100 {
 198                         compatible = "arm,cortex-a55";
 199                         reg = <0x30100>;
 200                         device_type = "cpu";
 201                         power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
 202                         next-level-cache = <&L3_CA55_3>;
 203                         enable-method = "psci";
 204                         cpu-idle-states = <&CPU_SLEEP_0>;
 205                         clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
 206                         operating-points-v2 = <&cluster23_opp>;
 207                 };
 208
 209                 L3_CA55_0: cache-controller-0 {
 210                         compatible = "cache";
 211                         power-domains = <&sysc R8A779F0_PD_A2E0D0>;
 212                         cache-unified;
 213                         cache-level = <3>;
 214                 };
 215
 216                 L3_CA55_1: cache-controller-1 {
 217                         compatible = "cache";
 218                         power-domains = <&sysc R8A779F0_PD_A2E0D1>;
 219                         cache-unified;
 220                         cache-level = <3>;
 221                 };
 222
 223                 L3_CA55_2: cache-controller-2 {
 224                         compatible = "cache";
 225                         power-domains = <&sysc R8A779F0_PD_A2E1D0>;
 226                         cache-unified;
 227                         cache-level = <3>;
 228                 };
 229
 230                 L3_CA55_3: cache-controller-3 {
 231                         compatible = "cache";
 232                         power-domains = <&sysc R8A779F0_PD_A2E1D1>;
 233                         cache-unified;
 234                         cache-level = <3>;
 235                 };
 236
 237                 idle-states {
 238                         entry-method = "psci";
 239
 240                         CPU_SLEEP_0: cpu-sleep-0 {
 241                                 compatible = "arm,idle-state";
 242                                 arm,psci-suspend-param = <0x0010000>;
 243                                 local-timer-stop;
 244                                 entry-latency-us = <400>;
 245                                 exit-latency-us = <500>;
 246                                 min-residency-us = <4000>;
 247                         };
 248                 };
 249         };
 250
 251         extal_clk: extal {
 252                 compatible = "fixed-clock";
 253                 #clock-cells = <0>;
 254                 /* This value must be overridden by the board */
 255                 clock-frequency = <0>;
 256         };
 257
 258         extalr_clk: extalr {
 259                 compatible = "fixed-clock";
 260                 #clock-cells = <0>;
 261                 /* This value must be overridden by the board */
 262                 clock-frequency = <0>;
 263         };
 264
 265         pcie0_clkref: pcie0-clkref {
 266                 compatible = "fixed-clock";
 267                 #clock-cells = <0>;
 268                 /* This value must be overridden by the board */
 269                 clock-frequency = <0>;
 270         };
 271
 272         pcie1_clkref: pcie1-clkref {
 273                 compatible = "fixed-clock";
 274                 #clock-cells = <0>;
 275                 /* This value must be overridden by the board */
 276                 clock-frequency = <0>;
 277         };
 278
 279         pmu_a55 {
 280                 compatible = "arm,cortex-a55-pmu";
 281                 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 282         };
 283
 284         psci {
 285                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 286                 method = "smc";
 287         };
 288
 289         /* External SCIF clock - to be overridden by boards that provide it */
 290         scif_clk: scif {
 291                 compatible = "fixed-clock";
 292                 #clock-cells = <0>;
 293                 clock-frequency = <0>;
 294         };
 295
 296         soc: soc {
 297                 compatible = "simple-bus";
 298                 interrupt-parent = <&gic>;
 299                 #address-cells = <2>;
 300                 #size-cells = <2>;
 301                 ranges;
 302
 303                 rwdt: watchdog@e6020000 {
 304                         compatible = "renesas,r8a779f0-wdt",
 305                                      "renesas,rcar-gen4-wdt";
 306                         reg = <0 0xe6020000 0 0x0c>;
 307                         interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&cpg CPG_MOD 907>;
 309                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 310                         resets = <&cpg 907>;
 311                         status = "disabled";
 312                 };
 313
 314                 pfc: pinctrl@e6050000 {
 315                         compatible = "renesas,pfc-r8a779f0";
 316                         reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
 317                               <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
 318                 };
 319
 320                 gpio0: gpio@e6050180 {
 321                         compatible = "renesas,gpio-r8a779f0",
 322                                      "renesas,rcar-gen4-gpio";
 323                         reg = <0 0xe6050180 0 0x54>;
 324                         interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
 325                         clocks = <&cpg CPG_MOD 915>;
 326                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 327                         resets = <&cpg 915>;
 328                         gpio-controller;
 329                         #gpio-cells = <2>;
 330                         gpio-ranges = <&pfc 0 0 21>;
 331                         interrupt-controller;
 332                         #interrupt-cells = <2>;
 333                 };
 334
 335                 gpio1: gpio@e6050980 {
 336                         compatible = "renesas,gpio-r8a779f0",
 337                                      "renesas,rcar-gen4-gpio";
 338                         reg = <0 0xe6050980 0 0x54>;
 339                         interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&cpg CPG_MOD 915>;
 341                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 342                         resets = <&cpg 915>;
 343                         gpio-controller;
 344                         #gpio-cells = <2>;
 345                         gpio-ranges = <&pfc 0 32 25>;
 346                         interrupt-controller;
 347                         #interrupt-cells = <2>;
 348                 };
 349
 350                 gpio2: gpio@e6051180 {
 351                         compatible = "renesas,gpio-r8a779f0",
 352                                      "renesas,rcar-gen4-gpio";
 353                         reg = <0 0xe6051180 0 0x54>;
 354                         interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&cpg CPG_MOD 915>;
 356                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 357                         resets = <&cpg 915>;
 358                         gpio-controller;
 359                         #gpio-cells = <2>;
 360                         gpio-ranges = <&pfc 0 64 17>;
 361                         interrupt-controller;
 362                         #interrupt-cells = <2>;
 363                 };
 364
 365                 gpio3: gpio@e6051980 {
 366                         compatible = "renesas,gpio-r8a779f0",
 367                                      "renesas,rcar-gen4-gpio";
 368                         reg = <0 0xe6051980 0 0x54>;
 369                         interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&cpg CPG_MOD 915>;
 371                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 372                         resets = <&cpg 915>;
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                         gpio-ranges = <&pfc 0 96 19>;
 376                         interrupt-controller;
 377                         #interrupt-cells = <2>;
 378                 };
 379
 380                 cmt0: timer@e60f0000 {
 381                         compatible = "renesas,r8a779f0-cmt0",
 382                                      "renesas,rcar-gen4-cmt0";
 383                         reg = <0 0xe60f0000 0 0x1004>;
 384                         interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
 385                                      <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&cpg CPG_MOD 910>;
 387                         clock-names = "fck";
 388                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 389                         resets = <&cpg 910>;
 390                         status = "disabled";
 391                 };
 392
 393                 cmt1: timer@e6130000 {
 394                         compatible = "renesas,r8a779f0-cmt1",
 395                                      "renesas,rcar-gen4-cmt1";
 396                         reg = <0 0xe6130000 0 0x1004>;
 397                         interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
 398                                      <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
 399                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
 400                                      <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
 401                                      <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
 402                                      <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 403                                      <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 404                                      <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&cpg CPG_MOD 911>;
 406                         clock-names = "fck";
 407                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 408                         resets = <&cpg 911>;
 409                         status = "disabled";
 410                 };
 411
 412                 cmt2: timer@e6140000 {
 413                         compatible = "renesas,r8a779f0-cmt1",
 414                                      "renesas,rcar-gen4-cmt1";
 415                         reg = <0 0xe6140000 0 0x1004>;
 416                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 417                                      <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 418                                      <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
 419                                      <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
 420                                      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 421                                      <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 422                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 423                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&cpg CPG_MOD 912>;
 425                         clock-names = "fck";
 426                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 427                         resets = <&cpg 912>;
 428                         status = "disabled";
 429                 };
 430
 431                 cmt3: timer@e6148000 {
 432                         compatible = "renesas,r8a779f0-cmt1",
 433                                      "renesas,rcar-gen4-cmt1";
 434                         reg = <0 0xe6148000 0 0x1004>;
 435                         interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 436                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 437                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 438                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
 440                                      <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
 441                                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 442                                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&cpg CPG_MOD 913>;
 444                         clock-names = "fck";
 445                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 446                         resets = <&cpg 913>;
 447                         status = "disabled";
 448                 };
 449
 450                 cpg: clock-controller@e6150000 {
 451                         compatible = "renesas,r8a779f0-cpg-mssr";
 452                         reg = <0 0xe6150000 0 0x4000>;
 453                         clocks = <&extal_clk>, <&extalr_clk>;
 454                         clock-names = "extal", "extalr";
 455                         #clock-cells = <2>;
 456                         #power-domain-cells = <0>;
 457                         #reset-cells = <1>;
 458                 };
 459
 460                 rst: reset-controller@e6160000 {
 461                         compatible = "renesas,r8a779f0-rst";
 462                         reg = <0 0xe6160000 0 0x4000>;
 463                 };
 464
 465                 sysc: system-controller@e6180000 {
 466                         compatible = "renesas,r8a779f0-sysc";
 467                         reg = <0 0xe6180000 0 0x4000>;
 468                         #power-domain-cells = <1>;
 469                 };
 470
 471                 tsc: thermal@e6198000 {
 472                         compatible = "renesas,r8a779f0-thermal";
 473                         /* The 4th sensor is in control domain and not for Linux */
 474                         reg = <0 0xe6198000 0 0x200>,
 475                               <0 0xe61a0000 0 0x200>,
 476                               <0 0xe61a8000 0 0x200>;
 477                         clocks = <&cpg CPG_MOD 919>;
 478                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 479                         resets = <&cpg 919>;
 480                         #thermal-sensor-cells = <1>;
 481                 };
 482
 483                 intc_ex: interrupt-controller@e61c0000 {
 484                         compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc";
 485                         #interrupt-cells = <2>;
 486                         interrupt-controller;
 487                         reg = <0 0xe61c0000 0 0x200>;
 488                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 493                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>;
 495                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 496                 };
 497
 498                 tmu0: timer@e61e0000 {
 499                         compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
 500                         reg = <0 0xe61e0000 0 0x30>;
 501                         interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
 502                                      <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
 503                                      <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&cpg CPG_MOD 713>;
 505                         clock-names = "fck";
 506                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 507                         resets = <&cpg 713>;
 508                         status = "disabled";
 509                 };
 510
 511                 tmu1: timer@e6fc0000 {
 512                         compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
 513                         reg = <0 0xe6fc0000 0 0x30>;
 514                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
 515                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
 516                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&cpg CPG_MOD 714>;
 518                         clock-names = "fck";
 519                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 520                         resets = <&cpg 714>;
 521                         status = "disabled";
 522                 };
 523
 524                 tmu2: timer@e6fd0000 {
 525                         compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
 526                         reg = <0 0xe6fd0000 0 0x30>;
 527                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
 529                                      <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
 530                         clocks = <&cpg CPG_MOD 715>;
 531                         clock-names = "fck";
 532                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 533                         resets = <&cpg 715>;
 534                         status = "disabled";
 535                 };
 536
 537                 tmu3: timer@e6fe0000 {
 538                         compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
 539                         reg = <0 0xe6fe0000 0 0x30>;
 540                         interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
 542                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&cpg CPG_MOD 716>;
 544                         clock-names = "fck";
 545                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 546                         resets = <&cpg 716>;
 547                         status = "disabled";
 548                 };
 549
 550                 tmu4: timer@ffc00000 {
 551                         compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
 552                         reg = <0 0xffc00000 0 0x30>;
 553                         interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
 554                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&cpg CPG_MOD 717>;
 557                         clock-names = "fck";
 558                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 559                         resets = <&cpg 717>;
 560                         status = "disabled";
 561                 };
 562
 563                 eth_serdes: phy@e6444000 {
 564                         compatible = "renesas,r8a779f0-ether-serdes";
 565                         reg = <0 0xe6444000 0 0x2800>;
 566                         clocks = <&cpg CPG_MOD 1506>;
 567                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 568                         resets = <&cpg 1506>;
 569                         #phy-cells = <1>;
 570                         status = "disabled";
 571                 };
 572
 573                 i2c0: i2c@e6500000 {
 574                         compatible = "renesas,i2c-r8a779f0",
 575                                      "renesas,rcar-gen4-i2c";
 576                         reg = <0 0xe6500000 0 0x40>;
 577                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&cpg CPG_MOD 518>;
 579                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 580                         resets = <&cpg 518>;
 581                         dmas = <&dmac0 0x91>, <&dmac0 0x90>,
 582                                <&dmac1 0x91>, <&dmac1 0x90>;
 583                         dma-names = "tx", "rx", "tx", "rx";
 584                         i2c-scl-internal-delay-ns = <110>;
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         status = "disabled";
 588                 };
 589
 590                 i2c1: i2c@e6508000 {
 591                         compatible = "renesas,i2c-r8a779f0",
 592                                      "renesas,rcar-gen4-i2c";
 593                         reg = <0 0xe6508000 0 0x40>;
 594                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&cpg CPG_MOD 519>;
 596                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 597                         resets = <&cpg 519>;
 598                         dmas = <&dmac0 0x93>, <&dmac0 0x92>,
 599                                <&dmac1 0x93>, <&dmac1 0x92>;
 600                         dma-names = "tx", "rx", "tx", "rx";
 601                         i2c-scl-internal-delay-ns = <110>;
 602                         #address-cells = <1>;
 603                         #size-cells = <0>;
 604                         status = "disabled";
 605                 };
 606
 607                 i2c2: i2c@e6510000 {
 608                         compatible = "renesas,i2c-r8a779f0",
 609                                      "renesas,rcar-gen4-i2c";
 610                         reg = <0 0xe6510000 0 0x40>;
 611                         interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
 612                         clocks = <&cpg CPG_MOD 520>;
 613                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 614                         resets = <&cpg 520>;
 615                         dmas = <&dmac0 0x95>, <&dmac0 0x94>,
 616                                <&dmac1 0x95>, <&dmac1 0x94>;
 617                         dma-names = "tx", "rx", "tx", "rx";
 618                         i2c-scl-internal-delay-ns = <110>;
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         status = "disabled";
 622                 };
 623
 624                 i2c3: i2c@e66d0000 {
 625                         compatible = "renesas,i2c-r8a779f0",
 626                                      "renesas,rcar-gen4-i2c";
 627                         reg = <0 0xe66d0000 0 0x40>;
 628                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 629                         clocks = <&cpg CPG_MOD 521>;
 630                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 631                         resets = <&cpg 521>;
 632                         dmas = <&dmac0 0x97>, <&dmac0 0x96>,
 633                                <&dmac1 0x97>, <&dmac1 0x96>;
 634                         dma-names = "tx", "rx", "tx", "rx";
 635                         i2c-scl-internal-delay-ns = <110>;
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                         status = "disabled";
 639                 };
 640
 641                 i2c4: i2c@e66d8000 {
 642                         compatible = "renesas,i2c-r8a779f0",
 643                                      "renesas,rcar-gen4-i2c";
 644                         reg = <0 0xe66d8000 0 0x40>;
 645                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 646                         clocks = <&cpg CPG_MOD 522>;
 647                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 648                         resets = <&cpg 522>;
 649                         dmas = <&dmac0 0x99>, <&dmac0 0x98>,
 650                                <&dmac1 0x99>, <&dmac1 0x98>;
 651                         dma-names = "tx", "rx", "tx", "rx";
 652                         i2c-scl-internal-delay-ns = <110>;
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         status = "disabled";
 656                 };
 657
 658                 i2c5: i2c@e66e0000 {
 659                         compatible = "renesas,i2c-r8a779f0",
 660                                      "renesas,rcar-gen4-i2c";
 661                         reg = <0 0xe66e0000 0 0x40>;
 662                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 663                         clocks = <&cpg CPG_MOD 523>;
 664                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 665                         resets = <&cpg 523>;
 666                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
 667                                <&dmac1 0x9b>, <&dmac1 0x9a>;
 668                         dma-names = "tx", "rx", "tx", "rx";
 669                         i2c-scl-internal-delay-ns = <110>;
 670                         #address-cells = <1>;
 671                         #size-cells = <0>;
 672                         status = "disabled";
 673                 };
 674
 675                 hscif0: serial@e6540000 {
 676                         compatible = "renesas,hscif-r8a779f0",
 677                                      "renesas,rcar-gen4-hscif", "renesas,hscif";
 678                         reg = <0 0xe6540000 0 0x60>;
 679                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
 680                         clocks = <&cpg CPG_MOD 514>,
 681                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
 682                                  <&scif_clk>;
 683                         clock-names = "fck", "brg_int", "scif_clk";
 684                         dmas = <&dmac0 0x31>, <&dmac0 0x30>,
 685                                <&dmac1 0x31>, <&dmac1 0x30>;
 686                         dma-names = "tx", "rx", "tx", "rx";
 687                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 688                         resets = <&cpg 514>;
 689                         status = "disabled";
 690                 };
 691
 692                 hscif1: serial@e6550000 {
 693                         compatible = "renesas,hscif-r8a779f0",
 694                                      "renesas,rcar-gen4-hscif", "renesas,hscif";
 695                         reg = <0 0xe6550000 0 0x60>;
 696                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&cpg CPG_MOD 515>,
 698                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
 699                                  <&scif_clk>;
 700                         clock-names = "fck", "brg_int", "scif_clk";
 701                         dmas = <&dmac0 0x33>, <&dmac0 0x32>,
 702                                <&dmac1 0x33>, <&dmac1 0x32>;
 703                         dma-names = "tx", "rx", "tx", "rx";
 704                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 705                         resets = <&cpg 515>;
 706                         status = "disabled";
 707                 };
 708
 709                 hscif2: serial@e6560000 {
 710                         compatible = "renesas,hscif-r8a779f0",
 711                                      "renesas,rcar-gen4-hscif", "renesas,hscif";
 712                         reg = <0 0xe6560000 0 0x60>;
 713                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 714                         clocks = <&cpg CPG_MOD 516>,
 715                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
 716                                  <&scif_clk>;
 717                         clock-names = "fck", "brg_int", "scif_clk";
 718                         dmas = <&dmac0 0x35>, <&dmac0 0x34>,
 719                                <&dmac1 0x35>, <&dmac1 0x34>;
 720                         dma-names = "tx", "rx", "tx", "rx";
 721                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 722                         resets = <&cpg 516>;
 723                         status = "disabled";
 724                 };
 725
 726                 hscif3: serial@e66a0000 {
 727                         compatible = "renesas,hscif-r8a779f0",
 728                                      "renesas,rcar-gen4-hscif", "renesas,hscif";
 729                         reg = <0 0xe66a0000 0 0x60>;
 730                         interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 731                         clocks = <&cpg CPG_MOD 517>,
 732                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
 733                                  <&scif_clk>;
 734                         clock-names = "fck", "brg_int", "scif_clk";
 735                         dmas = <&dmac0 0x37>, <&dmac0 0x36>,
 736                                <&dmac1 0x37>, <&dmac1 0x36>;
 737                         dma-names = "tx", "rx", "tx", "rx";
 738                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 739                         resets = <&cpg 517>;
 740                         status = "disabled";
 741                 };
 742
 743                 pciec0: pcie@e65d0000 {
 744                         compatible = "renesas,r8a779f0-pcie",
 745                                      "renesas,rcar-gen4-pcie";
 746                         reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
 747                               <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
 748                               <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
 749                               <0 0xfe000000 0 0x400000>;
 750                         reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
 751                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 755                         interrupt-names = "msi", "dma", "sft_ce", "app";
 756                         clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 757                         clock-names = "core", "ref";
 758                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 759                         resets = <&cpg 624>;
 760                         reset-names = "pwr";
 761                         max-link-speed = <4>;
 762                         num-lanes = <2>;
 763                         #address-cells = <3>;
 764                         #size-cells = <2>;
 765                         bus-range = <0x00 0xff>;
 766                         device_type = "pci";
 767                         ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
 768                                  <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
 769                         dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
 770                         #interrupt-cells = <1>;
 771                         interrupt-map-mask = <0 0 0 7>;
 772                         interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 773                                         <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 774                                         <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 775                                         <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
 776                         snps,enable-cdm-check;
 777                         status = "disabled";
 778                 };
 779
 780                 pciec1: pcie@e65d8000 {
 781                         compatible = "renesas,r8a779f0-pcie",
 782                                      "renesas,rcar-gen4-pcie";
 783                         reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
 784                               <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
 785                               <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
 786                               <0 0xee900000 0 0x400000>;
 787                         reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
 788                         interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 792                         interrupt-names = "msi", "dma", "sft_ce", "app";
 793                         clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
 794                         clock-names = "core", "ref";
 795                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 796                         resets = <&cpg 625>;
 797                         reset-names = "pwr";
 798                         max-link-speed = <4>;
 799                         num-lanes = <2>;
 800                         #address-cells = <3>;
 801                         #size-cells = <2>;
 802                         bus-range = <0x00 0xff>;
 803                         device_type = "pci";
 804                         ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
 805                                  <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
 806                         dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
 807                         #interrupt-cells = <1>;
 808                         interrupt-map-mask = <0 0 0 7>;
 809                         interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 810                                         <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 811                                         <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 812                                         <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
 813                         snps,enable-cdm-check;
 814                         status = "disabled";
 815                 };
 816
 817                 pciec0_ep: pcie-ep@e65d0000 {
 818                         compatible = "renesas,r8a779f0-pcie-ep",
 819                                      "renesas,rcar-gen4-pcie-ep";
 820                         reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
 821                               <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
 822                               <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
 823                               <0 0xfe000000 0 0x400000>;
 824                         reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
 825                         interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 826                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 827                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 828                         interrupt-names = "dma", "sft_ce", "app";
 829                         clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
 830                         clock-names = "core", "ref";
 831                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 832                         resets = <&cpg 624>;
 833                         reset-names = "pwr";
 834                         max-link-speed = <4>;
 835                         num-lanes = <2>;
 836                         max-functions = /bits/ 8 <2>;
 837                         status = "disabled";
 838                 };
 839
 840                 pciec1_ep: pcie-ep@e65d8000 {
 841                         compatible = "renesas,r8a779f0-pcie-ep",
 842                                      "renesas,rcar-gen4-pcie-ep";
 843                         reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
 844                               <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
 845                               <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
 846                               <0 0xee900000 0 0x400000>;
 847                         reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
 848                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 849                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 850                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 851                         interrupt-names = "dma", "sft_ce", "app";
 852                         clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
 853                         clock-names = "core", "ref";
 854                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 855                         resets = <&cpg 625>;
 856                         reset-names = "pwr";
 857                         max-link-speed = <4>;
 858                         num-lanes = <2>;
 859                         max-functions = /bits/ 8 <2>;
 860                         status = "disabled";
 861                 };
 862
 863                 ufs: ufs@e6860000 {
 864                         compatible = "renesas,r8a779f0-ufs";
 865                         reg = <0 0xe6860000 0 0x100>;
 866                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 867                         clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
 868                         clock-names = "fck", "ref_clk";
 869                         freq-table-hz = <200000000 200000000>, <38400000 38400000>;
 870                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 871                         resets = <&cpg 1514>;
 872                         status = "disabled";
 873                 };
 874
 875                 rswitch: ethernet@e6880000 {
 876                         compatible = "renesas,r8a779f0-ether-switch";
 877                         reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>;
 878                         reg-names = "base", "secure_base";
 879                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 880                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 881                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 882                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 883                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 884                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 885                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 886                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 887                                      <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 888                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 889                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 890                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 891                                      <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 892                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 893                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 894                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
 895                                      <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 896                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 897                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
 898                                      <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 899                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 900                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 902                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 903                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 904                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 905                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
 906                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 907                                      <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
 908                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
 911                                      <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
 912                                      <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 918                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
 921                                      <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
 922                                      <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
 925                                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 926                         interrupt-names = "mfwd_error", "race_error",
 927                                           "coma_error", "gwca0_error",
 928                                           "gwca1_error", "etha0_error",
 929                                           "etha1_error", "etha2_error",
 930                                           "gptp0_status", "gptp1_status",
 931                                           "mfwd_status", "race_status",
 932                                           "coma_status", "gwca0_status",
 933                                           "gwca1_status", "etha0_status",
 934                                           "etha1_status", "etha2_status",
 935                                           "rmac0_status", "rmac1_status",
 936                                           "rmac2_status",
 937                                           "gwca0_rxtx0", "gwca0_rxtx1",
 938                                           "gwca0_rxtx2", "gwca0_rxtx3",
 939                                           "gwca0_rxtx4", "gwca0_rxtx5",
 940                                           "gwca0_rxtx6", "gwca0_rxtx7",
 941                                           "gwca1_rxtx0", "gwca1_rxtx1",
 942                                           "gwca1_rxtx2", "gwca1_rxtx3",
 943                                           "gwca1_rxtx4", "gwca1_rxtx5",
 944                                           "gwca1_rxtx6", "gwca1_rxtx7",
 945                                           "gwca0_rxts0", "gwca0_rxts1",
 946                                           "gwca1_rxts0", "gwca1_rxts1",
 947                                           "rmac0_mdio", "rmac1_mdio",
 948                                           "rmac2_mdio",
 949                                           "rmac0_phy", "rmac1_phy",
 950                                           "rmac2_phy";
 951                         clocks = <&cpg CPG_MOD 1505>;
 952                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 953                         resets = <&cpg 1505>;
 954                         status = "disabled";
 955
 956                         ethernet-ports {
 957                                 #address-cells = <1>;
 958                                 #size-cells = <0>;
 959
 960                                 port@0 {
 961                                         reg = <0>;
 962                                         phys = <&eth_serdes 0>;
 963                                 };
 964                                 port@1 {
 965                                         reg = <1>;
 966                                         phys = <&eth_serdes 1>;
 967                                 };
 968                                 port@2 {
 969                                         reg = <2>;
 970                                         phys = <&eth_serdes 2>;
 971                                 };
 972                         };
 973                 };
 974
 975                 scif0: serial@e6e60000 {
 976                         compatible = "renesas,scif-r8a779f0",
 977                                      "renesas,rcar-gen4-scif", "renesas,scif";
 978                         reg = <0 0xe6e60000 0 64>;
 979                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 980                         clocks = <&cpg CPG_MOD 702>,
 981                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
 982                                  <&scif_clk>;
 983                         clock-names = "fck", "brg_int", "scif_clk";
 984                         dmas = <&dmac0 0x51>, <&dmac0 0x50>,
 985                                <&dmac1 0x51>, <&dmac1 0x50>;
 986                         dma-names = "tx", "rx", "tx", "rx";
 987                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
 988                         resets = <&cpg 702>;
 989                         status = "disabled";
 990                 };
 991
 992                 scif1: serial@e6e68000 {
 993                         compatible = "renesas,scif-r8a779f0",
 994                                      "renesas,rcar-gen4-scif", "renesas,scif";
 995                         reg = <0 0xe6e68000 0 64>;
 996                         interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
 997                         clocks = <&cpg CPG_MOD 703>,
 998                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
 999                                  <&scif_clk>;
1000                         clock-names = "fck", "brg_int", "scif_clk";
1001                         dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1002                                <&dmac1 0x53>, <&dmac1 0x52>;
1003                         dma-names = "tx", "rx", "tx", "rx";
1004                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1005                         resets = <&cpg 703>;
1006                         status = "disabled";
1007                 };
1008
1009                 scif3: serial@e6c50000 {
1010                         compatible = "renesas,scif-r8a779f0",
1011                                      "renesas,rcar-gen4-scif", "renesas,scif";
1012                         reg = <0 0xe6c50000 0 64>;
1013                         interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
1014                         clocks = <&cpg CPG_MOD 704>,
1015                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1016                                  <&scif_clk>;
1017                         clock-names = "fck", "brg_int", "scif_clk";
1018                         dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1019                                <&dmac1 0x57>, <&dmac1 0x56>;
1020                         dma-names = "tx", "rx", "tx", "rx";
1021                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1022                         resets = <&cpg 704>;
1023                         status = "disabled";
1024                 };
1025
1026                 scif4: serial@e6c40000 {
1027                         compatible = "renesas,scif-r8a779f0",
1028                                      "renesas,rcar-gen4-scif", "renesas,scif";
1029                         reg = <0 0xe6c40000 0 64>;
1030                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
1031                         clocks = <&cpg CPG_MOD 705>,
1032                                  <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1033                                  <&scif_clk>;
1034                         clock-names = "fck", "brg_int", "scif_clk";
1035                         dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1036                                <&dmac1 0x59>, <&dmac1 0x58>;
1037                         dma-names = "tx", "rx", "tx", "rx";
1038                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1039                         resets = <&cpg 705>;
1040                         status = "disabled";
1041                 };
1042
1043                 msiof0: spi@e6e90000 {
1044                         compatible = "renesas,msiof-r8a779f0",
1045                                      "renesas,rcar-gen4-msiof";
1046                         reg = <0 0xe6e90000 0 0x0064>;
1047                         interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1048                         clocks = <&cpg CPG_MOD 618>;
1049                         dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1050                                <&dmac1 0x41>, <&dmac1 0x40>;
1051                         dma-names = "tx", "rx", "tx", "rx";
1052                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1053                         resets = <&cpg 618>;
1054                         #address-cells = <1>;
1055                         #size-cells = <0>;
1056                         status = "disabled";
1057                 };
1058
1059                 msiof1: spi@e6ea0000 {
1060                         compatible = "renesas,msiof-r8a779f0",
1061                                      "renesas,rcar-gen4-msiof";
1062                         reg = <0 0xe6ea0000 0 0x0064>;
1063                         interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1064                         clocks = <&cpg CPG_MOD 619>;
1065                         dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1066                                <&dmac1 0x43>, <&dmac1 0x42>;
1067                         dma-names = "tx", "rx", "tx", "rx";
1068                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1069                         resets = <&cpg 619>;
1070                         #address-cells = <1>;
1071                         #size-cells = <0>;
1072                         status = "disabled";
1073                 };
1074
1075                 msiof2: spi@e6c00000 {
1076                         compatible = "renesas,msiof-r8a779f0",
1077                                      "renesas,rcar-gen4-msiof";
1078                         reg = <0 0xe6c00000 0 0x0064>;
1079                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1080                         clocks = <&cpg CPG_MOD 620>;
1081                         dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1082                                <&dmac1 0x45>, <&dmac1 0x44>;
1083                         dma-names = "tx", "rx", "tx", "rx";
1084                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1085                         resets = <&cpg 620>;
1086                         #address-cells = <1>;
1087                         #size-cells = <0>;
1088                         status = "disabled";
1089                 };
1090
1091                 msiof3: spi@e6c10000 {
1092                         compatible = "renesas,msiof-r8a779f0",
1093                                      "renesas,rcar-gen4-msiof";
1094                         reg = <0 0xe6c10000 0 0x0064>;
1095                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1096                         clocks = <&cpg CPG_MOD 621>;
1097                         dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1098                                <&dmac1 0x47>, <&dmac1 0x46>;
1099                         dma-names = "tx", "rx", "tx", "rx";
1100                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1101                         resets = <&cpg 621>;
1102                         #address-cells = <1>;
1103                         #size-cells = <0>;
1104                         status = "disabled";
1105                 };
1106
1107                 dmac0: dma-controller@e7350000 {
1108                         compatible = "renesas,dmac-r8a779f0",
1109                                      "renesas,rcar-gen4-dmac";
1110                         reg = <0 0xe7350000 0 0x1000>,
1111                               <0 0xe7300000 0 0x10000>;
1112                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1113                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1114                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1115                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1116                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1117                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1118                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1119                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1120                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1121                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1122                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1123                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1124                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1125                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1126                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1127                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1128                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1129                         interrupt-names = "error",
1130                                           "ch0", "ch1", "ch2", "ch3", "ch4",
1131                                           "ch5", "ch6", "ch7", "ch8", "ch9",
1132                                           "ch10", "ch11", "ch12", "ch13",
1133                                           "ch14", "ch15";
1134                         clocks = <&cpg CPG_MOD 709>;
1135                         clock-names = "fck";
1136                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1137                         resets = <&cpg 709>;
1138                         #dma-cells = <1>;
1139                         dma-channels = <16>;
1140                         iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1141                                  <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1142                                  <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1143                                  <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1144                                  <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1145                                  <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1146                                  <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1147                                  <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1148                 };
1149
1150                 dmac1: dma-controller@e7351000 {
1151                         compatible = "renesas,dmac-r8a779f0",
1152                                      "renesas,rcar-gen4-dmac";
1153                         reg = <0 0xe7351000 0 0x1000>,
1154                               <0 0xe7310000 0 0x10000>;
1155                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1156                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1157                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1158                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1159                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1160                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1162                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1163                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1164                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1167                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1168                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1169                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1170                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1171                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1172                         interrupt-names = "error",
1173                                           "ch0", "ch1", "ch2", "ch3", "ch4",
1174                                           "ch5", "ch6", "ch7", "ch8", "ch9",
1175                                           "ch10", "ch11", "ch12", "ch13",
1176                                           "ch14", "ch15";
1177                         clocks = <&cpg CPG_MOD 710>;
1178                         clock-names = "fck";
1179                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1180                         resets = <&cpg 710>;
1181                         #dma-cells = <1>;
1182                         dma-channels = <16>;
1183                         iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1184                                  <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1185                                  <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1186                                  <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
1187                                  <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
1188                                  <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
1189                                  <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
1190                                  <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
1191                 };
1192
1193                 mmc0: mmc@ee140000 {
1194                         compatible = "renesas,sdhi-r8a779f0",
1195                                      "renesas,rcar-gen4-sdhi";
1196                         reg = <0 0xee140000 0 0x2000>;
1197                         interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1198                         clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
1199                         clock-names = "core", "clkh";
1200                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1201                         resets = <&cpg 706>;
1202                         max-frequency = <200000000>;
1203                         iommus = <&ipmmu_ds0 32>;
1204                         status = "disabled";
1205                 };
1206
1207                 ipmmu_rt0: iommu@ee480000 {
1208                         compatible = "renesas,ipmmu-r8a779f0",
1209                                      "renesas,rcar-gen4-ipmmu-vmsa";
1210                         reg = <0 0xee480000 0 0x20000>;
1211                         renesas,ipmmu-main = <&ipmmu_mm>;
1212                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1213                         #iommu-cells = <1>;
1214                 };
1215
1216                 ipmmu_rt1: iommu@ee4c0000 {
1217                         compatible = "renesas,ipmmu-r8a779f0",
1218                                      "renesas,rcar-gen4-ipmmu-vmsa";
1219                         reg = <0 0xee4c0000 0 0x20000>;
1220                         renesas,ipmmu-main = <&ipmmu_mm>;
1221                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1222                         #iommu-cells = <1>;
1223                 };
1224
1225                 ipmmu_ds0: iommu@eed00000 {
1226                         compatible = "renesas,ipmmu-r8a779f0",
1227                                      "renesas,rcar-gen4-ipmmu-vmsa";
1228                         reg = <0 0xeed00000 0 0x20000>;
1229                         renesas,ipmmu-main = <&ipmmu_mm>;
1230                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1231                         #iommu-cells = <1>;
1232                 };
1233
1234                 ipmmu_hc: iommu@eed40000 {
1235                         compatible = "renesas,ipmmu-r8a779f0",
1236                                      "renesas,rcar-gen4-ipmmu-vmsa";
1237                         reg = <0 0xeed40000 0 0x20000>;
1238                         renesas,ipmmu-main = <&ipmmu_mm>;
1239                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240                         #iommu-cells = <1>;
1241                 };
1242
1243                 ipmmu_mm: iommu@eefc0000 {
1244                         compatible = "renesas,ipmmu-r8a779f0",
1245                                      "renesas,rcar-gen4-ipmmu-vmsa";
1246                         reg = <0 0xeefc0000 0 0x20000>;
1247                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1249                         power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1250                         #iommu-cells = <1>;
1251                 };
1252
1253                 gic: interrupt-controller@f1000000 {
1254                         compatible = "arm,gic-v3";
1255                         #interrupt-cells = <3>;
1256                         #address-cells = <0>;
1257                         interrupt-controller;
1258                         reg = <0x0 0xf1000000 0 0x20000>,
1259                               <0x0 0xf1060000 0 0x110000>;
1260                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1261                 };
1262
1263                 prr: chipid@fff00044 {
1264                         compatible = "renesas,prr";
1265                         reg = <0 0xfff00044 0 4>;
1266                 };
1267         };
1268
1269         thermal-zones {
1270                 sensor_thermal_rtcore: sensor1-thermal {
1271                         polling-delay-passive = <250>;
1272                         polling-delay = <1000>;
1273                         thermal-sensors = <&tsc 0>;
1274
1275                         trips {
1276                                 sensor1_crit: sensor1-crit {
1277                                         temperature = <120000>;
1278                                         hysteresis = <1000>;
1279                                         type = "critical";
1280                                 };
1281                         };
1282                 };
1283
1284                 sensor_thermal_apcore0: sensor2-thermal {
1285                         polling-delay-passive = <250>;
1286                         polling-delay = <1000>;
1287                         thermal-sensors = <&tsc 1>;
1288
1289                         trips {
1290                                 sensor2_crit: sensor2-crit {
1291                                         temperature = <120000>;
1292                                         hysteresis = <1000>;
1293                                         type = "critical";
1294                                 };
1295                         };
1296                 };
1297
1298                 sensor_thermal_apcore4: sensor3-thermal {
1299                         polling-delay-passive = <250>;
1300                         polling-delay = <1000>;
1301                         thermal-sensors = <&tsc 2>;
1302
1303                         trips {
1304                                 sensor3_crit: sensor3-crit {
1305                                         temperature = <120000>;
1306                                         hysteresis = <1000>;
1307                                         type = "critical";
1308                                 };
1309                         };
1310                 };
1311         };
1312
1313         timer {
1314                 compatible = "arm,armv8-timer";
1315                 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1316                                       <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1317                                       <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1318                                       <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1319         };
1320
1321         ufs30_clk: ufs30-clk {
1322                 compatible = "fixed-clock";
1323                 #clock-cells = <0>;
1324                 /* This value must be overridden by the board */
1325                 clock-frequency = <0>;
1326         };
1327 };