arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Spider Ethernet sub-board
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 &eth_serdes {
   9         status = "okay";
  10 };
  11
  12 &i2c4 {
  13         eeprom@52 {
  14                 compatible = "rohm,br24g01", "atmel,24c01";
  15                 label = "ethernet-sub-board";
  16                 reg = <0x52>;
  17                 pagesize = <8>;
  18         };
  19 };
  20
  21 &pfc {
  22         tsn0_pins: tsn0 {
  23                 groups = "tsn0_mdio_b", "tsn0_link_b";
  24                 function = "tsn0";
  25                 power-source = <1800>;
  26         };
  27
  28         tsn1_pins: tsn1 {
  29                 groups = "tsn1_mdio_b", "tsn1_link_b";
  30                 function = "tsn1";
  31                 power-source = <1800>;
  32         };
  33
  34         tsn2_pins: tsn2 {
  35                 groups = "tsn2_mdio_b", "tsn2_link_b";
  36                 function = "tsn2";
  37                 power-source = <1800>;
  38         };
  39 };
  40
  41 &rswitch {
  42         pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
  43         pinctrl-names = "default";
  44         status = "okay";
  45
  46         ethernet-ports {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 port@0 {
  51                         reg = <0>;
  52                         phy-handle = <&u101>;
  53                         phy-mode = "sgmii";
  54                         phys = <&eth_serdes 0>;
  55
  56                         mdio {
  57                                 #address-cells = <1>;
  58                                 #size-cells = <0>;
  59
  60                                 u101: ethernet-phy@1 {
  61                                         reg = <1>;
  62                                         compatible = "ethernet-phy-ieee802.3-c45";
  63                                         interrupt-parent = <&gpio3>;
  64                                         interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
  65                                 };
  66                         };
  67                 };
  68                 port@1 {
  69                         reg = <1>;
  70                         phy-handle = <&u201>;
  71                         phy-mode = "sgmii";
  72                         phys = <&eth_serdes 1>;
  73
  74                         mdio {
  75                                 #address-cells = <1>;
  76                                 #size-cells = <0>;
  77
  78                                 u201: ethernet-phy@2 {
  79                                         reg = <2>;
  80                                         compatible = "ethernet-phy-ieee802.3-c45";
  81                                         interrupt-parent = <&gpio3>;
  82                                         interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
  83                                 };
  84                         };
  85                 };
  86                 port@2 {
  87                         reg = <2>;
  88                         phy-handle = <&u301>;
  89                         phy-mode = "sgmii";
  90                         phys = <&eth_serdes 2>;
  91
  92                         mdio {
  93                                 #address-cells = <1>;
  94                                 #size-cells = <0>;
  95
  96                                 u301: ethernet-phy@3 {
  97                                         reg = <3>;
  98                                         compatible = "ethernet-phy-ieee802.3-c45";
  99                                         interrupt-parent = <&gpio3>;
 100                                         interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
 101                                 };
 102                         };
 103                 };
 104         };
 105 };