arch/arm64/boot/dts/renesas/r8a77995.dtsi

   1 /*
   2  * Device Tree Source for the r8a77995 SoC
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Glider bvba
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 / {
  16         compatible = "renesas,r8a77995";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         psci {
  21                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 a53_0: cpu@0 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         reg = <0x0>;
  32                         device_type = "cpu";
  33                         power-domains = <&sysc 5>;
  34                         next-level-cache = <&L2_CA53>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 L2_CA53: cache-controller-1 {
  39                         compatible = "cache";
  40                         power-domains = <&sysc 21>;
  41                         cache-unified;
  42                         cache-level = <2>;
  43                 };
  44         };
  45
  46         extal_clk: extal {
  47                 compatible = "fixed-clock";
  48                 #clock-cells = <0>;
  49                 /* This value must be overridden by the board */
  50                 clock-frequency = <0>;
  51         };
  52
  53         scif_clk: scif {
  54                 compatible = "fixed-clock";
  55                 #clock-cells = <0>;
  56                 clock-frequency = <0>;
  57         };
  58
  59         soc {
  60                 compatible = "simple-bus";
  61                 interrupt-parent = <&gic>;
  62                 #address-cells = <2>;
  63                 #size-cells = <2>;
  64                 ranges;
  65
  66                 gic: interrupt-controller@f1010000 {
  67                         compatible = "arm,gic-400";
  68                         #interrupt-cells = <3>;
  69                         #address-cells = <0>;
  70                         interrupt-controller;
  71                         reg = <0x0 0xf1010000 0 0x1000>,
  72                               <0x0 0xf1020000 0 0x20000>,
  73                               <0x0 0xf1040000 0 0x20000>,
  74                               <0x0 0xf1060000 0 0x20000>;
  75                         interrupts = <GIC_PPI 9
  76                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  77                         clocks = <&cpg CPG_MOD 408>;
  78                         clock-names = "clk";
  79                         power-domains = <&sysc 32>;
  80                         resets = <&cpg 408>;
  81                 };
  82
  83                 timer {
  84                         compatible = "arm,armv8-timer";
  85                         interrupts = <GIC_PPI 13
  86                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  87                                      <GIC_PPI 14
  88                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  89                                      <GIC_PPI 11
  90                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  91                                      <GIC_PPI 10
  92                                         (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  93                 };
  94
  95                 rwdt: watchdog@e6020000 {
  96                         compatible = "renesas,r8a77995-wdt",
  97                                      "renesas,rcar-gen3-wdt";
  98                         reg = <0 0xe6020000 0 0x0c>;
  99                         clocks = <&cpg CPG_MOD 402>;
 100                         power-domains = <&sysc 32>;
 101                         resets = <&cpg 402>;
 102                         status = "disabled";
 103                 };
 104
 105                 pmu_a53 {
 106                         compatible = "arm,cortex-a53-pmu";
 107                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 108                 };
 109
 110                 cpg: clock-controller@e6150000 {
 111                         compatible = "renesas,r8a77995-cpg-mssr";
 112                         reg = <0 0xe6150000 0 0x1000>;
 113                         clocks = <&extal_clk>;
 114                         clock-names = "extal";
 115                         #clock-cells = <2>;
 116                         #power-domain-cells = <0>;
 117                         #reset-cells = <1>;
 118                 };
 119
 120                 rst: reset-controller@e6160000 {
 121                         compatible = "renesas,r8a77995-rst";
 122                         reg = <0 0xe6160000 0 0x0200>;
 123                 };
 124
 125                 pfc: pfc@e6060000 {
 126                         compatible = "renesas,pfc-r8a77995";
 127                         reg = <0 0xe6060000 0 0x508>;
 128                 };
 129
 130                 prr: chipid@fff00044 {
 131                         compatible = "renesas,prr";
 132                         reg = <0 0xfff00044 0 4>;
 133                 };
 134
 135                 sysc: system-controller@e6180000 {
 136                         compatible = "renesas,r8a77995-sysc";
 137                         reg = <0 0xe6180000 0 0x0400>;
 138                         #power-domain-cells = <1>;
 139                 };
 140
 141                 scif2: serial@e6e88000 {
 142                         compatible = "renesas,scif-r8a77995",
 143                                      "renesas,rcar-gen3-scif", "renesas,scif";
 144                         reg = <0 0xe6e88000 0 64>;
 145                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 146                         clocks = <&cpg CPG_MOD 310>,
 147                                  <&cpg CPG_CORE 16>,
 148                                  <&scif_clk>;
 149                         clock-names = "fck", "brg_int", "scif_clk";
 150                         power-domains = <&sysc 32>;
 151                         resets = <&cpg 310>;
 152                         status = "disabled";
 153                 };
 154         };
 155 };