1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Draak board
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Glider bvba
10 #include "r8a77995.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Renesas Draak board based on r8a77995";
15 compatible = "renesas,draak", "renesas,r8a77995";
23 bootargs = "ignore_loglevel";
24 stdout-path = "serial0:115200n8";
28 compatible = "vga-connector";
32 remote-endpoint = <&adv7123_out>;
38 compatible = "adi,adv7123";
46 adv7123_in: endpoint {
47 remote-endpoint = <&du_out_rgb>;
52 adv7123_out: endpoint {
53 remote-endpoint = <&vga_in>;
60 compatible = "composite-video-connector";
63 composite_con_in: endpoint {
64 remote-endpoint = <&adv7180_in>;
70 compatible = "hdmi-connector";
74 hdmi_con_in: endpoint {
75 remote-endpoint = <&adv7612_in>;
81 device_type = "memory";
82 /* first 128MB is reserved for secure area. */
83 reg = <0x0 0x48000000 0x0 0x18000000>;
86 reg_1p8v: regulator0 {
87 compatible = "regulator-fixed";
88 regulator-name = "fixed-1.8V";
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
95 reg_3p3v: regulator1 {
96 compatible = "regulator-fixed";
97 regulator-name = "fixed-3.3V";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
105 compatible = "fixed-clock";
107 clock-frequency = <74250000>;
112 clock-frequency = <48000000>;
118 groups = "avb0_link", "avb0_mdio", "avb0_mii";
124 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
149 groups = "scif2_data";
154 groups = "mmc_data8", "mmc_ctrl";
156 power-source = <1800>;
159 sdhi2_pins_uhs: sd2_uhs {
160 groups = "mmc_data8", "mmc_ctrl";
162 power-source = <1800>;
170 vin4_pins_cvbs: vin4 {
171 groups = "vin4_data8", "vin4_sync", "vin4_clk";
177 pinctrl-0 = <&i2c0_pins>;
178 pinctrl-names = "default";
182 compatible = "rohm,br24t01", "atmel,24c01";
188 compatible = "adi,adv7180cp";
192 #address-cells = <1>;
197 adv7180_in: endpoint {
198 remote-endpoint = <&composite_con_in>;
206 * The VIN4 video input path is shared between
207 * CVBS and HDMI inputs through SW[49-53]
210 * CVBS is the default selection, link it to
213 adv7180_out: endpoint {
214 remote-endpoint = <&vin4_in>;
222 compatible = "adi,adv7612";
227 #address-cells = <1>;
233 adv7612_in: endpoint {
234 remote-endpoint = <&hdmi_con_in>;
242 * The VIN4 video input path is shared between
243 * CVBS and HDMI inputs through SW[49-53]
246 * CVBS is the default selection, leave HDMI
247 * not connected here.
249 adv7612_out: endpoint {
260 pinctrl-0 = <&i2c1_pins>;
261 pinctrl-names = "default";
266 pinctrl-0 = <&du_pins>;
267 pinctrl-names = "default";
270 clocks = <&cpg CPG_MOD 724>,
273 clock-names = "du.0", "du.1", "dclkin.0";
278 remote-endpoint = <&adv7123_in>;
293 pinctrl-0 = <&avb0_pins>;
294 pinctrl-names = "default";
295 renesas,no-ether-link;
296 phy-handle = <&phy0>;
297 phy-mode = "rgmii-txid";
300 phy0: ethernet-phy@0 {
301 rxc-skew-ps = <1500>;
303 interrupt-parent = <&gpio5>;
304 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
309 pinctrl-0 = <&scif2_pins>;
310 pinctrl-names = "default";
316 /* used for on-board eMMC */
317 pinctrl-0 = <&sdhi2_pins>;
318 pinctrl-1 = <&sdhi2_pins_uhs>;
319 pinctrl-names = "default", "state_uhs";
321 vmmc-supply = <®_3p3v>;
322 vqmmc-supply = <®_1p8v>;
330 pinctrl-0 = <&usb0_pins>;
331 pinctrl-names = "default";
337 pinctrl-0 = <&pwm0_pins>;
338 pinctrl-names = "default";
344 pinctrl-0 = <&pwm1_pins>;
345 pinctrl-names = "default";
356 pinctrl-0 = <&vin4_pins_cvbs>;
357 pinctrl-names = "default";
362 #address-cells = <1>;
369 remote-endpoint = <&adv7180_out>;