arch/arm64/boot/dts/renesas/r8a77980.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77980 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8
   9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/r8a77980-sysc.h>
  13
  14 / {
  15         compatible = "renesas,r8a77980";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 i2c4 = &i2c4;
  25                 i2c5 = &i2c5;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 a53_0: cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a53", "arm,armv8";
  35                         reg = <0>;
  36                         clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
  37                         power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
  38                         next-level-cache = <&L2_CA53>;
  39                         enable-method = "psci";
  40                 };
  41
  42                 a53_1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <1>;
  46                         clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
  47                         power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
  48                         next-level-cache = <&L2_CA53>;
  49                         enable-method = "psci";
  50                 };
  51
  52                 a53_2: cpu@2 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53", "arm,armv8";
  55                         reg = <2>;
  56                         clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
  57                         power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
  58                         next-level-cache = <&L2_CA53>;
  59                         enable-method = "psci";
  60                 };
  61
  62                 a53_3: cpu@3 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <3>;
  66                         clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
  67                         power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
  68                         next-level-cache = <&L2_CA53>;
  69                         enable-method = "psci";
  70                 };
  71
  72                 L2_CA53: cache-controller {
  73                         compatible = "cache";
  74                         power-domains = <&sysc R8A77980_PD_CA53_SCU>;
  75                         cache-unified;
  76                         cache-level = <2>;
  77                 };
  78         };
  79
  80         /* External CAN clock - to be overridden by boards that provide it */
  81         can_clk: can {
  82                 compatible = "fixed-clock";
  83                 #clock-cells = <0>;
  84                 clock-frequency = <0>;
  85         };
  86
  87         extal_clk: extal {
  88                 compatible = "fixed-clock";
  89                 #clock-cells = <0>;
  90                 /* This value must be overridden by the board */
  91                 clock-frequency = <0>;
  92         };
  93
  94         extalr_clk: extalr {
  95                 compatible = "fixed-clock";
  96                 #clock-cells = <0>;
  97                 /* This value must be overridden by the board */
  98                 clock-frequency = <0>;
  99         };
 100
 101         psci {
 102                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 103                 method = "smc";
 104         };
 105
 106         /* External SCIF clock - to be overridden by boards that provide it */
 107         scif_clk: scif {
 108                 compatible = "fixed-clock";
 109                 #clock-cells = <0>;
 110                 clock-frequency = <0>;
 111         };
 112
 113         soc {
 114                 compatible = "simple-bus";
 115                 interrupt-parent = <&gic>;
 116
 117                 #address-cells = <2>;
 118                 #size-cells = <2>;
 119                 ranges;
 120
 121                 gpio0: gpio@e6050000 {
 122                         compatible = "renesas,gpio-r8a77980",
 123                                      "renesas,rcar-gen3-gpio";
 124                         reg = <0 0xe6050000 0 0x50>;
 125                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 126                         #gpio-cells = <2>;
 127                         gpio-controller;
 128                         gpio-ranges = <&pfc 0 0 22>;
 129                         #interrupt-cells = <2>;
 130                         interrupt-controller;
 131                         clocks = <&cpg CPG_MOD 912>;
 132                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 133                         resets = <&cpg 912>;
 134                 };
 135
 136                 gpio1: gpio@e6051000 {
 137                         compatible = "renesas,gpio-r8a77980",
 138                                      "renesas,rcar-gen3-gpio";
 139                         reg = <0 0xe6051000 0 0x50>;
 140                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 141                         #gpio-cells = <2>;
 142                         gpio-controller;
 143                         gpio-ranges = <&pfc 0 32 28>;
 144                         #interrupt-cells = <2>;
 145                         interrupt-controller;
 146                         clocks = <&cpg CPG_MOD 911>;
 147                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 148                         resets = <&cpg 911>;
 149                 };
 150
 151                 gpio2: gpio@e6052000 {
 152                         compatible = "renesas,gpio-r8a77980",
 153                                      "renesas,rcar-gen3-gpio";
 154                         reg = <0 0xe6052000 0 0x50>;
 155                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 156                         #gpio-cells = <2>;
 157                         gpio-controller;
 158                         gpio-ranges = <&pfc 0 64 30>;
 159                         #interrupt-cells = <2>;
 160                         interrupt-controller;
 161                         clocks = <&cpg CPG_MOD 910>;
 162                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 163                         resets = <&cpg 910>;
 164                 };
 165
 166                 gpio3: gpio@e6053000 {
 167                         compatible = "renesas,gpio-r8a77980",
 168                                      "renesas,rcar-gen3-gpio";
 169                         reg = <0 0xe6053000 0 0x50>;
 170                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 171                         #gpio-cells = <2>;
 172                         gpio-controller;
 173                         gpio-ranges = <&pfc 0 96 17>;
 174                         #interrupt-cells = <2>;
 175                         interrupt-controller;
 176                         clocks = <&cpg CPG_MOD 909>;
 177                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 178                         resets = <&cpg 909>;
 179                 };
 180
 181                 gpio4: gpio@e6054000 {
 182                         compatible = "renesas,gpio-r8a77980",
 183                                      "renesas,rcar-gen3-gpio";
 184                         reg = <0 0xe6054000 0 0x50>;
 185                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 186                         #gpio-cells = <2>;
 187                         gpio-controller;
 188                         gpio-ranges = <&pfc 0 128 25>;
 189                         #interrupt-cells = <2>;
 190                         interrupt-controller;
 191                         clocks = <&cpg CPG_MOD 908>;
 192                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 193                         resets = <&cpg 908>;
 194                 };
 195
 196                 gpio5: gpio@e6055000 {
 197                         compatible = "renesas,gpio-r8a77980",
 198                                      "renesas,rcar-gen3-gpio";
 199                         reg = <0 0xe6055000 0 0x50>;
 200                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 201                         #gpio-cells = <2>;
 202                         gpio-controller;
 203                         gpio-ranges = <&pfc 0 160 15>;
 204                         #interrupt-cells = <2>;
 205                         interrupt-controller;
 206                         clocks = <&cpg CPG_MOD 907>;
 207                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 208                         resets = <&cpg 907>;
 209                 };
 210
 211                 pfc: pin-controller@e6060000 {
 212                         compatible = "renesas,pfc-r8a77980";
 213                         reg = <0 0xe6060000 0 0x50c>;
 214                 };
 215
 216                 cpg: clock-controller@e6150000 {
 217                         compatible = "renesas,r8a77980-cpg-mssr";
 218                         reg = <0 0xe6150000 0 0x1000>;
 219                         clocks = <&extal_clk>, <&extalr_clk>;
 220                         clock-names = "extal", "extalr";
 221                         #clock-cells = <2>;
 222                         #power-domain-cells = <0>;
 223                         #reset-cells = <1>;
 224                 };
 225
 226                 rst: reset-controller@e6160000 {
 227                         compatible = "renesas,r8a77980-rst";
 228                         reg = <0 0xe6160000 0 0x200>;
 229                 };
 230
 231                 sysc: system-controller@e6180000 {
 232                         compatible = "renesas,r8a77980-sysc";
 233                         reg = <0 0xe6180000 0 0x440>;
 234                         #power-domain-cells = <1>;
 235                 };
 236
 237                 intc_ex: interrupt-controller@e61c0000 {
 238                         compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
 239                         #interrupt-cells = <2>;
 240                         interrupt-controller;
 241                         reg = <0 0xe61c0000 0 0x200>;
 242                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 243                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 244                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 245                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 246                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 247                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 248                         clocks = <&cpg CPG_MOD 407>;
 249                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 250                         resets = <&cpg 407>;
 251                 };
 252
 253                 i2c0: i2c@e6500000 {
 254                         compatible = "renesas,i2c-r8a77980",
 255                                      "renesas,rcar-gen3-i2c";
 256                         reg = <0 0xe6500000 0 0x40>;
 257                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 258                         clocks = <&cpg CPG_MOD 931>;
 259                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 260                         resets = <&cpg 931>;
 261                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 262                                <&dmac2 0x91>, <&dmac2 0x90>;
 263                         dma-names = "tx", "rx", "tx", "rx";
 264                         i2c-scl-internal-delay-ns = <6>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         status = "disabled";
 268                 };
 269
 270                 i2c1: i2c@e6508000 {
 271                         compatible = "renesas,i2c-r8a77980",
 272                                      "renesas,rcar-gen3-i2c";
 273                         reg = <0 0xe6508000 0 0x40>;
 274                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&cpg CPG_MOD 930>;
 276                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 277                         resets = <&cpg 930>;
 278                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 279                                <&dmac2 0x93>, <&dmac2 0x92>;
 280                         dma-names = "tx", "rx", "tx", "rx";
 281                         i2c-scl-internal-delay-ns = <6>;
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         status = "disabled";
 285                 };
 286
 287                 i2c2: i2c@e6510000 {
 288                         compatible = "renesas,i2c-r8a77980",
 289                                      "renesas,rcar-gen3-i2c";
 290                         reg = <0 0xe6510000 0 0x40>;
 291                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&cpg CPG_MOD 929>;
 293                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 294                         resets = <&cpg 929>;
 295                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 296                                <&dmac2 0x95>, <&dmac2 0x94>;
 297                         dma-names = "tx", "rx", "tx", "rx";
 298                         i2c-scl-internal-delay-ns = <6>;
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         status = "disabled";
 302                 };
 303
 304                 i2c3: i2c@e66d0000 {
 305                         compatible = "renesas,i2c-r8a77980",
 306                                      "renesas,rcar-gen3-i2c";
 307                         reg = <0 0xe66d0000 0 0x40>;
 308                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 309                         clocks = <&cpg CPG_MOD 928>;
 310                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 311                         resets = <&cpg 928>;
 312                         i2c-scl-internal-delay-ns = <6>;
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         status = "disabled";
 316                 };
 317
 318                 i2c4: i2c@e66d8000 {
 319                         compatible = "renesas,i2c-r8a77980",
 320                                      "renesas,rcar-gen3-i2c";
 321                         reg = <0 0xe66d8000 0 0x40>;
 322                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&cpg CPG_MOD 927>;
 324                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 325                         resets = <&cpg 927>;
 326                         i2c-scl-internal-delay-ns = <6>;
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         status = "disabled";
 330                 };
 331
 332                 i2c5: i2c@e66e0000 {
 333                         compatible = "renesas,i2c-r8a77980",
 334                                      "renesas,rcar-gen3-i2c";
 335                         reg = <0 0xe66e0000 0 0x40>;
 336                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&cpg CPG_MOD 919>;
 338                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 339                         resets = <&cpg 919>;
 340                         dmas = <&dmac1 0x9b>, <&dmac1 0x9a>,
 341                                <&dmac2 0x9b>, <&dmac2 0x9a>;
 342                         dma-names = "tx", "rx", "tx", "rx";
 343                         i2c-scl-internal-delay-ns = <6>;
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         status = "disabled";
 347                 };
 348
 349                 hscif0: serial@e6540000 {
 350                         compatible = "renesas,hscif-r8a77980",
 351                                      "renesas,rcar-gen3-hscif",
 352                                      "renesas,hscif";
 353                         reg = <0 0xe6540000 0 0x60>;
 354                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&cpg CPG_MOD 520>,
 356                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 357                                  <&scif_clk>;
 358                         clock-names = "fck", "brg_int", "scif_clk";
 359                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 360                                <&dmac2 0x31>, <&dmac2 0x30>;
 361                         dma-names = "tx", "rx", "tx", "rx";
 362                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 363                         resets = <&cpg 520>;
 364                         status = "disabled";
 365                 };
 366
 367                 hscif1: serial@e6550000 {
 368                         compatible = "renesas,hscif-r8a77980",
 369                                      "renesas,rcar-gen3-hscif",
 370                                      "renesas,hscif";
 371                         reg = <0 0xe6550000 0 0x60>;
 372                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 373                         clocks = <&cpg CPG_MOD 519>,
 374                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 375                                  <&scif_clk>;
 376                         clock-names = "fck", "brg_int", "scif_clk";
 377                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 378                                <&dmac2 0x33>, <&dmac2 0x32>;
 379                         dma-names = "tx", "rx", "tx", "rx";
 380                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 381                         resets = <&cpg 519>;
 382                         status = "disabled";
 383                 };
 384
 385                 hscif2: serial@e6560000 {
 386                         compatible = "renesas,hscif-r8a77980",
 387                                      "renesas,rcar-gen3-hscif",
 388                                      "renesas,hscif";
 389                         reg = <0 0xe6560000 0 0x60>;
 390                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 391                         clocks = <&cpg CPG_MOD 518>,
 392                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 393                                  <&scif_clk>;
 394                         clock-names = "fck", "brg_int", "scif_clk";
 395                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 396                                <&dmac2 0x35>, <&dmac2 0x34>;
 397                         dma-names = "tx", "rx", "tx", "rx";
 398                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 399                         resets = <&cpg 518>;
 400                         status = "disabled";
 401                 };
 402
 403                 hscif3: serial@e66a0000 {
 404                         compatible = "renesas,hscif-r8a77980",
 405                                      "renesas,rcar-gen3-hscif",
 406                                      "renesas,hscif";
 407                         reg = <0 0xe66a0000 0 0x60>;
 408                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 409                         clocks = <&cpg CPG_MOD 517>,
 410                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 411                                  <&scif_clk>;
 412                         clock-names = "fck", "brg_int", "scif_clk";
 413                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 414                                <&dmac2 0x37>, <&dmac2 0x36>;
 415                         dma-names = "tx", "rx", "tx", "rx";
 416                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 417                         resets = <&cpg 517>;
 418                         status = "disabled";
 419                 };
 420
 421                 canfd: can@e66c0000 {
 422                         compatible = "renesas,r8a77980-canfd",
 423                                      "renesas,rcar-gen3-canfd";
 424                         reg = <0 0xe66c0000 0 0x8000>;
 425                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 426                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&cpg CPG_MOD 914>,
 428                                  <&cpg CPG_CORE R8A77980_CLK_CANFD>,
 429                                  <&can_clk>;
 430                         clock-names = "fck", "canfd", "can_clk";
 431                         assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
 432                         assigned-clock-rates = <40000000>;
 433                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 434                         resets = <&cpg 914>;
 435                         status = "disabled";
 436
 437                         channel0 {
 438                                 status = "disabled";
 439                         };
 440
 441                         channel1 {
 442                                 status = "disabled";
 443                         };
 444                 };
 445
 446                 ipmmu_ds1: mmu@e7740000 {
 447                         compatible = "renesas,ipmmu-r8a77980";
 448                         reg = <0 0xe7740000 0 0x1000>;
 449                         renesas,ipmmu-main = <&ipmmu_mm 0>;
 450                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 451                         #iommu-cells = <1>;
 452                 };
 453
 454                 ipmmu_vip0: mmu@e7b00000 {
 455                         compatible = "renesas,ipmmu-r8a77980";
 456                         reg = <0 0xe7b00000 0 0x1000>;
 457                         renesas,ipmmu-main = <&ipmmu_mm 4>;
 458                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 459                         #iommu-cells = <1>;
 460                 };
 461
 462                 ipmmu_vip1: mmu@e7960000 {
 463                         compatible = "renesas,ipmmu-r8a77980";
 464                         reg = <0 0xe7960000 0 0x1000>;
 465                         renesas,ipmmu-main = <&ipmmu_mm 11>;
 466                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 467                         #iommu-cells = <1>;
 468                 };
 469
 470                 ipmmu_ir: mmu@ff8b0000 {
 471                         compatible = "renesas,ipmmu-r8a77980";
 472                         reg = <0 0xff8b0000 0 0x1000>;
 473                         renesas,ipmmu-main = <&ipmmu_mm 3>;
 474                         power-domains = <&sysc R8A77980_PD_A3IR>;
 475                         #iommu-cells = <1>;
 476                 };
 477
 478                 ipmmu_mm: mmu@e67b0000 {
 479                         compatible = "renesas,ipmmu-r8a77980";
 480                         reg = <0 0xe67b0000 0 0x1000>;
 481                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 482                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 483                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 484                         #iommu-cells = <1>;
 485                 };
 486
 487                 ipmmu_rt: mmu@ffc80000 {
 488                         compatible = "renesas,ipmmu-r8a77980";
 489                         reg = <0 0xffc80000 0 0x1000>;
 490                         renesas,ipmmu-main = <&ipmmu_mm 10>;
 491                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 492                         #iommu-cells = <1>;
 493                 };
 494
 495                 ipmmu_vc0: mmu@fe6b0000 {
 496                         compatible = "renesas,ipmmu-r8a77980";
 497                         reg = <0 0xfe6b0000 0 0x1000>;
 498                         renesas,ipmmu-main = <&ipmmu_mm 12>;
 499                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 500                         #iommu-cells = <1>;
 501                 };
 502
 503                 ipmmu_vi0: mmu@febd0000 {
 504                         compatible = "renesas,ipmmu-r8a77980";
 505                         reg = <0 0xfebd0000 0 0x1000>;
 506                         renesas,ipmmu-main = <&ipmmu_mm 14>;
 507                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 508                         #iommu-cells = <1>;
 509                 };
 510
 511                 avb: ethernet@e6800000 {
 512                         compatible = "renesas,etheravb-r8a77980",
 513                                      "renesas,etheravb-rcar-gen3";
 514                         reg = <0 0xe6800000 0 0x800>;
 515                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 516                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 520                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 521                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 522                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 523                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 524                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 525                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 526                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 527                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 529                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 530                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 535                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 536                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 540                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 541                                           "ch4", "ch5", "ch6", "ch7",
 542                                           "ch8", "ch9", "ch10", "ch11",
 543                                           "ch12", "ch13", "ch14", "ch15",
 544                                           "ch16", "ch17", "ch18", "ch19",
 545                                           "ch20", "ch21", "ch22", "ch23",
 546                                           "ch24";
 547                         clocks = <&cpg CPG_MOD 812>;
 548                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 549                         resets = <&cpg 812>;
 550                         phy-mode = "rgmii";
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                         status = "disabled";
 554                 };
 555
 556                 scif0: serial@e6e60000 {
 557                         compatible = "renesas,scif-r8a77980",
 558                                      "renesas,rcar-gen3-scif",
 559                                      "renesas,scif";
 560                         reg = <0 0xe6e60000 0 0x40>;
 561                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&cpg CPG_MOD 207>,
 563                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 564                                  <&scif_clk>;
 565                         clock-names = "fck", "brg_int", "scif_clk";
 566                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 567                                <&dmac2 0x51>, <&dmac2 0x50>;
 568                         dma-names = "tx", "rx", "tx", "rx";
 569                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 570                         resets = <&cpg 207>;
 571                         status = "disabled";
 572                 };
 573
 574                 scif1: serial@e6e68000 {
 575                         compatible = "renesas,scif-r8a77980",
 576                                      "renesas,rcar-gen3-scif",
 577                                      "renesas,scif";
 578                         reg = <0 0xe6e68000 0 0x40>;
 579                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&cpg CPG_MOD 206>,
 581                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 582                                  <&scif_clk>;
 583                         clock-names = "fck", "brg_int", "scif_clk";
 584                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 585                                <&dmac2 0x53>, <&dmac2 0x52>;
 586                         dma-names = "tx", "rx", "tx", "rx";
 587                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 588                         resets = <&cpg 206>;
 589                         status = "disabled";
 590                 };
 591
 592                 scif3: serial@e6c50000 {
 593                         compatible = "renesas,scif-r8a77980",
 594                                      "renesas,rcar-gen3-scif",
 595                                      "renesas,scif";
 596                         reg = <0 0xe6c50000 0 0x40>;
 597                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&cpg CPG_MOD 204>,
 599                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 600                                  <&scif_clk>;
 601                         clock-names = "fck", "brg_int", "scif_clk";
 602                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 603                                <&dmac2 0x57>, <&dmac2 0x56>;
 604                         dma-names = "tx", "rx", "tx", "rx";
 605                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 606                         resets = <&cpg 204>;
 607                         status = "disabled";
 608                 };
 609
 610                 scif4: serial@e6c40000 {
 611                         compatible = "renesas,scif-r8a77980",
 612                                      "renesas,rcar-gen3-scif",
 613                                      "renesas,scif";
 614                         reg = <0 0xe6c40000 0 0x40>;
 615                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&cpg CPG_MOD 203>,
 617                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 618                                  <&scif_clk>;
 619                         clock-names = "fck", "brg_int", "scif_clk";
 620                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 621                                <&dmac2 0x59>, <&dmac2 0x58>;
 622                         dma-names = "tx", "rx", "tx", "rx";
 623                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 624                         resets = <&cpg 203>;
 625                         status = "disabled";
 626                 };
 627
 628                 dmac1: dma-controller@e7300000 {
 629                         compatible = "renesas,dmac-r8a77980",
 630                                      "renesas,rcar-dmac";
 631                         reg = <0 0xe7300000 0 0x10000>;
 632                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 633                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 634                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 635                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 636                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 637                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 638                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 639                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 640                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 641                                       GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
 642                                       GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
 643                                       GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
 644                                       GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
 645                                       GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
 646                                       GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
 647                                       GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
 648                                       GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 649                         interrupt-names = "error",
 650                                           "ch0", "ch1", "ch2", "ch3",
 651                                           "ch4", "ch5", "ch6", "ch7",
 652                                           "ch8", "ch9", "ch10", "ch11",
 653                                           "ch12", "ch13", "ch14", "ch15";
 654                         clocks = <&cpg CPG_MOD 218>;
 655                         clock-names = "fck";
 656                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 657                         resets = <&cpg 218>;
 658                         #dma-cells = <1>;
 659                         dma-channels = <16>;
 660                 };
 661
 662                 dmac2: dma-controller@e7310000 {
 663                         compatible = "renesas,dmac-r8a77980",
 664                                      "renesas,rcar-dmac";
 665                         reg = <0 0xe7310000 0 0x10000>;
 666                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 667                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 668                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 669                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 670                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 671                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 672                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 673                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 674                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
 675                                       GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
 676                                       GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
 677                                       GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
 678                                       GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
 679                                       GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
 680                                       GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
 681                                       GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
 682                                       GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 683                         interrupt-names = "error",
 684                                           "ch0", "ch1", "ch2", "ch3",
 685                                           "ch4", "ch5", "ch6", "ch7",
 686                                           "ch8", "ch9", "ch10", "ch11",
 687                                           "ch12", "ch13", "ch14", "ch15";
 688                         clocks = <&cpg CPG_MOD 217>;
 689                         clock-names = "fck";
 690                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 691                         resets = <&cpg 217>;
 692                         #dma-cells = <1>;
 693                         dma-channels = <16>;
 694                 };
 695
 696                 gether: ethernet@e7400000 {
 697                         compatible = "renesas,gether-r8a77980";
 698                         reg = <0 0xe7400000 0 0x1000>;
 699                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 700                         clocks = <&cpg CPG_MOD 813>;
 701                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 702                         resets = <&cpg 813>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         status = "disabled";
 706                 };
 707
 708                 mmc0: mmc@ee140000 {
 709                         compatible = "renesas,sdhi-r8a77980",
 710                                      "renesas,rcar-gen3-sdhi";
 711                         reg = <0 0xee140000 0 0x2000>;
 712                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&cpg CPG_MOD 314>;
 714                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 715                         resets = <&cpg 314>;
 716                         max-frequency = <200000000>;
 717                         status = "disabled";
 718                 };
 719
 720                 gic: interrupt-controller@f1010000 {
 721                         compatible = "arm,gic-400";
 722                         #interrupt-cells = <3>;
 723                         #address-cells = <0>;
 724                         interrupt-controller;
 725                         reg = <0x0 0xf1010000 0 0x1000>,
 726                               <0x0 0xf1020000 0 0x20000>,
 727                               <0x0 0xf1040000 0 0x20000>,
 728                               <0x0 0xf1060000 0 0x20000>;
 729                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
 730                                       IRQ_TYPE_LEVEL_HIGH)>;
 731                         clocks = <&cpg CPG_MOD 408>;
 732                         clock-names = "clk";
 733                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 734                         resets = <&cpg 408>;
 735                 };
 736
 737                 vspd0: vsp@fea20000 {
 738                         compatible = "renesas,vsp2";
 739                         reg = <0 0xfea20000 0 0x5000>;
 740                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 741                         clocks = <&cpg CPG_MOD 623>;
 742                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 743                         resets = <&cpg 623>;
 744                         renesas,fcp = <&fcpvd0>;
 745                 };
 746
 747                 fcpvd0: fcp@fea27000 {
 748                         compatible = "renesas,fcpv";
 749                         reg = <0 0xfea27000 0 0x200>;
 750                         clocks = <&cpg CPG_MOD 603>;
 751                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 752                         resets = <&cpg 603>;
 753                 };
 754
 755                 du: display@feb00000 {
 756                         compatible = "renesas,du-r8a77980",
 757                                      "renesas,du-r8a77970";
 758                         reg = <0 0xfeb00000 0 0x80000>;
 759                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 760                         clocks = <&cpg CPG_MOD 724>;
 761                         clock-names = "du.0";
 762                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 763                         resets = <&cpg 724>;
 764                         vsps = <&vspd0>;
 765                         status = "disabled";
 766
 767                         ports {
 768                                 #address-cells = <1>;
 769                                 #size-cells = <0>;
 770
 771                                 port@0 {
 772                                         reg = <0>;
 773                                         du_out_rgb: endpoint {
 774                                         };
 775                                 };
 776
 777                                 port@1 {
 778                                         reg = <1>;
 779                                         du_out_lvds0: endpoint {
 780                                                 remote-endpoint = <&lvds0_in>;
 781                                         };
 782                                 };
 783                         };
 784                 };
 785
 786                 lvds0: lvds-encoder@feb90000 {
 787                         compatible = "renesas,r8a77980-lvds";
 788                         reg = <0 0xfeb90000 0 0x14>;
 789                         clocks = <&cpg CPG_MOD 727>;
 790                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 791                         resets = <&cpg 727>;
 792                         status = "disabled";
 793
 794                         ports {
 795                                 #address-cells = <1>;
 796                                 #size-cells = <0>;
 797
 798                                 port@0 {
 799                                         reg = <0>;
 800                                         lvds0_in: endpoint {
 801                                                 remote-endpoint =
 802                                                         <&du_out_lvds0>;
 803                                         };
 804                                 };
 805
 806                                 port@1 {
 807                                         reg = <1>;
 808                                         lvds0_out: endpoint {
 809                                         };
 810                                 };
 811                         };
 812                 };
 813
 814                 prr: chipid@fff00044 {
 815                         compatible = "renesas,prr";
 816                         reg = <0 0xfff00044 0 4>;
 817                 };
 818         };
 819
 820         timer {
 821                 compatible = "arm,armv8-timer";
 822                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 823                                        IRQ_TYPE_LEVEL_LOW)>,
 824                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 825                                        IRQ_TYPE_LEVEL_LOW)>,
 826                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 827                                        IRQ_TYPE_LEVEL_LOW)>,
 828                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 829                                        IRQ_TYPE_LEVEL_LOW)>;
 830         };
 831 };