arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the V3H Starter Kit board
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a77980.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Renesas V3H Starter Kit board";
  15         compatible = "renesas,v3hsk", "renesas,r8a77980";
  16
  17         aliases {
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c1;
  20                 i2c2 = &i2c2;
  21                 i2c3 = &i2c3;
  22                 i2c4 = &i2c4;
  23                 i2c5 = &i2c5;
  24                 serial0 = &scif0;
  25                 ethernet0 = &gether;
  26         };
  27
  28         chosen {
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         hdmi-out {
  33                 compatible = "hdmi-connector";
  34                 type = "a";
  35
  36                 port {
  37                         hdmi_con: endpoint {
  38                                 remote-endpoint = <&adv7511_out>;
  39                         };
  40                 };
  41         };
  42
  43         lvds-decoder {
  44                 compatible = "thine,thc63lvd1024";
  45                 vcc-supply = <&vcc3v3_d5>;
  46
  47                 ports {
  48                         #address-cells = <1>;
  49                         #size-cells = <0>;
  50
  51                         port@0 {
  52                                 reg = <0>;
  53                                 thc63lvd1024_in: endpoint {
  54                                         remote-endpoint = <&lvds0_out>;
  55                                 };
  56                         };
  57
  58                         port@2 {
  59                                 reg = <2>;
  60                                 thc63lvd1024_out: endpoint {
  61                                         remote-endpoint = <&adv7511_in>;
  62                                 };
  63                         };
  64                 };
  65         };
  66
  67         memory@48000000 {
  68                 device_type = "memory";
  69                 /* first 128MB is reserved for secure area. */
  70                 reg = <0 0x48000000 0 0x78000000>;
  71         };
  72
  73         osc1_clk: osc1-clock {
  74                 compatible = "fixed-clock";
  75                 #clock-cells = <0>;
  76                 clock-frequency = <148500000>;
  77         };
  78
  79         vcc1v8_d4: regulator-0 {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "VCC1V8_D4";
  82                 regulator-min-microvolt = <1800000>;
  83                 regulator-max-microvolt = <1800000>;
  84                 regulator-boot-on;
  85                 regulator-always-on;
  86         };
  87
  88         vcc3v3_d5: regulator-1 {
  89                 compatible = "regulator-fixed";
  90                 regulator-name = "VCC3V3_D5";
  91                 regulator-min-microvolt = <3300000>;
  92                 regulator-max-microvolt = <3300000>;
  93                 regulator-boot-on;
  94                 regulator-always-on;
  95         };
  96 };
  97
  98 &du {
  99         clocks = <&cpg CPG_MOD 724>,
 100                  <&osc1_clk>;
 101         clock-names = "du.0", "dclkin.0";
 102         status = "okay";
 103 };
 104
 105 &extal_clk {
 106         clock-frequency = <16666666>;
 107 };
 108
 109 &extalr_clk {
 110         clock-frequency = <32768>;
 111 };
 112
 113 &gether {
 114         pinctrl-0 = <&gether_pins>;
 115         pinctrl-names = "default";
 116
 117         phy-mode = "rgmii";
 118         phy-handle = <&phy0>;
 119         renesas,no-ether-link;
 120         status = "okay";
 121
 122         phy0: ethernet-phy@0 {
 123                 compatible = "ethernet-phy-id0022.1622",
 124                              "ethernet-phy-ieee802.3-c22";
 125                 reg = <0>;
 126                 interrupt-parent = <&gpio4>;
 127                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 128                 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 129         };
 130 };
 131
 132 &i2c0 {
 133         pinctrl-0 = <&i2c0_pins>;
 134         pinctrl-names = "default";
 135
 136         status = "okay";
 137         clock-frequency = <400000>;
 138
 139         hdmi@39 {
 140                 compatible = "adi,adv7511w";
 141                 #sound-dai-cells = <0>;
 142                 reg = <0x39>;
 143                 interrupt-parent = <&gpio1>;
 144                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 145                 avdd-supply = <&vcc1v8_d4>;
 146                 dvdd-supply = <&vcc1v8_d4>;
 147                 pvdd-supply = <&vcc1v8_d4>;
 148                 bgvdd-supply = <&vcc1v8_d4>;
 149                 dvdd-3v-supply = <&vcc3v3_d5>;
 150
 151                 adi,input-depth = <8>;
 152                 adi,input-colorspace = "rgb";
 153                 adi,input-clock = "1x";
 154
 155                 ports {
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158
 159                         port@0 {
 160                                 reg = <0>;
 161                                 adv7511_in: endpoint {
 162                                         remote-endpoint = <&thc63lvd1024_out>;
 163                                 };
 164                         };
 165
 166                         port@1 {
 167                                 reg = <1>;
 168                                 adv7511_out: endpoint {
 169                                         remote-endpoint = <&hdmi_con>;
 170                                 };
 171                         };
 172                 };
 173         };
 174 };
 175
 176 &lvds0 {
 177         status = "okay";
 178
 179         ports {
 180                 port@1 {
 181                         lvds0_out: endpoint {
 182                                 remote-endpoint = <&thc63lvd1024_in>;
 183                         };
 184                 };
 185         };
 186 };
 187
 188 &pfc {
 189         gether_pins: gether {
 190                 groups = "gether_mdio_a", "gether_rgmii",
 191                          "gether_txcrefclk", "gether_txcrefclk_mega";
 192                 function = "gether";
 193         };
 194
 195         i2c0_pins: i2c0 {
 196                 groups = "i2c0";
 197                 function = "i2c0";
 198         };
 199
 200         qspi0_pins: qspi0 {
 201                 groups = "qspi0_ctrl", "qspi0_data4";
 202                 function = "qspi0";
 203         };
 204
 205         scif0_pins: scif0 {
 206                 groups = "scif0_data";
 207                 function = "scif0";
 208         };
 209
 210         scif_clk_pins: scif_clk {
 211                 groups = "scif_clk_b";
 212                 function = "scif_clk";
 213         };
 214 };
 215
 216 &rpc {
 217         pinctrl-0 = <&qspi0_pins>;
 218         pinctrl-names = "default";
 219
 220         status = "okay";
 221
 222         flash@0 {
 223                 compatible = "spansion,s25fs512s", "jedec,spi-nor";
 224                 reg = <0>;
 225                 spi-max-frequency = <50000000>;
 226                 spi-rx-bus-width = <4>;
 227
 228                 partitions {
 229                         compatible = "fixed-partitions";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232
 233                         bootparam@0 {
 234                                 reg = <0x00000000 0x040000>;
 235                                 read-only;
 236                         };
 237                         cr7@40000 {
 238                                 reg = <0x00040000 0x080000>;
 239                                 read-only;
 240                         };
 241                         cert_header_sa3@c0000 {
 242                                 reg = <0x000c0000 0x080000>;
 243                                 read-only;
 244                         };
 245                         bl2@140000 {
 246                                 reg = <0x00140000 0x040000>;
 247                                 read-only;
 248                         };
 249                         cert_header_sa6@180000 {
 250                                 reg = <0x00180000 0x040000>;
 251                                 read-only;
 252                         };
 253                         bl31@1c0000 {
 254                                 reg = <0x001c0000 0x460000>;
 255                                 read-only;
 256                         };
 257                         uboot@640000 {
 258                                 reg = <0x00640000 0x0c0000>;
 259                                 read-only;
 260                         };
 261                         uboot-env@700000 {
 262                                 reg = <0x00700000 0x040000>;
 263                                 read-only;
 264                         };
 265                         dtb@740000 {
 266                                 reg = <0x00740000 0x080000>;
 267                         };
 268                         kernel@7c0000 {
 269                                 reg = <0x007c0000 0x1400000>;
 270                         };
 271                         user@1bc0000 {
 272                                 reg = <0x01bc0000 0x2440000>;
 273                         };
 274                 };
 275         };
 276 };
 277
 278 &rwdt {
 279         timeout-sec = <60>;
 280         status = "okay";
 281 };
 282
 283 &scif0 {
 284         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
 285         pinctrl-names = "default";
 286
 287         status = "okay";
 288 };
 289
 290 &scif_clk {
 291         clock-frequency = <14745600>;
 292 };