1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the V3H Starter Kit board
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
10 #include "r8a77980.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Renesas V3H Starter Kit board";
15 compatible = "renesas,v3hsk", "renesas,r8a77980";
29 stdout-path = "serial0:115200n8";
33 compatible = "hdmi-connector";
38 remote-endpoint = <&adv7511_out>;
44 compatible = "thine,thc63lvd1024";
45 vcc-supply = <&vcc3v3_d5>;
53 thc63lvd1024_in: endpoint {
54 remote-endpoint = <&lvds0_out>;
60 thc63lvd1024_out: endpoint {
61 remote-endpoint = <&adv7511_in>;
68 device_type = "memory";
69 /* first 128MB is reserved for secure area. */
70 reg = <0 0x48000000 0 0x78000000>;
73 osc1_clk: osc1-clock {
74 compatible = "fixed-clock";
76 clock-frequency = <148500000>;
79 vcc1v8_d4: regulator-0 {
80 compatible = "regulator-fixed";
81 regulator-name = "VCC1V8_D4";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
88 vcc3v3_d5: regulator-1 {
89 compatible = "regulator-fixed";
90 regulator-name = "VCC3V3_D5";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
99 clocks = <&cpg CPG_MOD 724>,
101 clock-names = "du.0", "dclkin.0";
106 clock-frequency = <16666666>;
110 clock-frequency = <32768>;
114 pinctrl-0 = <&gether_pins>;
115 pinctrl-names = "default";
118 phy-handle = <&phy0>;
119 renesas,no-ether-link;
122 phy0: ethernet-phy@0 {
123 compatible = "ethernet-phy-id0022.1622",
124 "ethernet-phy-ieee802.3-c22";
125 rxc-skew-ps = <1500>;
127 interrupt-parent = <&gpio4>;
128 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
129 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
134 pinctrl-0 = <&i2c0_pins>;
135 pinctrl-names = "default";
138 clock-frequency = <400000>;
141 compatible = "adi,adv7511w";
142 #sound-dai-cells = <0>;
144 interrupt-parent = <&gpio1>;
145 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
146 avdd-supply = <&vcc1v8_d4>;
147 dvdd-supply = <&vcc1v8_d4>;
148 pvdd-supply = <&vcc1v8_d4>;
149 bgvdd-supply = <&vcc1v8_d4>;
150 dvdd-3v-supply = <&vcc3v3_d5>;
152 adi,input-depth = <8>;
153 adi,input-colorspace = "rgb";
154 adi,input-clock = "1x";
157 #address-cells = <1>;
162 adv7511_in: endpoint {
163 remote-endpoint = <&thc63lvd1024_out>;
169 adv7511_out: endpoint {
170 remote-endpoint = <&hdmi_con>;
182 lvds0_out: endpoint {
183 remote-endpoint = <&thc63lvd1024_in>;
190 gether_pins: gether {
191 groups = "gether_mdio_a", "gether_rgmii",
192 "gether_txcrefclk", "gether_txcrefclk_mega";
202 groups = "qspi0_ctrl", "qspi0_data4";
207 groups = "scif0_data";
211 scif_clk_pins: scif_clk {
212 groups = "scif_clk_b";
213 function = "scif_clk";
218 pinctrl-0 = <&qspi0_pins>;
219 pinctrl-names = "default";
224 compatible = "spansion,s25fs512s", "jedec,spi-nor";
226 spi-max-frequency = <50000000>;
227 spi-rx-bus-width = <4>;
230 compatible = "fixed-partitions";
231 #address-cells = <1>;
235 reg = <0x00000000 0x040000>;
239 reg = <0x00040000 0x080000>;
242 cert_header_sa3@c0000 {
243 reg = <0x000c0000 0x080000>;
247 reg = <0x00140000 0x040000>;
250 cert_header_sa6@180000 {
251 reg = <0x00180000 0x040000>;
255 reg = <0x001c0000 0x460000>;
259 reg = <0x00640000 0x0c0000>;
263 reg = <0x00700000 0x040000>;
267 reg = <0x00740000 0x080000>;
270 reg = <0x007c0000 0x1400000>;
273 reg = <0x01bc0000 0x2440000>;
285 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
286 pinctrl-names = "default";
292 clock-frequency = <14745600>;