2 * Device Tree Source for the r8a7796 SoC
4 * Copyright (C) 2016 Renesas Electronics Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a7796-sysc.h>
16 compatible = "renesas,r8a7796";
21 compatible = "arm,psci-0.2";
29 /* 1 core only at this point */
31 compatible = "arm,cortex-a57", "arm,armv8";
34 power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
35 next-level-cache = <&L2_CA57>;
36 enable-method = "psci";
39 L2_CA57: cache-controller-0 {
41 power-domains = <&sysc R8A7796_PD_CA57_SCU>;
48 compatible = "fixed-clock";
50 /* This value must be overridden by the board */
51 clock-frequency = <0>;
55 compatible = "fixed-clock";
57 /* This value must be overridden by the board */
58 clock-frequency = <0>;
61 /* External SCIF clock - to be overridden by boards that provide it */
63 compatible = "fixed-clock";
65 clock-frequency = <0>;
69 compatible = "simple-bus";
70 interrupt-parent = <&gic>;
75 gic: interrupt-controller@f1010000 {
76 compatible = "arm,gic-400";
77 #interrupt-cells = <3>;
80 reg = <0x0 0xf1010000 0 0x1000>,
81 <0x0 0xf1020000 0 0x20000>,
82 <0x0 0xf1040000 0 0x20000>,
83 <0x0 0xf1060000 0 0x20000>;
84 interrupts = <GIC_PPI 9
85 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
89 compatible = "arm,armv8-timer";
90 interrupts = <GIC_PPI 13
91 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
93 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
95 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
97 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
100 wdt0: watchdog@e6020000 {
101 compatible = "renesas,r8a7796-wdt",
102 "renesas,rcar-gen3-wdt";
103 reg = <0 0xe6020000 0 0x0c>;
104 clocks = <&cpg CPG_MOD 402>;
105 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
109 gpio0: gpio@e6050000 {
110 compatible = "renesas,gpio-r8a7796",
112 reg = <0 0xe6050000 0 0x50>;
113 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
116 gpio-ranges = <&pfc 0 0 16>;
117 #interrupt-cells = <2>;
118 interrupt-controller;
119 clocks = <&cpg CPG_MOD 912>;
120 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
123 gpio1: gpio@e6051000 {
124 compatible = "renesas,gpio-r8a7796",
126 reg = <0 0xe6051000 0 0x50>;
127 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
130 gpio-ranges = <&pfc 0 32 29>;
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 clocks = <&cpg CPG_MOD 911>;
134 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
137 gpio2: gpio@e6052000 {
138 compatible = "renesas,gpio-r8a7796",
140 reg = <0 0xe6052000 0 0x50>;
141 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
144 gpio-ranges = <&pfc 0 64 15>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
147 clocks = <&cpg CPG_MOD 910>;
148 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
151 gpio3: gpio@e6053000 {
152 compatible = "renesas,gpio-r8a7796",
154 reg = <0 0xe6053000 0 0x50>;
155 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
158 gpio-ranges = <&pfc 0 96 16>;
159 #interrupt-cells = <2>;
160 interrupt-controller;
161 clocks = <&cpg CPG_MOD 909>;
162 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
165 gpio4: gpio@e6054000 {
166 compatible = "renesas,gpio-r8a7796",
168 reg = <0 0xe6054000 0 0x50>;
169 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
172 gpio-ranges = <&pfc 0 128 18>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
175 clocks = <&cpg CPG_MOD 908>;
176 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
179 gpio5: gpio@e6055000 {
180 compatible = "renesas,gpio-r8a7796",
182 reg = <0 0xe6055000 0 0x50>;
183 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
186 gpio-ranges = <&pfc 0 160 26>;
187 #interrupt-cells = <2>;
188 interrupt-controller;
189 clocks = <&cpg CPG_MOD 907>;
190 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
193 gpio6: gpio@e6055400 {
194 compatible = "renesas,gpio-r8a7796",
196 reg = <0 0xe6055400 0 0x50>;
197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
200 gpio-ranges = <&pfc 0 192 32>;
201 #interrupt-cells = <2>;
202 interrupt-controller;
203 clocks = <&cpg CPG_MOD 906>;
204 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
207 gpio7: gpio@e6055800 {
208 compatible = "renesas,gpio-r8a7796",
210 reg = <0 0xe6055800 0 0x50>;
211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
214 gpio-ranges = <&pfc 0 224 4>;
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 clocks = <&cpg CPG_MOD 905>;
218 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
221 pfc: pin-controller@e6060000 {
222 compatible = "renesas,pfc-r8a7796";
223 reg = <0 0xe6060000 0 0x50c>;
226 cpg: clock-controller@e6150000 {
227 compatible = "renesas,r8a7796-cpg-mssr";
228 reg = <0 0xe6150000 0 0x1000>;
229 clocks = <&extal_clk>, <&extalr_clk>;
230 clock-names = "extal", "extalr";
232 #power-domain-cells = <0>;
235 sysc: system-controller@e6180000 {
236 compatible = "renesas,r8a7796-sysc";
237 reg = <0 0xe6180000 0 0x0400>;
238 #power-domain-cells = <1>;
241 scif2: serial@e6e88000 {
242 compatible = "renesas,scif-r8a7796",
243 "renesas,rcar-gen3-scif", "renesas,scif";
244 reg = <0 0xe6e88000 0 64>;
245 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&cpg CPG_MOD 310>,
247 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
249 clock-names = "fck", "brg_int", "scif_clk";
250 power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;