2 * Device Tree Source for the H3ULCB board
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2016 Cogent Embedded, Inc.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
13 #include "r8a7795.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
18 model = "Renesas H3ULCB board based on r8a7795";
19 compatible = "renesas,h3ulcb", "renesas,r8a7795";
27 stdout-path = "serial0:115200n8";
31 device_type = "memory";
32 /* first 128MB is reserved for secure area. */
33 reg = <0x0 0x48000000 0x0 0x38000000>;
37 compatible = "gpio-leds";
40 gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
43 gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
48 compatible = "gpio-keys";
54 debounce-interval = <20>;
55 gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
60 compatible = "fixed-clock";
62 clock-frequency = <24576000>;
65 vcc_sdhi0: regulator-vcc-sdhi0 {
66 compatible = "regulator-fixed";
68 regulator-name = "SDHI0 Vcc";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
72 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
76 vccq_sdhi0: regulator-vccq-sdhi0 {
77 compatible = "regulator-gpio";
79 regulator-name = "SDHI0 VccQ";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <3300000>;
83 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
89 audio_clkout: audio-clkout {
91 * This is same as <&rcar_sound 0>
92 * but needed to avoid cs2000/rcar_sound probe dead-lock
94 compatible = "fixed-clock";
96 clock-frequency = <11289600>;
100 compatible = "simple-audio-card";
102 simple-audio-card,format = "left_j";
103 simple-audio-card,bitclock-master = <&sndcpu>;
104 simple-audio-card,frame-master = <&sndcpu>;
106 sndcpu: simple-audio-card,cpu {
107 sound-dai = <&rcar_sound>;
110 sndcodec: simple-audio-card,codec {
111 sound-dai = <&ak4613>;
117 clock-frequency = <16666666>;
121 clock-frequency = <32768>;
125 pinctrl-0 = <&scif_clk_pins>;
126 pinctrl-names = "default";
129 groups = "scif2_data_a";
133 scif_clk_pins: scif_clk {
134 groups = "scif_clk_a";
135 function = "scif_clk";
148 sdhi0_pins_3v3: sd0_3v3 {
149 groups = "sdhi0_data4", "sdhi0_ctrl";
151 power-source = <3300>;
154 sdhi0_pins_1v8: sd0_1v8 {
155 groups = "sdhi0_data4", "sdhi0_ctrl";
157 power-source = <1800>;
161 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
165 sound_clk_pins: sound-clk {
166 groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
167 "audio_clkout_a", "audio_clkout3_a";
168 function = "audio_clk";
178 pinctrl-0 = <&scif2_pins>;
179 pinctrl-names = "default";
185 clock-frequency = <14745600>;
190 pinctrl-0 = <&i2c2_pins>;
191 pinctrl-names = "default";
195 clock-frequency = <100000>;
198 compatible = "asahi-kasei,ak4613";
199 #sound-dai-cells = <0>;
201 clocks = <&rcar_sound 3>;
203 asahi-kasei,in1-single-end;
204 asahi-kasei,in2-single-end;
205 asahi-kasei,out1-single-end;
206 asahi-kasei,out2-single-end;
207 asahi-kasei,out3-single-end;
208 asahi-kasei,out4-single-end;
209 asahi-kasei,out5-single-end;
210 asahi-kasei,out6-single-end;
213 cs2000: clk-multiplier@4f {
215 compatible = "cirrus,cs2000-cp";
217 clocks = <&audio_clkout>, <&x12_clk>;
218 clock-names = "clk_in", "ref_clk";
220 assigned-clocks = <&cs2000>;
221 assigned-clock-rates = <24576000>; /* 1/1 divide */
226 pinctrl-0 = <&sound_pins &sound_clk_pins>;
227 pinctrl-names = "default";
230 #sound-dai-cells = <0>;
232 /* audio_clkout0/1/2/3 */
234 clock-frequency = <11289600>;
238 /* update <audio_clk_b> to <cs2000> */
239 clocks = <&cpg CPG_MOD 1005>,
240 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
241 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
242 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
243 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
244 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
245 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
246 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
247 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
248 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
249 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
250 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
251 <&audio_clk_a>, <&cs2000>,
253 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
257 playback = <&ssi0 &src0 &dvc0>;
258 capture = <&ssi1 &src1 &dvc1>;
264 pinctrl-0 = <&sdhi0_pins_3v3>;
265 pinctrl-1 = <&sdhi0_pins_1v8>;
266 pinctrl-names = "default", "state_uhs";
268 vmmc-supply = <&vcc_sdhi0>;
269 vqmmc-supply = <&vccq_sdhi0>;
270 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
286 clock-frequency = <22579200>;
290 pinctrl-0 = <&avb_pins>;
291 pinctrl-names = "default";
292 renesas,no-ether-link;
293 phy-handle = <&phy0>;
296 phy0: ethernet-phy@0 {
310 interrupt-parent = <&gpio2>;
311 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
316 pinctrl-0 = <&usb1_pins>;
317 pinctrl-names = "default";