arch/arm64/boot/dts/renesas/condor-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the Condor board with R-Car V3H
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 serial0 = &scif0;
  19                 ethernet0 = &gether;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
  25         };
  26
  27         d1_8v: regulator-2 {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "D1.8V";
  30                 regulator-min-microvolt = <1800000>;
  31                 regulator-max-microvolt = <1800000>;
  32                 regulator-boot-on;
  33                 regulator-always-on;
  34         };
  35
  36         d3_3v: regulator-0 {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "D3.3V";
  39                 regulator-min-microvolt = <3300000>;
  40                 regulator-max-microvolt = <3300000>;
  41                 regulator-boot-on;
  42                 regulator-always-on;
  43         };
  44
  45         hdmi-out {
  46                 compatible = "hdmi-connector";
  47                 type = "a";
  48
  49                 port {
  50                         hdmi_con: endpoint {
  51                                 remote-endpoint = <&adv7511_out>;
  52                         };
  53                 };
  54         };
  55
  56         lvds-decoder {
  57                 compatible = "thine,thc63lvd1024";
  58                 vcc-supply = <&d3_3v>;
  59
  60                 ports {
  61                         #address-cells = <1>;
  62                         #size-cells = <0>;
  63
  64                         port@0 {
  65                                 reg = <0>;
  66                                 thc63lvd1024_in: endpoint {
  67                                         remote-endpoint = <&lvds0_out>;
  68                                 };
  69                         };
  70
  71                         port@2 {
  72                                 reg = <2>;
  73                                 thc63lvd1024_out: endpoint {
  74                                         remote-endpoint = <&adv7511_in>;
  75                                 };
  76                         };
  77                 };
  78         };
  79
  80         memory@48000000 {
  81                 device_type = "memory";
  82                 /* first 128MB is reserved for secure area. */
  83                 reg = <0 0x48000000 0 0x78000000>;
  84         };
  85
  86         vddq_vin01: regulator-1 {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "VDDQ_VIN01";
  89                 regulator-min-microvolt = <1800000>;
  90                 regulator-max-microvolt = <1800000>;
  91                 regulator-boot-on;
  92                 regulator-always-on;
  93         };
  94
  95         x1_clk: x1-clock {
  96                 compatible = "fixed-clock";
  97                 #clock-cells = <0>;
  98                 clock-frequency = <148500000>;
  99         };
 100 };
 101
 102 &canfd {
 103         pinctrl-0 = <&canfd0_pins>;
 104         pinctrl-names = "default";
 105         status = "okay";
 106
 107         channel0 {
 108                 status = "okay";
 109         };
 110 };
 111
 112 &csi40 {
 113         status = "okay";
 114
 115         ports {
 116                 port@0 {
 117                         csi40_in: endpoint {
 118                                 clock-lanes = <0>;
 119                                 data-lanes = <1 2 3 4>;
 120                                 remote-endpoint = <&max9286_out0>;
 121                         };
 122                 };
 123         };
 124 };
 125
 126 &csi41 {
 127         status = "okay";
 128
 129         ports {
 130                 port@0 {
 131                         csi41_in: endpoint {
 132                                 clock-lanes = <0>;
 133                                 data-lanes = <1 2 3 4>;
 134                                 remote-endpoint = <&max9286_out1>;
 135                         };
 136                 };
 137         };
 138 };
 139
 140 &du {
 141         clocks = <&cpg CPG_MOD 724>,
 142                  <&x1_clk>;
 143         clock-names = "du.0", "dclkin.0";
 144         status = "okay";
 145 };
 146
 147 &extal_clk {
 148         clock-frequency = <16666666>;
 149 };
 150
 151 &extalr_clk {
 152         clock-frequency = <32768>;
 153 };
 154
 155 &gether {
 156         pinctrl-0 = <&gether_pins>;
 157         pinctrl-names = "default";
 158
 159         phy-mode = "rgmii-id";
 160         phy-handle = <&phy0>;
 161         renesas,no-ether-link;
 162         status = "okay";
 163
 164         phy0: ethernet-phy@0 {
 165                 compatible = "ethernet-phy-id0022.1622",
 166                              "ethernet-phy-ieee802.3-c22";
 167                 rxc-skew-ps = <1500>;
 168                 reg = <0>;
 169                 interrupt-parent = <&gpio4>;
 170                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
 171                 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 172         };
 173 };
 174
 175 &i2c0 {
 176         pinctrl-0 = <&i2c0_pins>;
 177         pinctrl-names = "default";
 178
 179         status = "okay";
 180         clock-frequency = <400000>;
 181
 182         io_expander0: gpio@20 {
 183                 compatible = "onnn,pca9654";
 184                 reg = <0x20>;
 185                 gpio-controller;
 186                 #gpio-cells = <2>;
 187         };
 188
 189         io_expander1: gpio@21 {
 190                 compatible = "onnn,pca9654";
 191                 reg = <0x21>;
 192                 gpio-controller;
 193                 #gpio-cells = <2>;
 194         };
 195
 196         hdmi@39 {
 197                 compatible = "adi,adv7511w";
 198                 reg = <0x39>;
 199                 interrupt-parent = <&gpio1>;
 200                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
 201                 avdd-supply = <&d1_8v>;
 202                 dvdd-supply = <&d1_8v>;
 203                 pvdd-supply = <&d1_8v>;
 204                 bgvdd-supply = <&d1_8v>;
 205                 dvdd-3v-supply = <&d3_3v>;
 206
 207                 adi,input-depth = <8>;
 208                 adi,input-colorspace = "rgb";
 209                 adi,input-clock = "1x";
 210
 211                 ports {
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214
 215                         port@0 {
 216                                 reg = <0>;
 217                                 adv7511_in: endpoint {
 218                                         remote-endpoint = <&thc63lvd1024_out>;
 219                                 };
 220                         };
 221
 222                         port@1 {
 223                                 reg = <1>;
 224                                 adv7511_out: endpoint {
 225                                         remote-endpoint = <&hdmi_con>;
 226                                 };
 227                         };
 228                 };
 229         };
 230 };
 231
 232 &i2c1 {
 233         pinctrl-0 = <&i2c1_pins>;
 234         pinctrl-names = "default";
 235
 236         status = "okay";
 237         clock-frequency = <400000>;
 238
 239         gmsl0: gmsl-deserializer@48 {
 240                 compatible = "maxim,max9286";
 241                 reg = <0x48>;
 242
 243                 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
 244                 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
 245
 246                 ports {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249
 250                         port@0 {
 251                                 reg = <0>;
 252                         };
 253
 254                         port@1 {
 255                                 reg = <1>;
 256                         };
 257
 258                         port@2 {
 259                                 reg = <2>;
 260                         };
 261
 262                         port@3 {
 263                                 reg = <3>;
 264                         };
 265
 266                         port@4 {
 267                                 reg = <4>;
 268                                 max9286_out0: endpoint {
 269                                         clock-lanes = <0>;
 270                                         data-lanes = <1 2 3 4>;
 271                                         remote-endpoint = <&csi40_in>;
 272                                 };
 273                         };
 274                 };
 275
 276                 i2c-mux {
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279
 280                         i2c@0 {
 281                                 #address-cells = <1>;
 282                                 #size-cells = <0>;
 283                                 reg = <0>;
 284
 285                                 status = "disabled";
 286                         };
 287
 288                         i2c@1 {
 289                                 #address-cells = <1>;
 290                                 #size-cells = <0>;
 291                                 reg = <1>;
 292
 293                                 status = "disabled";
 294                         };
 295
 296                         i2c@2 {
 297                                 #address-cells = <1>;
 298                                 #size-cells = <0>;
 299                                 reg = <2>;
 300
 301                                 status = "disabled";
 302                         };
 303
 304                         i2c@3 {
 305                                 #address-cells = <1>;
 306                                 #size-cells = <0>;
 307                                 reg = <3>;
 308
 309                                 status = "disabled";
 310                         };
 311                 };
 312         };
 313
 314         gmsl1: gmsl-deserializer@4a {
 315                 compatible = "maxim,max9286";
 316                 reg = <0x4a>;
 317
 318                 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
 319                 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
 320
 321                 ports {
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324
 325                         port@0 {
 326                                 reg = <0>;
 327                         };
 328
 329                         port@1 {
 330                                 reg = <1>;
 331                         };
 332
 333                         port@2 {
 334                                 reg = <2>;
 335                         };
 336
 337                         port@3 {
 338                                 reg = <3>;
 339                         };
 340
 341                         port@4 {
 342                                 reg = <4>;
 343                                 max9286_out1: endpoint {
 344                                         clock-lanes = <0>;
 345                                         data-lanes = <1 2 3 4>;
 346                                         remote-endpoint = <&csi41_in>;
 347                                 };
 348                         };
 349                 };
 350
 351                 i2c-mux {
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354
 355                         i2c@0 {
 356                                 #address-cells = <1>;
 357                                 #size-cells = <0>;
 358                                 reg = <0>;
 359
 360                                 status = "disabled";
 361                         };
 362
 363                         i2c@1 {
 364                                 #address-cells = <1>;
 365                                 #size-cells = <0>;
 366                                 reg = <1>;
 367
 368                                 status = "disabled";
 369                         };
 370
 371                         i2c@2 {
 372                                 #address-cells = <1>;
 373                                 #size-cells = <0>;
 374                                 reg = <2>;
 375
 376                                 status = "disabled";
 377                         };
 378
 379                         i2c@3 {
 380                                 #address-cells = <1>;
 381                                 #size-cells = <0>;
 382                                 reg = <3>;
 383
 384                                 status = "disabled";
 385                         };
 386                 };
 387         };
 388 };
 389
 390 &lvds0 {
 391         status = "okay";
 392
 393         ports {
 394                 port@1 {
 395                         lvds0_out: endpoint {
 396                                 remote-endpoint = <&thc63lvd1024_in>;
 397                         };
 398                 };
 399         };
 400 };
 401
 402 &mmc0 {
 403         pinctrl-0 = <&mmc_pins>;
 404         pinctrl-1 = <&mmc_pins>;
 405         pinctrl-names = "default", "state_uhs";
 406
 407         vmmc-supply = <&d3_3v>;
 408         vqmmc-supply = <&vddq_vin01>;
 409         mmc-hs200-1_8v;
 410         bus-width = <8>;
 411         no-sd;
 412         no-sdio;
 413         non-removable;
 414         status = "okay";
 415 };
 416
 417 &pciec {
 418         status = "okay";
 419 };
 420
 421 &pcie_bus_clk {
 422         clock-frequency = <100000000>;
 423 };
 424
 425 &pcie_phy {
 426         status = "okay";
 427 };
 428
 429 &pfc {
 430         canfd0_pins: canfd0 {
 431                 groups = "canfd0_data_a";
 432                 function = "canfd0";
 433         };
 434
 435         gether_pins: gether {
 436                 groups = "gether_mdio_a", "gether_rgmii",
 437                          "gether_txcrefclk", "gether_txcrefclk_mega";
 438                 function = "gether";
 439         };
 440
 441         i2c0_pins: i2c0 {
 442                 groups = "i2c0";
 443                 function = "i2c0";
 444         };
 445
 446         i2c1_pins: i2c1 {
 447                 groups = "i2c1";
 448                 function = "i2c1";
 449         };
 450
 451         mmc_pins: mmc {
 452                 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
 453                 function = "mmc";
 454                 power-source = <1800>;
 455         };
 456
 457         qspi0_pins: qspi0 {
 458                 groups = "qspi0_ctrl", "qspi0_data4";
 459                 function = "qspi0";
 460         };
 461
 462         scif0_pins: scif0 {
 463                 groups = "scif0_data";
 464                 function = "scif0";
 465         };
 466
 467         scif_clk_pins: scif_clk {
 468                 groups = "scif_clk_b";
 469                 function = "scif_clk";
 470         };
 471 };
 472
 473 &rpc {
 474         pinctrl-0 = <&qspi0_pins>;
 475         pinctrl-names = "default";
 476
 477         status = "okay";
 478
 479         flash@0 {
 480                 compatible = "spansion,s25fs512s", "jedec,spi-nor";
 481                 reg = <0>;
 482                 spi-max-frequency = <50000000>;
 483                 spi-rx-bus-width = <4>;
 484
 485                 partitions {
 486                         compatible = "fixed-partitions";
 487                         #address-cells = <1>;
 488                         #size-cells = <1>;
 489
 490                         bootparam@0 {
 491                                 reg = <0x00000000 0x040000>;
 492                                 read-only;
 493                         };
 494                         cr7@40000 {
 495                                 reg = <0x00040000 0x080000>;
 496                                 read-only;
 497                         };
 498                         cert_header_sa3@c0000 {
 499                                 reg = <0x000c0000 0x080000>;
 500                                 read-only;
 501                         };
 502                         bl2@140000 {
 503                                 reg = <0x00140000 0x040000>;
 504                                 read-only;
 505                         };
 506                         cert_header_sa6@180000 {
 507                                 reg = <0x00180000 0x040000>;
 508                                 read-only;
 509                         };
 510                         bl31@1c0000 {
 511                                 reg = <0x001c0000 0x460000>;
 512                                 read-only;
 513                         };
 514                         uboot@640000 {
 515                                 reg = <0x00640000 0x0c0000>;
 516                                 read-only;
 517                         };
 518                         uboot-env@700000 {
 519                                 reg = <0x00700000 0x040000>;
 520                                 read-only;
 521                         };
 522                         dtb@740000 {
 523                                 reg = <0x00740000 0x080000>;
 524                         };
 525                         kernel@7c0000 {
 526                                 reg = <0x007c0000 0x1400000>;
 527                         };
 528                         user@1bc0000 {
 529                                 reg = <0x01bc0000 0x2440000>;
 530                         };
 531                 };
 532         };
 533 };
 534
 535 &rwdt {
 536         timeout-sec = <60>;
 537         status = "okay";
 538 };
 539
 540 &scif0 {
 541         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
 542         pinctrl-names = "default";
 543
 544         status = "okay";
 545 };
 546
 547 &scif_clk {
 548         clock-frequency = <14745600>;
 549 };