1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Condor board with R-Car V3H
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 * Copyright (C) 2018 Cogent Embedded, Inc.
8 #include <dt-bindings/gpio/gpio.h>
23 stdout-path = "serial0:115200n8";
24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
28 compatible = "regulator-fixed";
29 regulator-name = "D1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
37 compatible = "regulator-fixed";
38 regulator-name = "D3.3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
46 compatible = "hdmi-connector";
51 remote-endpoint = <&adv7511_out>;
57 compatible = "thine,thc63lvd1024";
58 vcc-supply = <&d3_3v>;
66 thc63lvd1024_in: endpoint {
67 remote-endpoint = <&lvds0_out>;
73 thc63lvd1024_out: endpoint {
74 remote-endpoint = <&adv7511_in>;
81 device_type = "memory";
82 /* first 128MB is reserved for secure area. */
83 reg = <0 0x48000000 0 0x78000000>;
86 vddq_vin01: regulator-1 {
87 compatible = "regulator-fixed";
88 regulator-name = "VDDQ_VIN01";
89 regulator-min-microvolt = <1800000>;
90 regulator-max-microvolt = <1800000>;
96 compatible = "fixed-clock";
98 clock-frequency = <148500000>;
103 pinctrl-0 = <&canfd0_pins>;
104 pinctrl-names = "default";
119 data-lanes = <1 2 3 4>;
120 remote-endpoint = <&max9286_out0>;
133 data-lanes = <1 2 3 4>;
134 remote-endpoint = <&max9286_out1>;
141 clocks = <&cpg CPG_MOD 724>,
143 clock-names = "du.0", "dclkin.0";
148 clock-frequency = <16666666>;
152 clock-frequency = <32768>;
156 pinctrl-0 = <&gether_pins>;
157 pinctrl-names = "default";
159 phy-mode = "rgmii-id";
160 phy-handle = <&phy0>;
161 renesas,no-ether-link;
164 phy0: ethernet-phy@0 {
165 compatible = "ethernet-phy-id0022.1622",
166 "ethernet-phy-ieee802.3-c22";
167 rxc-skew-ps = <1500>;
169 interrupt-parent = <&gpio4>;
170 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
171 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
176 pinctrl-0 = <&i2c0_pins>;
177 pinctrl-names = "default";
180 clock-frequency = <400000>;
182 io_expander0: gpio@20 {
183 compatible = "onnn,pca9654";
189 io_expander1: gpio@21 {
190 compatible = "onnn,pca9654";
197 compatible = "adi,adv7511w";
199 interrupt-parent = <&gpio1>;
200 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
201 avdd-supply = <&d1_8v>;
202 dvdd-supply = <&d1_8v>;
203 pvdd-supply = <&d1_8v>;
204 bgvdd-supply = <&d1_8v>;
205 dvdd-3v-supply = <&d3_3v>;
207 adi,input-depth = <8>;
208 adi,input-colorspace = "rgb";
209 adi,input-clock = "1x";
212 #address-cells = <1>;
217 adv7511_in: endpoint {
218 remote-endpoint = <&thc63lvd1024_out>;
224 adv7511_out: endpoint {
225 remote-endpoint = <&hdmi_con>;
233 pinctrl-0 = <&i2c1_pins>;
234 pinctrl-names = "default";
237 clock-frequency = <400000>;
239 gmsl0: gmsl-deserializer@48 {
240 compatible = "maxim,max9286";
243 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
244 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
247 #address-cells = <1>;
268 max9286_out0: endpoint {
270 data-lanes = <1 2 3 4>;
271 remote-endpoint = <&csi40_in>;
277 #address-cells = <1>;
281 #address-cells = <1>;
289 #address-cells = <1>;
297 #address-cells = <1>;
305 #address-cells = <1>;
314 gmsl1: gmsl-deserializer@4a {
315 compatible = "maxim,max9286";
318 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
319 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
322 #address-cells = <1>;
343 max9286_out1: endpoint {
345 data-lanes = <1 2 3 4>;
346 remote-endpoint = <&csi41_in>;
352 #address-cells = <1>;
356 #address-cells = <1>;
364 #address-cells = <1>;
372 #address-cells = <1>;
380 #address-cells = <1>;
395 lvds0_out: endpoint {
396 remote-endpoint = <&thc63lvd1024_in>;
403 pinctrl-0 = <&mmc_pins>;
404 pinctrl-1 = <&mmc_pins>;
405 pinctrl-names = "default", "state_uhs";
407 vmmc-supply = <&d3_3v>;
408 vqmmc-supply = <&vddq_vin01>;
422 clock-frequency = <100000000>;
430 canfd0_pins: canfd0 {
431 groups = "canfd0_data_a";
435 gether_pins: gether {
436 groups = "gether_mdio_a", "gether_rgmii",
437 "gether_txcrefclk", "gether_txcrefclk_mega";
452 groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
454 power-source = <1800>;
458 groups = "qspi0_ctrl", "qspi0_data4";
463 groups = "scif0_data";
467 scif_clk_pins: scif_clk {
468 groups = "scif_clk_b";
469 function = "scif_clk";
474 pinctrl-0 = <&qspi0_pins>;
475 pinctrl-names = "default";
480 compatible = "spansion,s25fs512s", "jedec,spi-nor";
482 spi-max-frequency = <50000000>;
483 spi-rx-bus-width = <4>;
486 compatible = "fixed-partitions";
487 #address-cells = <1>;
491 reg = <0x00000000 0x040000>;
495 reg = <0x00040000 0x080000>;
498 cert_header_sa3@c0000 {
499 reg = <0x000c0000 0x080000>;
503 reg = <0x00140000 0x040000>;
506 cert_header_sa6@180000 {
507 reg = <0x00180000 0x040000>;
511 reg = <0x001c0000 0x460000>;
515 reg = <0x00640000 0x0c0000>;
519 reg = <0x00700000 0x040000>;
523 reg = <0x00740000 0x080000>;
526 reg = <0x007c0000 0x1400000>;
529 reg = <0x01bc0000 0x2440000>;
541 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
542 pinctrl-names = "default";
548 clock-frequency = <14745600>;