1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Realtek RTD1395 SoC family
5 * Copyright (c) 2019 Andreas Färber
8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
25 reg = <0x2f000 0x1000>;
28 rpc_ringbuf: rpc@1ffe000 {
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
39 compatible = "arm,cortex-a53-pmu";
40 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
44 compatible = "fixed-clock";
45 clock-frequency = <27000000>;
47 clock-output-names = "osc27M";
51 compatible = "simple-bus";
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
58 compatible = "simple-bus";
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
65 compatible = "syscon", "simple-mfd";
70 ranges = <0x0 0x0 0x1000>;
74 compatible = "syscon", "simple-mfd";
75 reg = <0x7000 0x1000>;
79 ranges = <0x0 0x7000 0x1000>;
83 compatible = "syscon", "simple-mfd";
84 reg = <0x1a000 0x1000>;
88 ranges = <0x0 0x1a000 0x1000>;
92 compatible = "syscon", "simple-mfd";
93 reg = <0x1b000 0x1000>;
97 ranges = <0x0 0x1b000 0x1000>;
100 scpu_wrapper: syscon@1d000 {
101 compatible = "syscon", "simple-mfd";
102 reg = <0x1d000 0x2000>;
104 #address-cells = <1>;
106 ranges = <0x0 0x1d000 0x2000>;
110 gic: interrupt-controller@ff011000 {
111 compatible = "arm,gic-400";
112 reg = <0xff011000 0x1000>,
116 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
117 interrupt-controller;
118 #interrupt-cells = <3>;
124 reset1: reset-controller@0 {
125 compatible = "snps,dw-low-reset";
130 reset2: reset-controller@4 {
131 compatible = "snps,dw-low-reset";
136 reset3: reset-controller@8 {
137 compatible = "snps,dw-low-reset";
142 reset4: reset-controller@50 {
143 compatible = "snps,dw-low-reset";
150 iso_reset: reset-controller@88 {
151 compatible = "snps,dw-low-reset";
157 compatible = "realtek,rtd1295-watchdog";
163 compatible = "snps,dw-apb-uart";
167 clock-frequency = <27000000>;
168 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
175 compatible = "snps,dw-apb-uart";
179 clock-frequency = <432000000>;
180 resets = <&reset2 RTD1295_RSTN_UR1>;
185 compatible = "snps,dw-apb-uart";
189 clock-frequency = <432000000>;
190 resets = <&reset2 RTD1295_RSTN_UR2>;