arch/arm64/boot/dts/realtek/rtd1295.dtsi

   1 /*
   2  * Realtek RTD1295 SoC
   3  *
   4  * Copyright (c) 2016-2017 Andreas Färber
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         compatible = "realtek,rtd1295";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53", "arm,armv8";
  24                         reg = <0x0 0x0>;
  25                         next-level-cache = <&l2>;
  26                 };
  27
  28                 cpu1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         reg = <0x0 0x1>;
  32                         next-level-cache = <&l2>;
  33                 };
  34
  35                 cpu2: cpu@2 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53", "arm,armv8";
  38                         reg = <0x0 0x2>;
  39                         next-level-cache = <&l2>;
  40                 };
  41
  42                 cpu3: cpu@3 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <0x0 0x3>;
  46                         next-level-cache = <&l2>;
  47                 };
  48
  49                 l2: l2-cache {
  50                         compatible = "cache";
  51                 };
  52         };
  53
  54         reserved-memory {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 tee@10100000 {
  60                         reg = <0x10100000 0xf00000>;
  61                         no-map;
  62                 };
  63         };
  64
  65         arm-pmu {
  66                 compatible = "arm,cortex-a53-pmu";
  67                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  68                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  69         };
  70
  71         timer {
  72                 compatible = "arm,armv8-timer";
  73                 interrupts = <GIC_PPI 13
  74                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
  75                              <GIC_PPI 14
  76                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
  77                              <GIC_PPI 11
  78                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 10
  80                         (GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
  81         };
  82
  83         soc {
  84                 compatible = "simple-bus";
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87                 /* Exclude up to 2 GiB of RAM */
  88                 ranges = <0x80000000 0x80000000 0x80000000>;
  89
  90                 uart0: serial@98007800 {
  91                         compatible = "snps,dw-apb-uart";
  92                         reg = <0x98007800 0x400>,
  93                               <0x98007000 0x100>;
  94                         reg-shift = <2>;
  95                         reg-io-width = <4>;
  96                         clock-frequency = <27000000>;
  97                         status = "disabled";
  98                 };
  99
 100                 uart1: serial@9801b200 {
 101                         compatible = "snps,dw-apb-uart";
 102                         reg = <0x9801b200 0x100>,
 103                               <0x9801b00c 0x100>;
 104                         reg-shift = <2>;
 105                         reg-io-width = <4>;
 106                         clock-frequency = <432000000>;
 107                         status = "disabled";
 108                 };
 109
 110                 uart2: serial@9801b400 {
 111                         compatible = "snps,dw-apb-uart";
 112                         reg = <0x9801b400 0x100>,
 113                               <0x9801b00c 0x100>;
 114                         reg-shift = <2>;
 115                         reg-io-width = <4>;
 116                         clock-frequency = <432000000>;
 117                         status = "disabled";
 118                 };
 119
 120                 gic: interrupt-controller@ff011000 {
 121                         compatible = "arm,gic-400";
 122                         reg = <0xff011000 0x1000>,
 123                               <0xff012000 0x2000>,
 124                               <0xff014000 0x2000>,
 125                               <0xff016000 0x2000>;
 126                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 127                         interrupt-controller;
 128                         #interrupt-cells = <3>;
 129                 };
 130         };
 131 };