arch/arm64/boot/dts/qcom/sm8450.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
  10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
  11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
  12 #include <dt-bindings/dma/qcom-gpi.h>
  13 #include <dt-bindings/firmware/qcom,scm.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/mailbox/qcom-ipcc.h>
  16 #include <dt-bindings/phy/phy-qcom-qmp.h>
  17 #include <dt-bindings/power/qcom,rpmhpd.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/interconnect/qcom,icc.h>
  20 #include <dt-bindings/interconnect/qcom,sm8450.h>
  21 #include <dt-bindings/soc/qcom,gpr.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25
  26 / {
  27         interrupt-parent = <&intc>;
  28
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         chosen { };
  33
  34         clocks {
  35                 xo_board: xo-board {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <76800000>;
  39                 };
  40
  41                 sleep_clk: sleep-clk {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                         clock-frequency = <32000>;
  45                 };
  46         };
  47
  48         cpus {
  49                 #address-cells = <2>;
  50                 #size-cells = <0>;
  51
  52                 CPU0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "qcom,kryo780";
  55                         reg = <0x0 0x0>;
  56                         enable-method = "psci";
  57                         next-level-cache = <&L2_0>;
  58                         power-domains = <&CPU_PD0>;
  59                         power-domain-names = "psci";
  60                         qcom,freq-domain = <&cpufreq_hw 0>;
  61                         #cooling-cells = <2>;
  62                         clocks = <&cpufreq_hw 0>;
  63                         L2_0: l2-cache {
  64                                 compatible = "cache";
  65                                 cache-level = <2>;
  66                                 cache-unified;
  67                                 next-level-cache = <&L3_0>;
  68                                 L3_0: l3-cache {
  69                                         compatible = "cache";
  70                                         cache-level = <3>;
  71                                         cache-unified;
  72                                 };
  73                         };
  74                 };
  75
  76                 CPU1: cpu@100 {
  77                         device_type = "cpu";
  78                         compatible = "qcom,kryo780";
  79                         reg = <0x0 0x100>;
  80                         enable-method = "psci";
  81                         next-level-cache = <&L2_100>;
  82                         power-domains = <&CPU_PD1>;
  83                         power-domain-names = "psci";
  84                         qcom,freq-domain = <&cpufreq_hw 0>;
  85                         #cooling-cells = <2>;
  86                         clocks = <&cpufreq_hw 0>;
  87                         L2_100: l2-cache {
  88                                 compatible = "cache";
  89                                 cache-level = <2>;
  90                                 cache-unified;
  91                                 next-level-cache = <&L3_0>;
  92                         };
  93                 };
  94
  95                 CPU2: cpu@200 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo780";
  98                         reg = <0x0 0x200>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_200>;
 101                         power-domains = <&CPU_PD2>;
 102                         power-domain-names = "psci";
 103                         qcom,freq-domain = <&cpufreq_hw 0>;
 104                         #cooling-cells = <2>;
 105                         clocks = <&cpufreq_hw 0>;
 106                         L2_200: l2-cache {
 107                                 compatible = "cache";
 108                                 cache-level = <2>;
 109                                 cache-unified;
 110                                 next-level-cache = <&L3_0>;
 111                         };
 112                 };
 113
 114                 CPU3: cpu@300 {
 115                         device_type = "cpu";
 116                         compatible = "qcom,kryo780";
 117                         reg = <0x0 0x300>;
 118                         enable-method = "psci";
 119                         next-level-cache = <&L2_300>;
 120                         power-domains = <&CPU_PD3>;
 121                         power-domain-names = "psci";
 122                         qcom,freq-domain = <&cpufreq_hw 0>;
 123                         #cooling-cells = <2>;
 124                         clocks = <&cpufreq_hw 0>;
 125                         L2_300: l2-cache {
 126                                 compatible = "cache";
 127                                 cache-level = <2>;
 128                                 cache-unified;
 129                                 next-level-cache = <&L3_0>;
 130                         };
 131                 };
 132
 133                 CPU4: cpu@400 {
 134                         device_type = "cpu";
 135                         compatible = "qcom,kryo780";
 136                         reg = <0x0 0x400>;
 137                         enable-method = "psci";
 138                         next-level-cache = <&L2_400>;
 139                         power-domains = <&CPU_PD4>;
 140                         power-domain-names = "psci";
 141                         qcom,freq-domain = <&cpufreq_hw 1>;
 142                         #cooling-cells = <2>;
 143                         clocks = <&cpufreq_hw 1>;
 144                         L2_400: l2-cache {
 145                                 compatible = "cache";
 146                                 cache-level = <2>;
 147                                 cache-unified;
 148                                 next-level-cache = <&L3_0>;
 149                         };
 150                 };
 151
 152                 CPU5: cpu@500 {
 153                         device_type = "cpu";
 154                         compatible = "qcom,kryo780";
 155                         reg = <0x0 0x500>;
 156                         enable-method = "psci";
 157                         next-level-cache = <&L2_500>;
 158                         power-domains = <&CPU_PD5>;
 159                         power-domain-names = "psci";
 160                         qcom,freq-domain = <&cpufreq_hw 1>;
 161                         #cooling-cells = <2>;
 162                         clocks = <&cpufreq_hw 1>;
 163                         L2_500: l2-cache {
 164                                 compatible = "cache";
 165                                 cache-level = <2>;
 166                                 cache-unified;
 167                                 next-level-cache = <&L3_0>;
 168                         };
 169                 };
 170
 171                 CPU6: cpu@600 {
 172                         device_type = "cpu";
 173                         compatible = "qcom,kryo780";
 174                         reg = <0x0 0x600>;
 175                         enable-method = "psci";
 176                         next-level-cache = <&L2_600>;
 177                         power-domains = <&CPU_PD6>;
 178                         power-domain-names = "psci";
 179                         qcom,freq-domain = <&cpufreq_hw 1>;
 180                         #cooling-cells = <2>;
 181                         clocks = <&cpufreq_hw 1>;
 182                         L2_600: l2-cache {
 183                                 compatible = "cache";
 184                                 cache-level = <2>;
 185                                 cache-unified;
 186                                 next-level-cache = <&L3_0>;
 187                         };
 188                 };
 189
 190                 CPU7: cpu@700 {
 191                         device_type = "cpu";
 192                         compatible = "qcom,kryo780";
 193                         reg = <0x0 0x700>;
 194                         enable-method = "psci";
 195                         next-level-cache = <&L2_700>;
 196                         power-domains = <&CPU_PD7>;
 197                         power-domain-names = "psci";
 198                         qcom,freq-domain = <&cpufreq_hw 2>;
 199                         #cooling-cells = <2>;
 200                         clocks = <&cpufreq_hw 2>;
 201                         L2_700: l2-cache {
 202                                 compatible = "cache";
 203                                 cache-level = <2>;
 204                                 cache-unified;
 205                                 next-level-cache = <&L3_0>;
 206                         };
 207                 };
 208
 209                 cpu-map {
 210                         cluster0 {
 211                                 core0 {
 212                                         cpu = <&CPU0>;
 213                                 };
 214
 215                                 core1 {
 216                                         cpu = <&CPU1>;
 217                                 };
 218
 219                                 core2 {
 220                                         cpu = <&CPU2>;
 221                                 };
 222
 223                                 core3 {
 224                                         cpu = <&CPU3>;
 225                                 };
 226
 227                                 core4 {
 228                                         cpu = <&CPU4>;
 229                                 };
 230
 231                                 core5 {
 232                                         cpu = <&CPU5>;
 233                                 };
 234
 235                                 core6 {
 236                                         cpu = <&CPU6>;
 237                                 };
 238
 239                                 core7 {
 240                                         cpu = <&CPU7>;
 241                                 };
 242                         };
 243                 };
 244
 245                 idle-states {
 246                         entry-method = "psci";
 247
 248                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 249                                 compatible = "arm,idle-state";
 250                                 idle-state-name = "silver-rail-power-collapse";
 251                                 arm,psci-suspend-param = <0x40000004>;
 252                                 entry-latency-us = <800>;
 253                                 exit-latency-us = <750>;
 254                                 min-residency-us = <4090>;
 255                                 local-timer-stop;
 256                         };
 257
 258                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 259                                 compatible = "arm,idle-state";
 260                                 idle-state-name = "gold-rail-power-collapse";
 261                                 arm,psci-suspend-param = <0x40000004>;
 262                                 entry-latency-us = <600>;
 263                                 exit-latency-us = <1550>;
 264                                 min-residency-us = <4791>;
 265                                 local-timer-stop;
 266                         };
 267                 };
 268
 269                 domain-idle-states {
 270                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 271                                 compatible = "domain-idle-state";
 272                                 arm,psci-suspend-param = <0x41000044>;
 273                                 entry-latency-us = <1050>;
 274                                 exit-latency-us = <2500>;
 275                                 min-residency-us = <5309>;
 276                         };
 277
 278                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 279                                 compatible = "domain-idle-state";
 280                                 arm,psci-suspend-param = <0x4100c344>;
 281                                 entry-latency-us = <2700>;
 282                                 exit-latency-us = <3500>;
 283                                 min-residency-us = <13959>;
 284                         };
 285                 };
 286         };
 287
 288         firmware {
 289                 scm: scm {
 290                         compatible = "qcom,scm-sm8450", "qcom,scm";
 291                         qcom,dload-mode = <&tcsr 0x13000>;
 292                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 293                         #reset-cells = <1>;
 294                 };
 295         };
 296
 297         clk_virt: interconnect-0 {
 298                 compatible = "qcom,sm8450-clk-virt";
 299                 #interconnect-cells = <2>;
 300                 qcom,bcm-voters = <&apps_bcm_voter>;
 301         };
 302
 303         mc_virt: interconnect-1 {
 304                 compatible = "qcom,sm8450-mc-virt";
 305                 #interconnect-cells = <2>;
 306                 qcom,bcm-voters = <&apps_bcm_voter>;
 307         };
 308
 309         memory@a0000000 {
 310                 device_type = "memory";
 311                 /* We expect the bootloader to fill in the size */
 312                 reg = <0x0 0xa0000000 0x0 0x0>;
 313         };
 314
 315         pmu {
 316                 compatible = "arm,armv8-pmuv3";
 317                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 318         };
 319
 320         psci {
 321                 compatible = "arm,psci-1.0";
 322                 method = "smc";
 323
 324                 CPU_PD0: power-domain-cpu0 {
 325                         #power-domain-cells = <0>;
 326                         power-domains = <&CLUSTER_PD>;
 327                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 328                 };
 329
 330                 CPU_PD1: power-domain-cpu1 {
 331                         #power-domain-cells = <0>;
 332                         power-domains = <&CLUSTER_PD>;
 333                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 334                 };
 335
 336                 CPU_PD2: power-domain-cpu2 {
 337                         #power-domain-cells = <0>;
 338                         power-domains = <&CLUSTER_PD>;
 339                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 340                 };
 341
 342                 CPU_PD3: power-domain-cpu3 {
 343                         #power-domain-cells = <0>;
 344                         power-domains = <&CLUSTER_PD>;
 345                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 346                 };
 347
 348                 CPU_PD4: power-domain-cpu4 {
 349                         #power-domain-cells = <0>;
 350                         power-domains = <&CLUSTER_PD>;
 351                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 352                 };
 353
 354                 CPU_PD5: power-domain-cpu5 {
 355                         #power-domain-cells = <0>;
 356                         power-domains = <&CLUSTER_PD>;
 357                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 358                 };
 359
 360                 CPU_PD6: power-domain-cpu6 {
 361                         #power-domain-cells = <0>;
 362                         power-domains = <&CLUSTER_PD>;
 363                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 364                 };
 365
 366                 CPU_PD7: power-domain-cpu7 {
 367                         #power-domain-cells = <0>;
 368                         power-domains = <&CLUSTER_PD>;
 369                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 370                 };
 371
 372                 CLUSTER_PD: power-domain-cpu-cluster0 {
 373                         #power-domain-cells = <0>;
 374                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 375                 };
 376         };
 377
 378         qup_opp_table_100mhz: opp-table-qup {
 379                 compatible = "operating-points-v2";
 380
 381                 opp-50000000 {
 382                         opp-hz = /bits/ 64 <50000000>;
 383                         required-opps = <&rpmhpd_opp_min_svs>;
 384                 };
 385
 386                 opp-75000000 {
 387                         opp-hz = /bits/ 64 <75000000>;
 388                         required-opps = <&rpmhpd_opp_low_svs>;
 389                 };
 390
 391                 opp-100000000 {
 392                         opp-hz = /bits/ 64 <100000000>;
 393                         required-opps = <&rpmhpd_opp_svs>;
 394                 };
 395         };
 396
 397         reserved_memory: reserved-memory {
 398                 #address-cells = <2>;
 399                 #size-cells = <2>;
 400                 ranges;
 401
 402                 hyp_mem: memory@80000000 {
 403                         reg = <0x0 0x80000000 0x0 0x600000>;
 404                         no-map;
 405                 };
 406
 407                 xbl_dt_log_mem: memory@80600000 {
 408                         reg = <0x0 0x80600000 0x0 0x40000>;
 409                         no-map;
 410                 };
 411
 412                 xbl_ramdump_mem: memory@80640000 {
 413                         reg = <0x0 0x80640000 0x0 0x180000>;
 414                         no-map;
 415                 };
 416
 417                 xbl_sc_mem: memory@807c0000 {
 418                         reg = <0x0 0x807c0000 0x0 0x40000>;
 419                         no-map;
 420                 };
 421
 422                 aop_image_mem: memory@80800000 {
 423                         reg = <0x0 0x80800000 0x0 0x60000>;
 424                         no-map;
 425                 };
 426
 427                 aop_cmd_db_mem: memory@80860000 {
 428                         compatible = "qcom,cmd-db";
 429                         reg = <0x0 0x80860000 0x0 0x20000>;
 430                         no-map;
 431                 };
 432
 433                 aop_config_mem: memory@80880000 {
 434                         reg = <0x0 0x80880000 0x0 0x20000>;
 435                         no-map;
 436                 };
 437
 438                 tme_crash_dump_mem: memory@808a0000 {
 439                         reg = <0x0 0x808a0000 0x0 0x40000>;
 440                         no-map;
 441                 };
 442
 443                 tme_log_mem: memory@808e0000 {
 444                         reg = <0x0 0x808e0000 0x0 0x4000>;
 445                         no-map;
 446                 };
 447
 448                 uefi_log_mem: memory@808e4000 {
 449                         reg = <0x0 0x808e4000 0x0 0x10000>;
 450                         no-map;
 451                 };
 452
 453                 /* secdata region can be reused by apps */
 454                 smem: memory@80900000 {
 455                         compatible = "qcom,smem";
 456                         reg = <0x0 0x80900000 0x0 0x200000>;
 457                         hwlocks = <&tcsr_mutex 3>;
 458                         no-map;
 459                 };
 460
 461                 cpucp_fw_mem: memory@80b00000 {
 462                         reg = <0x0 0x80b00000 0x0 0x100000>;
 463                         no-map;
 464                 };
 465
 466                 cdsp_secure_heap: memory@80c00000 {
 467                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 468                         no-map;
 469                 };
 470
 471                 video_mem: memory@85700000 {
 472                         reg = <0x0 0x85700000 0x0 0x700000>;
 473                         no-map;
 474                 };
 475
 476                 adsp_mem: memory@85e00000 {
 477                         reg = <0x0 0x85e00000 0x0 0x2100000>;
 478                         no-map;
 479                 };
 480
 481                 slpi_mem: memory@88000000 {
 482                         reg = <0x0 0x88000000 0x0 0x1900000>;
 483                         no-map;
 484                 };
 485
 486                 cdsp_mem: memory@89900000 {
 487                         reg = <0x0 0x89900000 0x0 0x2000000>;
 488                         no-map;
 489                 };
 490
 491                 ipa_fw_mem: memory@8b900000 {
 492                         reg = <0x0 0x8b900000 0x0 0x10000>;
 493                         no-map;
 494                 };
 495
 496                 ipa_gsi_mem: memory@8b910000 {
 497                         reg = <0x0 0x8b910000 0x0 0xa000>;
 498                         no-map;
 499                 };
 500
 501                 gpu_micro_code_mem: memory@8b91a000 {
 502                         reg = <0x0 0x8b91a000 0x0 0x2000>;
 503                         no-map;
 504                 };
 505
 506                 spss_region_mem: memory@8ba00000 {
 507                         reg = <0x0 0x8ba00000 0x0 0x180000>;
 508                         no-map;
 509                 };
 510
 511                 /* First part of the "SPU secure shared memory" region */
 512                 spu_tz_shared_mem: memory@8bb80000 {
 513                         reg = <0x0 0x8bb80000 0x0 0x60000>;
 514                         no-map;
 515                 };
 516
 517                 /* Second part of the "SPU secure shared memory" region */
 518                 spu_modem_shared_mem: memory@8bbe0000 {
 519                         reg = <0x0 0x8bbe0000 0x0 0x20000>;
 520                         no-map;
 521                 };
 522
 523                 mpss_mem: memory@8bc00000 {
 524                         reg = <0x0 0x8bc00000 0x0 0x13200000>;
 525                         no-map;
 526                 };
 527
 528                 cvp_mem: memory@9ee00000 {
 529                         reg = <0x0 0x9ee00000 0x0 0x700000>;
 530                         no-map;
 531                 };
 532
 533                 camera_mem: memory@9f500000 {
 534                         reg = <0x0 0x9f500000 0x0 0x800000>;
 535                         no-map;
 536                 };
 537
 538                 rmtfs_mem: memory@9fd00000 {
 539                         compatible = "qcom,rmtfs-mem";
 540                         reg = <0x0 0x9fd00000 0x0 0x280000>;
 541                         no-map;
 542
 543                         qcom,client-id = <1>;
 544                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 545                 };
 546
 547                 xbl_sc_mem2: memory@a6e00000 {
 548                         reg = <0x0 0xa6e00000 0x0 0x40000>;
 549                         no-map;
 550                 };
 551
 552                 global_sync_mem: memory@a6f00000 {
 553                         reg = <0x0 0xa6f00000 0x0 0x100000>;
 554                         no-map;
 555                 };
 556
 557                 /* uefi region can be reused by APPS */
 558
 559                 /* Linux kernel image is loaded at 0xa0000000 */
 560
 561                 oem_vm_mem: memory@bb000000 {
 562                         reg = <0x0 0xbb000000 0x0 0x5000000>;
 563                         no-map;
 564                 };
 565
 566                 mte_mem: memory@c0000000 {
 567                         reg = <0x0 0xc0000000 0x0 0x20000000>;
 568                         no-map;
 569                 };
 570
 571                 qheebsp_reserved_mem: memory@e0000000 {
 572                         reg = <0x0 0xe0000000 0x0 0x600000>;
 573                         no-map;
 574                 };
 575
 576                 cpusys_vm_mem: memory@e0600000 {
 577                         reg = <0x0 0xe0600000 0x0 0x400000>;
 578                         no-map;
 579                 };
 580
 581                 hyp_reserved_mem: memory@e0a00000 {
 582                         reg = <0x0 0xe0a00000 0x0 0x100000>;
 583                         no-map;
 584                 };
 585
 586                 trust_ui_vm_mem: memory@e0b00000 {
 587                         reg = <0x0 0xe0b00000 0x0 0x4af3000>;
 588                         no-map;
 589                 };
 590
 591                 trust_ui_vm_qrtr: memory@e55f3000 {
 592                         reg = <0x0 0xe55f3000 0x0 0x9000>;
 593                         no-map;
 594                 };
 595
 596                 trust_ui_vm_vblk0_ring: memory@e55fc000 {
 597                         reg = <0x0 0xe55fc000 0x0 0x4000>;
 598                         no-map;
 599                 };
 600
 601                 trust_ui_vm_swiotlb: memory@e5600000 {
 602                         reg = <0x0 0xe5600000 0x0 0x100000>;
 603                         no-map;
 604                 };
 605
 606                 tz_stat_mem: memory@e8800000 {
 607                         reg = <0x0 0xe8800000 0x0 0x100000>;
 608                         no-map;
 609                 };
 610
 611                 tags_mem: memory@e8900000 {
 612                         reg = <0x0 0xe8900000 0x0 0x1200000>;
 613                         no-map;
 614                 };
 615
 616                 qtee_mem: memory@e9b00000 {
 617                         reg = <0x0 0xe9b00000 0x0 0x500000>;
 618                         no-map;
 619                 };
 620
 621                 trusted_apps_mem: memory@ea000000 {
 622                         reg = <0x0 0xea000000 0x0 0x3900000>;
 623                         no-map;
 624                 };
 625
 626                 trusted_apps_ext_mem: memory@ed900000 {
 627                         reg = <0x0 0xed900000 0x0 0x3b00000>;
 628                         no-map;
 629                 };
 630         };
 631
 632         smp2p-adsp {
 633                 compatible = "qcom,smp2p";
 634                 qcom,smem = <443>, <429>;
 635                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 636                                              IPCC_MPROC_SIGNAL_SMP2P
 637                                              IRQ_TYPE_EDGE_RISING>;
 638                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 639                                 IPCC_MPROC_SIGNAL_SMP2P>;
 640
 641                 qcom,local-pid = <0>;
 642                 qcom,remote-pid = <2>;
 643
 644                 smp2p_adsp_out: master-kernel {
 645                         qcom,entry-name = "master-kernel";
 646                         #qcom,smem-state-cells = <1>;
 647                 };
 648
 649                 smp2p_adsp_in: slave-kernel {
 650                         qcom,entry-name = "slave-kernel";
 651                         interrupt-controller;
 652                         #interrupt-cells = <2>;
 653                 };
 654         };
 655
 656         smp2p-cdsp {
 657                 compatible = "qcom,smp2p";
 658                 qcom,smem = <94>, <432>;
 659                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 660                                              IPCC_MPROC_SIGNAL_SMP2P
 661                                              IRQ_TYPE_EDGE_RISING>;
 662                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 663                                 IPCC_MPROC_SIGNAL_SMP2P>;
 664
 665                 qcom,local-pid = <0>;
 666                 qcom,remote-pid = <5>;
 667
 668                 smp2p_cdsp_out: master-kernel {
 669                         qcom,entry-name = "master-kernel";
 670                         #qcom,smem-state-cells = <1>;
 671                 };
 672
 673                 smp2p_cdsp_in: slave-kernel {
 674                         qcom,entry-name = "slave-kernel";
 675                         interrupt-controller;
 676                         #interrupt-cells = <2>;
 677                 };
 678         };
 679
 680         smp2p-modem {
 681                 compatible = "qcom,smp2p";
 682                 qcom,smem = <435>, <428>;
 683                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 684                                              IPCC_MPROC_SIGNAL_SMP2P
 685                                              IRQ_TYPE_EDGE_RISING>;
 686                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 687                                 IPCC_MPROC_SIGNAL_SMP2P>;
 688
 689                 qcom,local-pid = <0>;
 690                 qcom,remote-pid = <1>;
 691
 692                 smp2p_modem_out: master-kernel {
 693                         qcom,entry-name = "master-kernel";
 694                         #qcom,smem-state-cells = <1>;
 695                 };
 696
 697                 smp2p_modem_in: slave-kernel {
 698                         qcom,entry-name = "slave-kernel";
 699                         interrupt-controller;
 700                         #interrupt-cells = <2>;
 701                 };
 702
 703                 ipa_smp2p_out: ipa-ap-to-modem {
 704                         qcom,entry-name = "ipa";
 705                         #qcom,smem-state-cells = <1>;
 706                 };
 707
 708                 ipa_smp2p_in: ipa-modem-to-ap {
 709                         qcom,entry-name = "ipa";
 710                         interrupt-controller;
 711                         #interrupt-cells = <2>;
 712                 };
 713         };
 714
 715         smp2p-slpi {
 716                 compatible = "qcom,smp2p";
 717                 qcom,smem = <481>, <430>;
 718                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 719                                              IPCC_MPROC_SIGNAL_SMP2P
 720                                              IRQ_TYPE_EDGE_RISING>;
 721                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 722                                 IPCC_MPROC_SIGNAL_SMP2P>;
 723
 724                 qcom,local-pid = <0>;
 725                 qcom,remote-pid = <3>;
 726
 727                 smp2p_slpi_out: master-kernel {
 728                         qcom,entry-name = "master-kernel";
 729                         #qcom,smem-state-cells = <1>;
 730                 };
 731
 732                 smp2p_slpi_in: slave-kernel {
 733                         qcom,entry-name = "slave-kernel";
 734                         interrupt-controller;
 735                         #interrupt-cells = <2>;
 736                 };
 737         };
 738
 739         soc: soc@0 {
 740                 #address-cells = <2>;
 741                 #size-cells = <2>;
 742                 ranges = <0 0 0 0 0x10 0>;
 743                 dma-ranges = <0 0 0 0 0x10 0>;
 744                 compatible = "simple-bus";
 745
 746                 gcc: clock-controller@100000 {
 747                         compatible = "qcom,gcc-sm8450";
 748                         reg = <0x0 0x00100000 0x0 0x1f4200>;
 749                         #clock-cells = <1>;
 750                         #reset-cells = <1>;
 751                         #power-domain-cells = <1>;
 752                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 753                                  <&sleep_clk>,
 754                                  <&pcie0_phy>,
 755                                  <&pcie1_phy>,
 756                                  <0>,
 757                                  <&ufs_mem_phy_lanes 0>,
 758                                  <&ufs_mem_phy_lanes 1>,
 759                                  <&ufs_mem_phy_lanes 2>,
 760                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 761                         clock-names = "bi_tcxo",
 762                                       "sleep_clk",
 763                                       "pcie_0_pipe_clk",
 764                                       "pcie_1_pipe_clk",
 765                                       "pcie_1_phy_aux_clk",
 766                                       "ufs_phy_rx_symbol_0_clk",
 767                                       "ufs_phy_rx_symbol_1_clk",
 768                                       "ufs_phy_tx_symbol_0_clk",
 769                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 770                 };
 771
 772                 gpi_dma2: dma-controller@800000 {
 773                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
 774                         #dma-cells = <3>;
 775                         reg = <0 0x00800000 0 0x60000>;
 776                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 777                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 778                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 779                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 780                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 781                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 782                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 783                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 784                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 787                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 788                         dma-channels = <12>;
 789                         dma-channel-mask = <0x7e>;
 790                         iommus = <&apps_smmu 0x496 0x0>;
 791                         status = "disabled";
 792                 };
 793
 794                 qupv3_id_2: geniqup@8c0000 {
 795                         compatible = "qcom,geni-se-qup";
 796                         reg = <0x0 0x008c0000 0x0 0x2000>;
 797                         clock-names = "m-ahb", "s-ahb";
 798                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 799                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 800                         iommus = <&apps_smmu 0x483 0x0>;
 801                         #address-cells = <2>;
 802                         #size-cells = <2>;
 803                         ranges;
 804                         status = "disabled";
 805
 806                         i2c15: i2c@880000 {
 807                                 compatible = "qcom,geni-i2c";
 808                                 reg = <0x0 0x00880000 0x0 0x4000>;
 809                                 clock-names = "se";
 810                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 811                                 pinctrl-names = "default";
 812                                 pinctrl-0 = <&qup_i2c15_data_clk>;
 813                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 814                                 #address-cells = <1>;
 815                                 #size-cells = <0>;
 816                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 817                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 818                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 819                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 820                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 821                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 822                                 dma-names = "tx", "rx";
 823                                 status = "disabled";
 824                         };
 825
 826                         spi15: spi@880000 {
 827                                 compatible = "qcom,geni-spi";
 828                                 reg = <0x0 0x00880000 0x0 0x4000>;
 829                                 clock-names = "se";
 830                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 831                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 832                                 pinctrl-names = "default";
 833                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
 834                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 835                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 836                                 interconnect-names = "qup-core", "qup-config";
 837                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 838                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 839                                 dma-names = "tx", "rx";
 840                                 #address-cells = <1>;
 841                                 #size-cells = <0>;
 842                                 status = "disabled";
 843                         };
 844
 845                         i2c16: i2c@884000 {
 846                                 compatible = "qcom,geni-i2c";
 847                                 reg = <0x0 0x00884000 0x0 0x4000>;
 848                                 clock-names = "se";
 849                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 850                                 pinctrl-names = "default";
 851                                 pinctrl-0 = <&qup_i2c16_data_clk>;
 852                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 853                                 #address-cells = <1>;
 854                                 #size-cells = <0>;
 855                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 856                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 857                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 858                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 859                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 860                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 861                                 dma-names = "tx", "rx";
 862                                 status = "disabled";
 863                         };
 864
 865                         spi16: spi@884000 {
 866                                 compatible = "qcom,geni-spi";
 867                                 reg = <0x0 0x00884000 0x0 0x4000>;
 868                                 clock-names = "se";
 869                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 870                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 871                                 pinctrl-names = "default";
 872                                 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
 873                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 874                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 875                                 interconnect-names = "qup-core", "qup-config";
 876                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 877                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 878                                 dma-names = "tx", "rx";
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 status = "disabled";
 882                         };
 883
 884                         i2c17: i2c@888000 {
 885                                 compatible = "qcom,geni-i2c";
 886                                 reg = <0x0 0x00888000 0x0 0x4000>;
 887                                 clock-names = "se";
 888                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 889                                 pinctrl-names = "default";
 890                                 pinctrl-0 = <&qup_i2c17_data_clk>;
 891                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 892                                 #address-cells = <1>;
 893                                 #size-cells = <0>;
 894                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 895                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 896                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 897                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 898                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 899                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 900                                 dma-names = "tx", "rx";
 901                                 status = "disabled";
 902                         };
 903
 904                         spi17: spi@888000 {
 905                                 compatible = "qcom,geni-spi";
 906                                 reg = <0x0 0x00888000 0x0 0x4000>;
 907                                 clock-names = "se";
 908                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 909                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 910                                 pinctrl-names = "default";
 911                                 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
 912                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 913                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 914                                 interconnect-names = "qup-core", "qup-config";
 915                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 916                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 917                                 dma-names = "tx", "rx";
 918                                 #address-cells = <1>;
 919                                 #size-cells = <0>;
 920                                 status = "disabled";
 921                         };
 922
 923                         i2c18: i2c@88c000 {
 924                                 compatible = "qcom,geni-i2c";
 925                                 reg = <0x0 0x0088c000 0x0 0x4000>;
 926                                 clock-names = "se";
 927                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 928                                 pinctrl-names = "default";
 929                                 pinctrl-0 = <&qup_i2c18_data_clk>;
 930                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 931                                 #address-cells = <1>;
 932                                 #size-cells = <0>;
 933                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 934                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 935                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 936                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 937                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 938                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 939                                 dma-names = "tx", "rx";
 940                                 status = "disabled";
 941                         };
 942
 943                         spi18: spi@88c000 {
 944                                 compatible = "qcom,geni-spi";
 945                                 reg = <0 0x0088c000 0 0x4000>;
 946                                 clock-names = "se";
 947                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 948                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
 951                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 952                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 953                                 interconnect-names = "qup-core", "qup-config";
 954                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 955                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 956                                 dma-names = "tx", "rx";
 957                                 #address-cells = <1>;
 958                                 #size-cells = <0>;
 959                                 status = "disabled";
 960                         };
 961
 962                         i2c19: i2c@890000 {
 963                                 compatible = "qcom,geni-i2c";
 964                                 reg = <0x0 0x00890000 0x0 0x4000>;
 965                                 clock-names = "se";
 966                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 967                                 pinctrl-names = "default";
 968                                 pinctrl-0 = <&qup_i2c19_data_clk>;
 969                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 970                                 #address-cells = <1>;
 971                                 #size-cells = <0>;
 972                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 973                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 974                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 975                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 976                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 977                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 978                                 dma-names = "tx", "rx";
 979                                 status = "disabled";
 980                         };
 981
 982                         spi19: spi@890000 {
 983                                 compatible = "qcom,geni-spi";
 984                                 reg = <0 0x00890000 0 0x4000>;
 985                                 clock-names = "se";
 986                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 987                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 988                                 pinctrl-names = "default";
 989                                 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
 990                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 991                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 992                                 interconnect-names = "qup-core", "qup-config";
 993                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 994                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 995                                 dma-names = "tx", "rx";
 996                                 #address-cells = <1>;
 997                                 #size-cells = <0>;
 998                                 status = "disabled";
 999                         };
1000
1001                         i2c20: i2c@894000 {
1002                                 compatible = "qcom,geni-i2c";
1003                                 reg = <0x0 0x00894000 0x0 0x4000>;
1004                                 clock-names = "se";
1005                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1006                                 pinctrl-names = "default";
1007                                 pinctrl-0 = <&qup_i2c20_data_clk>;
1008                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1009                                 #address-cells = <1>;
1010                                 #size-cells = <0>;
1011                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1012                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1013                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1014                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1015                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1016                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1017                                 dma-names = "tx", "rx";
1018                                 status = "disabled";
1019                         };
1020
1021                         uart20: serial@894000 {
1022                                 compatible = "qcom,geni-uart";
1023                                 reg = <0 0x00894000 0 0x4000>;
1024                                 clock-names = "se";
1025                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1026                                 pinctrl-names = "default";
1027                                 pinctrl-0 = <&qup_uart20_default>;
1028                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1029                                 status = "disabled";
1030                         };
1031
1032                         spi20: spi@894000 {
1033                                 compatible = "qcom,geni-spi";
1034                                 reg = <0 0x00894000 0 0x4000>;
1035                                 clock-names = "se";
1036                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1037                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1038                                 pinctrl-names = "default";
1039                                 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1040                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1041                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1042                                 interconnect-names = "qup-core", "qup-config";
1043                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1044                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1045                                 dma-names = "tx", "rx";
1046                                 #address-cells = <1>;
1047                                 #size-cells = <0>;
1048                                 status = "disabled";
1049                         };
1050
1051                         i2c21: i2c@898000 {
1052                                 compatible = "qcom,geni-i2c";
1053                                 reg = <0x0 0x00898000 0x0 0x4000>;
1054                                 clock-names = "se";
1055                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1056                                 pinctrl-names = "default";
1057                                 pinctrl-0 = <&qup_i2c21_data_clk>;
1058                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1062                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1063                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1064                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1065                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1066                                        <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1067                                 dma-names = "tx", "rx";
1068                                 status = "disabled";
1069                         };
1070
1071                         spi21: spi@898000 {
1072                                 compatible = "qcom,geni-spi";
1073                                 reg = <0 0x00898000 0 0x4000>;
1074                                 clock-names = "se";
1075                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1076                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1077                                 pinctrl-names = "default";
1078                                 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1079                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1080                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1081                                 interconnect-names = "qup-core", "qup-config";
1082                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1083                                        <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1084                                 dma-names = "tx", "rx";
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087                                 status = "disabled";
1088                         };
1089                 };
1090
1091                 gpi_dma0: dma-controller@900000 {
1092                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1093                         #dma-cells = <3>;
1094                         reg = <0 0x00900000 0 0x60000>;
1095                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1096                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1097                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1098                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1099                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1100                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1101                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1102                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1103                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1104                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1105                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1106                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1107                         dma-channels = <12>;
1108                         dma-channel-mask = <0x7e>;
1109                         iommus = <&apps_smmu 0x5b6 0x0>;
1110                         status = "disabled";
1111                 };
1112
1113                 qupv3_id_0: geniqup@9c0000 {
1114                         compatible = "qcom,geni-se-qup";
1115                         reg = <0x0 0x009c0000 0x0 0x2000>;
1116                         clock-names = "m-ahb", "s-ahb";
1117                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1118                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1119                         iommus = <&apps_smmu 0x5a3 0x0>;
1120                         interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1121                         interconnect-names = "qup-core";
1122                         #address-cells = <2>;
1123                         #size-cells = <2>;
1124                         ranges;
1125                         status = "disabled";
1126
1127                         i2c0: i2c@980000 {
1128                                 compatible = "qcom,geni-i2c";
1129                                 reg = <0x0 0x00980000 0x0 0x4000>;
1130                                 clock-names = "se";
1131                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1132                                 pinctrl-names = "default";
1133                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1134                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1135                                 #address-cells = <1>;
1136                                 #size-cells = <0>;
1137                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1138                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1139                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1140                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1141                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1142                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1143                                 dma-names = "tx", "rx";
1144                                 status = "disabled";
1145                         };
1146
1147                         spi0: spi@980000 {
1148                                 compatible = "qcom,geni-spi";
1149                                 reg = <0x0 0x00980000 0x0 0x4000>;
1150                                 clock-names = "se";
1151                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1152                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1153                                 pinctrl-names = "default";
1154                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1155                                 power-domains = <&rpmhpd RPMHPD_CX>;
1156                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1157                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1158                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1159                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1160                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1161                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1162                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1163                                 dma-names = "tx", "rx";
1164                                 #address-cells = <1>;
1165                                 #size-cells = <0>;
1166                                 status = "disabled";
1167                         };
1168
1169                         i2c1: i2c@984000 {
1170                                 compatible = "qcom,geni-i2c";
1171                                 reg = <0x0 0x00984000 0x0 0x4000>;
1172                                 clock-names = "se";
1173                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1174                                 pinctrl-names = "default";
1175                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1176                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1177                                 #address-cells = <1>;
1178                                 #size-cells = <0>;
1179                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1180                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1181                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1182                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1183                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1184                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1185                                 dma-names = "tx", "rx";
1186                                 status = "disabled";
1187                         };
1188
1189                         spi1: spi@984000 {
1190                                 compatible = "qcom,geni-spi";
1191                                 reg = <0x0 0x00984000 0x0 0x4000>;
1192                                 clock-names = "se";
1193                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1194                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1195                                 pinctrl-names = "default";
1196                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1197                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1199                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1200                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1201                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1202                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1203                                 dma-names = "tx", "rx";
1204                                 #address-cells = <1>;
1205                                 #size-cells = <0>;
1206                                 status = "disabled";
1207                         };
1208
1209                         i2c2: i2c@988000 {
1210                                 compatible = "qcom,geni-i2c";
1211                                 reg = <0x0 0x00988000 0x0 0x4000>;
1212                                 clock-names = "se";
1213                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1214                                 pinctrl-names = "default";
1215                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1216                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1217                                 #address-cells = <1>;
1218                                 #size-cells = <0>;
1219                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1220                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1221                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1222                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1223                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1224                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1225                                 dma-names = "tx", "rx";
1226                                 status = "disabled";
1227                         };
1228
1229                         spi2: spi@988000 {
1230                                 compatible = "qcom,geni-spi";
1231                                 reg = <0x0 0x00988000 0x0 0x4000>;
1232                                 clock-names = "se";
1233                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1234                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1235                                 pinctrl-names = "default";
1236                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1237                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1239                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1240                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1241                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1242                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1243                                 dma-names = "tx", "rx";
1244                                 #address-cells = <1>;
1245                                 #size-cells = <0>;
1246                                 status = "disabled";
1247                         };
1248
1249
1250                         i2c3: i2c@98c000 {
1251                                 compatible = "qcom,geni-i2c";
1252                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1253                                 clock-names = "se";
1254                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1255                                 pinctrl-names = "default";
1256                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1257                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1258                                 #address-cells = <1>;
1259                                 #size-cells = <0>;
1260                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1261                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1262                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1263                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1264                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1265                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1266                                 dma-names = "tx", "rx";
1267                                 status = "disabled";
1268                         };
1269
1270                         spi3: spi@98c000 {
1271                                 compatible = "qcom,geni-spi";
1272                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1273                                 clock-names = "se";
1274                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1275                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1276                                 pinctrl-names = "default";
1277                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1278                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1279                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1280                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1281                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1282                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1283                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1284                                 dma-names = "tx", "rx";
1285                                 #address-cells = <1>;
1286                                 #size-cells = <0>;
1287                                 status = "disabled";
1288                         };
1289
1290                         i2c4: i2c@990000 {
1291                                 compatible = "qcom,geni-i2c";
1292                                 reg = <0x0 0x00990000 0x0 0x4000>;
1293                                 clock-names = "se";
1294                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1295                                 pinctrl-names = "default";
1296                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1297                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1298                                 #address-cells = <1>;
1299                                 #size-cells = <0>;
1300                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1301                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1302                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1303                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1304                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1305                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1306                                 dma-names = "tx", "rx";
1307                                 status = "disabled";
1308                         };
1309
1310                         spi4: spi@990000 {
1311                                 compatible = "qcom,geni-spi";
1312                                 reg = <0x0 0x00990000 0x0 0x4000>;
1313                                 clock-names = "se";
1314                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1315                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1316                                 pinctrl-names = "default";
1317                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1318                                 power-domains = <&rpmhpd RPMHPD_CX>;
1319                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1320                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1321                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1322                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1325                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1326                                 dma-names = "tx", "rx";
1327                                 #address-cells = <1>;
1328                                 #size-cells = <0>;
1329                                 status = "disabled";
1330                         };
1331
1332                         i2c5: i2c@994000 {
1333                                 compatible = "qcom,geni-i2c";
1334                                 reg = <0x0 0x00994000 0x0 0x4000>;
1335                                 clock-names = "se";
1336                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1337                                 pinctrl-names = "default";
1338                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1339                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1340                                 #address-cells = <1>;
1341                                 #size-cells = <0>;
1342                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1343                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1344                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1345                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1346                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1347                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1348                                 dma-names = "tx", "rx";
1349                                 status = "disabled";
1350                         };
1351
1352                         spi5: spi@994000 {
1353                                 compatible = "qcom,geni-spi";
1354                                 reg = <0x0 0x00994000 0x0 0x4000>;
1355                                 clock-names = "se";
1356                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1357                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1358                                 pinctrl-names = "default";
1359                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1360                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1361                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1362                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1363                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1364                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1365                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1366                                 dma-names = "tx", "rx";
1367                                 #address-cells = <1>;
1368                                 #size-cells = <0>;
1369                                 status = "disabled";
1370                         };
1371
1372
1373                         i2c6: i2c@998000 {
1374                                 compatible = "qcom,geni-i2c";
1375                                 reg = <0x0 0x00998000 0x0 0x4000>;
1376                                 clock-names = "se";
1377                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1378                                 pinctrl-names = "default";
1379                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1380                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1381                                 #address-cells = <1>;
1382                                 #size-cells = <0>;
1383                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1384                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1385                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1386                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1387                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1388                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1389                                 dma-names = "tx", "rx";
1390                                 status = "disabled";
1391                         };
1392
1393                         spi6: spi@998000 {
1394                                 compatible = "qcom,geni-spi";
1395                                 reg = <0x0 0x00998000 0x0 0x4000>;
1396                                 clock-names = "se";
1397                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1398                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1399                                 pinctrl-names = "default";
1400                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1401                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1402                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1403                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1404                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1405                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1406                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1407                                 dma-names = "tx", "rx";
1408                                 #address-cells = <1>;
1409                                 #size-cells = <0>;
1410                                 status = "disabled";
1411                         };
1412
1413                         uart7: serial@99c000 {
1414                                 compatible = "qcom,geni-debug-uart";
1415                                 reg = <0 0x0099c000 0 0x4000>;
1416                                 clock-names = "se";
1417                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1418                                 pinctrl-names = "default";
1419                                 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1420                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1421                                 status = "disabled";
1422                         };
1423                 };
1424
1425                 gpi_dma1: dma-controller@a00000 {
1426                         compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1427                         #dma-cells = <3>;
1428                         reg = <0 0x00a00000 0 0x60000>;
1429                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1430                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1431                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1432                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1433                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1434                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1435                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1436                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1437                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1438                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1439                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1440                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1441                         dma-channels = <12>;
1442                         dma-channel-mask = <0x7e>;
1443                         iommus = <&apps_smmu 0x56 0x0>;
1444                         status = "disabled";
1445                 };
1446
1447                 qupv3_id_1: geniqup@ac0000 {
1448                         compatible = "qcom,geni-se-qup";
1449                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1450                         clock-names = "m-ahb", "s-ahb";
1451                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1452                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1453                         iommus = <&apps_smmu 0x43 0x0>;
1454                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1455                         interconnect-names = "qup-core";
1456                         #address-cells = <2>;
1457                         #size-cells = <2>;
1458                         ranges;
1459                         status = "disabled";
1460
1461                         i2c8: i2c@a80000 {
1462                                 compatible = "qcom,geni-i2c";
1463                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1464                                 clock-names = "se";
1465                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1466                                 pinctrl-names = "default";
1467                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1468                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1469                                 #address-cells = <1>;
1470                                 #size-cells = <0>;
1471                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1472                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1473                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1474                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1475                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1476                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1477                                 dma-names = "tx", "rx";
1478                                 status = "disabled";
1479                         };
1480
1481                         spi8: spi@a80000 {
1482                                 compatible = "qcom,geni-spi";
1483                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1484                                 clock-names = "se";
1485                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1486                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1487                                 pinctrl-names = "default";
1488                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1489                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1490                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1491                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1492                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1493                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1494                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1495                                 dma-names = "tx", "rx";
1496                                 #address-cells = <1>;
1497                                 #size-cells = <0>;
1498                                 status = "disabled";
1499                         };
1500
1501                         i2c9: i2c@a84000 {
1502                                 compatible = "qcom,geni-i2c";
1503                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1504                                 clock-names = "se";
1505                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1506                                 pinctrl-names = "default";
1507                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1508                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1509                                 #address-cells = <1>;
1510                                 #size-cells = <0>;
1511                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1512                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1513                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1515                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1516                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1517                                 dma-names = "tx", "rx";
1518                                 status = "disabled";
1519                         };
1520
1521                         spi9: spi@a84000 {
1522                                 compatible = "qcom,geni-spi";
1523                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1524                                 clock-names = "se";
1525                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1526                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1527                                 pinctrl-names = "default";
1528                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1529                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1530                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1531                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1532                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1533                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1534                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1535                                 dma-names = "tx", "rx";
1536                                 #address-cells = <1>;
1537                                 #size-cells = <0>;
1538                                 status = "disabled";
1539                         };
1540
1541                         i2c10: i2c@a88000 {
1542                                 compatible = "qcom,geni-i2c";
1543                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1544                                 clock-names = "se";
1545                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1546                                 pinctrl-names = "default";
1547                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1548                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1549                                 #address-cells = <1>;
1550                                 #size-cells = <0>;
1551                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1552                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1553                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1554                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1555                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1556                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1557                                 dma-names = "tx", "rx";
1558                                 status = "disabled";
1559                         };
1560
1561                         spi10: spi@a88000 {
1562                                 compatible = "qcom,geni-spi";
1563                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1564                                 clock-names = "se";
1565                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1566                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1567                                 pinctrl-names = "default";
1568                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1569                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1570                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1571                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1572                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1573                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1574                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1575                                 dma-names = "tx", "rx";
1576                                 #address-cells = <1>;
1577                                 #size-cells = <0>;
1578                                 status = "disabled";
1579                         };
1580
1581                         i2c11: i2c@a8c000 {
1582                                 compatible = "qcom,geni-i2c";
1583                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1584                                 clock-names = "se";
1585                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1586                                 pinctrl-names = "default";
1587                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1588                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1589                                 #address-cells = <1>;
1590                                 #size-cells = <0>;
1591                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1593                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1595                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1596                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1597                                 dma-names = "tx", "rx";
1598                                 status = "disabled";
1599                         };
1600
1601                         spi11: spi@a8c000 {
1602                                 compatible = "qcom,geni-spi";
1603                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1604                                 clock-names = "se";
1605                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1606                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1607                                 pinctrl-names = "default";
1608                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1609                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1610                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1611                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1612                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1613                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1614                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1615                                 dma-names = "tx", "rx";
1616                                 #address-cells = <1>;
1617                                 #size-cells = <0>;
1618                                 status = "disabled";
1619                         };
1620
1621                         i2c12: i2c@a90000 {
1622                                 compatible = "qcom,geni-i2c";
1623                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1624                                 clock-names = "se";
1625                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1626                                 pinctrl-names = "default";
1627                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1628                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1629                                 #address-cells = <1>;
1630                                 #size-cells = <0>;
1631                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1632                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1633                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1634                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1635                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1636                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1637                                 dma-names = "tx", "rx";
1638                                 status = "disabled";
1639                         };
1640
1641                         spi12: spi@a90000 {
1642                                 compatible = "qcom,geni-spi";
1643                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1644                                 clock-names = "se";
1645                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1646                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1647                                 pinctrl-names = "default";
1648                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1649                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1650                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1651                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1652                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1653                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1654                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1655                                 dma-names = "tx", "rx";
1656                                 #address-cells = <1>;
1657                                 #size-cells = <0>;
1658                                 status = "disabled";
1659                         };
1660
1661                         i2c13: i2c@a94000 {
1662                                 compatible = "qcom,geni-i2c";
1663                                 reg = <0 0x00a94000 0 0x4000>;
1664                                 clock-names = "se";
1665                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1666                                 pinctrl-names = "default";
1667                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1668                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1669                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1670                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1671                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1672                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1673                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1674                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1675                                 dma-names = "tx", "rx";
1676                                 #address-cells = <1>;
1677                                 #size-cells = <0>;
1678                                 status = "disabled";
1679                         };
1680
1681                         spi13: spi@a94000 {
1682                                 compatible = "qcom,geni-spi";
1683                                 reg = <0x0 0x00a94000 0x0 0x4000>;
1684                                 clock-names = "se";
1685                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1686                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1687                                 pinctrl-names = "default";
1688                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1689                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1690                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1691                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1692                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1693                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1694                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1695                                 dma-names = "tx", "rx";
1696                                 #address-cells = <1>;
1697                                 #size-cells = <0>;
1698                                 status = "disabled";
1699                         };
1700
1701                         i2c14: i2c@a98000 {
1702                                 compatible = "qcom,geni-i2c";
1703                                 reg = <0 0x00a98000 0 0x4000>;
1704                                 clock-names = "se";
1705                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1706                                 pinctrl-names = "default";
1707                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1708                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1709                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1710                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1711                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1712                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1713                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1714                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1715                                 dma-names = "tx", "rx";
1716                                 #address-cells = <1>;
1717                                 #size-cells = <0>;
1718                                 status = "disabled";
1719                         };
1720
1721                         spi14: spi@a98000 {
1722                                 compatible = "qcom,geni-spi";
1723                                 reg = <0x0 0x00a98000 0x0 0x4000>;
1724                                 clock-names = "se";
1725                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1726                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1727                                 pinctrl-names = "default";
1728                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1729                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1730                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1731                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1732                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1733                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1734                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1735                                 dma-names = "tx", "rx";
1736                                 #address-cells = <1>;
1737                                 #size-cells = <0>;
1738                                 status = "disabled";
1739                         };
1740                 };
1741
1742                 pcie0: pci@1c00000 {
1743                         compatible = "qcom,pcie-sm8450-pcie0";
1744                         reg = <0 0x01c00000 0 0x3000>,
1745                               <0 0x60000000 0 0xf1d>,
1746                               <0 0x60000f20 0 0xa8>,
1747                               <0 0x60001000 0 0x1000>,
1748                               <0 0x60100000 0 0x100000>;
1749                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1750                         device_type = "pci";
1751                         linux,pci-domain = <0>;
1752                         bus-range = <0x00 0xff>;
1753                         num-lanes = <1>;
1754
1755                         #address-cells = <3>;
1756                         #size-cells = <2>;
1757
1758                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1759                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1760
1761                         /*
1762                          * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1763                          * Hence, the IDs are swapped.
1764                          */
1765                         msi-map = <0x0 &gic_its 0x5981 0x1>,
1766                                   <0x100 &gic_its 0x5980 0x1>;
1767                         msi-map-mask = <0xff00>;
1768                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1769                         interrupt-names = "msi";
1770                         #interrupt-cells = <1>;
1771                         interrupt-map-mask = <0 0 0 0x7>;
1772                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1773                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1774                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1775                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1776
1777                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1778                                  <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1779                                  <&pcie0_phy>,
1780                                  <&rpmhcc RPMH_CXO_CLK>,
1781                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1782                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1783                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1784                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1785                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1786                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1787                                  <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1788                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1789                         clock-names = "pipe",
1790                                       "pipe_mux",
1791                                       "phy_pipe",
1792                                       "ref",
1793                                       "aux",
1794                                       "cfg",
1795                                       "bus_master",
1796                                       "bus_slave",
1797                                       "slave_q2a",
1798                                       "ddrss_sf_tbu",
1799                                       "aggre0",
1800                                       "aggre1";
1801
1802                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1803                                     <0x100 &apps_smmu 0x1c01 0x1>;
1804
1805                         resets = <&gcc GCC_PCIE_0_BCR>;
1806                         reset-names = "pci";
1807
1808                         power-domains = <&gcc PCIE_0_GDSC>;
1809
1810                         phys = <&pcie0_phy>;
1811                         phy-names = "pciephy";
1812
1813                         perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1814                         wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1815
1816                         pinctrl-names = "default";
1817                         pinctrl-0 = <&pcie0_default_state>;
1818
1819                         status = "disabled";
1820                 };
1821
1822                 pcie0_phy: phy@1c06000 {
1823                         compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1824                         reg = <0 0x01c06000 0 0x2000>;
1825
1826                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1827                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1828                                  <&gcc GCC_PCIE_0_CLKREF_EN>,
1829                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1830                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1831                         clock-names = "aux",
1832                                       "cfg_ahb",
1833                                       "ref",
1834                                       "rchng",
1835                                       "pipe";
1836
1837                         clock-output-names = "pcie_0_pipe_clk";
1838                         #clock-cells = <0>;
1839
1840                         #phy-cells = <0>;
1841
1842                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1843                         reset-names = "phy";
1844
1845                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1846                         assigned-clock-rates = <100000000>;
1847
1848                         status = "disabled";
1849                 };
1850
1851                 pcie1: pci@1c08000 {
1852                         compatible = "qcom,pcie-sm8450-pcie1";
1853                         reg = <0 0x01c08000 0 0x3000>,
1854                               <0 0x40000000 0 0xf1d>,
1855                               <0 0x40000f20 0 0xa8>,
1856                               <0 0x40001000 0 0x1000>,
1857                               <0 0x40100000 0 0x100000>;
1858                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1859                         device_type = "pci";
1860                         linux,pci-domain = <1>;
1861                         bus-range = <0x00 0xff>;
1862                         num-lanes = <2>;
1863
1864                         #address-cells = <3>;
1865                         #size-cells = <2>;
1866
1867                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1868                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1869
1870                         /*
1871                          * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1872                          * Hence, the IDs are swapped.
1873                          */
1874                         msi-map = <0x0 &gic_its 0x5a01 0x1>,
1875                                   <0x100 &gic_its 0x5a00 0x1>;
1876                         msi-map-mask = <0xff00>;
1877                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1878                         interrupt-names = "msi";
1879                         #interrupt-cells = <1>;
1880                         interrupt-map-mask = <0 0 0 0x7>;
1881                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1882                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1883                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1884                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1885
1886                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1887                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1888                                  <&pcie1_phy>,
1889                                  <&rpmhcc RPMH_CXO_CLK>,
1890                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1891                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1892                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1893                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1894                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1895                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1896                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1897                         clock-names = "pipe",
1898                                       "pipe_mux",
1899                                       "phy_pipe",
1900                                       "ref",
1901                                       "aux",
1902                                       "cfg",
1903                                       "bus_master",
1904                                       "bus_slave",
1905                                       "slave_q2a",
1906                                       "ddrss_sf_tbu",
1907                                       "aggre1";
1908
1909                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1910                                     <0x100 &apps_smmu 0x1c81 0x1>;
1911
1912                         resets = <&gcc GCC_PCIE_1_BCR>;
1913                         reset-names = "pci";
1914
1915                         power-domains = <&gcc PCIE_1_GDSC>;
1916
1917                         phys = <&pcie1_phy>;
1918                         phy-names = "pciephy";
1919
1920                         perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1921                         wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1922
1923                         pinctrl-names = "default";
1924                         pinctrl-0 = <&pcie1_default_state>;
1925
1926                         status = "disabled";
1927                 };
1928
1929                 pcie1_phy: phy@1c0e000 {
1930                         compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1931                         reg = <0 0x01c0e000 0 0x2000>;
1932
1933                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1934                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1935                                  <&gcc GCC_PCIE_1_CLKREF_EN>,
1936                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1937                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1938                         clock-names = "aux",
1939                                       "cfg_ahb",
1940                                       "ref",
1941                                       "rchng",
1942                                       "pipe";
1943
1944                         clock-output-names = "pcie_1_pipe_clk";
1945                         #clock-cells = <0>;
1946
1947                         #phy-cells = <0>;
1948
1949                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1950                         reset-names = "phy";
1951
1952                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1953                         assigned-clock-rates = <100000000>;
1954
1955                         status = "disabled";
1956                 };
1957
1958                 config_noc: interconnect@1500000 {
1959                         compatible = "qcom,sm8450-config-noc";
1960                         reg = <0 0x01500000 0 0x1c000>;
1961                         #interconnect-cells = <2>;
1962                         qcom,bcm-voters = <&apps_bcm_voter>;
1963                 };
1964
1965                 system_noc: interconnect@1680000 {
1966                         compatible = "qcom,sm8450-system-noc";
1967                         reg = <0 0x01680000 0 0x1e200>;
1968                         #interconnect-cells = <2>;
1969                         qcom,bcm-voters = <&apps_bcm_voter>;
1970                 };
1971
1972                 pcie_noc: interconnect@16c0000 {
1973                         compatible = "qcom,sm8450-pcie-anoc";
1974                         reg = <0 0x016c0000 0 0xe280>;
1975                         #interconnect-cells = <2>;
1976                         qcom,bcm-voters = <&apps_bcm_voter>;
1977                 };
1978
1979                 aggre1_noc: interconnect@16e0000 {
1980                         compatible = "qcom,sm8450-aggre1-noc";
1981                         reg = <0 0x016e0000 0 0x1c080>;
1982                         #interconnect-cells = <2>;
1983                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1984                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1985                         qcom,bcm-voters = <&apps_bcm_voter>;
1986                 };
1987
1988                 aggre2_noc: interconnect@1700000 {
1989                         compatible = "qcom,sm8450-aggre2-noc";
1990                         reg = <0 0x01700000 0 0x31080>;
1991                         #interconnect-cells = <2>;
1992                         qcom,bcm-voters = <&apps_bcm_voter>;
1993                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1994                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1995                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1996                                  <&rpmhcc RPMH_IPA_CLK>;
1997                 };
1998
1999                 mmss_noc: interconnect@1740000 {
2000                         compatible = "qcom,sm8450-mmss-noc";
2001                         reg = <0 0x01740000 0 0x1f080>;
2002                         #interconnect-cells = <2>;
2003                         qcom,bcm-voters = <&apps_bcm_voter>;
2004                 };
2005
2006                 tcsr_mutex: hwlock@1f40000 {
2007                         compatible = "qcom,tcsr-mutex";
2008                         reg = <0x0 0x01f40000 0x0 0x40000>;
2009                         #hwlock-cells = <1>;
2010                 };
2011
2012                 tcsr: syscon@1fc0000 {
2013                         compatible = "qcom,sm8450-tcsr", "syscon";
2014                         reg = <0x0 0x1fc0000 0x0 0x30000>;
2015                 };
2016
2017                 usb_1_hsphy: phy@88e3000 {
2018                         compatible = "qcom,sm8450-usb-hs-phy",
2019                                      "qcom,usb-snps-hs-7nm-phy";
2020                         reg = <0 0x088e3000 0 0x400>;
2021                         status = "disabled";
2022                         #phy-cells = <0>;
2023
2024                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2025                         clock-names = "ref";
2026
2027                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2028                 };
2029
2030                 usb_1_qmpphy: phy@88e8000 {
2031                         compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2032                         reg = <0 0x088e8000 0 0x3000>;
2033
2034                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2035                                  <&rpmhcc RPMH_CXO_CLK>,
2036                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2037                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2038                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2039
2040                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2041                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2042                         reset-names = "phy", "common";
2043
2044                         #clock-cells = <1>;
2045                         #phy-cells = <1>;
2046
2047                         status = "disabled";
2048
2049                         ports {
2050                                 #address-cells = <1>;
2051                                 #size-cells = <0>;
2052
2053                                 port@0 {
2054                                         reg = <0>;
2055
2056                                         usb_1_qmpphy_out: endpoint {
2057                                         };
2058                                 };
2059
2060                                 port@1 {
2061                                         reg = <1>;
2062
2063                                         usb_1_qmpphy_usb_ss_in: endpoint {
2064                                         };
2065                                 };
2066
2067                                 port@2 {
2068                                         reg = <2>;
2069
2070                                         usb_1_qmpphy_dp_in: endpoint {
2071                                         };
2072                                 };
2073                         };
2074                 };
2075
2076                 remoteproc_slpi: remoteproc@2400000 {
2077                         compatible = "qcom,sm8450-slpi-pas";
2078                         reg = <0 0x02400000 0 0x4000>;
2079
2080                         interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2081                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2082                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2083                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2084                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2085                         interrupt-names = "wdog", "fatal", "ready",
2086                                           "handover", "stop-ack";
2087
2088                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2089                         clock-names = "xo";
2090
2091                         power-domains = <&rpmhpd RPMHPD_LCX>,
2092                                         <&rpmhpd RPMHPD_LMX>;
2093                         power-domain-names = "lcx", "lmx";
2094
2095                         memory-region = <&slpi_mem>;
2096
2097                         qcom,qmp = <&aoss_qmp>;
2098
2099                         qcom,smem-states = <&smp2p_slpi_out 0>;
2100                         qcom,smem-state-names = "stop";
2101
2102                         status = "disabled";
2103
2104                         glink-edge {
2105                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2106                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2107                                                              IRQ_TYPE_EDGE_RISING>;
2108                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2109                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2110
2111                                 label = "slpi";
2112                                 qcom,remote-pid = <3>;
2113
2114                                 fastrpc {
2115                                         compatible = "qcom,fastrpc";
2116                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2117                                         label = "sdsp";
2118                                         #address-cells = <1>;
2119                                         #size-cells = <0>;
2120
2121                                         compute-cb@1 {
2122                                                 compatible = "qcom,fastrpc-compute-cb";
2123                                                 reg = <1>;
2124                                                 iommus = <&apps_smmu 0x0541 0x0>;
2125                                         };
2126
2127                                         compute-cb@2 {
2128                                                 compatible = "qcom,fastrpc-compute-cb";
2129                                                 reg = <2>;
2130                                                 iommus = <&apps_smmu 0x0542 0x0>;
2131                                         };
2132
2133                                         compute-cb@3 {
2134                                                 compatible = "qcom,fastrpc-compute-cb";
2135                                                 reg = <3>;
2136                                                 iommus = <&apps_smmu 0x0543 0x0>;
2137                                                 /* note: shared-cb = <4> in downstream */
2138                                         };
2139                                 };
2140                         };
2141                 };
2142
2143                 wsa2macro: codec@31e0000 {
2144                         compatible = "qcom,sm8450-lpass-wsa-macro";
2145                         reg = <0 0x031e0000 0 0x1000>;
2146                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2147                                  <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2148                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2149                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2150                                  <&vamacro>;
2151                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2152                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2153                                           <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2154                         assigned-clock-rates = <19200000>, <19200000>;
2155
2156                         #clock-cells = <0>;
2157                         clock-output-names = "wsa2-mclk";
2158                         pinctrl-names = "default";
2159                         pinctrl-0 = <&wsa2_swr_active>;
2160                         #sound-dai-cells = <1>;
2161                 };
2162
2163                 swr4: soundwire-controller@31f0000 {
2164                         compatible = "qcom,soundwire-v1.7.0";
2165                         reg = <0 0x031f0000 0 0x2000>;
2166                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2167                         clocks = <&wsa2macro>;
2168                         clock-names = "iface";
2169                         label = "WSA2";
2170
2171                         qcom,din-ports = <2>;
2172                         qcom,dout-ports = <6>;
2173
2174                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2175                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2176                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2177                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2178                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2179                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2180                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2181                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2182                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2183
2184                         #address-cells = <2>;
2185                         #size-cells = <0>;
2186                         #sound-dai-cells = <1>;
2187                         status = "disabled";
2188                 };
2189
2190                 rxmacro: codec@3200000 {
2191                         compatible = "qcom,sm8450-lpass-rx-macro";
2192                         reg = <0 0x03200000 0 0x1000>;
2193                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2194                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2195                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2196                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2197                                  <&vamacro>;
2198                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2199
2200                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2201                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2202                         assigned-clock-rates = <19200000>, <19200000>;
2203
2204                         #clock-cells = <0>;
2205                         clock-output-names = "mclk";
2206                         pinctrl-names = "default";
2207                         pinctrl-0 = <&rx_swr_active>;
2208                         #sound-dai-cells = <1>;
2209                 };
2210
2211                 swr1: soundwire-controller@3210000 {
2212                         compatible = "qcom,soundwire-v1.7.0";
2213                         reg = <0 0x03210000 0 0x2000>;
2214                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2215                         clocks = <&rxmacro>;
2216                         clock-names = "iface";
2217                         label = "RX";
2218                         qcom,din-ports = <0>;
2219                         qcom,dout-ports = <5>;
2220
2221                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2222                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2223                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2224                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2225                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2226                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2227                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2228                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2229                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2230
2231                         #address-cells = <2>;
2232                         #size-cells = <0>;
2233                         #sound-dai-cells = <1>;
2234                         status = "disabled";
2235                 };
2236
2237                 txmacro: codec@3220000 {
2238                         compatible = "qcom,sm8450-lpass-tx-macro";
2239                         reg = <0 0x03220000 0 0x1000>;
2240                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2241                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2242                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2243                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2244                                  <&vamacro>;
2245                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2246                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2247                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2248                         assigned-clock-rates = <19200000>, <19200000>;
2249
2250                         #clock-cells = <0>;
2251                         clock-output-names = "mclk";
2252                         pinctrl-names = "default";
2253                         pinctrl-0 = <&tx_swr_active>;
2254                         #sound-dai-cells = <1>;
2255                 };
2256
2257                 wsamacro: codec@3240000 {
2258                         compatible = "qcom,sm8450-lpass-wsa-macro";
2259                         reg = <0 0x03240000 0 0x1000>;
2260                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2261                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2262                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2263                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2264                                  <&vamacro>;
2265                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2266
2267                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2268                                           <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2269                         assigned-clock-rates = <19200000>, <19200000>;
2270
2271                         #clock-cells = <0>;
2272                         clock-output-names = "mclk";
2273                         pinctrl-names = "default";
2274                         pinctrl-0 = <&wsa_swr_active>;
2275                         #sound-dai-cells = <1>;
2276                 };
2277
2278                 swr0: soundwire-controller@3250000 {
2279                         compatible = "qcom,soundwire-v1.7.0";
2280                         reg = <0 0x03250000 0 0x2000>;
2281                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2282                         clocks = <&wsamacro>;
2283                         clock-names = "iface";
2284                         label = "WSA";
2285
2286                         qcom,din-ports = <2>;
2287                         qcom,dout-ports = <6>;
2288
2289                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2290                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2291                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2292                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2293                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2294                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2295                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2296                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2297                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2298
2299                         #address-cells = <2>;
2300                         #size-cells = <0>;
2301                         #sound-dai-cells = <1>;
2302                         status = "disabled";
2303                 };
2304
2305                 swr2: soundwire-controller@33b0000 {
2306                         compatible = "qcom,soundwire-v1.7.0";
2307                         reg = <0 0x033b0000 0 0x2000>;
2308                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2309                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2310                         interrupt-names = "core", "wakeup";
2311
2312                         clocks = <&vamacro>;
2313                         clock-names = "iface";
2314                         label = "TX";
2315
2316                         qcom,din-ports = <4>;
2317                         qcom,dout-ports = <0>;
2318                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2319                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2320                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2321                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2322                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2323                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2324                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2325                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2326                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2327
2328                         #address-cells = <2>;
2329                         #size-cells = <0>;
2330                         #sound-dai-cells = <1>;
2331                         status = "disabled";
2332                 };
2333
2334                 vamacro: codec@33f0000 {
2335                         compatible = "qcom,sm8450-lpass-va-macro";
2336                         reg = <0 0x033f0000 0 0x1000>;
2337                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2338                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2339                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2340                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2341                         clock-names = "mclk", "macro", "dcodec", "npl";
2342                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2343                         assigned-clock-rates = <19200000>;
2344
2345                         #clock-cells = <0>;
2346                         clock-output-names = "fsgen";
2347                         #sound-dai-cells = <1>;
2348                         status = "disabled";
2349                 };
2350
2351                 remoteproc_adsp: remoteproc@30000000 {
2352                         compatible = "qcom,sm8450-adsp-pas";
2353                         reg = <0 0x30000000 0 0x100>;
2354
2355                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2356                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2357                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2358                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2359                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2360                         interrupt-names = "wdog", "fatal", "ready",
2361                                           "handover", "stop-ack";
2362
2363                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2364                         clock-names = "xo";
2365
2366                         power-domains = <&rpmhpd RPMHPD_LCX>,
2367                                         <&rpmhpd RPMHPD_LMX>;
2368                         power-domain-names = "lcx", "lmx";
2369
2370                         memory-region = <&adsp_mem>;
2371
2372                         qcom,qmp = <&aoss_qmp>;
2373
2374                         qcom,smem-states = <&smp2p_adsp_out 0>;
2375                         qcom,smem-state-names = "stop";
2376
2377                         status = "disabled";
2378
2379                         remoteproc_adsp_glink: glink-edge {
2380                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2381                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2382                                                              IRQ_TYPE_EDGE_RISING>;
2383                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2384                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2385
2386                                 label = "lpass";
2387                                 qcom,remote-pid = <2>;
2388
2389                                 gpr {
2390                                         compatible = "qcom,gpr";
2391                                         qcom,glink-channels = "adsp_apps";
2392                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2393                                         qcom,intents = <512 20>;
2394                                         #address-cells = <1>;
2395                                         #size-cells = <0>;
2396
2397                                         q6apm: service@1 {
2398                                                 compatible = "qcom,q6apm";
2399                                                 reg = <GPR_APM_MODULE_IID>;
2400                                                 #sound-dai-cells = <0>;
2401                                                 qcom,protection-domain = "avs/audio",
2402                                                                          "msm/adsp/audio_pd";
2403
2404                                                 q6apmdai: dais {
2405                                                         compatible = "qcom,q6apm-dais";
2406                                                         iommus = <&apps_smmu 0x1801 0x0>;
2407                                                 };
2408
2409                                                 q6apmbedai: bedais {
2410                                                         compatible = "qcom,q6apm-lpass-dais";
2411                                                         #sound-dai-cells = <1>;
2412                                                 };
2413                                         };
2414
2415                                         q6prm: service@2 {
2416                                                 compatible = "qcom,q6prm";
2417                                                 reg = <GPR_PRM_MODULE_IID>;
2418                                                 qcom,protection-domain = "avs/audio",
2419                                                                          "msm/adsp/audio_pd";
2420
2421                                                 q6prmcc: clock-controller {
2422                                                         compatible = "qcom,q6prm-lpass-clocks";
2423                                                         #clock-cells = <2>;
2424                                                 };
2425                                         };
2426                                 };
2427
2428                                 fastrpc {
2429                                         compatible = "qcom,fastrpc";
2430                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2431                                         label = "adsp";
2432                                         #address-cells = <1>;
2433                                         #size-cells = <0>;
2434
2435                                         compute-cb@3 {
2436                                                 compatible = "qcom,fastrpc-compute-cb";
2437                                                 reg = <3>;
2438                                                 iommus = <&apps_smmu 0x1803 0x0>;
2439                                         };
2440
2441                                         compute-cb@4 {
2442                                                 compatible = "qcom,fastrpc-compute-cb";
2443                                                 reg = <4>;
2444                                                 iommus = <&apps_smmu 0x1804 0x0>;
2445                                         };
2446
2447                                         compute-cb@5 {
2448                                                 compatible = "qcom,fastrpc-compute-cb";
2449                                                 reg = <5>;
2450                                                 iommus = <&apps_smmu 0x1805 0x0>;
2451                                         };
2452                                 };
2453                         };
2454                 };
2455
2456                 remoteproc_cdsp: remoteproc@32300000 {
2457                         compatible = "qcom,sm8450-cdsp-pas";
2458                         reg = <0 0x32300000 0 0x1400000>;
2459
2460                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2461                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2462                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2463                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2464                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2465                         interrupt-names = "wdog", "fatal", "ready",
2466                                           "handover", "stop-ack";
2467
2468                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2469                         clock-names = "xo";
2470
2471                         power-domains = <&rpmhpd RPMHPD_CX>,
2472                                         <&rpmhpd RPMHPD_MXC>;
2473                         power-domain-names = "cx", "mxc";
2474
2475                         memory-region = <&cdsp_mem>;
2476
2477                         qcom,qmp = <&aoss_qmp>;
2478
2479                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2480                         qcom,smem-state-names = "stop";
2481
2482                         status = "disabled";
2483
2484                         glink-edge {
2485                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2486                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2487                                                              IRQ_TYPE_EDGE_RISING>;
2488                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2489                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2490
2491                                 label = "cdsp";
2492                                 qcom,remote-pid = <5>;
2493
2494                                 fastrpc {
2495                                         compatible = "qcom,fastrpc";
2496                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2497                                         label = "cdsp";
2498                                         #address-cells = <1>;
2499                                         #size-cells = <0>;
2500
2501                                         compute-cb@1 {
2502                                                 compatible = "qcom,fastrpc-compute-cb";
2503                                                 reg = <1>;
2504                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2505                                                          <&apps_smmu 0x1021 0x1420>;
2506                                         };
2507
2508                                         compute-cb@2 {
2509                                                 compatible = "qcom,fastrpc-compute-cb";
2510                                                 reg = <2>;
2511                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2512                                                          <&apps_smmu 0x1022 0x1420>;
2513                                         };
2514
2515                                         compute-cb@3 {
2516                                                 compatible = "qcom,fastrpc-compute-cb";
2517                                                 reg = <3>;
2518                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2519                                                          <&apps_smmu 0x1023 0x1420>;
2520                                         };
2521
2522                                         compute-cb@4 {
2523                                                 compatible = "qcom,fastrpc-compute-cb";
2524                                                 reg = <4>;
2525                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2526                                                          <&apps_smmu 0x1024 0x1420>;
2527                                         };
2528
2529                                         compute-cb@5 {
2530                                                 compatible = "qcom,fastrpc-compute-cb";
2531                                                 reg = <5>;
2532                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2533                                                          <&apps_smmu 0x1025 0x1420>;
2534                                         };
2535
2536                                         compute-cb@6 {
2537                                                 compatible = "qcom,fastrpc-compute-cb";
2538                                                 reg = <6>;
2539                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2540                                                          <&apps_smmu 0x1026 0x1420>;
2541                                         };
2542
2543                                         compute-cb@7 {
2544                                                 compatible = "qcom,fastrpc-compute-cb";
2545                                                 reg = <7>;
2546                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2547                                                          <&apps_smmu 0x1027 0x1420>;
2548                                         };
2549
2550                                         compute-cb@8 {
2551                                                 compatible = "qcom,fastrpc-compute-cb";
2552                                                 reg = <8>;
2553                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2554                                                          <&apps_smmu 0x1028 0x1420>;
2555                                         };
2556
2557                                         /* note: secure cb9 in downstream */
2558                                 };
2559                         };
2560                 };
2561
2562                 remoteproc_mpss: remoteproc@4080000 {
2563                         compatible = "qcom,sm8450-mpss-pas";
2564                         reg = <0x0 0x04080000 0x0 0x4040>;
2565
2566                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2567                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2568                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2569                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2570                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2571                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2572                         interrupt-names = "wdog", "fatal", "ready", "handover",
2573                                           "stop-ack", "shutdown-ack";
2574
2575                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2576                         clock-names = "xo";
2577
2578                         power-domains = <&rpmhpd RPMHPD_CX>,
2579                                         <&rpmhpd RPMHPD_MSS>;
2580                         power-domain-names = "cx", "mss";
2581
2582                         memory-region = <&mpss_mem>;
2583
2584                         qcom,qmp = <&aoss_qmp>;
2585
2586                         qcom,smem-states = <&smp2p_modem_out 0>;
2587                         qcom,smem-state-names = "stop";
2588
2589                         status = "disabled";
2590
2591                         glink-edge {
2592                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2593                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2594                                                              IRQ_TYPE_EDGE_RISING>;
2595                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2596                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2597                                 label = "modem";
2598                                 qcom,remote-pid = <1>;
2599                         };
2600                 };
2601
2602                 videocc: clock-controller@aaf0000 {
2603                         compatible = "qcom,sm8450-videocc";
2604                         reg = <0 0x0aaf0000 0 0x10000>;
2605                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2606                                  <&gcc GCC_VIDEO_AHB_CLK>;
2607                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2608                         required-opps = <&rpmhpd_opp_low_svs>;
2609                         #clock-cells = <1>;
2610                         #reset-cells = <1>;
2611                         #power-domain-cells = <1>;
2612                 };
2613
2614                 cci0: cci@ac15000 {
2615                         compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2616                         reg = <0 0x0ac15000 0 0x1000>;
2617                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
2618                         power-domains = <&camcc TITAN_TOP_GDSC>;
2619
2620                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2621                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2622                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
2623                                  <&camcc CAM_CC_CCI_0_CLK>,
2624                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
2625                         clock-names = "camnoc_axi",
2626                                       "slow_ahb_src",
2627                                       "cpas_ahb",
2628                                       "cci",
2629                                       "cci_src";
2630                         pinctrl-0 = <&cci0_default &cci1_default>;
2631                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2632                         pinctrl-names = "default", "sleep";
2633
2634                         status = "disabled";
2635                         #address-cells = <1>;
2636                         #size-cells = <0>;
2637
2638                         cci0_i2c0: i2c-bus@0 {
2639                                 reg = <0>;
2640                                 clock-frequency = <1000000>;
2641                                 #address-cells = <1>;
2642                                 #size-cells = <0>;
2643                         };
2644
2645                         cci0_i2c1: i2c-bus@1 {
2646                                 reg = <1>;
2647                                 clock-frequency = <1000000>;
2648                                 #address-cells = <1>;
2649                                 #size-cells = <0>;
2650                         };
2651                 };
2652
2653                 cci1: cci@ac16000 {
2654                         compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2655                         reg = <0 0x0ac16000 0 0x1000>;
2656                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
2657                         power-domains = <&camcc TITAN_TOP_GDSC>;
2658
2659                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
2660                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
2661                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
2662                                  <&camcc CAM_CC_CCI_1_CLK>,
2663                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
2664                         clock-names = "camnoc_axi",
2665                                       "slow_ahb_src",
2666                                       "cpas_ahb",
2667                                       "cci",
2668                                       "cci_src";
2669                         pinctrl-0 = <&cci2_default &cci3_default>;
2670                         pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2671                         pinctrl-names = "default", "sleep";
2672
2673                         status = "disabled";
2674                         #address-cells = <1>;
2675                         #size-cells = <0>;
2676
2677                         cci1_i2c0: i2c-bus@0 {
2678                                 reg = <0>;
2679                                 clock-frequency = <1000000>;
2680                                 #address-cells = <1>;
2681                                 #size-cells = <0>;
2682                         };
2683
2684                         cci1_i2c1: i2c-bus@1 {
2685                                 reg = <1>;
2686                                 clock-frequency = <1000000>;
2687                                 #address-cells = <1>;
2688                                 #size-cells = <0>;
2689                         };
2690                 };
2691
2692                 camcc: clock-controller@ade0000 {
2693                         compatible = "qcom,sm8450-camcc";
2694                         reg = <0 0x0ade0000 0 0x20000>;
2695                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2696                                  <&rpmhcc RPMH_CXO_CLK>,
2697                                  <&rpmhcc RPMH_CXO_CLK_A>,
2698                                  <&sleep_clk>;
2699                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2700                         required-opps = <&rpmhpd_opp_low_svs>;
2701                         #clock-cells = <1>;
2702                         #reset-cells = <1>;
2703                         #power-domain-cells = <1>;
2704                         status = "disabled";
2705                 };
2706
2707                 mdss: display-subsystem@ae00000 {
2708                         compatible = "qcom,sm8450-mdss";
2709                         reg = <0 0x0ae00000 0 0x1000>;
2710                         reg-names = "mdss";
2711
2712                         /* same path used twice */
2713                         interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2714                                         <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2715                                         <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2716                                          &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
2717                         interconnect-names = "mdp0-mem",
2718                                              "mdp1-mem",
2719                                              "cpu-cfg";
2720
2721                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2722
2723                         power-domains = <&dispcc MDSS_GDSC>;
2724
2725                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2726                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2727                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2728                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2729
2730                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2731                         interrupt-controller;
2732                         #interrupt-cells = <1>;
2733
2734                         iommus = <&apps_smmu 0x2800 0x402>;
2735
2736                         #address-cells = <2>;
2737                         #size-cells = <2>;
2738                         ranges;
2739
2740                         status = "disabled";
2741
2742                         mdss_mdp: display-controller@ae01000 {
2743                                 compatible = "qcom,sm8450-dpu";
2744                                 reg = <0 0x0ae01000 0 0x8f000>,
2745                                       <0 0x0aeb0000 0 0x2008>;
2746                                 reg-names = "mdp", "vbif";
2747
2748                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2749                                         <&gcc GCC_DISP_SF_AXI_CLK>,
2750                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
2751                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2752                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
2753                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2754                                 clock-names = "bus",
2755                                               "nrt_bus",
2756                                               "iface",
2757                                               "lut",
2758                                               "core",
2759                                               "vsync";
2760
2761                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2762                                 assigned-clock-rates = <19200000>;
2763
2764                                 operating-points-v2 = <&mdp_opp_table>;
2765                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2766
2767                                 interrupt-parent = <&mdss>;
2768                                 interrupts = <0>;
2769
2770                                 ports {
2771                                         #address-cells = <1>;
2772                                         #size-cells = <0>;
2773
2774                                         port@0 {
2775                                                 reg = <0>;
2776                                                 dpu_intf1_out: endpoint {
2777                                                         remote-endpoint = <&mdss_dsi0_in>;
2778                                                 };
2779                                         };
2780
2781                                         port@1 {
2782                                                 reg = <1>;
2783                                                 dpu_intf2_out: endpoint {
2784                                                         remote-endpoint = <&mdss_dsi1_in>;
2785                                                 };
2786                                         };
2787
2788                                         port@2 {
2789                                                 reg = <2>;
2790                                                 dpu_intf0_out: endpoint {
2791                                                         remote-endpoint = <&mdss_dp0_in>;
2792                                                 };
2793                                         };
2794                                 };
2795
2796                                 mdp_opp_table: opp-table {
2797                                         compatible = "operating-points-v2";
2798
2799                                         opp-172000000 {
2800                                                 opp-hz = /bits/ 64 <172000000>;
2801                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
2802                                         };
2803
2804                                         opp-200000000 {
2805                                                 opp-hz = /bits/ 64 <200000000>;
2806                                                 required-opps = <&rpmhpd_opp_low_svs>;
2807                                         };
2808
2809                                         opp-325000000 {
2810                                                 opp-hz = /bits/ 64 <325000000>;
2811                                                 required-opps = <&rpmhpd_opp_svs>;
2812                                         };
2813
2814                                         opp-375000000 {
2815                                                 opp-hz = /bits/ 64 <375000000>;
2816                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2817                                         };
2818
2819                                         opp-500000000 {
2820                                                 opp-hz = /bits/ 64 <500000000>;
2821                                                 required-opps = <&rpmhpd_opp_nom>;
2822                                         };
2823                                 };
2824                         };
2825
2826                         mdss_dp0: displayport-controller@ae90000 {
2827                                 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
2828                                 reg = <0 0xae90000 0 0x200>,
2829                                       <0 0xae90200 0 0x200>,
2830                                       <0 0xae90400 0 0xc00>,
2831                                       <0 0xae91000 0 0x400>,
2832                                       <0 0xae91400 0 0x400>;
2833                                 interrupt-parent = <&mdss>;
2834                                 interrupts = <12>;
2835                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2836                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2837                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2838                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2839                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2840                                 clock-names = "core_iface",
2841                                               "core_aux",
2842                                               "ctrl_link",
2843                                               "ctrl_link_iface",
2844                                               "stream_pixel";
2845
2846                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2847                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2848                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2849                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2850
2851                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
2852                                 phy-names = "dp";
2853
2854                                 #sound-dai-cells = <0>;
2855
2856                                 operating-points-v2 = <&dp_opp_table>;
2857                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2858
2859                                 status = "disabled";
2860
2861                                 ports {
2862                                         #address-cells = <1>;
2863                                         #size-cells = <0>;
2864
2865                                         port@0 {
2866                                                 reg = <0>;
2867                                                 mdss_dp0_in: endpoint {
2868                                                         remote-endpoint = <&dpu_intf0_out>;
2869                                                 };
2870                                         };
2871                                 };
2872
2873                                 dp_opp_table: opp-table {
2874                                         compatible = "operating-points-v2";
2875
2876                                         opp-160000000 {
2877                                                 opp-hz = /bits/ 64 <160000000>;
2878                                                 required-opps = <&rpmhpd_opp_low_svs>;
2879                                         };
2880
2881                                         opp-270000000 {
2882                                                 opp-hz = /bits/ 64 <270000000>;
2883                                                 required-opps = <&rpmhpd_opp_svs>;
2884                                         };
2885
2886                                         opp-540000000 {
2887                                                 opp-hz = /bits/ 64 <540000000>;
2888                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2889                                         };
2890
2891                                         opp-810000000 {
2892                                                 opp-hz = /bits/ 64 <810000000>;
2893                                                 required-opps = <&rpmhpd_opp_nom>;
2894                                         };
2895                                 };
2896                         };
2897
2898                         mdss_dsi0: dsi@ae94000 {
2899                                 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2900                                 reg = <0 0x0ae94000 0 0x400>;
2901                                 reg-names = "dsi_ctrl";
2902
2903                                 interrupt-parent = <&mdss>;
2904                                 interrupts = <4>;
2905
2906                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2907                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2908                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2909                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2910                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2911                                         <&gcc GCC_DISP_HF_AXI_CLK>;
2912                                 clock-names = "byte",
2913                                               "byte_intf",
2914                                               "pixel",
2915                                               "core",
2916                                               "iface",
2917                                               "bus";
2918
2919                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2920                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2921
2922                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2923                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2924
2925                                 phys = <&mdss_dsi0_phy>;
2926                                 phy-names = "dsi";
2927
2928                                 #address-cells = <1>;
2929                                 #size-cells = <0>;
2930
2931                                 status = "disabled";
2932
2933                                 ports {
2934                                         #address-cells = <1>;
2935                                         #size-cells = <0>;
2936
2937                                         port@0 {
2938                                                 reg = <0>;
2939                                                 mdss_dsi0_in: endpoint {
2940                                                         remote-endpoint = <&dpu_intf1_out>;
2941                                                 };
2942                                         };
2943
2944                                         port@1 {
2945                                                 reg = <1>;
2946                                                 mdss_dsi0_out: endpoint {
2947                                                 };
2948                                         };
2949                                 };
2950
2951                                 mdss_dsi_opp_table: opp-table {
2952                                         compatible = "operating-points-v2";
2953
2954                                         opp-187500000 {
2955                                                 opp-hz = /bits/ 64 <187500000>;
2956                                                 required-opps = <&rpmhpd_opp_low_svs>;
2957                                         };
2958
2959                                         opp-300000000 {
2960                                                 opp-hz = /bits/ 64 <300000000>;
2961                                                 required-opps = <&rpmhpd_opp_svs>;
2962                                         };
2963
2964                                         opp-358000000 {
2965                                                 opp-hz = /bits/ 64 <358000000>;
2966                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2967                                         };
2968                                 };
2969                         };
2970
2971                         mdss_dsi0_phy: phy@ae94400 {
2972                                 compatible = "qcom,sm8450-dsi-phy-5nm";
2973                                 reg = <0 0x0ae94400 0 0x200>,
2974                                       <0 0x0ae94600 0 0x280>,
2975                                       <0 0x0ae94900 0 0x260>;
2976                                 reg-names = "dsi_phy",
2977                                             "dsi_phy_lane",
2978                                             "dsi_pll";
2979
2980                                 #clock-cells = <1>;
2981                                 #phy-cells = <0>;
2982
2983                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2984                                          <&rpmhcc RPMH_CXO_CLK>;
2985                                 clock-names = "iface", "ref";
2986
2987                                 status = "disabled";
2988                         };
2989
2990                         mdss_dsi1: dsi@ae96000 {
2991                                 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2992                                 reg = <0 0x0ae96000 0 0x400>;
2993                                 reg-names = "dsi_ctrl";
2994
2995                                 interrupt-parent = <&mdss>;
2996                                 interrupts = <5>;
2997
2998                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2999                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3000                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3001                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3002                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3003                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3004                                 clock-names = "byte",
3005                                               "byte_intf",
3006                                               "pixel",
3007                                               "core",
3008                                               "iface",
3009                                               "bus";
3010
3011                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3012                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3013
3014                                 operating-points-v2 = <&mdss_dsi_opp_table>;
3015                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
3016
3017                                 phys = <&mdss_dsi1_phy>;
3018                                 phy-names = "dsi";
3019
3020                                 #address-cells = <1>;
3021                                 #size-cells = <0>;
3022
3023                                 status = "disabled";
3024
3025                                 ports {
3026                                         #address-cells = <1>;
3027                                         #size-cells = <0>;
3028
3029                                         port@0 {
3030                                                 reg = <0>;
3031                                                 mdss_dsi1_in: endpoint {
3032                                                         remote-endpoint = <&dpu_intf2_out>;
3033                                                 };
3034                                         };
3035
3036                                         port@1 {
3037                                                 reg = <1>;
3038                                                 mdss_dsi1_out: endpoint {
3039                                                 };
3040                                         };
3041                                 };
3042                         };
3043
3044                         mdss_dsi1_phy: phy@ae96400 {
3045                                 compatible = "qcom,sm8450-dsi-phy-5nm";
3046                                 reg = <0 0x0ae96400 0 0x200>,
3047                                       <0 0x0ae96600 0 0x280>,
3048                                       <0 0x0ae96900 0 0x260>;
3049                                 reg-names = "dsi_phy",
3050                                             "dsi_phy_lane",
3051                                             "dsi_pll";
3052
3053                                 #clock-cells = <1>;
3054                                 #phy-cells = <0>;
3055
3056                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3057                                          <&rpmhcc RPMH_CXO_CLK>;
3058                                 clock-names = "iface", "ref";
3059
3060                                 status = "disabled";
3061                         };
3062                 };
3063
3064                 dispcc: clock-controller@af00000 {
3065                         compatible = "qcom,sm8450-dispcc";
3066                         reg = <0 0x0af00000 0 0x20000>;
3067                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3068                                  <&rpmhcc RPMH_CXO_CLK_A>,
3069                                  <&gcc GCC_DISP_AHB_CLK>,
3070                                  <&sleep_clk>,
3071                                  <&mdss_dsi0_phy 0>,
3072                                  <&mdss_dsi0_phy 1>,
3073                                  <&mdss_dsi1_phy 0>,
3074                                  <&mdss_dsi1_phy 1>,
3075                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3076                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3077                                  <0>, /* dp1 */
3078                                  <0>,
3079                                  <0>, /* dp2 */
3080                                  <0>,
3081                                  <0>, /* dp3 */
3082                                  <0>;
3083                         power-domains = <&rpmhpd RPMHPD_MMCX>;
3084                         required-opps = <&rpmhpd_opp_low_svs>;
3085                         #clock-cells = <1>;
3086                         #reset-cells = <1>;
3087                         #power-domain-cells = <1>;
3088                         status = "disabled";
3089                 };
3090
3091                 pdc: interrupt-controller@b220000 {
3092                         compatible = "qcom,sm8450-pdc", "qcom,pdc";
3093                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3094                         qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3095                                           <94 609 31>, <125 63 1>, <126 716 12>;
3096                         #interrupt-cells = <2>;
3097                         interrupt-parent = <&intc>;
3098                         interrupt-controller;
3099                 };
3100
3101                 tsens0: thermal-sensor@c263000 {
3102                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3103                         reg = <0 0x0c263000 0 0x1000>, /* TM */
3104                               <0 0x0c222000 0 0x1000>; /* SROT */
3105                         #qcom,sensors = <16>;
3106                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3107                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3108                         interrupt-names = "uplow", "critical";
3109                         #thermal-sensor-cells = <1>;
3110                 };
3111
3112                 tsens1: thermal-sensor@c265000 {
3113                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3114                         reg = <0 0x0c265000 0 0x1000>, /* TM */
3115                               <0 0x0c223000 0 0x1000>; /* SROT */
3116                         #qcom,sensors = <16>;
3117                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3118                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3119                         interrupt-names = "uplow", "critical";
3120                         #thermal-sensor-cells = <1>;
3121                 };
3122
3123                 aoss_qmp: power-management@c300000 {
3124                         compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3125                         reg = <0 0x0c300000 0 0x400>;
3126                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3127                                                      IRQ_TYPE_EDGE_RISING>;
3128                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3129
3130                         #clock-cells = <0>;
3131                 };
3132
3133                 sram@c3f0000 {
3134                         compatible = "qcom,rpmh-stats";
3135                         reg = <0 0x0c3f0000 0 0x400>;
3136                 };
3137
3138                 spmi_bus: spmi@c400000 {
3139                         compatible = "qcom,spmi-pmic-arb";
3140                         reg = <0 0x0c400000 0 0x00003000>,
3141                               <0 0x0c500000 0 0x00400000>,
3142                               <0 0x0c440000 0 0x00080000>,
3143                               <0 0x0c4c0000 0 0x00010000>,
3144                               <0 0x0c42d000 0 0x00010000>;
3145                         reg-names = "core",
3146                                     "chnls",
3147                                     "obsrvr",
3148                                     "intr",
3149                                     "cnfg";
3150                         interrupt-names = "periph_irq";
3151                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3152                         qcom,ee = <0>;
3153                         qcom,channel = <0>;
3154                         interrupt-controller;
3155                         #interrupt-cells = <4>;
3156                         #address-cells = <2>;
3157                         #size-cells = <0>;
3158                 };
3159
3160                 ipcc: mailbox@ed18000 {
3161                         compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3162                         reg = <0 0x0ed18000 0 0x1000>;
3163                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3164                         interrupt-controller;
3165                         #interrupt-cells = <3>;
3166                         #mbox-cells = <2>;
3167                 };
3168
3169                 tlmm: pinctrl@f100000 {
3170                         compatible = "qcom,sm8450-tlmm";
3171                         reg = <0 0x0f100000 0 0x300000>;
3172                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3173                         gpio-controller;
3174                         #gpio-cells = <2>;
3175                         interrupt-controller;
3176                         #interrupt-cells = <2>;
3177                         gpio-ranges = <&tlmm 0 0 211>;
3178                         wakeup-parent = <&pdc>;
3179
3180                         sdc2_default_state: sdc2-default-state {
3181                                 clk-pins {
3182                                         pins = "sdc2_clk";
3183                                         drive-strength = <16>;
3184                                         bias-disable;
3185                                 };
3186
3187                                 cmd-pins {
3188                                         pins = "sdc2_cmd";
3189                                         drive-strength = <16>;
3190                                         bias-pull-up;
3191                                 };
3192
3193                                 data-pins {
3194                                         pins = "sdc2_data";
3195                                         drive-strength = <16>;
3196                                         bias-pull-up;
3197                                 };
3198                         };
3199
3200                         sdc2_sleep_state: sdc2-sleep-state {
3201                                 clk-pins {
3202                                         pins = "sdc2_clk";
3203                                         drive-strength = <2>;
3204                                         bias-disable;
3205                                 };
3206
3207                                 cmd-pins {
3208                                         pins = "sdc2_cmd";
3209                                         drive-strength = <2>;
3210                                         bias-pull-up;
3211                                 };
3212
3213                                 data-pins {
3214                                         pins = "sdc2_data";
3215                                         drive-strength = <2>;
3216                                         bias-pull-up;
3217                                 };
3218                         };
3219
3220                         cci0_default: cci0-default-state {
3221                                 /* SDA, SCL */
3222                                 pins = "gpio110", "gpio111";
3223                                 function = "cci_i2c";
3224                                 drive-strength = <2>;
3225                                 bias-pull-up;
3226                         };
3227
3228                         cci0_sleep: cci0-sleep-state {
3229                                 /* SDA, SCL */
3230                                 pins = "gpio110", "gpio111";
3231                                 function = "cci_i2c";
3232                                 drive-strength = <2>;
3233                                 bias-pull-down;
3234                         };
3235
3236                         cci1_default: cci1-default-state {
3237                                 /* SDA, SCL */
3238                                 pins = "gpio112", "gpio113";
3239                                 function = "cci_i2c";
3240                                 drive-strength = <2>;
3241                                 bias-pull-up;
3242                         };
3243
3244                         cci1_sleep: cci1-sleep-state {
3245                                 /* SDA, SCL */
3246                                 pins = "gpio112", "gpio113";
3247                                 function = "cci_i2c";
3248                                 drive-strength = <2>;
3249                                 bias-pull-down;
3250                         };
3251
3252                         cci2_default: cci2-default-state {
3253                                 /* SDA, SCL */
3254                                 pins = "gpio114", "gpio115";
3255                                 function = "cci_i2c";
3256                                 drive-strength = <2>;
3257                                 bias-pull-up;
3258                         };
3259
3260                         cci2_sleep: cci2-sleep-state {
3261                                 /* SDA, SCL */
3262                                 pins = "gpio114", "gpio115";
3263                                 function = "cci_i2c";
3264                                 drive-strength = <2>;
3265                                 bias-pull-down;
3266                         };
3267
3268                         cci3_default: cci3-default-state {
3269                                 /* SDA, SCL */
3270                                 pins = "gpio208", "gpio209";
3271                                 function = "cci_i2c";
3272                                 drive-strength = <2>;
3273                                 bias-pull-up;
3274                         };
3275
3276                         cci3_sleep: cci3-sleep-state {
3277                                 /* SDA, SCL */
3278                                 pins = "gpio208", "gpio209";
3279                                 function = "cci_i2c";
3280                                 drive-strength = <2>;
3281                                 bias-pull-down;
3282                         };
3283
3284                         pcie0_default_state: pcie0-default-state {
3285                                 perst-pins {
3286                                         pins = "gpio94";
3287                                         function = "gpio";
3288                                         drive-strength = <2>;
3289                                         bias-pull-down;
3290                                 };
3291
3292                                 clkreq-pins {
3293                                         pins = "gpio95";
3294                                         function = "pcie0_clkreqn";
3295                                         drive-strength = <2>;
3296                                         bias-pull-up;
3297                                 };
3298
3299                                 wake-pins {
3300                                         pins = "gpio96";
3301                                         function = "gpio";
3302                                         drive-strength = <2>;
3303                                         bias-pull-up;
3304                                 };
3305                         };
3306
3307                         pcie1_default_state: pcie1-default-state {
3308                                 perst-pins {
3309                                         pins = "gpio97";
3310                                         function = "gpio";
3311                                         drive-strength = <2>;
3312                                         bias-pull-down;
3313                                 };
3314
3315                                 clkreq-pins {
3316                                         pins = "gpio98";
3317                                         function = "pcie1_clkreqn";
3318                                         drive-strength = <2>;
3319                                         bias-pull-up;
3320                                 };
3321
3322                                 wake-pins {
3323                                         pins = "gpio99";
3324                                         function = "gpio";
3325                                         drive-strength = <2>;
3326                                         bias-pull-up;
3327                                 };
3328                         };
3329
3330                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3331                                 pins = "gpio0", "gpio1";
3332                                 function = "qup0";
3333                         };
3334
3335                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3336                                 pins = "gpio4", "gpio5";
3337                                 function = "qup1";
3338                         };
3339
3340                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3341                                 pins = "gpio8", "gpio9";
3342                                 function = "qup2";
3343                         };
3344
3345                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3346                                 pins = "gpio12", "gpio13";
3347                                 function = "qup3";
3348                         };
3349
3350                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3351                                 pins = "gpio16", "gpio17";
3352                                 function = "qup4";
3353                         };
3354
3355                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3356                                 pins = "gpio206", "gpio207";
3357                                 function = "qup5";
3358                         };
3359
3360                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3361                                 pins = "gpio20", "gpio21";
3362                                 function = "qup6";
3363                         };
3364
3365                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3366                                 pins = "gpio28", "gpio29";
3367                                 function = "qup8";
3368                         };
3369
3370                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3371                                 pins = "gpio32", "gpio33";
3372                                 function = "qup9";
3373                         };
3374
3375                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3376                                 pins = "gpio36", "gpio37";
3377                                 function = "qup10";
3378                         };
3379
3380                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3381                                 pins = "gpio40", "gpio41";
3382                                 function = "qup11";
3383                         };
3384
3385                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3386                                 pins = "gpio44", "gpio45";
3387                                 function = "qup12";
3388                         };
3389
3390                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3391                                 pins = "gpio48", "gpio49";
3392                                 function = "qup13";
3393                                 drive-strength = <2>;
3394                                 bias-pull-up;
3395                         };
3396
3397                         qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3398                                 pins = "gpio52", "gpio53";
3399                                 function = "qup14";
3400                                 drive-strength = <2>;
3401                                 bias-pull-up;
3402                         };
3403
3404                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3405                                 pins = "gpio56", "gpio57";
3406                                 function = "qup15";
3407                         };
3408
3409                         qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3410                                 pins = "gpio60", "gpio61";
3411                                 function = "qup16";
3412                         };
3413
3414                         qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3415                                 pins = "gpio64", "gpio65";
3416                                 function = "qup17";
3417                         };
3418
3419                         qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3420                                 pins = "gpio68", "gpio69";
3421                                 function = "qup18";
3422                         };
3423
3424                         qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3425                                 pins = "gpio72", "gpio73";
3426                                 function = "qup19";
3427                         };
3428
3429                         qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3430                                 pins = "gpio76", "gpio77";
3431                                 function = "qup20";
3432                         };
3433
3434                         qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3435                                 pins = "gpio80", "gpio81";
3436                                 function = "qup21";
3437                         };
3438
3439                         qup_spi0_cs: qup-spi0-cs-state {
3440                                 pins = "gpio3";
3441                                 function = "qup0";
3442                         };
3443
3444                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3445                                 pins = "gpio0", "gpio1", "gpio2";
3446                                 function = "qup0";
3447                         };
3448
3449                         qup_spi1_cs: qup-spi1-cs-state {
3450                                 pins = "gpio7";
3451                                 function = "qup1";
3452                         };
3453
3454                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3455                                 pins = "gpio4", "gpio5", "gpio6";
3456                                 function = "qup1";
3457                         };
3458
3459                         qup_spi2_cs: qup-spi2-cs-state {
3460                                 pins = "gpio11";
3461                                 function = "qup2";
3462                         };
3463
3464                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3465                                 pins = "gpio8", "gpio9", "gpio10";
3466                                 function = "qup2";
3467                         };
3468
3469                         qup_spi3_cs: qup-spi3-cs-state {
3470                                 pins = "gpio15";
3471                                 function = "qup3";
3472                         };
3473
3474                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3475                                 pins = "gpio12", "gpio13", "gpio14";
3476                                 function = "qup3";
3477                         };
3478
3479                         qup_spi4_cs: qup-spi4-cs-state {
3480                                 pins = "gpio19";
3481                                 function = "qup4";
3482                                 drive-strength = <6>;
3483                                 bias-disable;
3484                         };
3485
3486                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3487                                 pins = "gpio16", "gpio17", "gpio18";
3488                                 function = "qup4";
3489                         };
3490
3491                         qup_spi5_cs: qup-spi5-cs-state {
3492                                 pins = "gpio85";
3493                                 function = "qup5";
3494                         };
3495
3496                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3497                                 pins = "gpio206", "gpio207", "gpio84";
3498                                 function = "qup5";
3499                         };
3500
3501                         qup_spi6_cs: qup-spi6-cs-state {
3502                                 pins = "gpio23";
3503                                 function = "qup6";
3504                         };
3505
3506                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3507                                 pins = "gpio20", "gpio21", "gpio22";
3508                                 function = "qup6";
3509                         };
3510
3511                         qup_spi8_cs: qup-spi8-cs-state {
3512                                 pins = "gpio31";
3513                                 function = "qup8";
3514                         };
3515
3516                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3517                                 pins = "gpio28", "gpio29", "gpio30";
3518                                 function = "qup8";
3519                         };
3520
3521                         qup_spi9_cs: qup-spi9-cs-state {
3522                                 pins = "gpio35";
3523                                 function = "qup9";
3524                         };
3525
3526                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3527                                 pins = "gpio32", "gpio33", "gpio34";
3528                                 function = "qup9";
3529                         };
3530
3531                         qup_spi10_cs: qup-spi10-cs-state {
3532                                 pins = "gpio39";
3533                                 function = "qup10";
3534                         };
3535
3536                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3537                                 pins = "gpio36", "gpio37", "gpio38";
3538                                 function = "qup10";
3539                         };
3540
3541                         qup_spi11_cs: qup-spi11-cs-state {
3542                                 pins = "gpio43";
3543                                 function = "qup11";
3544                         };
3545
3546                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3547                                 pins = "gpio40", "gpio41", "gpio42";
3548                                 function = "qup11";
3549                         };
3550
3551                         qup_spi12_cs: qup-spi12-cs-state {
3552                                 pins = "gpio47";
3553                                 function = "qup12";
3554                         };
3555
3556                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3557                                 pins = "gpio44", "gpio45", "gpio46";
3558                                 function = "qup12";
3559                         };
3560
3561                         qup_spi13_cs: qup-spi13-cs-state {
3562                                 pins = "gpio51";
3563                                 function = "qup13";
3564                         };
3565
3566                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3567                                 pins = "gpio48", "gpio49", "gpio50";
3568                                 function = "qup13";
3569                         };
3570
3571                         qup_spi14_cs: qup-spi14-cs-state {
3572                                 pins = "gpio55";
3573                                 function = "qup14";
3574                         };
3575
3576                         qup_spi14_data_clk: qup-spi14-data-clk-state {
3577                                 pins = "gpio52", "gpio53", "gpio54";
3578                                 function = "qup14";
3579                         };
3580
3581                         qup_spi15_cs: qup-spi15-cs-state {
3582                                 pins = "gpio59";
3583                                 function = "qup15";
3584                         };
3585
3586                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3587                                 pins = "gpio56", "gpio57", "gpio58";
3588                                 function = "qup15";
3589                         };
3590
3591                         qup_spi16_cs: qup-spi16-cs-state {
3592                                 pins = "gpio63";
3593                                 function = "qup16";
3594                         };
3595
3596                         qup_spi16_data_clk: qup-spi16-data-clk-state {
3597                                 pins = "gpio60", "gpio61", "gpio62";
3598                                 function = "qup16";
3599                         };
3600
3601                         qup_spi17_cs: qup-spi17-cs-state {
3602                                 pins = "gpio67";
3603                                 function = "qup17";
3604                         };
3605
3606                         qup_spi17_data_clk: qup-spi17-data-clk-state {
3607                                 pins = "gpio64", "gpio65", "gpio66";
3608                                 function = "qup17";
3609                         };
3610
3611                         qup_spi18_cs: qup-spi18-cs-state {
3612                                 pins = "gpio71";
3613                                 function = "qup18";
3614                                 drive-strength = <6>;
3615                                 bias-disable;
3616                         };
3617
3618                         qup_spi18_data_clk: qup-spi18-data-clk-state {
3619                                 pins = "gpio68", "gpio69", "gpio70";
3620                                 function = "qup18";
3621                                 drive-strength = <6>;
3622                                 bias-disable;
3623                         };
3624
3625                         qup_spi19_cs: qup-spi19-cs-state {
3626                                 pins = "gpio75";
3627                                 function = "qup19";
3628                                 drive-strength = <6>;
3629                                 bias-disable;
3630                         };
3631
3632                         qup_spi19_data_clk: qup-spi19-data-clk-state {
3633                                 pins = "gpio72", "gpio73", "gpio74";
3634                                 function = "qup19";
3635                                 drive-strength = <6>;
3636                                 bias-disable;
3637                         };
3638
3639                         qup_spi20_cs: qup-spi20-cs-state {
3640                                 pins = "gpio79";
3641                                 function = "qup20";
3642                         };
3643
3644                         qup_spi20_data_clk: qup-spi20-data-clk-state {
3645                                 pins = "gpio76", "gpio77", "gpio78";
3646                                 function = "qup20";
3647                         };
3648
3649                         qup_spi21_cs: qup-spi21-cs-state {
3650                                 pins = "gpio83";
3651                                 function = "qup21";
3652                         };
3653
3654                         qup_spi21_data_clk: qup-spi21-data-clk-state {
3655                                 pins = "gpio80", "gpio81", "gpio82";
3656                                 function = "qup21";
3657                         };
3658
3659                         qup_uart7_rx: qup-uart7-rx-state {
3660                                 pins = "gpio26";
3661                                 function = "qup7";
3662                                 drive-strength = <2>;
3663                                 bias-disable;
3664                         };
3665
3666                         qup_uart7_tx: qup-uart7-tx-state {
3667                                 pins = "gpio27";
3668                                 function = "qup7";
3669                                 drive-strength = <2>;
3670                                 bias-disable;
3671                         };
3672
3673                         qup_uart20_default: qup-uart20-default-state {
3674                                 pins = "gpio76", "gpio77", "gpio78", "gpio79";
3675                                 function = "qup20";
3676                         };
3677                 };
3678
3679                 lpass_tlmm: pinctrl@3440000 {
3680                         compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3681                         reg = <0 0x03440000 0x0 0x20000>,
3682                               <0 0x034d0000 0x0 0x10000>;
3683                         gpio-controller;
3684                         #gpio-cells = <2>;
3685                         gpio-ranges = <&lpass_tlmm 0 0 23>;
3686
3687                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
3688                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
3689                         clock-names = "core", "audio";
3690
3691                         tx_swr_active: tx-swr-active-state {
3692                                 clk-pins {
3693                                         pins = "gpio0";
3694                                         function = "swr_tx_clk";
3695                                         drive-strength = <2>;
3696                                         slew-rate = <1>;
3697                                         bias-disable;
3698                                 };
3699
3700                                 data-pins {
3701                                         pins = "gpio1", "gpio2", "gpio14";
3702                                         function = "swr_tx_data";
3703                                         drive-strength = <2>;
3704                                         slew-rate = <1>;
3705                                         bias-bus-hold;
3706                                 };
3707                         };
3708
3709                         rx_swr_active: rx-swr-active-state {
3710                                 clk-pins {
3711                                         pins = "gpio3";
3712                                         function = "swr_rx_clk";
3713                                         drive-strength = <2>;
3714                                         slew-rate = <1>;
3715                                         bias-disable;
3716                                 };
3717
3718                                 data-pins {
3719                                         pins = "gpio4", "gpio5";
3720                                         function = "swr_rx_data";
3721                                         drive-strength = <2>;
3722                                         slew-rate = <1>;
3723                                         bias-bus-hold;
3724                                 };
3725                         };
3726
3727                         dmic01_default: dmic01-default-state {
3728                                 clk-pins {
3729                                         pins = "gpio6";
3730                                         function = "dmic1_clk";
3731                                         drive-strength = <8>;
3732                                         output-high;
3733                                 };
3734
3735                                 data-pins {
3736                                         pins = "gpio7";
3737                                         function = "dmic1_data";
3738                                         drive-strength = <8>;
3739                                 };
3740                         };
3741
3742                         dmic02_default: dmic02-default-state {
3743                                 clk-pins {
3744                                         pins = "gpio8";
3745                                         function = "dmic2_clk";
3746                                         drive-strength = <8>;
3747                                         output-high;
3748                                 };
3749
3750                                 data-pins {
3751                                         pins = "gpio9";
3752                                         function = "dmic2_data";
3753                                         drive-strength = <8>;
3754                                 };
3755                         };
3756
3757                         wsa_swr_active: wsa-swr-active-state {
3758                                 clk-pins {
3759                                         pins = "gpio10";
3760                                         function = "wsa_swr_clk";
3761                                         drive-strength = <2>;
3762                                         slew-rate = <1>;
3763                                         bias-disable;
3764                                 };
3765
3766                                 data-pins {
3767                                         pins = "gpio11";
3768                                         function = "wsa_swr_data";
3769                                         drive-strength = <2>;
3770                                         slew-rate = <1>;
3771                                         bias-bus-hold;
3772                                 };
3773                         };
3774
3775                         wsa2_swr_active: wsa2-swr-active-state {
3776                                 clk-pins {
3777                                         pins = "gpio15";
3778                                         function = "wsa2_swr_clk";
3779                                         drive-strength = <2>;
3780                                         slew-rate = <1>;
3781                                         bias-disable;
3782                                 };
3783
3784                                 data-pins {
3785                                         pins = "gpio16";
3786                                         function = "wsa2_swr_data";
3787                                         drive-strength = <2>;
3788                                         slew-rate = <1>;
3789                                         bias-bus-hold;
3790                                 };
3791                         };
3792                 };
3793
3794                 sram@146aa000 {
3795                         compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3796                         reg = <0 0x146aa000 0 0x1000>;
3797                         ranges = <0 0 0x146aa000 0x1000>;
3798
3799                         #address-cells = <1>;
3800                         #size-cells = <1>;
3801
3802                         pil-reloc@94c {
3803                                 compatible = "qcom,pil-reloc-info";
3804                                 reg = <0x94c 0xc8>;
3805                         };
3806                 };
3807
3808                 apps_smmu: iommu@15000000 {
3809                         compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
3810                         reg = <0 0x15000000 0 0x100000>;
3811                         #iommu-cells = <2>;
3812                         #global-interrupts = <1>;
3813                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3814                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3815                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3816                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3817                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3818                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3819                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3820                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3821                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3822                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3823                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3824                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3825                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3826                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3827                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3828                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3829                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3830                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3831                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3832                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3833                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3834                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3835                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3836                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3837                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3838                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3839                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3840                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3841                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3842                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3843                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3844                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3845                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3846                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3847                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3848                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3849                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3850                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3851                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3852                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3853                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3854                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3855                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3856                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3857                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3858                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3859                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3860                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3861                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3862                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3863                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3864                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3865                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3866                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3867                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3868                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3869                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3870                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3871                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3872                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3873                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3874                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3875                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3876                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3877                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3878                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3879                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3880                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3881                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3882                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3883                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3884                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3885                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3886                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3887                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3888                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3889                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3890                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3892                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3893                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3894                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3895                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3896                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3897                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3898                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3899                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3900                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3901                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3902                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3903                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3904                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3905                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3906                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3907                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3908                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
3909                                      <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
3910                 };
3911
3912                 intc: interrupt-controller@17100000 {
3913                         compatible = "arm,gic-v3";
3914                         #interrupt-cells = <3>;
3915                         interrupt-controller;
3916                         #redistributor-regions = <1>;
3917                         redistributor-stride = <0x0 0x40000>;
3918                         reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
3919                               <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
3920                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3921                         #address-cells = <2>;
3922                         #size-cells = <2>;
3923                         ranges;
3924
3925                         gic_its: msi-controller@17140000 {
3926                                 compatible = "arm,gic-v3-its";
3927                                 reg = <0x0 0x17140000 0x0 0x20000>;
3928                                 msi-controller;
3929                                 #msi-cells = <1>;
3930                         };
3931                 };
3932
3933                 timer@17420000 {
3934                         compatible = "arm,armv7-timer-mem";
3935                         #address-cells = <1>;
3936                         #size-cells = <1>;
3937                         ranges = <0 0 0 0x20000000>;
3938                         reg = <0x0 0x17420000 0x0 0x1000>;
3939                         clock-frequency = <19200000>;
3940
3941                         frame@17421000 {
3942                                 frame-number = <0>;
3943                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3944                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3945                                 reg = <0x17421000 0x1000>,
3946                                       <0x17422000 0x1000>;
3947                         };
3948
3949                         frame@17423000 {
3950                                 frame-number = <1>;
3951                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3952                                 reg = <0x17423000 0x1000>;
3953                                 status = "disabled";
3954                         };
3955
3956                         frame@17425000 {
3957                                 frame-number = <2>;
3958                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3959                                 reg = <0x17425000 0x1000>;
3960                                 status = "disabled";
3961                         };
3962
3963                         frame@17427000 {
3964                                 frame-number = <3>;
3965                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3966                                 reg = <0x17427000 0x1000>;
3967                                 status = "disabled";
3968                         };
3969
3970                         frame@17429000 {
3971                                 frame-number = <4>;
3972                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3973                                 reg = <0x17429000 0x1000>;
3974                                 status = "disabled";
3975                         };
3976
3977                         frame@1742b000 {
3978                                 frame-number = <5>;
3979                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3980                                 reg = <0x1742b000 0x1000>;
3981                                 status = "disabled";
3982                         };
3983
3984                         frame@1742d000 {
3985                                 frame-number = <6>;
3986                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3987                                 reg = <0x1742d000 0x1000>;
3988                                 status = "disabled";
3989                         };
3990                 };
3991
3992                 apps_rsc: rsc@17a00000 {
3993                         label = "apps_rsc";
3994                         compatible = "qcom,rpmh-rsc";
3995                         reg = <0x0 0x17a00000 0x0 0x10000>,
3996                               <0x0 0x17a10000 0x0 0x10000>,
3997                               <0x0 0x17a20000 0x0 0x10000>,
3998                               <0x0 0x17a30000 0x0 0x10000>;
3999                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4000                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4001                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4002                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4003                         qcom,tcs-offset = <0xd00>;
4004                         qcom,drv-id = <2>;
4005                         qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
4006                                           <WAKE_TCS    2>, <CONTROL_TCS 0>;
4007                         power-domains = <&CLUSTER_PD>;
4008
4009                         apps_bcm_voter: bcm-voter {
4010                                 compatible = "qcom,bcm-voter";
4011                         };
4012
4013                         rpmhcc: clock-controller {
4014                                 compatible = "qcom,sm8450-rpmh-clk";
4015                                 #clock-cells = <1>;
4016                                 clock-names = "xo";
4017                                 clocks = <&xo_board>;
4018                         };
4019
4020                         rpmhpd: power-controller {
4021                                 compatible = "qcom,sm8450-rpmhpd";
4022                                 #power-domain-cells = <1>;
4023                                 operating-points-v2 = <&rpmhpd_opp_table>;
4024
4025                                 rpmhpd_opp_table: opp-table {
4026                                         compatible = "operating-points-v2";
4027
4028                                         rpmhpd_opp_ret: opp1 {
4029                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4030                                         };
4031
4032                                         rpmhpd_opp_min_svs: opp2 {
4033                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4034                                         };
4035
4036                                         rpmhpd_opp_low_svs_d1: opp3 {
4037                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4038                                         };
4039
4040                                         rpmhpd_opp_low_svs: opp4 {
4041                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4042                                         };
4043
4044                                         rpmhpd_opp_low_svs_l1: opp5 {
4045                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4046                                         };
4047
4048                                         rpmhpd_opp_svs: opp6 {
4049                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4050                                         };
4051
4052                                         rpmhpd_opp_svs_l0: opp7 {
4053                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4054                                         };
4055
4056                                         rpmhpd_opp_svs_l1: opp8 {
4057                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4058                                         };
4059
4060                                         rpmhpd_opp_svs_l2: opp9 {
4061                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4062                                         };
4063
4064                                         rpmhpd_opp_nom: opp10 {
4065                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4066                                         };
4067
4068                                         rpmhpd_opp_nom_l1: opp11 {
4069                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4070                                         };
4071
4072                                         rpmhpd_opp_nom_l2: opp12 {
4073                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4074                                         };
4075
4076                                         rpmhpd_opp_turbo: opp13 {
4077                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4078                                         };
4079
4080                                         rpmhpd_opp_turbo_l1: opp14 {
4081                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4082                                         };
4083                                 };
4084                         };
4085                 };
4086
4087                 cpufreq_hw: cpufreq@17d91000 {
4088                         compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4089                         reg = <0 0x17d91000 0 0x1000>,
4090                               <0 0x17d92000 0 0x1000>,
4091                               <0 0x17d93000 0 0x1000>;
4092                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4093                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4094                         clock-names = "xo", "alternate";
4095                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4096                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4097                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4098                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4099                         #freq-domain-cells = <1>;
4100                         #clock-cells = <1>;
4101                 };
4102
4103                 gem_noc: interconnect@19100000 {
4104                         compatible = "qcom,sm8450-gem-noc";
4105                         reg = <0 0x19100000 0 0xbb800>;
4106                         #interconnect-cells = <2>;
4107                         qcom,bcm-voters = <&apps_bcm_voter>;
4108                 };
4109
4110                 system-cache-controller@19200000 {
4111                         compatible = "qcom,sm8450-llcc";
4112                         reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4113                               <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4114                               <0 0x19a00000 0 0x80000>;
4115                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4116                                     "llcc3_base", "llcc_broadcast_base";
4117                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4118                 };
4119
4120                 ufs_mem_hc: ufshc@1d84000 {
4121                         compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4122                                      "jedec,ufs-2.0";
4123                         reg = <0 0x01d84000 0 0x3000>;
4124                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
4125                         phys = <&ufs_mem_phy_lanes>;
4126                         phy-names = "ufsphy";
4127                         lanes-per-direction = <2>;
4128                         #reset-cells = <1>;
4129                         resets = <&gcc GCC_UFS_PHY_BCR>;
4130                         reset-names = "rst";
4131
4132                         power-domains = <&gcc UFS_PHY_GDSC>;
4133
4134                         iommus = <&apps_smmu 0xe0 0x0>;
4135                         dma-coherent;
4136
4137                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4138                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4139                         interconnect-names = "ufs-ddr", "cpu-ufs";
4140                         clock-names =
4141                                 "core_clk",
4142                                 "bus_aggr_clk",
4143                                 "iface_clk",
4144                                 "core_clk_unipro",
4145                                 "ref_clk",
4146                                 "tx_lane0_sync_clk",
4147                                 "rx_lane0_sync_clk",
4148                                 "rx_lane1_sync_clk";
4149                         clocks =
4150                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
4151                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
4152                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
4153                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
4154                                 <&rpmhcc RPMH_CXO_CLK>,
4155                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
4156                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
4157                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
4158                         freq-table-hz =
4159                                 <75000000 300000000>,
4160                                 <0 0>,
4161                                 <0 0>,
4162                                 <75000000 300000000>,
4163                                 <75000000 300000000>,
4164                                 <0 0>,
4165                                 <0 0>,
4166                                 <0 0>;
4167                         qcom,ice = <&ice>;
4168
4169                         status = "disabled";
4170                 };
4171
4172                 ufs_mem_phy: phy@1d87000 {
4173                         compatible = "qcom,sm8450-qmp-ufs-phy";
4174                         reg = <0 0x01d87000 0 0x1c4>;
4175                         #address-cells = <2>;
4176                         #size-cells = <2>;
4177                         ranges;
4178                         clock-names = "ref", "ref_aux", "qref";
4179                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4180                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
4181                                  <&gcc GCC_UFS_0_CLKREF_EN>;
4182
4183                         resets = <&ufs_mem_hc 0>;
4184                         reset-names = "ufsphy";
4185                         status = "disabled";
4186
4187                         ufs_mem_phy_lanes: phy@1d87400 {
4188                                 reg = <0 0x01d87400 0 0x188>,
4189                                       <0 0x01d87600 0 0x200>,
4190                                       <0 0x01d87c00 0 0x200>,
4191                                       <0 0x01d87800 0 0x188>,
4192                                       <0 0x01d87a00 0 0x200>;
4193                                 #clock-cells = <1>;
4194                                 #phy-cells = <0>;
4195                         };
4196                 };
4197
4198                 ice: crypto@1d88000 {
4199                         compatible = "qcom,sm8450-inline-crypto-engine",
4200                                      "qcom,inline-crypto-engine";
4201                         reg = <0 0x01d88000 0 0x8000>;
4202                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
4203                 };
4204
4205                 cryptobam: dma-controller@1dc4000 {
4206                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4207                         reg = <0 0x01dc4000 0 0x28000>;
4208                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4209                         #dma-cells = <1>;
4210                         qcom,ee = <0>;
4211                         qcom,controlled-remotely;
4212                         iommus = <&apps_smmu 0x584 0x11>,
4213                                  <&apps_smmu 0x588 0x0>,
4214                                  <&apps_smmu 0x598 0x5>,
4215                                  <&apps_smmu 0x59a 0x0>,
4216                                  <&apps_smmu 0x59f 0x0>;
4217                 };
4218
4219                 crypto: crypto@1dfa000 {
4220                         compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4221                         reg = <0 0x01dfa000 0 0x6000>;
4222                         dmas = <&cryptobam 4>, <&cryptobam 5>;
4223                         dma-names = "rx", "tx";
4224                         iommus = <&apps_smmu 0x584 0x11>,
4225                                  <&apps_smmu 0x588 0x0>,
4226                                  <&apps_smmu 0x598 0x5>,
4227                                  <&apps_smmu 0x59a 0x0>,
4228                                  <&apps_smmu 0x59f 0x0>;
4229                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4230                         interconnect-names = "memory";
4231                 };
4232
4233                 sdhc_2: mmc@8804000 {
4234                         compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4235                         reg = <0 0x08804000 0 0x1000>;
4236
4237                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4238                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4239                         interrupt-names = "hc_irq", "pwr_irq";
4240
4241                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4242                                  <&gcc GCC_SDCC2_APPS_CLK>,
4243                                  <&rpmhcc RPMH_CXO_CLK>;
4244                         clock-names = "iface", "core", "xo";
4245                         resets = <&gcc GCC_SDCC2_BCR>;
4246                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4247                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4248                         interconnect-names = "sdhc-ddr","cpu-sdhc";
4249                         iommus = <&apps_smmu 0x4a0 0x0>;
4250                         power-domains = <&rpmhpd RPMHPD_CX>;
4251                         operating-points-v2 = <&sdhc2_opp_table>;
4252                         bus-width = <4>;
4253                         dma-coherent;
4254
4255                         /* Forbid SDR104/SDR50 - broken hw! */
4256                         sdhci-caps-mask = <0x3 0x0>;
4257
4258                         status = "disabled";
4259
4260                         sdhc2_opp_table: opp-table {
4261                                 compatible = "operating-points-v2";
4262
4263                                 opp-100000000 {
4264                                         opp-hz = /bits/ 64 <100000000>;
4265                                         required-opps = <&rpmhpd_opp_low_svs>;
4266                                 };
4267
4268                                 opp-202000000 {
4269                                         opp-hz = /bits/ 64 <202000000>;
4270                                         required-opps = <&rpmhpd_opp_svs_l1>;
4271                                 };
4272                         };
4273                 };
4274
4275                 usb_1: usb@a6f8800 {
4276                         compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4277                         reg = <0 0x0a6f8800 0 0x400>;
4278                         status = "disabled";
4279                         #address-cells = <2>;
4280                         #size-cells = <2>;
4281                         ranges;
4282
4283                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4284                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4285                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4286                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4287                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4288                                  <&gcc GCC_USB3_0_CLKREF_EN>;
4289                         clock-names = "cfg_noc",
4290                                       "core",
4291                                       "iface",
4292                                       "sleep",
4293                                       "mock_utmi",
4294                                       "xo";
4295
4296                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4297                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4298                         assigned-clock-rates = <19200000>, <200000000>;
4299
4300                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4301                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4302                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4303                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4304                         interrupt-names = "hs_phy_irq",
4305                                           "ss_phy_irq",
4306                                           "dm_hs_phy_irq",
4307                                           "dp_hs_phy_irq";
4308
4309                         power-domains = <&gcc USB30_PRIM_GDSC>;
4310
4311                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4312
4313                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4314                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4315                         interconnect-names = "usb-ddr", "apps-usb";
4316
4317                         usb_1_dwc3: usb@a600000 {
4318                                 compatible = "snps,dwc3";
4319                                 reg = <0 0x0a600000 0 0xcd00>;
4320                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4321                                 iommus = <&apps_smmu 0x0 0x0>;
4322                                 snps,dis_u2_susphy_quirk;
4323                                 snps,dis_enblslpm_quirk;
4324                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4325                                 phy-names = "usb2-phy", "usb3-phy";
4326
4327                                 ports {
4328                                         #address-cells = <1>;
4329                                         #size-cells = <0>;
4330
4331                                         port@0 {
4332                                                 reg = <0>;
4333
4334                                                 usb_1_dwc3_hs: endpoint {
4335                                                 };
4336                                         };
4337
4338                                         port@1 {
4339                                                 reg = <1>;
4340
4341                                                 usb_1_dwc3_ss: endpoint {
4342                                                 };
4343                                         };
4344                                 };
4345                         };
4346                 };
4347
4348                 nsp_noc: interconnect@320c0000 {
4349                         compatible = "qcom,sm8450-nsp-noc";
4350                         reg = <0 0x320c0000 0 0x10000>;
4351                         #interconnect-cells = <2>;
4352                         qcom,bcm-voters = <&apps_bcm_voter>;
4353                 };
4354
4355                 lpass_ag_noc: interconnect@3c40000 {
4356                         compatible = "qcom,sm8450-lpass-ag-noc";
4357                         reg = <0 0x03c40000 0 0x17200>;
4358                         #interconnect-cells = <2>;
4359                         qcom,bcm-voters = <&apps_bcm_voter>;
4360                 };
4361         };
4362
4363         sound: sound {
4364         };
4365
4366         thermal-zones {
4367                 aoss0-thermal {
4368                         polling-delay-passive = <0>;
4369                         polling-delay = <0>;
4370                         thermal-sensors = <&tsens0 0>;
4371
4372                         trips {
4373                                 thermal-engine-config {
4374                                         temperature = <125000>;
4375                                         hysteresis = <1000>;
4376                                         type = "passive";
4377                                 };
4378
4379                                 reset-mon-cfg {
4380                                         temperature = <115000>;
4381                                         hysteresis = <5000>;
4382                                         type = "passive";
4383                                 };
4384                         };
4385                 };
4386
4387                 cpuss0-thermal {
4388                         polling-delay-passive = <0>;
4389                         polling-delay = <0>;
4390                         thermal-sensors = <&tsens0 1>;
4391
4392                         trips {
4393                                 thermal-engine-config {
4394                                         temperature = <125000>;
4395                                         hysteresis = <1000>;
4396                                         type = "passive";
4397                                 };
4398
4399                                 reset-mon-cfg {
4400                                         temperature = <115000>;
4401                                         hysteresis = <5000>;
4402                                         type = "passive";
4403                                 };
4404                         };
4405                 };
4406
4407                 cpuss1-thermal {
4408                         polling-delay-passive = <0>;
4409                         polling-delay = <0>;
4410                         thermal-sensors = <&tsens0 2>;
4411
4412                         trips {
4413                                 thermal-engine-config {
4414                                         temperature = <125000>;
4415                                         hysteresis = <1000>;
4416                                         type = "passive";
4417                                 };
4418
4419                                 reset-mon-cfg {
4420                                         temperature = <115000>;
4421                                         hysteresis = <5000>;
4422                                         type = "passive";
4423                                 };
4424                         };
4425                 };
4426
4427                 cpuss3-thermal {
4428                         polling-delay-passive = <0>;
4429                         polling-delay = <0>;
4430                         thermal-sensors = <&tsens0 3>;
4431
4432                         trips {
4433                                 thermal-engine-config {
4434                                         temperature = <125000>;
4435                                         hysteresis = <1000>;
4436                                         type = "passive";
4437                                 };
4438
4439                                 reset-mon-cfg {
4440                                         temperature = <115000>;
4441                                         hysteresis = <5000>;
4442                                         type = "passive";
4443                                 };
4444                         };
4445                 };
4446
4447                 cpuss4-thermal {
4448                         polling-delay-passive = <0>;
4449                         polling-delay = <0>;
4450                         thermal-sensors = <&tsens0 4>;
4451
4452                         trips {
4453                                 thermal-engine-config {
4454                                         temperature = <125000>;
4455                                         hysteresis = <1000>;
4456                                         type = "passive";
4457                                 };
4458
4459                                 reset-mon-cfg {
4460                                         temperature = <115000>;
4461                                         hysteresis = <5000>;
4462                                         type = "passive";
4463                                 };
4464                         };
4465                 };
4466
4467                 cpu4-top-thermal {
4468                         polling-delay-passive = <0>;
4469                         polling-delay = <0>;
4470                         thermal-sensors = <&tsens0 5>;
4471
4472                         trips {
4473                                 cpu4_top_alert0: trip-point0 {
4474                                         temperature = <90000>;
4475                                         hysteresis = <2000>;
4476                                         type = "passive";
4477                                 };
4478
4479                                 cpu4_top_alert1: trip-point1 {
4480                                         temperature = <95000>;
4481                                         hysteresis = <2000>;
4482                                         type = "passive";
4483                                 };
4484
4485                                 cpu4_top_crit: cpu-crit {
4486                                         temperature = <110000>;
4487                                         hysteresis = <1000>;
4488                                         type = "critical";
4489                                 };
4490                         };
4491                 };
4492
4493                 cpu4-bottom-thermal {
4494                         polling-delay-passive = <0>;
4495                         polling-delay = <0>;
4496                         thermal-sensors = <&tsens0 6>;
4497
4498                         trips {
4499                                 cpu4_bottom_alert0: trip-point0 {
4500                                         temperature = <90000>;
4501                                         hysteresis = <2000>;
4502                                         type = "passive";
4503                                 };
4504
4505                                 cpu4_bottom_alert1: trip-point1 {
4506                                         temperature = <95000>;
4507                                         hysteresis = <2000>;
4508                                         type = "passive";
4509                                 };
4510
4511                                 cpu4_bottom_crit: cpu-crit {
4512                                         temperature = <110000>;
4513                                         hysteresis = <1000>;
4514                                         type = "critical";
4515                                 };
4516                         };
4517                 };
4518
4519                 cpu5-top-thermal {
4520                         polling-delay-passive = <0>;
4521                         polling-delay = <0>;
4522                         thermal-sensors = <&tsens0 7>;
4523
4524                         trips {
4525                                 cpu5_top_alert0: trip-point0 {
4526                                         temperature = <90000>;
4527                                         hysteresis = <2000>;
4528                                         type = "passive";
4529                                 };
4530
4531                                 cpu5_top_alert1: trip-point1 {
4532                                         temperature = <95000>;
4533                                         hysteresis = <2000>;
4534                                         type = "passive";
4535                                 };
4536
4537                                 cpu5_top_crit: cpu-crit {
4538                                         temperature = <110000>;
4539                                         hysteresis = <1000>;
4540                                         type = "critical";
4541                                 };
4542                         };
4543                 };
4544
4545                 cpu5-bottom-thermal {
4546                         polling-delay-passive = <0>;
4547                         polling-delay = <0>;
4548                         thermal-sensors = <&tsens0 8>;
4549
4550                         trips {
4551                                 cpu5_bottom_alert0: trip-point0 {
4552                                         temperature = <90000>;
4553                                         hysteresis = <2000>;
4554                                         type = "passive";
4555                                 };
4556
4557                                 cpu5_bottom_alert1: trip-point1 {
4558                                         temperature = <95000>;
4559                                         hysteresis = <2000>;
4560                                         type = "passive";
4561                                 };
4562
4563                                 cpu5_bottom_crit: cpu-crit {
4564                                         temperature = <110000>;
4565                                         hysteresis = <1000>;
4566                                         type = "critical";
4567                                 };
4568                         };
4569                 };
4570
4571                 cpu6-top-thermal {
4572                         polling-delay-passive = <0>;
4573                         polling-delay = <0>;
4574                         thermal-sensors = <&tsens0 9>;
4575
4576                         trips {
4577                                 cpu6_top_alert0: trip-point0 {
4578                                         temperature = <90000>;
4579                                         hysteresis = <2000>;
4580                                         type = "passive";
4581                                 };
4582
4583                                 cpu6_top_alert1: trip-point1 {
4584                                         temperature = <95000>;
4585                                         hysteresis = <2000>;
4586                                         type = "passive";
4587                                 };
4588
4589                                 cpu6_top_crit: cpu-crit {
4590                                         temperature = <110000>;
4591                                         hysteresis = <1000>;
4592                                         type = "critical";
4593                                 };
4594                         };
4595                 };
4596
4597                 cpu6-bottom-thermal {
4598                         polling-delay-passive = <0>;
4599                         polling-delay = <0>;
4600                         thermal-sensors = <&tsens0 10>;
4601
4602                         trips {
4603                                 cpu6_bottom_alert0: trip-point0 {
4604                                         temperature = <90000>;
4605                                         hysteresis = <2000>;
4606                                         type = "passive";
4607                                 };
4608
4609                                 cpu6_bottom_alert1: trip-point1 {
4610                                         temperature = <95000>;
4611                                         hysteresis = <2000>;
4612                                         type = "passive";
4613                                 };
4614
4615                                 cpu6_bottom_crit: cpu-crit {
4616                                         temperature = <110000>;
4617                                         hysteresis = <1000>;
4618                                         type = "critical";
4619                                 };
4620                         };
4621                 };
4622
4623                 cpu7-top-thermal {
4624                         polling-delay-passive = <0>;
4625                         polling-delay = <0>;
4626                         thermal-sensors = <&tsens0 11>;
4627
4628                         trips {
4629                                 cpu7_top_alert0: trip-point0 {
4630                                         temperature = <90000>;
4631                                         hysteresis = <2000>;
4632                                         type = "passive";
4633                                 };
4634
4635                                 cpu7_top_alert1: trip-point1 {
4636                                         temperature = <95000>;
4637                                         hysteresis = <2000>;
4638                                         type = "passive";
4639                                 };
4640
4641                                 cpu7_top_crit: cpu-crit {
4642                                         temperature = <110000>;
4643                                         hysteresis = <1000>;
4644                                         type = "critical";
4645                                 };
4646                         };
4647                 };
4648
4649                 cpu7-middle-thermal {
4650                         polling-delay-passive = <0>;
4651                         polling-delay = <0>;
4652                         thermal-sensors = <&tsens0 12>;
4653
4654                         trips {
4655                                 cpu7_middle_alert0: trip-point0 {
4656                                         temperature = <90000>;
4657                                         hysteresis = <2000>;
4658                                         type = "passive";
4659                                 };
4660
4661                                 cpu7_middle_alert1: trip-point1 {
4662                                         temperature = <95000>;
4663                                         hysteresis = <2000>;
4664                                         type = "passive";
4665                                 };
4666
4667                                 cpu7_middle_crit: cpu-crit {
4668                                         temperature = <110000>;
4669                                         hysteresis = <1000>;
4670                                         type = "critical";
4671                                 };
4672                         };
4673                 };
4674
4675                 cpu7-bottom-thermal {
4676                         polling-delay-passive = <0>;
4677                         polling-delay = <0>;
4678                         thermal-sensors = <&tsens0 13>;
4679
4680                         trips {
4681                                 cpu7_bottom_alert0: trip-point0 {
4682                                         temperature = <90000>;
4683                                         hysteresis = <2000>;
4684                                         type = "passive";
4685                                 };
4686
4687                                 cpu7_bottom_alert1: trip-point1 {
4688                                         temperature = <95000>;
4689                                         hysteresis = <2000>;
4690                                         type = "passive";
4691                                 };
4692
4693                                 cpu7_bottom_crit: cpu-crit {
4694                                         temperature = <110000>;
4695                                         hysteresis = <1000>;
4696                                         type = "critical";
4697                                 };
4698                         };
4699                 };
4700
4701                 gpu-top-thermal {
4702                         polling-delay-passive = <10>;
4703                         polling-delay = <0>;
4704                         thermal-sensors = <&tsens0 14>;
4705
4706                         trips {
4707                                 thermal-engine-config {
4708                                         temperature = <125000>;
4709                                         hysteresis = <1000>;
4710                                         type = "passive";
4711                                 };
4712
4713                                 thermal-hal-config {
4714                                         temperature = <125000>;
4715                                         hysteresis = <1000>;
4716                                         type = "passive";
4717                                 };
4718
4719                                 reset-mon-cfg {
4720                                         temperature = <115000>;
4721                                         hysteresis = <5000>;
4722                                         type = "passive";
4723                                 };
4724
4725                                 gpu0_tj_cfg: tj-cfg {
4726                                         temperature = <95000>;
4727                                         hysteresis = <5000>;
4728                                         type = "passive";
4729                                 };
4730                         };
4731                 };
4732
4733                 gpu-bottom-thermal {
4734                         polling-delay-passive = <10>;
4735                         polling-delay = <0>;
4736                         thermal-sensors = <&tsens0 15>;
4737
4738                         trips {
4739                                 thermal-engine-config {
4740                                         temperature = <125000>;
4741                                         hysteresis = <1000>;
4742                                         type = "passive";
4743                                 };
4744
4745                                 thermal-hal-config {
4746                                         temperature = <125000>;
4747                                         hysteresis = <1000>;
4748                                         type = "passive";
4749                                 };
4750
4751                                 reset-mon-cfg {
4752                                         temperature = <115000>;
4753                                         hysteresis = <5000>;
4754                                         type = "passive";
4755                                 };
4756
4757                                 gpu1_tj_cfg: tj-cfg {
4758                                         temperature = <95000>;
4759                                         hysteresis = <5000>;
4760                                         type = "passive";
4761                                 };
4762                         };
4763                 };
4764
4765                 aoss1-thermal {
4766                         polling-delay-passive = <0>;
4767                         polling-delay = <0>;
4768                         thermal-sensors = <&tsens1 0>;
4769
4770                         trips {
4771                                 thermal-engine-config {
4772                                         temperature = <125000>;
4773                                         hysteresis = <1000>;
4774                                         type = "passive";
4775                                 };
4776
4777                                 reset-mon-cfg {
4778                                         temperature = <115000>;
4779                                         hysteresis = <5000>;
4780                                         type = "passive";
4781                                 };
4782                         };
4783                 };
4784
4785                 cpu0-thermal {
4786                         polling-delay-passive = <0>;
4787                         polling-delay = <0>;
4788                         thermal-sensors = <&tsens1 1>;
4789
4790                         trips {
4791                                 cpu0_alert0: trip-point0 {
4792                                         temperature = <90000>;
4793                                         hysteresis = <2000>;
4794                                         type = "passive";
4795                                 };
4796
4797                                 cpu0_alert1: trip-point1 {
4798                                         temperature = <95000>;
4799                                         hysteresis = <2000>;
4800                                         type = "passive";
4801                                 };
4802
4803                                 cpu0_crit: cpu-crit {
4804                                         temperature = <110000>;
4805                                         hysteresis = <1000>;
4806                                         type = "critical";
4807                                 };
4808                         };
4809                 };
4810
4811                 cpu1-thermal {
4812                         polling-delay-passive = <0>;
4813                         polling-delay = <0>;
4814                         thermal-sensors = <&tsens1 2>;
4815
4816                         trips {
4817                                 cpu1_alert0: trip-point0 {
4818                                         temperature = <90000>;
4819                                         hysteresis = <2000>;
4820                                         type = "passive";
4821                                 };
4822
4823                                 cpu1_alert1: trip-point1 {
4824                                         temperature = <95000>;
4825                                         hysteresis = <2000>;
4826                                         type = "passive";
4827                                 };
4828
4829                                 cpu1_crit: cpu-crit {
4830                                         temperature = <110000>;
4831                                         hysteresis = <1000>;
4832                                         type = "critical";
4833                                 };
4834                         };
4835                 };
4836
4837                 cpu2-thermal {
4838                         polling-delay-passive = <0>;
4839                         polling-delay = <0>;
4840                         thermal-sensors = <&tsens1 3>;
4841
4842                         trips {
4843                                 cpu2_alert0: trip-point0 {
4844                                         temperature = <90000>;
4845                                         hysteresis = <2000>;
4846                                         type = "passive";
4847                                 };
4848
4849                                 cpu2_alert1: trip-point1 {
4850                                         temperature = <95000>;
4851                                         hysteresis = <2000>;
4852                                         type = "passive";
4853                                 };
4854
4855                                 cpu2_crit: cpu-crit {
4856                                         temperature = <110000>;
4857                                         hysteresis = <1000>;
4858                                         type = "critical";
4859                                 };
4860                         };
4861                 };
4862
4863                 cpu3-thermal {
4864                         polling-delay-passive = <0>;
4865                         polling-delay = <0>;
4866                         thermal-sensors = <&tsens1 4>;
4867
4868                         trips {
4869                                 cpu3_alert0: trip-point0 {
4870                                         temperature = <90000>;
4871                                         hysteresis = <2000>;
4872                                         type = "passive";
4873                                 };
4874
4875                                 cpu3_alert1: trip-point1 {
4876                                         temperature = <95000>;
4877                                         hysteresis = <2000>;
4878                                         type = "passive";
4879                                 };
4880
4881                                 cpu3_crit: cpu-crit {
4882                                         temperature = <110000>;
4883                                         hysteresis = <1000>;
4884                                         type = "critical";
4885                                 };
4886                         };
4887                 };
4888
4889                 cdsp0-thermal {
4890                         polling-delay-passive = <10>;
4891                         polling-delay = <0>;
4892                         thermal-sensors = <&tsens1 5>;
4893
4894                         trips {
4895                                 thermal-engine-config {
4896                                         temperature = <125000>;
4897                                         hysteresis = <1000>;
4898                                         type = "passive";
4899                                 };
4900
4901                                 thermal-hal-config {
4902                                         temperature = <125000>;
4903                                         hysteresis = <1000>;
4904                                         type = "passive";
4905                                 };
4906
4907                                 reset-mon-cfg {
4908                                         temperature = <115000>;
4909                                         hysteresis = <5000>;
4910                                         type = "passive";
4911                                 };
4912
4913                                 cdsp_0_config: junction-config {
4914                                         temperature = <95000>;
4915                                         hysteresis = <5000>;
4916                                         type = "passive";
4917                                 };
4918                         };
4919                 };
4920
4921                 cdsp1-thermal {
4922                         polling-delay-passive = <10>;
4923                         polling-delay = <0>;
4924                         thermal-sensors = <&tsens1 6>;
4925
4926                         trips {
4927                                 thermal-engine-config {
4928                                         temperature = <125000>;
4929                                         hysteresis = <1000>;
4930                                         type = "passive";
4931                                 };
4932
4933                                 thermal-hal-config {
4934                                         temperature = <125000>;
4935                                         hysteresis = <1000>;
4936                                         type = "passive";
4937                                 };
4938
4939                                 reset-mon-cfg {
4940                                         temperature = <115000>;
4941                                         hysteresis = <5000>;
4942                                         type = "passive";
4943                                 };
4944
4945                                 cdsp_1_config: junction-config {
4946                                         temperature = <95000>;
4947                                         hysteresis = <5000>;
4948                                         type = "passive";
4949                                 };
4950                         };
4951                 };
4952
4953                 cdsp2-thermal {
4954                         polling-delay-passive = <10>;
4955                         polling-delay = <0>;
4956                         thermal-sensors = <&tsens1 7>;
4957
4958                         trips {
4959                                 thermal-engine-config {
4960                                         temperature = <125000>;
4961                                         hysteresis = <1000>;
4962                                         type = "passive";
4963                                 };
4964
4965                                 thermal-hal-config {
4966                                         temperature = <125000>;
4967                                         hysteresis = <1000>;
4968                                         type = "passive";
4969                                 };
4970
4971                                 reset-mon-cfg {
4972                                         temperature = <115000>;
4973                                         hysteresis = <5000>;
4974                                         type = "passive";
4975                                 };
4976
4977                                 cdsp_2_config: junction-config {
4978                                         temperature = <95000>;
4979                                         hysteresis = <5000>;
4980                                         type = "passive";
4981                                 };
4982                         };
4983                 };
4984
4985                 video-thermal {
4986                         polling-delay-passive = <0>;
4987                         polling-delay = <0>;
4988                         thermal-sensors = <&tsens1 8>;
4989
4990                         trips {
4991                                 thermal-engine-config {
4992                                         temperature = <125000>;
4993                                         hysteresis = <1000>;
4994                                         type = "passive";
4995                                 };
4996
4997                                 reset-mon-cfg {
4998                                         temperature = <115000>;
4999                                         hysteresis = <5000>;
5000                                         type = "passive";
5001                                 };
5002                         };
5003                 };
5004
5005                 mem-thermal {
5006                         polling-delay-passive = <10>;
5007                         polling-delay = <0>;
5008                         thermal-sensors = <&tsens1 9>;
5009
5010                         trips {
5011                                 thermal-engine-config {
5012                                         temperature = <125000>;
5013                                         hysteresis = <1000>;
5014                                         type = "passive";
5015                                 };
5016
5017                                 ddr_config0: ddr0-config {
5018                                         temperature = <90000>;
5019                                         hysteresis = <5000>;
5020                                         type = "passive";
5021                                 };
5022
5023                                 reset-mon-cfg {
5024                                         temperature = <115000>;
5025                                         hysteresis = <5000>;
5026                                         type = "passive";
5027                                 };
5028                         };
5029                 };
5030
5031                 modem0-thermal {
5032                         polling-delay-passive = <0>;
5033                         polling-delay = <0>;
5034                         thermal-sensors = <&tsens1 10>;
5035
5036                         trips {
5037                                 thermal-engine-config {
5038                                         temperature = <125000>;
5039                                         hysteresis = <1000>;
5040                                         type = "passive";
5041                                 };
5042
5043                                 mdmss0_config0: mdmss0-config0 {
5044                                         temperature = <102000>;
5045                                         hysteresis = <3000>;
5046                                         type = "passive";
5047                                 };
5048
5049                                 mdmss0_config1: mdmss0-config1 {
5050                                         temperature = <105000>;
5051                                         hysteresis = <3000>;
5052                                         type = "passive";
5053                                 };
5054
5055                                 reset-mon-cfg {
5056                                         temperature = <115000>;
5057                                         hysteresis = <5000>;
5058                                         type = "passive";
5059                                 };
5060                         };
5061                 };
5062
5063                 modem1-thermal {
5064                         polling-delay-passive = <0>;
5065                         polling-delay = <0>;
5066                         thermal-sensors = <&tsens1 11>;
5067
5068                         trips {
5069                                 thermal-engine-config {
5070                                         temperature = <125000>;
5071                                         hysteresis = <1000>;
5072                                         type = "passive";
5073                                 };
5074
5075                                 mdmss1_config0: mdmss1-config0 {
5076                                         temperature = <102000>;
5077                                         hysteresis = <3000>;
5078                                         type = "passive";
5079                                 };
5080
5081                                 mdmss1_config1: mdmss1-config1 {
5082                                         temperature = <105000>;
5083                                         hysteresis = <3000>;
5084                                         type = "passive";
5085                                 };
5086
5087                                 reset-mon-cfg {
5088                                         temperature = <115000>;
5089                                         hysteresis = <5000>;
5090                                         type = "passive";
5091                                 };
5092                         };
5093                 };
5094
5095                 modem2-thermal {
5096                         polling-delay-passive = <0>;
5097                         polling-delay = <0>;
5098                         thermal-sensors = <&tsens1 12>;
5099
5100                         trips {
5101                                 thermal-engine-config {
5102                                         temperature = <125000>;
5103                                         hysteresis = <1000>;
5104                                         type = "passive";
5105                                 };
5106
5107                                 mdmss2_config0: mdmss2-config0 {
5108                                         temperature = <102000>;
5109                                         hysteresis = <3000>;
5110                                         type = "passive";
5111                                 };
5112
5113                                 mdmss2_config1: mdmss2-config1 {
5114                                         temperature = <105000>;
5115                                         hysteresis = <3000>;
5116                                         type = "passive";
5117                                 };
5118
5119                                 reset-mon-cfg {
5120                                         temperature = <115000>;
5121                                         hysteresis = <5000>;
5122                                         type = "passive";
5123                                 };
5124                         };
5125                 };
5126
5127                 modem3-thermal {
5128                         polling-delay-passive = <0>;
5129                         polling-delay = <0>;
5130                         thermal-sensors = <&tsens1 13>;
5131
5132                         trips {
5133                                 thermal-engine-config {
5134                                         temperature = <125000>;
5135                                         hysteresis = <1000>;
5136                                         type = "passive";
5137                                 };
5138
5139                                 mdmss3_config0: mdmss3-config0 {
5140                                         temperature = <102000>;
5141                                         hysteresis = <3000>;
5142                                         type = "passive";
5143                                 };
5144
5145                                 mdmss3_config1: mdmss3-config1 {
5146                                         temperature = <105000>;
5147                                         hysteresis = <3000>;
5148                                         type = "passive";
5149                                 };
5150
5151                                 reset-mon-cfg {
5152                                         temperature = <115000>;
5153                                         hysteresis = <5000>;
5154                                         type = "passive";
5155                                 };
5156                         };
5157                 };
5158
5159                 camera0-thermal {
5160                         polling-delay-passive = <0>;
5161                         polling-delay = <0>;
5162                         thermal-sensors = <&tsens1 14>;
5163
5164                         trips {
5165                                 thermal-engine-config {
5166                                         temperature = <125000>;
5167                                         hysteresis = <1000>;
5168                                         type = "passive";
5169                                 };
5170
5171                                 reset-mon-cfg {
5172                                         temperature = <115000>;
5173                                         hysteresis = <5000>;
5174                                         type = "passive";
5175                                 };
5176                         };
5177                 };
5178
5179                 camera1-thermal {
5180                         polling-delay-passive = <0>;
5181                         polling-delay = <0>;
5182                         thermal-sensors = <&tsens1 15>;
5183
5184                         trips {
5185                                 thermal-engine-config {
5186                                         temperature = <125000>;
5187                                         hysteresis = <1000>;
5188                                         type = "passive";
5189                                 };
5190
5191                                 reset-mon-cfg {
5192                                         temperature = <115000>;
5193                                         hysteresis = <5000>;
5194                                         type = "passive";
5195                                 };
5196                         };
5197                 };
5198         };
5199
5200         timer {
5201                 compatible = "arm,armv8-timer";
5202                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5203                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5204                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5205                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5206                 clock-frequency = <19200000>;
5207         };
5208 };