arch/arm64/boot/dts/qcom/sm8450.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
  10 #include <dt-bindings/dma/qcom-gpi.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/mailbox/qcom-ipcc.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/interconnect/qcom,sm8450.h>
  15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <76800000>;
  31                 };
  32
  33                 sleep_clk: sleep-clk {
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <32000>;
  37                 };
  38         };
  39
  40         cpus {
  41                 #address-cells = <2>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "qcom,kryo780";
  47                         reg = <0x0 0x0>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&L2_0>;
  50                         power-domains = <&CPU_PD0>;
  51                         power-domain-names = "psci";
  52                         qcom,freq-domain = <&cpufreq_hw 0>;
  53                         #cooling-cells = <2>;
  54                         L2_0: l2-cache {
  55                               compatible = "cache";
  56                               next-level-cache = <&L3_0>;
  57                                 L3_0: l3-cache {
  58                                       compatible = "cache";
  59                                 };
  60                         };
  61                 };
  62
  63                 CPU1: cpu@100 {
  64                         device_type = "cpu";
  65                         compatible = "qcom,kryo780";
  66                         reg = <0x0 0x100>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&L2_100>;
  69                         power-domains = <&CPU_PD1>;
  70                         power-domain-names = "psci";
  71                         qcom,freq-domain = <&cpufreq_hw 0>;
  72                         #cooling-cells = <2>;
  73                         L2_100: l2-cache {
  74                               compatible = "cache";
  75                               next-level-cache = <&L3_0>;
  76                         };
  77                 };
  78
  79                 CPU2: cpu@200 {
  80                         device_type = "cpu";
  81                         compatible = "qcom,kryo780";
  82                         reg = <0x0 0x200>;
  83                         enable-method = "psci";
  84                         next-level-cache = <&L2_200>;
  85                         power-domains = <&CPU_PD2>;
  86                         power-domain-names = "psci";
  87                         qcom,freq-domain = <&cpufreq_hw 0>;
  88                         #cooling-cells = <2>;
  89                         L2_200: l2-cache {
  90                               compatible = "cache";
  91                               next-level-cache = <&L3_0>;
  92                         };
  93                 };
  94
  95                 CPU3: cpu@300 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo780";
  98                         reg = <0x0 0x300>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_300>;
 101                         power-domains = <&CPU_PD3>;
 102                         power-domain-names = "psci";
 103                         qcom,freq-domain = <&cpufreq_hw 0>;
 104                         #cooling-cells = <2>;
 105                         L2_300: l2-cache {
 106                               compatible = "cache";
 107                               next-level-cache = <&L3_0>;
 108                         };
 109                 };
 110
 111                 CPU4: cpu@400 {
 112                         device_type = "cpu";
 113                         compatible = "qcom,kryo780";
 114                         reg = <0x0 0x400>;
 115                         enable-method = "psci";
 116                         next-level-cache = <&L2_400>;
 117                         power-domains = <&CPU_PD4>;
 118                         power-domain-names = "psci";
 119                         qcom,freq-domain = <&cpufreq_hw 1>;
 120                         #cooling-cells = <2>;
 121                         L2_400: l2-cache {
 122                               compatible = "cache";
 123                               next-level-cache = <&L3_0>;
 124                         };
 125                 };
 126
 127                 CPU5: cpu@500 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo780";
 130                         reg = <0x0 0x500>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&L2_500>;
 133                         power-domains = <&CPU_PD5>;
 134                         power-domain-names = "psci";
 135                         qcom,freq-domain = <&cpufreq_hw 1>;
 136                         #cooling-cells = <2>;
 137                         L2_500: l2-cache {
 138                               compatible = "cache";
 139                               next-level-cache = <&L3_0>;
 140                         };
 141
 142                 };
 143
 144                 CPU6: cpu@600 {
 145                         device_type = "cpu";
 146                         compatible = "qcom,kryo780";
 147                         reg = <0x0 0x600>;
 148                         enable-method = "psci";
 149                         next-level-cache = <&L2_600>;
 150                         power-domains = <&CPU_PD6>;
 151                         power-domain-names = "psci";
 152                         qcom,freq-domain = <&cpufreq_hw 1>;
 153                         #cooling-cells = <2>;
 154                         L2_600: l2-cache {
 155                               compatible = "cache";
 156                               next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159
 160                 CPU7: cpu@700 {
 161                         device_type = "cpu";
 162                         compatible = "qcom,kryo780";
 163                         reg = <0x0 0x700>;
 164                         enable-method = "psci";
 165                         next-level-cache = <&L2_700>;
 166                         power-domains = <&CPU_PD7>;
 167                         power-domain-names = "psci";
 168                         qcom,freq-domain = <&cpufreq_hw 2>;
 169                         #cooling-cells = <2>;
 170                         L2_700: l2-cache {
 171                               compatible = "cache";
 172                               next-level-cache = <&L3_0>;
 173                         };
 174                 };
 175
 176                 cpu-map {
 177                         cluster0 {
 178                                 core0 {
 179                                         cpu = <&CPU0>;
 180                                 };
 181
 182                                 core1 {
 183                                         cpu = <&CPU1>;
 184                                 };
 185
 186                                 core2 {
 187                                         cpu = <&CPU2>;
 188                                 };
 189
 190                                 core3 {
 191                                         cpu = <&CPU3>;
 192                                 };
 193
 194                                 core4 {
 195                                         cpu = <&CPU4>;
 196                                 };
 197
 198                                 core5 {
 199                                         cpu = <&CPU5>;
 200                                 };
 201
 202                                 core6 {
 203                                         cpu = <&CPU6>;
 204                                 };
 205
 206                                 core7 {
 207                                         cpu = <&CPU7>;
 208                                 };
 209                         };
 210                 };
 211
 212                 idle-states {
 213                         entry-method = "psci";
 214
 215                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 216                                 compatible = "arm,idle-state";
 217                                 idle-state-name = "silver-rail-power-collapse";
 218                                 arm,psci-suspend-param = <0x40000004>;
 219                                 entry-latency-us = <800>;
 220                                 exit-latency-us = <750>;
 221                                 min-residency-us = <4090>;
 222                                 local-timer-stop;
 223                         };
 224
 225                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 226                                 compatible = "arm,idle-state";
 227                                 idle-state-name = "gold-rail-power-collapse";
 228                                 arm,psci-suspend-param = <0x40000004>;
 229                                 entry-latency-us = <600>;
 230                                 exit-latency-us = <1550>;
 231                                 min-residency-us = <4791>;
 232                                 local-timer-stop;
 233                         };
 234                 };
 235
 236                 domain-idle-states {
 237                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 238                                 compatible = "domain-idle-state";
 239                                 idle-state-name = "cluster-l3-off";
 240                                 arm,psci-suspend-param = <0x41000044>;
 241                                 entry-latency-us = <1050>;
 242                                 exit-latency-us = <2500>;
 243                                 min-residency-us = <5309>;
 244                                 local-timer-stop;
 245                         };
 246
 247                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 248                                 compatible = "domain-idle-state";
 249                                 idle-state-name = "cluster-power-collapse";
 250                                 arm,psci-suspend-param = <0x4100c344>;
 251                                 entry-latency-us = <2700>;
 252                                 exit-latency-us = <3500>;
 253                                 min-residency-us = <13959>;
 254                                 local-timer-stop;
 255                         };
 256                 };
 257         };
 258
 259         firmware {
 260                 scm: scm {
 261                         compatible = "qcom,scm-sm8450", "qcom,scm";
 262                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 263                         #reset-cells = <1>;
 264                 };
 265         };
 266
 267         clk_virt: interconnect-0 {
 268                 compatible = "qcom,sm8450-clk-virt";
 269                 #interconnect-cells = <2>;
 270                 qcom,bcm-voters = <&apps_bcm_voter>;
 271         };
 272
 273         mc_virt: interconnect-1 {
 274                 compatible = "qcom,sm8450-mc-virt";
 275                 #interconnect-cells = <2>;
 276                 qcom,bcm-voters = <&apps_bcm_voter>;
 277         };
 278
 279         memory@a0000000 {
 280                 device_type = "memory";
 281                 /* We expect the bootloader to fill in the size */
 282                 reg = <0x0 0xa0000000 0x0 0x0>;
 283         };
 284
 285         pmu {
 286                 compatible = "arm,armv8-pmuv3";
 287                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 288         };
 289
 290         psci {
 291                 compatible = "arm,psci-1.0";
 292                 method = "smc";
 293
 294                 CPU_PD0: cpu0 {
 295                         #power-domain-cells = <0>;
 296                         power-domains = <&CLUSTER_PD>;
 297                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 298                 };
 299
 300                 CPU_PD1: cpu1 {
 301                         #power-domain-cells = <0>;
 302                         power-domains = <&CLUSTER_PD>;
 303                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 304                 };
 305
 306                 CPU_PD2: cpu2 {
 307                         #power-domain-cells = <0>;
 308                         power-domains = <&CLUSTER_PD>;
 309                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 310                 };
 311
 312                 CPU_PD3: cpu3 {
 313                         #power-domain-cells = <0>;
 314                         power-domains = <&CLUSTER_PD>;
 315                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 316                 };
 317
 318                 CPU_PD4: cpu4 {
 319                         #power-domain-cells = <0>;
 320                         power-domains = <&CLUSTER_PD>;
 321                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 322                 };
 323
 324                 CPU_PD5: cpu5 {
 325                         #power-domain-cells = <0>;
 326                         power-domains = <&CLUSTER_PD>;
 327                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 328                 };
 329
 330                 CPU_PD6: cpu6 {
 331                         #power-domain-cells = <0>;
 332                         power-domains = <&CLUSTER_PD>;
 333                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 334                 };
 335
 336                 CPU_PD7: cpu7 {
 337                         #power-domain-cells = <0>;
 338                         power-domains = <&CLUSTER_PD>;
 339                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 340                 };
 341
 342                 CLUSTER_PD: cpu-cluster0 {
 343                         #power-domain-cells = <0>;
 344                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 345                 };
 346         };
 347
 348         qup_opp_table_100mhz: opp-table-qup {
 349                 compatible = "operating-points-v2";
 350
 351                 opp-50000000 {
 352                         opp-hz = /bits/ 64 <50000000>;
 353                         required-opps = <&rpmhpd_opp_min_svs>;
 354                 };
 355
 356                 opp-75000000 {
 357                         opp-hz = /bits/ 64 <75000000>;
 358                         required-opps = <&rpmhpd_opp_low_svs>;
 359                 };
 360
 361                 opp-100000000 {
 362                         opp-hz = /bits/ 64 <100000000>;
 363                         required-opps = <&rpmhpd_opp_svs>;
 364                 };
 365         };
 366
 367         reserved_memory: reserved-memory {
 368                 #address-cells = <2>;
 369                 #size-cells = <2>;
 370                 ranges;
 371
 372                 hyp_mem: memory@80000000 {
 373                         reg = <0x0 0x80000000 0x0 0x600000>;
 374                         no-map;
 375                 };
 376
 377                 xbl_dt_log_mem: memory@80600000 {
 378                         reg = <0x0 0x80600000 0x0 0x40000>;
 379                         no-map;
 380                 };
 381
 382                 xbl_ramdump_mem: memory@80640000 {
 383                         reg = <0x0 0x80640000 0x0 0x180000>;
 384                         no-map;
 385                 };
 386
 387                 xbl_sc_mem: memory@807c0000 {
 388                         reg = <0x0 0x807c0000 0x0 0x40000>;
 389                         no-map;
 390                 };
 391
 392                 aop_image_mem: memory@80800000 {
 393                         reg = <0x0 0x80800000 0x0 0x60000>;
 394                         no-map;
 395                 };
 396
 397                 aop_cmd_db_mem: memory@80860000 {
 398                         compatible = "qcom,cmd-db";
 399                         reg = <0x0 0x80860000 0x0 0x20000>;
 400                         no-map;
 401                 };
 402
 403                 aop_config_mem: memory@80880000 {
 404                         reg = <0x0 0x80880000 0x0 0x20000>;
 405                         no-map;
 406                 };
 407
 408                 tme_crash_dump_mem: memory@808a0000 {
 409                         reg = <0x0 0x808a0000 0x0 0x40000>;
 410                         no-map;
 411                 };
 412
 413                 tme_log_mem: memory@808e0000 {
 414                         reg = <0x0 0x808e0000 0x0 0x4000>;
 415                         no-map;
 416                 };
 417
 418                 uefi_log_mem: memory@808e4000 {
 419                         reg = <0x0 0x808e4000 0x0 0x10000>;
 420                         no-map;
 421                 };
 422
 423                 /* secdata region can be reused by apps */
 424                 smem: memory@80900000 {
 425                         compatible = "qcom,smem";
 426                         reg = <0x0 0x80900000 0x0 0x200000>;
 427                         hwlocks = <&tcsr_mutex 3>;
 428                         no-map;
 429                 };
 430
 431                 cpucp_fw_mem: memory@80b00000 {
 432                         reg = <0x0 0x80b00000 0x0 0x100000>;
 433                         no-map;
 434                 };
 435
 436                 cdsp_secure_heap: memory@80c00000 {
 437                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 438                         no-map;
 439                 };
 440
 441                 video_mem: memory@85700000 {
 442                         reg = <0x0 0x85700000 0x0 0x700000>;
 443                         no-map;
 444                 };
 445
 446                 adsp_mem: memory@85e00000 {
 447                         reg = <0x0 0x85e00000 0x0 0x2100000>;
 448                         no-map;
 449                 };
 450
 451                 slpi_mem: memory@88000000 {
 452                         reg = <0x0 0x88000000 0x0 0x1900000>;
 453                         no-map;
 454                 };
 455
 456                 cdsp_mem: memory@89900000 {
 457                         reg = <0x0 0x89900000 0x0 0x2000000>;
 458                         no-map;
 459                 };
 460
 461                 ipa_fw_mem: memory@8b900000 {
 462                         reg = <0x0 0x8b900000 0x0 0x10000>;
 463                         no-map;
 464                 };
 465
 466                 ipa_gsi_mem: memory@8b910000 {
 467                         reg = <0x0 0x8b910000 0x0 0xa000>;
 468                         no-map;
 469                 };
 470
 471                 gpu_micro_code_mem: memory@8b91a000 {
 472                         reg = <0x0 0x8b91a000 0x0 0x2000>;
 473                         no-map;
 474                 };
 475
 476                 spss_region_mem: memory@8ba00000 {
 477                         reg = <0x0 0x8ba00000 0x0 0x180000>;
 478                         no-map;
 479                 };
 480
 481                 /* First part of the "SPU secure shared memory" region */
 482                 spu_tz_shared_mem: memory@8bb80000 {
 483                         reg = <0x0 0x8bb80000 0x0 0x60000>;
 484                         no-map;
 485                 };
 486
 487                 /* Second part of the "SPU secure shared memory" region */
 488                 spu_modem_shared_mem: memory@8bbe0000 {
 489                         reg = <0x0 0x8bbe0000 0x0 0x20000>;
 490                         no-map;
 491                 };
 492
 493                 mpss_mem: memory@8bc00000 {
 494                         reg = <0x0 0x8bc00000 0x0 0x13200000>;
 495                         no-map;
 496                 };
 497
 498                 cvp_mem: memory@9ee00000 {
 499                         reg = <0x0 0x9ee00000 0x0 0x700000>;
 500                         no-map;
 501                 };
 502
 503                 camera_mem: memory@9f500000 {
 504                         reg = <0x0 0x9f500000 0x0 0x800000>;
 505                         no-map;
 506                 };
 507
 508                 rmtfs_mem: memory@9fd00000 {
 509                         compatible = "qcom,rmtfs-mem";
 510                         reg = <0x0 0x9fd00000 0x0 0x280000>;
 511                         no-map;
 512
 513                         qcom,client-id = <1>;
 514                         qcom,vmid = <15>;
 515                 };
 516
 517                 xbl_sc_mem2: memory@a6e00000 {
 518                         reg = <0x0 0xa6e00000 0x0 0x40000>;
 519                         no-map;
 520                 };
 521
 522                 global_sync_mem: memory@a6f00000 {
 523                         reg = <0x0 0xa6f00000 0x0 0x100000>;
 524                         no-map;
 525                 };
 526
 527                 /* uefi region can be reused by APPS */
 528
 529                 /* Linux kernel image is loaded at 0xa0000000 */
 530
 531                 oem_vm_mem: memory@bb000000 {
 532                         reg = <0x0 0xbb000000 0x0 0x5000000>;
 533                         no-map;
 534                 };
 535
 536                 mte_mem: memory@c0000000 {
 537                         reg = <0x0 0xc0000000 0x0 0x20000000>;
 538                         no-map;
 539                 };
 540
 541                 qheebsp_reserved_mem: memory@e0000000 {
 542                         reg = <0x0 0xe0000000 0x0 0x600000>;
 543                         no-map;
 544                 };
 545
 546                 cpusys_vm_mem: memory@e0600000 {
 547                         reg = <0x0 0xe0600000 0x0 0x400000>;
 548                         no-map;
 549                 };
 550
 551                 hyp_reserved_mem: memory@e0a00000 {
 552                         reg = <0x0 0xe0a00000 0x0 0x100000>;
 553                         no-map;
 554                 };
 555
 556                 trust_ui_vm_mem: memory@e0b00000 {
 557                         reg = <0x0 0xe0b00000 0x0 0x4af3000>;
 558                         no-map;
 559                 };
 560
 561                 trust_ui_vm_qrtr: memory@e55f3000 {
 562                         reg = <0x0 0xe55f3000 0x0 0x9000>;
 563                         no-map;
 564                 };
 565
 566                 trust_ui_vm_vblk0_ring: memory@e55fc000 {
 567                         reg = <0x0 0xe55fc000 0x0 0x4000>;
 568                         no-map;
 569                 };
 570
 571                 trust_ui_vm_swiotlb: memory@e5600000 {
 572                         reg = <0x0 0xe5600000 0x0 0x100000>;
 573                         no-map;
 574                 };
 575
 576                 tz_stat_mem: memory@e8800000 {
 577                         reg = <0x0 0xe8800000 0x0 0x100000>;
 578                         no-map;
 579                 };
 580
 581                 tags_mem: memory@e8900000 {
 582                         reg = <0x0 0xe8900000 0x0 0x1200000>;
 583                         no-map;
 584                 };
 585
 586                 qtee_mem: memory@e9b00000 {
 587                         reg = <0x0 0xe9b00000 0x0 0x500000>;
 588                         no-map;
 589                 };
 590
 591                 trusted_apps_mem: memory@ea000000 {
 592                         reg = <0x0 0xea000000 0x0 0x3900000>;
 593                         no-map;
 594                 };
 595
 596                 trusted_apps_ext_mem: memory@ed900000 {
 597                         reg = <0x0 0xed900000 0x0 0x3b00000>;
 598                         no-map;
 599                 };
 600         };
 601
 602         smp2p-adsp {
 603                 compatible = "qcom,smp2p";
 604                 qcom,smem = <443>, <429>;
 605                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 606                                              IPCC_MPROC_SIGNAL_SMP2P
 607                                              IRQ_TYPE_EDGE_RISING>;
 608                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 609                                 IPCC_MPROC_SIGNAL_SMP2P>;
 610
 611                 qcom,local-pid = <0>;
 612                 qcom,remote-pid = <2>;
 613
 614                 smp2p_adsp_out: master-kernel {
 615                         qcom,entry-name = "master-kernel";
 616                         #qcom,smem-state-cells = <1>;
 617                 };
 618
 619                 smp2p_adsp_in: slave-kernel {
 620                         qcom,entry-name = "slave-kernel";
 621                         interrupt-controller;
 622                         #interrupt-cells = <2>;
 623                 };
 624         };
 625
 626         smp2p-cdsp {
 627                 compatible = "qcom,smp2p";
 628                 qcom,smem = <94>, <432>;
 629                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 630                                              IPCC_MPROC_SIGNAL_SMP2P
 631                                              IRQ_TYPE_EDGE_RISING>;
 632                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 633                                 IPCC_MPROC_SIGNAL_SMP2P>;
 634
 635                 qcom,local-pid = <0>;
 636                 qcom,remote-pid = <5>;
 637
 638                 smp2p_cdsp_out: master-kernel {
 639                         qcom,entry-name = "master-kernel";
 640                         #qcom,smem-state-cells = <1>;
 641                 };
 642
 643                 smp2p_cdsp_in: slave-kernel {
 644                         qcom,entry-name = "slave-kernel";
 645                         interrupt-controller;
 646                         #interrupt-cells = <2>;
 647                 };
 648         };
 649
 650         smp2p-modem {
 651                 compatible = "qcom,smp2p";
 652                 qcom,smem = <435>, <428>;
 653                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 654                                              IPCC_MPROC_SIGNAL_SMP2P
 655                                              IRQ_TYPE_EDGE_RISING>;
 656                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 657                                 IPCC_MPROC_SIGNAL_SMP2P>;
 658
 659                 qcom,local-pid = <0>;
 660                 qcom,remote-pid = <1>;
 661
 662                 smp2p_modem_out: master-kernel {
 663                         qcom,entry-name = "master-kernel";
 664                         #qcom,smem-state-cells = <1>;
 665                 };
 666
 667                 smp2p_modem_in: slave-kernel {
 668                         qcom,entry-name = "slave-kernel";
 669                         interrupt-controller;
 670                         #interrupt-cells = <2>;
 671                 };
 672
 673                 ipa_smp2p_out: ipa-ap-to-modem {
 674                         qcom,entry-name = "ipa";
 675                         #qcom,smem-state-cells = <1>;
 676                 };
 677
 678                 ipa_smp2p_in: ipa-modem-to-ap {
 679                         qcom,entry-name = "ipa";
 680                         interrupt-controller;
 681                         #interrupt-cells = <2>;
 682                 };
 683         };
 684
 685         smp2p-slpi {
 686                 compatible = "qcom,smp2p";
 687                 qcom,smem = <481>, <430>;
 688                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 689                                              IPCC_MPROC_SIGNAL_SMP2P
 690                                              IRQ_TYPE_EDGE_RISING>;
 691                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 692                                 IPCC_MPROC_SIGNAL_SMP2P>;
 693
 694                 qcom,local-pid = <0>;
 695                 qcom,remote-pid = <3>;
 696
 697                 smp2p_slpi_out: master-kernel {
 698                         qcom,entry-name = "master-kernel";
 699                         #qcom,smem-state-cells = <1>;
 700                 };
 701
 702                 smp2p_slpi_in: slave-kernel {
 703                         qcom,entry-name = "slave-kernel";
 704                         interrupt-controller;
 705                         #interrupt-cells = <2>;
 706                 };
 707         };
 708
 709         soc: soc@0 {
 710                 #address-cells = <2>;
 711                 #size-cells = <2>;
 712                 ranges = <0 0 0 0 0x10 0>;
 713                 dma-ranges = <0 0 0 0 0x10 0>;
 714                 compatible = "simple-bus";
 715
 716                 gcc: clock-controller@100000 {
 717                         compatible = "qcom,gcc-sm8450";
 718                         reg = <0x0 0x00100000 0x0 0x1f4200>;
 719                         #clock-cells = <1>;
 720                         #reset-cells = <1>;
 721                         #power-domain-cells = <1>;
 722                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 723                                  <&pcie0_lane>,
 724                                  <&pcie1_lane>,
 725                                  <&sleep_clk>;
 726                         clock-names = "bi_tcxo",
 727                                       "pcie_0_pipe_clk",
 728                                       "pcie_1_pipe_clk",
 729                                       "sleep_clk";
 730                 };
 731
 732                 gpi_dma2: dma-controller@800000 {
 733                         compatible = "qcom,sm8450-gpi-dma";
 734                         #dma-cells = <3>;
 735                         reg = <0 0x800000 0 0x60000>;
 736                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 748                         dma-channels = <12>;
 749                         dma-channel-mask = <0x7e>;
 750                         iommus = <&apps_smmu 0x496 0x0>;
 751                         status = "disabled";
 752                 };
 753
 754                 qupv3_id_2: geniqup@8c0000 {
 755                         compatible = "qcom,geni-se-qup";
 756                         reg = <0x0 0x008c0000 0x0 0x2000>;
 757                         clock-names = "m-ahb", "s-ahb";
 758                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 759                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 760                         iommus = <&apps_smmu 0x483 0x0>;
 761                         #address-cells = <2>;
 762                         #size-cells = <2>;
 763                         ranges;
 764                         status = "disabled";
 765
 766                         i2c15: i2c@880000 {
 767                                 compatible = "qcom,geni-i2c";
 768                                 reg = <0x0 0x00880000 0x0 0x4000>;
 769                                 clock-names = "se";
 770                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 771                                 pinctrl-names = "default";
 772                                 pinctrl-0 = <&qup_i2c15_data_clk>;
 773                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 777                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 778                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 779                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 780                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 781                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 782                                 dma-names = "tx", "rx";
 783                                 status = "disabled";
 784                         };
 785
 786                         spi15: spi@880000 {
 787                                 compatible = "qcom,geni-spi";
 788                                 reg = <0x0 0x00880000 0x0 0x4000>;
 789                                 clock-names = "se";
 790                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 791                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 792                                 pinctrl-names = "default";
 793                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
 794                                 spi-max-frequency = <50000000>;
 795                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 796                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 797                                 interconnect-names = "qup-core", "qup-config";
 798                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 799                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 800                                 dma-names = "tx", "rx";
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803                                 status = "disabled";
 804                         };
 805
 806                         i2c16: i2c@884000 {
 807                                 compatible = "qcom,geni-i2c";
 808                                 reg = <0x0 0x00884000 0x0 0x4000>;
 809                                 clock-names = "se";
 810                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 811                                 pinctrl-names = "default";
 812                                 pinctrl-0 = <&qup_i2c16_data_clk>;
 813                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 814                                 #address-cells = <1>;
 815                                 #size-cells = <0>;
 816                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 817                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 818                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 819                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 820                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 821                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 822                                 dma-names = "tx", "rx";
 823                                 status = "disabled";
 824                         };
 825
 826                         spi16: spi@884000 {
 827                                 compatible = "qcom,geni-spi";
 828                                 reg = <0x0 0x00884000 0x0 0x4000>;
 829                                 clock-names = "se";
 830                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 831                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 832                                 pinctrl-names = "default";
 833                                 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
 834                                 spi-max-frequency = <50000000>;
 835                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 836                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 837                                 interconnect-names = "qup-core", "qup-config";
 838                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 839                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 840                                 dma-names = "tx", "rx";
 841                                 #address-cells = <1>;
 842                                 #size-cells = <0>;
 843                                 status = "disabled";
 844                         };
 845
 846                         i2c17: i2c@888000 {
 847                                 compatible = "qcom,geni-i2c";
 848                                 reg = <0x0 0x00888000 0x0 0x4000>;
 849                                 clock-names = "se";
 850                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 851                                 pinctrl-names = "default";
 852                                 pinctrl-0 = <&qup_i2c17_data_clk>;
 853                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 854                                 #address-cells = <1>;
 855                                 #size-cells = <0>;
 856                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 857                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 858                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 859                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 860                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 861                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 862                                 dma-names = "tx", "rx";
 863                                 status = "disabled";
 864                         };
 865
 866                         spi17: spi@888000 {
 867                                 compatible = "qcom,geni-spi";
 868                                 reg = <0x0 0x00888000 0x0 0x4000>;
 869                                 clock-names = "se";
 870                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 871                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 872                                 pinctrl-names = "default";
 873                                 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
 874                                 spi-max-frequency = <50000000>;
 875                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 876                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 877                                 interconnect-names = "qup-core", "qup-config";
 878                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 879                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 880                                 dma-names = "tx", "rx";
 881                                 #address-cells = <1>;
 882                                 #size-cells = <0>;
 883                                 status = "disabled";
 884                         };
 885
 886                         i2c18: i2c@88c000 {
 887                                 compatible = "qcom,geni-i2c";
 888                                 reg = <0x0 0x0088c000 0x0 0x4000>;
 889                                 clock-names = "se";
 890                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 891                                 pinctrl-names = "default";
 892                                 pinctrl-0 = <&qup_i2c18_data_clk>;
 893                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 894                                 #address-cells = <1>;
 895                                 #size-cells = <0>;
 896                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 897                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 898                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 899                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 900                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 901                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 902                                 dma-names = "tx", "rx";
 903                                 status = "disabled";
 904                         };
 905
 906                         spi18: spi@88c000 {
 907                                 compatible = "qcom,geni-spi";
 908                                 reg = <0 0x0088c000 0 0x4000>;
 909                                 clock-names = "se";
 910                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 911                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
 914                                 spi-max-frequency = <50000000>;
 915                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 916                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 917                                 interconnect-names = "qup-core", "qup-config";
 918                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 919                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 920                                 dma-names = "tx", "rx";
 921                                 #address-cells = <1>;
 922                                 #size-cells = <0>;
 923                                 status = "disabled";
 924                         };
 925
 926                         i2c19: i2c@890000 {
 927                                 compatible = "qcom,geni-i2c";
 928                                 reg = <0x0 0x00890000 0x0 0x4000>;
 929                                 clock-names = "se";
 930                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 931                                 pinctrl-names = "default";
 932                                 pinctrl-0 = <&qup_i2c19_data_clk>;
 933                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 937                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 938                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 939                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 940                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 941                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 942                                 dma-names = "tx", "rx";
 943                                 status = "disabled";
 944                         };
 945
 946                         spi19: spi@890000 {
 947                                 compatible = "qcom,geni-spi";
 948                                 reg = <0 0x00890000 0 0x4000>;
 949                                 clock-names = "se";
 950                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 951                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 952                                 pinctrl-names = "default";
 953                                 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
 954                                 spi-max-frequency = <50000000>;
 955                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 956                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
 957                                 interconnect-names = "qup-core", "qup-config";
 958                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
 959                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
 960                                 dma-names = "tx", "rx";
 961                                 #address-cells = <1>;
 962                                 #size-cells = <0>;
 963                                 status = "disabled";
 964                         };
 965
 966                         i2c20: i2c@894000 {
 967                                 compatible = "qcom,geni-i2c";
 968                                 reg = <0x0 0x00894000 0x0 0x4000>;
 969                                 clock-names = "se";
 970                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 971                                 pinctrl-names = "default";
 972                                 pinctrl-0 = <&qup_i2c20_data_clk>;
 973                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 974                                 #address-cells = <1>;
 975                                 #size-cells = <0>;
 976                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 977                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
 978                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 979                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 980                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 981                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 982                                 dma-names = "tx", "rx";
 983                                 status = "disabled";
 984                         };
 985
 986                         uart20: serial@894000 {
 987                                 compatible = "qcom,geni-uart";
 988                                 reg = <0 0x00894000 0 0x4000>;
 989                                 clock-names = "se";
 990                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 991                                 pinctrl-names = "default";
 992                                 pinctrl-0 = <&qup_uart20_default>;
 993                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 994                                 status = "disabled";
 995                         };
 996
 997                         spi20: spi@894000 {
 998                                 compatible = "qcom,geni-spi";
 999                                 reg = <0 0x00894000 0 0x4000>;
1000                                 clock-names = "se";
1001                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1002                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1003                                 pinctrl-names = "default";
1004                                 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1005                                 spi-max-frequency = <50000000>;
1006                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1007                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1008                                 interconnect-names = "qup-core", "qup-config";
1009                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1010                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1011                                 dma-names = "tx", "rx";
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 status = "disabled";
1015                         };
1016
1017                         i2c21: i2c@898000 {
1018                                 compatible = "qcom,geni-i2c";
1019                                 reg = <0x0 0x00898000 0x0 0x4000>;
1020                                 clock-names = "se";
1021                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1022                                 pinctrl-names = "default";
1023                                 pinctrl-0 = <&qup_i2c21_data_clk>;
1024                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1025                                 #address-cells = <1>;
1026                                 #size-cells = <0>;
1027                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1028                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1029                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1030                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1031                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1032                                        <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1033                                 dma-names = "tx", "rx";
1034                                 status = "disabled";
1035                         };
1036
1037                         spi21: spi@898000 {
1038                                 compatible = "qcom,geni-spi";
1039                                 reg = <0 0x00898000 0 0x4000>;
1040                                 clock-names = "se";
1041                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1042                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1043                                 pinctrl-names = "default";
1044                                 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1045                                 spi-max-frequency = <50000000>;
1046                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1047                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1048                                 interconnect-names = "qup-core", "qup-config";
1049                                 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1050                                        <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1051                                 dma-names = "tx", "rx";
1052                                 #address-cells = <1>;
1053                                 #size-cells = <0>;
1054                                 status = "disabled";
1055                         };
1056                 };
1057
1058                 gpi_dma0: dma-controller@900000 {
1059                         compatible = "qcom,sm8450-gpi-dma";
1060                         #dma-cells = <3>;
1061                         reg = <0 0x900000 0 0x60000>;
1062                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1063                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1064                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1065                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1066                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1067                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1068                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1069                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1070                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1071                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1072                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1073                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1074                         dma-channels = <12>;
1075                         dma-channel-mask = <0x7e>;
1076                         iommus = <&apps_smmu 0x5b6 0x0>;
1077                         status = "disabled";
1078                 };
1079
1080                 qupv3_id_0: geniqup@9c0000 {
1081                         compatible = "qcom,geni-se-qup";
1082                         reg = <0x0 0x009c0000 0x0 0x2000>;
1083                         clock-names = "m-ahb", "s-ahb";
1084                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1085                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1086                         iommus = <&apps_smmu 0x5a3 0x0>;
1087                         interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1088                         interconnect-names = "qup-core";
1089                         #address-cells = <2>;
1090                         #size-cells = <2>;
1091                         ranges;
1092                         status = "disabled";
1093
1094                         i2c0: i2c@980000 {
1095                                 compatible = "qcom,geni-i2c";
1096                                 reg = <0x0 0x00980000 0x0 0x4000>;
1097                                 clock-names = "se";
1098                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1099                                 pinctrl-names = "default";
1100                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1101                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1102                                 #address-cells = <1>;
1103                                 #size-cells = <0>;
1104                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1105                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1106                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1107                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1108                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1109                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1110                                 dma-names = "tx", "rx";
1111                                 status = "disabled";
1112                         };
1113
1114                         spi0: spi@980000 {
1115                                 compatible = "qcom,geni-spi";
1116                                 reg = <0x0 0x00980000 0x0 0x4000>;
1117                                 clock-names = "se";
1118                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1119                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1122                                 power-domains = <&rpmhpd SM8450_CX>;
1123                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1124                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1125                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1126                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1127                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1128                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1129                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1130                                 dma-names = "tx", "rx";
1131                                 #address-cells = <1>;
1132                                 #size-cells = <0>;
1133                                 status = "disabled";
1134                         };
1135
1136                         i2c1: i2c@984000 {
1137                                 compatible = "qcom,geni-i2c";
1138                                 reg = <0x0 0x00984000 0x0 0x4000>;
1139                                 clock-names = "se";
1140                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1141                                 pinctrl-names = "default";
1142                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1143                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1144                                 #address-cells = <1>;
1145                                 #size-cells = <0>;
1146                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1148                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1149                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1150                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1151                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1152                                 dma-names = "tx", "rx";
1153                                 status = "disabled";
1154                         };
1155
1156                         spi1: spi@984000 {
1157                                 compatible = "qcom,geni-spi";
1158                                 reg = <0x0 0x00984000 0x0 0x4000>;
1159                                 clock-names = "se";
1160                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1161                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1162                                 pinctrl-names = "default";
1163                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1164                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1165                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1166                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1167                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1168                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1169                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1170                                 dma-names = "tx", "rx";
1171                                 #address-cells = <1>;
1172                                 #size-cells = <0>;
1173                                 status = "disabled";
1174                         };
1175
1176                         i2c2: i2c@988000 {
1177                                 compatible = "qcom,geni-i2c";
1178                                 reg = <0x0 0x00988000 0x0 0x4000>;
1179                                 clock-names = "se";
1180                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1181                                 pinctrl-names = "default";
1182                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1183                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1187                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1188                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1189                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1191                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1192                                 dma-names = "tx", "rx";
1193                                 status = "disabled";
1194                         };
1195
1196                         spi2: spi@988000 {
1197                                 compatible = "qcom,geni-spi";
1198                                 reg = <0x0 0x00988000 0x0 0x4000>;
1199                                 clock-names = "se";
1200                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1201                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1202                                 pinctrl-names = "default";
1203                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1204                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1205                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1206                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1207                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1208                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1209                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1210                                 dma-names = "tx", "rx";
1211                                 #address-cells = <1>;
1212                                 #size-cells = <0>;
1213                                 status = "disabled";
1214                         };
1215
1216
1217                         i2c3: i2c@98c000 {
1218                                 compatible = "qcom,geni-i2c";
1219                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1222                                 pinctrl-names = "default";
1223                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1224                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1225                                 #address-cells = <1>;
1226                                 #size-cells = <0>;
1227                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1228                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1229                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1230                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1232                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1233                                 dma-names = "tx", "rx";
1234                                 status = "disabled";
1235                         };
1236
1237                         spi3: spi@98c000 {
1238                                 compatible = "qcom,geni-spi";
1239                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1240                                 clock-names = "se";
1241                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1242                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1245                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1246                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1247                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1248                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1249                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1250                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1251                                 dma-names = "tx", "rx";
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 status = "disabled";
1255                         };
1256
1257                         i2c4: i2c@990000 {
1258                                 compatible = "qcom,geni-i2c";
1259                                 reg = <0x0 0x00990000 0x0 0x4000>;
1260                                 clock-names = "se";
1261                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1262                                 pinctrl-names = "default";
1263                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1264                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1265                                 #address-cells = <1>;
1266                                 #size-cells = <0>;
1267                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1268                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1269                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1270                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1271                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1272                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1273                                 dma-names = "tx", "rx";
1274                                 status = "disabled";
1275                         };
1276
1277                         spi4: spi@990000 {
1278                                 compatible = "qcom,geni-spi";
1279                                 reg = <0x0 0x00990000 0x0 0x4000>;
1280                                 clock-names = "se";
1281                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1282                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1283                                 pinctrl-names = "default";
1284                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1285                                 power-domains = <&rpmhpd SM8450_CX>;
1286                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1287                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1288                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1289                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1290                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1291                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1292                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1293                                 dma-names = "tx", "rx";
1294                                 #address-cells = <1>;
1295                                 #size-cells = <0>;
1296                                 status = "disabled";
1297                         };
1298
1299                         i2c5: i2c@994000 {
1300                                 compatible = "qcom,geni-i2c";
1301                                 reg = <0x0 0x00994000 0x0 0x4000>;
1302                                 clock-names = "se";
1303                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1304                                 pinctrl-names = "default";
1305                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1306                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1307                                 #address-cells = <1>;
1308                                 #size-cells = <0>;
1309                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1310                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1311                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1312                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1313                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1314                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1315                                 dma-names = "tx", "rx";
1316                                 status = "disabled";
1317                         };
1318
1319                         spi5: spi@994000 {
1320                                 compatible = "qcom,geni-spi";
1321                                 reg = <0x0 0x00994000 0x0 0x4000>;
1322                                 clock-names = "se";
1323                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1324                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1325                                 pinctrl-names = "default";
1326                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1327                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1328                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1329                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1330                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1331                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1332                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1333                                 dma-names = "tx", "rx";
1334                                 #address-cells = <1>;
1335                                 #size-cells = <0>;
1336                                 status = "disabled";
1337                         };
1338
1339
1340                         i2c6: i2c@998000 {
1341                                 compatible = "qcom,geni-i2c";
1342                                 reg = <0x0 0x998000 0x0 0x4000>;
1343                                 clock-names = "se";
1344                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1345                                 pinctrl-names = "default";
1346                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1347                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1348                                 #address-cells = <1>;
1349                                 #size-cells = <0>;
1350                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1351                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1352                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1353                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1355                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1356                                 dma-names = "tx", "rx";
1357                                 status = "disabled";
1358                         };
1359
1360                         spi6: spi@998000 {
1361                                 compatible = "qcom,geni-spi";
1362                                 reg = <0x0 0x998000 0x0 0x4000>;
1363                                 clock-names = "se";
1364                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1365                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1366                                 pinctrl-names = "default";
1367                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1368                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1369                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1370                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1372                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1373                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1374                                 dma-names = "tx", "rx";
1375                                 #address-cells = <1>;
1376                                 #size-cells = <0>;
1377                                 status = "disabled";
1378                         };
1379
1380                         uart7: serial@99c000 {
1381                                 compatible = "qcom,geni-debug-uart";
1382                                 reg = <0 0x0099c000 0 0x4000>;
1383                                 clock-names = "se";
1384                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1385                                 pinctrl-names = "default";
1386                                 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1387                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1388                                 status = "disabled";
1389                         };
1390                 };
1391
1392                 gpi_dma1: dma-controller@a00000 {
1393                         compatible = "qcom,sm8450-gpi-dma";
1394                         #dma-cells = <3>;
1395                         reg = <0 0xa00000 0 0x60000>;
1396                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1397                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1398                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1399                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1400                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1401                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1402                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1403                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1404                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1405                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1406                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1407                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1408                         dma-channels = <12>;
1409                         dma-channel-mask = <0x7e>;
1410                         iommus = <&apps_smmu 0x56 0x0>;
1411                         status = "disabled";
1412                 };
1413
1414                 qupv3_id_1: geniqup@ac0000 {
1415                         compatible = "qcom,geni-se-qup";
1416                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1417                         clock-names = "m-ahb", "s-ahb";
1418                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1419                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1420                         iommus = <&apps_smmu 0x43 0x0>;
1421                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1422                         interconnect-names = "qup-core";
1423                         #address-cells = <2>;
1424                         #size-cells = <2>;
1425                         ranges;
1426                         status = "disabled";
1427
1428                         i2c8: i2c@a80000 {
1429                                 compatible = "qcom,geni-i2c";
1430                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1431                                 clock-names = "se";
1432                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1433                                 pinctrl-names = "default";
1434                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1435                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1436                                 #address-cells = <1>;
1437                                 #size-cells = <0>;
1438                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1439                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1440                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1441                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1442                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1443                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1444                                 dma-names = "tx", "rx";
1445                                 status = "disabled";
1446                         };
1447
1448                         spi8: spi@a80000 {
1449                                 compatible = "qcom,geni-spi";
1450                                 reg = <0x0 0x00a80000 0x0 0x4000>;
1451                                 clock-names = "se";
1452                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1453                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1454                                 pinctrl-names = "default";
1455                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1456                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1457                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1458                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1459                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1460                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1461                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1462                                 dma-names = "tx", "rx";
1463                                 #address-cells = <1>;
1464                                 #size-cells = <0>;
1465                                 status = "disabled";
1466                         };
1467
1468                         i2c9: i2c@a84000 {
1469                                 compatible = "qcom,geni-i2c";
1470                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1471                                 clock-names = "se";
1472                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1473                                 pinctrl-names = "default";
1474                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1475                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1476                                 #address-cells = <1>;
1477                                 #size-cells = <0>;
1478                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1479                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1480                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1481                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1482                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1483                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1484                                 dma-names = "tx", "rx";
1485                                 status = "disabled";
1486                         };
1487
1488                         spi9: spi@a84000 {
1489                                 compatible = "qcom,geni-spi";
1490                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1491                                 clock-names = "se";
1492                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1493                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1494                                 pinctrl-names = "default";
1495                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1496                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1497                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1498                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1499                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1500                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1501                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1502                                 dma-names = "tx", "rx";
1503                                 #address-cells = <1>;
1504                                 #size-cells = <0>;
1505                                 status = "disabled";
1506                         };
1507
1508                         i2c10: i2c@a88000 {
1509                                 compatible = "qcom,geni-i2c";
1510                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1511                                 clock-names = "se";
1512                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1513                                 pinctrl-names = "default";
1514                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1515                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1516                                 #address-cells = <1>;
1517                                 #size-cells = <0>;
1518                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1519                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1520                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1521                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1522                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1523                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1524                                 dma-names = "tx", "rx";
1525                                 status = "disabled";
1526                         };
1527
1528                         spi10: spi@a88000 {
1529                                 compatible = "qcom,geni-spi";
1530                                 reg = <0x0 0x00a88000 0x0 0x4000>;
1531                                 clock-names = "se";
1532                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1533                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1534                                 pinctrl-names = "default";
1535                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1536                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1537                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1538                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1539                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1540                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1541                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1542                                 dma-names = "tx", "rx";
1543                                 #address-cells = <1>;
1544                                 #size-cells = <0>;
1545                                 status = "disabled";
1546                         };
1547
1548                         i2c11: i2c@a8c000 {
1549                                 compatible = "qcom,geni-i2c";
1550                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1551                                 clock-names = "se";
1552                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1553                                 pinctrl-names = "default";
1554                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1555                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1556                                 #address-cells = <1>;
1557                                 #size-cells = <0>;
1558                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1559                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1560                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1561                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1562                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1563                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1564                                 dma-names = "tx", "rx";
1565                                 status = "disabled";
1566                         };
1567
1568                         spi11: spi@a8c000 {
1569                                 compatible = "qcom,geni-spi";
1570                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1571                                 clock-names = "se";
1572                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1573                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1574                                 pinctrl-names = "default";
1575                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1576                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1577                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1578                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1579                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1580                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1581                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1582                                 dma-names = "tx", "rx";
1583                                 #address-cells = <1>;
1584                                 #size-cells = <0>;
1585                                 status = "disabled";
1586                         };
1587
1588                         i2c12: i2c@a90000 {
1589                                 compatible = "qcom,geni-i2c";
1590                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1591                                 clock-names = "se";
1592                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1593                                 pinctrl-names = "default";
1594                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1595                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1596                                 #address-cells = <1>;
1597                                 #size-cells = <0>;
1598                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1599                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1600                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1601                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1602                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1603                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1604                                 dma-names = "tx", "rx";
1605                                 status = "disabled";
1606                         };
1607
1608                         spi12: spi@a90000 {
1609                                 compatible = "qcom,geni-spi";
1610                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1611                                 clock-names = "se";
1612                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1613                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1614                                 pinctrl-names = "default";
1615                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1616                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1617                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1618                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1619                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1620                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1621                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1622                                 dma-names = "tx", "rx";
1623                                 #address-cells = <1>;
1624                                 #size-cells = <0>;
1625                                 status = "disabled";
1626                         };
1627
1628                         i2c13: i2c@a94000 {
1629                                 compatible = "qcom,geni-i2c";
1630                                 reg = <0 0x00a94000 0 0x4000>;
1631                                 clock-names = "se";
1632                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1633                                 pinctrl-names = "default";
1634                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1635                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1636                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1637                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1638                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1639                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1640                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1641                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1642                                 dma-names = "tx", "rx";
1643                                 #address-cells = <1>;
1644                                 #size-cells = <0>;
1645                                 status = "disabled";
1646                         };
1647
1648                         spi13: spi@a94000 {
1649                                 compatible = "qcom,geni-spi";
1650                                 reg = <0x0 0x00a94000 0x0 0x4000>;
1651                                 clock-names = "se";
1652                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1653                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1654                                 pinctrl-names = "default";
1655                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1656                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1657                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1658                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1659                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1660                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1661                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1662                                 dma-names = "tx", "rx";
1663                                 #address-cells = <1>;
1664                                 #size-cells = <0>;
1665                                 status = "disabled";
1666                         };
1667
1668                         i2c14: i2c@a98000 {
1669                                 compatible = "qcom,geni-i2c";
1670                                 reg = <0 0x00a98000 0 0x4000>;
1671                                 clock-names = "se";
1672                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1673                                 pinctrl-names = "default";
1674                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1675                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1676                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1677                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1678                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1679                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1680                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1681                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1682                                 dma-names = "tx", "rx";
1683                                 #address-cells = <1>;
1684                                 #size-cells = <0>;
1685                                 status = "disabled";
1686                         };
1687
1688                         spi14: spi@a98000 {
1689                                 compatible = "qcom,geni-spi";
1690                                 reg = <0x0 0x00a98000 0x0 0x4000>;
1691                                 clock-names = "se";
1692                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1693                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1694                                 pinctrl-names = "default";
1695                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1696                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1697                                                 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1698                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1699                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1700                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1701                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1702                                 dma-names = "tx", "rx";
1703                                 #address-cells = <1>;
1704                                 #size-cells = <0>;
1705                                 status = "disabled";
1706                         };
1707                 };
1708
1709                 pcie0: pci@1c00000 {
1710                         compatible = "qcom,pcie-sm8450-pcie0";
1711                         reg = <0 0x01c00000 0 0x3000>,
1712                               <0 0x60000000 0 0xf1d>,
1713                               <0 0x60000f20 0 0xa8>,
1714                               <0 0x60001000 0 0x1000>,
1715                               <0 0x60100000 0 0x100000>;
1716                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1717                         device_type = "pci";
1718                         linux,pci-domain = <0>;
1719                         bus-range = <0x00 0xff>;
1720                         num-lanes = <1>;
1721
1722                         #address-cells = <3>;
1723                         #size-cells = <2>;
1724
1725                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1726                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1727
1728                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1729                         interrupt-names = "msi";
1730                         #interrupt-cells = <1>;
1731                         interrupt-map-mask = <0 0 0 0x7>;
1732                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1733                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1734                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1735                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1736
1737                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1738                                  <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
1739                                  <&pcie0_lane>,
1740                                  <&rpmhcc RPMH_CXO_CLK>,
1741                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1742                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1743                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1744                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1745                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1746                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1747                                  <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1748                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1749                         clock-names = "pipe",
1750                                       "pipe_mux",
1751                                       "phy_pipe",
1752                                       "ref",
1753                                       "aux",
1754                                       "cfg",
1755                                       "bus_master",
1756                                       "bus_slave",
1757                                       "slave_q2a",
1758                                       "ddrss_sf_tbu",
1759                                       "aggre0",
1760                                       "aggre1";
1761
1762                         iommus = <&apps_smmu 0x1c00 0x7f>;
1763                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1764                                     <0x100 &apps_smmu 0x1c01 0x1>;
1765
1766                         resets = <&gcc GCC_PCIE_0_BCR>;
1767                         reset-names = "pci";
1768
1769                         power-domains = <&gcc PCIE_0_GDSC>;
1770                         power-domain-names = "gdsc";
1771
1772                         phys = <&pcie0_lane>;
1773                         phy-names = "pciephy";
1774
1775                         perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1776                         wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1777
1778                         pinctrl-names = "default";
1779                         pinctrl-0 = <&pcie0_default_state>;
1780
1781                         status = "disabled";
1782                 };
1783
1784                 pcie0_phy: phy@1c06000 {
1785                         compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1786                         reg = <0 0x01c06000 0 0x200>;
1787                         #address-cells = <2>;
1788                         #size-cells = <2>;
1789                         ranges;
1790                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1791                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1792                                  <&gcc GCC_PCIE_0_CLKREF_EN>,
1793                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1794                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1795
1796                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1797                         reset-names = "phy";
1798
1799                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1800                         assigned-clock-rates = <100000000>;
1801
1802                         status = "disabled";
1803
1804                         pcie0_lane: phy@1c06200 {
1805                                 reg = <0 0x1c06e00 0 0x200>, /* tx */
1806                                       <0 0x1c07000 0 0x200>, /* rx */
1807                                       <0 0x1c06200 0 0x200>, /* pcs */
1808                                       <0 0x1c06600 0 0x200>; /* pcs_pcie */
1809                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1810                                 clock-names = "pipe0";
1811
1812                                 #clock-cells = <0>;
1813                                 #phy-cells = <0>;
1814                                 clock-output-names = "pcie_0_pipe_clk";
1815                         };
1816                 };
1817
1818                 pcie1: pci@1c08000 {
1819                         compatible = "qcom,pcie-sm8450-pcie1";
1820                         reg = <0 0x01c08000 0 0x3000>,
1821                               <0 0x40000000 0 0xf1d>,
1822                               <0 0x40000f20 0 0xa8>,
1823                               <0 0x40001000 0 0x1000>,
1824                               <0 0x40100000 0 0x100000>;
1825                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1826                         device_type = "pci";
1827                         linux,pci-domain = <1>;
1828                         bus-range = <0x00 0xff>;
1829                         num-lanes = <2>;
1830
1831                         #address-cells = <3>;
1832                         #size-cells = <2>;
1833
1834                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1835                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1836
1837                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1838                         interrupt-names = "msi";
1839                         #interrupt-cells = <1>;
1840                         interrupt-map-mask = <0 0 0 0x7>;
1841                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1842                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1843                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1844                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1845
1846                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1847                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
1848                                  <&pcie1_lane>,
1849                                  <&rpmhcc RPMH_CXO_CLK>,
1850                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1851                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1852                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1853                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1854                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1855                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1856                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
1857                         clock-names = "pipe",
1858                                       "pipe_mux",
1859                                       "phy_pipe",
1860                                       "ref",
1861                                       "aux",
1862                                       "cfg",
1863                                       "bus_master",
1864                                       "bus_slave",
1865                                       "slave_q2a",
1866                                       "ddrss_sf_tbu",
1867                                       "aggre1";
1868
1869                         iommus = <&apps_smmu 0x1c80 0x7f>;
1870                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1871                                     <0x100 &apps_smmu 0x1c81 0x1>;
1872
1873                         resets = <&gcc GCC_PCIE_1_BCR>;
1874                         reset-names = "pci";
1875
1876                         power-domains = <&gcc PCIE_1_GDSC>;
1877                         power-domain-names = "gdsc";
1878
1879                         phys = <&pcie1_lane>;
1880                         phy-names = "pciephy";
1881
1882                         perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1883                         wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1884
1885                         pinctrl-names = "default";
1886                         pinctrl-0 = <&pcie1_default_state>;
1887
1888                         status = "disabled";
1889                 };
1890
1891                 pcie1_phy: phy@1c0f000 {
1892                         compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1893                         reg = <0 0x01c0f000 0 0x200>;
1894                         #address-cells = <2>;
1895                         #size-cells = <2>;
1896                         ranges;
1897                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1898                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1899                                  <&gcc GCC_PCIE_1_CLKREF_EN>,
1900                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1901                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1902
1903                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1904                         reset-names = "phy";
1905
1906                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1907                         assigned-clock-rates = <100000000>;
1908
1909                         status = "disabled";
1910
1911                         pcie1_lane: phy@1c0e000 {
1912                                 reg = <0 0x1c0e000 0 0x200>, /* tx */
1913                                       <0 0x1c0e200 0 0x300>, /* rx */
1914                                       <0 0x1c0f200 0 0x200>, /* pcs */
1915                                       <0 0x1c0e800 0 0x200>, /* tx */
1916                                       <0 0x1c0ea00 0 0x300>, /* rx */
1917                                       <0 0x1c0f400 0 0xc00>; /* pcs_pcie */
1918                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1919                                 clock-names = "pipe0";
1920
1921                                 #clock-cells = <0>;
1922                                 #phy-cells = <0>;
1923                                 clock-output-names = "pcie_1_pipe_clk";
1924                         };
1925                 };
1926
1927                 config_noc: interconnect@1500000 {
1928                         compatible = "qcom,sm8450-config-noc";
1929                         reg = <0 0x01500000 0 0x1c000>;
1930                         #interconnect-cells = <2>;
1931                         qcom,bcm-voters = <&apps_bcm_voter>;
1932                 };
1933
1934                 system_noc: interconnect@1680000 {
1935                         compatible = "qcom,sm8450-system-noc";
1936                         reg = <0 0x01680000 0 0x1e200>;
1937                         #interconnect-cells = <2>;
1938                         qcom,bcm-voters = <&apps_bcm_voter>;
1939                 };
1940
1941                 pcie_noc: interconnect@16c0000 {
1942                         compatible = "qcom,sm8450-pcie-anoc";
1943                         reg = <0 0x016c0000 0 0xe280>;
1944                         #interconnect-cells = <2>;
1945                         qcom,bcm-voters = <&apps_bcm_voter>;
1946                 };
1947
1948                 aggre1_noc: interconnect@16e0000 {
1949                         compatible = "qcom,sm8450-aggre1-noc";
1950                         reg = <0 0x016e0000 0 0x1c080>;
1951                         #interconnect-cells = <2>;
1952                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1953                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1954                         qcom,bcm-voters = <&apps_bcm_voter>;
1955                 };
1956
1957                 aggre2_noc: interconnect@1700000 {
1958                         compatible = "qcom,sm8450-aggre2-noc";
1959                         reg = <0 0x01700000 0 0x31080>;
1960                         #interconnect-cells = <2>;
1961                         qcom,bcm-voters = <&apps_bcm_voter>;
1962                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
1963                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
1964                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1965                                  <&rpmhcc RPMH_IPA_CLK>;
1966                 };
1967
1968                 mmss_noc: interconnect@1740000 {
1969                         compatible = "qcom,sm8450-mmss-noc";
1970                         reg = <0 0x01740000 0 0x1f080>;
1971                         #interconnect-cells = <2>;
1972                         qcom,bcm-voters = <&apps_bcm_voter>;
1973                 };
1974
1975                 tcsr_mutex: hwlock@1f40000 {
1976                         compatible = "qcom,tcsr-mutex";
1977                         reg = <0x0 0x01f40000 0x0 0x40000>;
1978                         #hwlock-cells = <1>;
1979                 };
1980
1981                 usb_1_hsphy: phy@88e3000 {
1982                         compatible = "qcom,sm8450-usb-hs-phy",
1983                                      "qcom,usb-snps-hs-7nm-phy";
1984                         reg = <0 0x088e3000 0 0x400>;
1985                         status = "disabled";
1986                         #phy-cells = <0>;
1987
1988                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1989                         clock-names = "ref";
1990
1991                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1992                 };
1993
1994                 usb_1_qmpphy: phy-wrapper@88e9000 {
1995                         compatible = "qcom,sm8450-qmp-usb3-phy";
1996                         reg = <0 0x088e9000 0 0x200>,
1997                               <0 0x088e8000 0 0x20>;
1998                         status = "disabled";
1999                         #address-cells = <2>;
2000                         #size-cells = <2>;
2001                         ranges;
2002
2003                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2004                                  <&rpmhcc RPMH_CXO_CLK>,
2005                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2006                         clock-names = "aux", "ref_clk_src", "com_aux";
2007
2008                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2009                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2010                         reset-names = "phy", "common";
2011
2012                         usb_1_ssphy: phy@88e9200 {
2013                                 reg = <0 0x088e9200 0 0x200>,
2014                                       <0 0x088e9400 0 0x200>,
2015                                       <0 0x088e9c00 0 0x400>,
2016                                       <0 0x088e9600 0 0x200>,
2017                                       <0 0x088e9800 0 0x200>,
2018                                       <0 0x088e9a00 0 0x100>;
2019                                 #phy-cells = <0>;
2020                                 #clock-cells = <0>;
2021                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2022                                 clock-names = "pipe0";
2023                                 clock-output-names = "usb3_phy_pipe_clk_src";
2024                         };
2025                 };
2026
2027                 remoteproc_slpi: remoteproc@2400000 {
2028                         compatible = "qcom,sm8450-slpi-pas";
2029                         reg = <0 0x02400000 0 0x4000>;
2030
2031                         interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2032                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2033                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2034                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2035                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2036                         interrupt-names = "wdog", "fatal", "ready",
2037                                           "handover", "stop-ack";
2038
2039                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2040                         clock-names = "xo";
2041
2042                         power-domains = <&rpmhpd SM8450_LCX>,
2043                                         <&rpmhpd SM8450_LMX>;
2044                         power-domain-names = "lcx", "lmx";
2045
2046                         memory-region = <&slpi_mem>;
2047
2048                         qcom,qmp = <&aoss_qmp>;
2049
2050                         qcom,smem-states = <&smp2p_slpi_out 0>;
2051                         qcom,smem-state-names = "stop";
2052
2053                         status = "disabled";
2054
2055                         glink-edge {
2056                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2057                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2058                                                              IRQ_TYPE_EDGE_RISING>;
2059                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2060                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2061
2062                                 label = "slpi";
2063                                 qcom,remote-pid = <3>;
2064
2065                                 fastrpc {
2066                                         compatible = "qcom,fastrpc";
2067                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2068                                         label = "sdsp";
2069                                         #address-cells = <1>;
2070                                         #size-cells = <0>;
2071
2072                                         compute-cb@1 {
2073                                                 compatible = "qcom,fastrpc-compute-cb";
2074                                                 reg = <1>;
2075                                                 iommus = <&apps_smmu 0x0541 0x0>;
2076                                         };
2077
2078                                         compute-cb@2 {
2079                                                 compatible = "qcom,fastrpc-compute-cb";
2080                                                 reg = <2>;
2081                                                 iommus = <&apps_smmu 0x0542 0x0>;
2082                                         };
2083
2084                                         compute-cb@3 {
2085                                                 compatible = "qcom,fastrpc-compute-cb";
2086                                                 reg = <3>;
2087                                                 iommus = <&apps_smmu 0x0543 0x0>;
2088                                                 /* note: shared-cb = <4> in downstream */
2089                                         };
2090                                 };
2091                         };
2092                 };
2093
2094                 remoteproc_adsp: remoteproc@30000000 {
2095                         compatible = "qcom,sm8450-adsp-pas";
2096                         reg = <0 0x030000000 0 0x100>;
2097
2098                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2099                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2100                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2101                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2102                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2103                         interrupt-names = "wdog", "fatal", "ready",
2104                                           "handover", "stop-ack";
2105
2106                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2107                         clock-names = "xo";
2108
2109                         power-domains = <&rpmhpd SM8450_LCX>,
2110                                         <&rpmhpd SM8450_LMX>;
2111                         power-domain-names = "lcx", "lmx";
2112
2113                         memory-region = <&adsp_mem>;
2114
2115                         qcom,qmp = <&aoss_qmp>;
2116
2117                         qcom,smem-states = <&smp2p_adsp_out 0>;
2118                         qcom,smem-state-names = "stop";
2119
2120                         status = "disabled";
2121
2122                         remoteproc_adsp_glink: glink-edge {
2123                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2124                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2125                                                              IRQ_TYPE_EDGE_RISING>;
2126                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2127                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2128
2129                                 label = "lpass";
2130                                 qcom,remote-pid = <2>;
2131
2132                                 fastrpc {
2133                                         compatible = "qcom,fastrpc";
2134                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2135                                         label = "adsp";
2136                                         #address-cells = <1>;
2137                                         #size-cells = <0>;
2138
2139                                         compute-cb@3 {
2140                                                 compatible = "qcom,fastrpc-compute-cb";
2141                                                 reg = <3>;
2142                                                 iommus = <&apps_smmu 0x1803 0x0>;
2143                                         };
2144
2145                                         compute-cb@4 {
2146                                                 compatible = "qcom,fastrpc-compute-cb";
2147                                                 reg = <4>;
2148                                                 iommus = <&apps_smmu 0x1804 0x0>;
2149                                         };
2150
2151                                         compute-cb@5 {
2152                                                 compatible = "qcom,fastrpc-compute-cb";
2153                                                 reg = <5>;
2154                                                 iommus = <&apps_smmu 0x1805 0x0>;
2155                                         };
2156                                 };
2157                         };
2158                 };
2159
2160                 remoteproc_cdsp: remoteproc@32300000 {
2161                         compatible = "qcom,sm8450-cdsp-pas";
2162                         reg = <0 0x032300000 0 0x1400000>;
2163
2164                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2165                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2166                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2167                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2168                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2169                         interrupt-names = "wdog", "fatal", "ready",
2170                                           "handover", "stop-ack";
2171
2172                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2173                         clock-names = "xo";
2174
2175                         power-domains = <&rpmhpd SM8450_CX>,
2176                                         <&rpmhpd SM8450_MXC>;
2177                         power-domain-names = "cx", "mxc";
2178
2179                         memory-region = <&cdsp_mem>;
2180
2181                         qcom,qmp = <&aoss_qmp>;
2182
2183                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2184                         qcom,smem-state-names = "stop";
2185
2186                         status = "disabled";
2187
2188                         glink-edge {
2189                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2190                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2191                                                              IRQ_TYPE_EDGE_RISING>;
2192                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2193                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2194
2195                                 label = "cdsp";
2196                                 qcom,remote-pid = <5>;
2197
2198                                 fastrpc {
2199                                         compatible = "qcom,fastrpc";
2200                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2201                                         label = "cdsp";
2202                                         #address-cells = <1>;
2203                                         #size-cells = <0>;
2204
2205                                         compute-cb@1 {
2206                                                 compatible = "qcom,fastrpc-compute-cb";
2207                                                 reg = <1>;
2208                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2209                                                          <&apps_smmu 0x1021 0x1420>;
2210                                         };
2211
2212                                         compute-cb@2 {
2213                                                 compatible = "qcom,fastrpc-compute-cb";
2214                                                 reg = <2>;
2215                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2216                                                          <&apps_smmu 0x1022 0x1420>;
2217                                         };
2218
2219                                         compute-cb@3 {
2220                                                 compatible = "qcom,fastrpc-compute-cb";
2221                                                 reg = <3>;
2222                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2223                                                          <&apps_smmu 0x1023 0x1420>;
2224                                         };
2225
2226                                         compute-cb@4 {
2227                                                 compatible = "qcom,fastrpc-compute-cb";
2228                                                 reg = <4>;
2229                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2230                                                          <&apps_smmu 0x1024 0x1420>;
2231                                         };
2232
2233                                         compute-cb@5 {
2234                                                 compatible = "qcom,fastrpc-compute-cb";
2235                                                 reg = <5>;
2236                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2237                                                          <&apps_smmu 0x1025 0x1420>;
2238                                         };
2239
2240                                         compute-cb@6 {
2241                                                 compatible = "qcom,fastrpc-compute-cb";
2242                                                 reg = <6>;
2243                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2244                                                          <&apps_smmu 0x1026 0x1420>;
2245                                         };
2246
2247                                         compute-cb@7 {
2248                                                 compatible = "qcom,fastrpc-compute-cb";
2249                                                 reg = <7>;
2250                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2251                                                          <&apps_smmu 0x1027 0x1420>;
2252                                         };
2253
2254                                         compute-cb@8 {
2255                                                 compatible = "qcom,fastrpc-compute-cb";
2256                                                 reg = <8>;
2257                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2258                                                          <&apps_smmu 0x1028 0x1420>;
2259                                         };
2260
2261                                         /* note: secure cb9 in downstream */
2262                                 };
2263                         };
2264                 };
2265
2266                 remoteproc_mpss: remoteproc@4080000 {
2267                         compatible = "qcom,sm8450-mpss-pas";
2268                         reg = <0x0 0x04080000 0x0 0x4040>;
2269
2270                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2271                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2272                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2273                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2274                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2275                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2276                         interrupt-names = "wdog", "fatal", "ready", "handover",
2277                                           "stop-ack", "shutdown-ack";
2278
2279                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2280                         clock-names = "xo";
2281
2282                         power-domains = <&rpmhpd 0>,
2283                                         <&rpmhpd 12>;
2284                         power-domain-names = "cx", "mss";
2285
2286                         memory-region = <&mpss_mem>;
2287
2288                         qcom,qmp = <&aoss_qmp>;
2289
2290                         qcom,smem-states = <&smp2p_modem_out 0>;
2291                         qcom,smem-state-names = "stop";
2292
2293                         status = "disabled";
2294
2295                         glink-edge {
2296                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2297                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2298                                                              IRQ_TYPE_EDGE_RISING>;
2299                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2300                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2301                                 label = "modem";
2302                                 qcom,remote-pid = <1>;
2303                         };
2304                 };
2305
2306                 camcc: clock-controller@ade0000 {
2307                         compatible = "qcom,sm8450-camcc";
2308                         reg = <0 0x0ade0000 0 0x20000>;
2309                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2310                                  <&rpmhcc RPMH_CXO_CLK>,
2311                                  <&rpmhcc RPMH_CXO_CLK_A>,
2312                                  <&sleep_clk>;
2313                         power-domains = <&rpmhpd SM8450_MMCX>;
2314                         required-opps = <&rpmhpd_opp_low_svs>;
2315                         #clock-cells = <1>;
2316                         #reset-cells = <1>;
2317                         #power-domain-cells = <1>;
2318                         status = "disabled";
2319                 };
2320
2321                 pdc: interrupt-controller@b220000 {
2322                         compatible = "qcom,sm8450-pdc", "qcom,pdc";
2323                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2324                         qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
2325                                           <94 609 31>, <125 63 1>, <126 716 12>;
2326                         #interrupt-cells = <2>;
2327                         interrupt-parent = <&intc>;
2328                         interrupt-controller;
2329                 };
2330
2331                 tsens0: thermal-sensor@c263000 {
2332                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2333                         reg = <0 0x0c263000 0 0x1000>, /* TM */
2334                               <0 0x0c222000 0 0x1000>; /* SROT */
2335                         #qcom,sensors = <16>;
2336                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
2337                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
2338                         interrupt-names = "uplow", "critical";
2339                         #thermal-sensor-cells = <1>;
2340                 };
2341
2342                 tsens1: thermal-sensor@c265000 {
2343                         compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
2344                         reg = <0 0x0c265000 0 0x1000>, /* TM */
2345                               <0 0x0c223000 0 0x1000>; /* SROT */
2346                         #qcom,sensors = <16>;
2347                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
2348                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
2349                         interrupt-names = "uplow", "critical";
2350                         #thermal-sensor-cells = <1>;
2351                 };
2352
2353                 aoss_qmp: power-controller@c300000 {
2354                         compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
2355                         reg = <0 0x0c300000 0 0x400>;
2356                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2357                                                      IRQ_TYPE_EDGE_RISING>;
2358                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2359
2360                         #clock-cells = <0>;
2361                 };
2362
2363                 ipcc: mailbox@ed18000 {
2364                         compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
2365                         reg = <0 0x0ed18000 0 0x1000>;
2366                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
2367                         interrupt-controller;
2368                         #interrupt-cells = <3>;
2369                         #mbox-cells = <2>;
2370                 };
2371
2372                 tlmm: pinctrl@f100000 {
2373                         compatible = "qcom,sm8450-tlmm";
2374                         reg = <0 0x0f100000 0 0x300000>;
2375                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2376                         gpio-controller;
2377                         #gpio-cells = <2>;
2378                         interrupt-controller;
2379                         #interrupt-cells = <2>;
2380                         gpio-ranges = <&tlmm 0 0 211>;
2381                         wakeup-parent = <&pdc>;
2382
2383                         sdc2_sleep_state: sdc2-sleep-state {
2384                                 clk-pins {
2385                                         pins = "sdc2_clk";
2386                                         drive-strength = <2>;
2387                                         bias-disable;
2388                                 };
2389
2390                                 cmd-pins {
2391                                         pins = "sdc2_cmd";
2392                                         drive-strength = <2>;
2393                                         bias-pull-up;
2394                                 };
2395
2396                                 data-pins {
2397                                         pins = "sdc2_data";
2398                                         drive-strength = <2>;
2399                                         bias-pull-up;
2400                                 };
2401                         };
2402
2403                         pcie0_default_state: pcie0-default-state {
2404                                 perst-pins {
2405                                         pins = "gpio94";
2406                                         function = "gpio";
2407                                         drive-strength = <2>;
2408                                         bias-pull-down;
2409                                 };
2410
2411                                 clkreq-pins {
2412                                         pins = "gpio95";
2413                                         function = "pcie0_clkreqn";
2414                                         drive-strength = <2>;
2415                                         bias-pull-up;
2416                                 };
2417
2418                                 wake-pins {
2419                                         pins = "gpio96";
2420                                         function = "gpio";
2421                                         drive-strength = <2>;
2422                                         bias-pull-up;
2423                                 };
2424                         };
2425
2426                         pcie1_default_state: pcie1-default-state {
2427                                 perst-pins {
2428                                         pins = "gpio97";
2429                                         function = "gpio";
2430                                         drive-strength = <2>;
2431                                         bias-pull-down;
2432                                 };
2433
2434                                 clkreq-pins {
2435                                         pins = "gpio98";
2436                                         function = "pcie1_clkreqn";
2437                                         drive-strength = <2>;
2438                                         bias-pull-up;
2439                                 };
2440
2441                                 wake-pins {
2442                                         pins = "gpio99";
2443                                         function = "gpio";
2444                                         drive-strength = <2>;
2445                                         bias-pull-up;
2446                                 };
2447                         };
2448
2449                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
2450                                 pins = "gpio0", "gpio1";
2451                                 function = "qup0";
2452                         };
2453
2454                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
2455                                 pins = "gpio4", "gpio5";
2456                                 function = "qup1";
2457                         };
2458
2459                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
2460                                 pins = "gpio8", "gpio9";
2461                                 function = "qup2";
2462                         };
2463
2464                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
2465                                 pins = "gpio12", "gpio13";
2466                                 function = "qup3";
2467                         };
2468
2469                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
2470                                 pins = "gpio16", "gpio17";
2471                                 function = "qup4";
2472                         };
2473
2474                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
2475                                 pins = "gpio206", "gpio207";
2476                                 function = "qup5";
2477                         };
2478
2479                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
2480                                 pins = "gpio20", "gpio21";
2481                                 function = "qup6";
2482                         };
2483
2484                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
2485                                 pins = "gpio28", "gpio29";
2486                                 function = "qup8";
2487                         };
2488
2489                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
2490                                 pins = "gpio32", "gpio33";
2491                                 function = "qup9";
2492                         };
2493
2494                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
2495                                 pins = "gpio36", "gpio37";
2496                                 function = "qup10";
2497                         };
2498
2499                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
2500                                 pins = "gpio40", "gpio41";
2501                                 function = "qup11";
2502                         };
2503
2504                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
2505                                 pins = "gpio44", "gpio45";
2506                                 function = "qup12";
2507                         };
2508
2509                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
2510                                 pins = "gpio48", "gpio49";
2511                                 function = "qup13";
2512                                 drive-strength = <2>;
2513                                 bias-pull-up;
2514                         };
2515
2516                         qup_i2c14_data_clk: qup-i2c14-data-clk-state {
2517                                 pins = "gpio52", "gpio53";
2518                                 function = "qup14";
2519                                 drive-strength = <2>;
2520                                 bias-pull-up;
2521                         };
2522
2523                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
2524                                 pins = "gpio56", "gpio57";
2525                                 function = "qup15";
2526                         };
2527
2528                         qup_i2c16_data_clk: qup-i2c16-data-clk-state {
2529                                 pins = "gpio60", "gpio61";
2530                                 function = "qup16";
2531                         };
2532
2533                         qup_i2c17_data_clk: qup-i2c17-data-clk-state {
2534                                 pins = "gpio64", "gpio65";
2535                                 function = "qup17";
2536                         };
2537
2538                         qup_i2c18_data_clk: qup-i2c18-data-clk-state {
2539                                 pins = "gpio68", "gpio69";
2540                                 function = "qup18";
2541                         };
2542
2543                         qup_i2c19_data_clk: qup-i2c19-data-clk-state {
2544                                 pins = "gpio72", "gpio73";
2545                                 function = "qup19";
2546                         };
2547
2548                         qup_i2c20_data_clk: qup-i2c20-data-clk-state {
2549                                 pins = "gpio76", "gpio77";
2550                                 function = "qup20";
2551                         };
2552
2553                         qup_i2c21_data_clk: qup-i2c21-data-clk-state {
2554                                 pins = "gpio80", "gpio81";
2555                                 function = "qup21";
2556                         };
2557
2558                         qup_spi0_cs: qup-spi0-cs-state {
2559                                 pins = "gpio3";
2560                                 function = "qup0";
2561                         };
2562
2563                         qup_spi0_data_clk: qup-spi0-data-clk-state {
2564                                 pins = "gpio0", "gpio1", "gpio2";
2565                                 function = "qup0";
2566                         };
2567
2568                         qup_spi1_cs: qup-spi1-cs-state {
2569                                 pins = "gpio7";
2570                                 function = "qup1";
2571                         };
2572
2573                         qup_spi1_data_clk: qup-spi1-data-clk-state {
2574                                 pins = "gpio4", "gpio5", "gpio6";
2575                                 function = "qup1";
2576                         };
2577
2578                         qup_spi2_cs: qup-spi2-cs-state {
2579                                 pins = "gpio11";
2580                                 function = "qup2";
2581                         };
2582
2583                         qup_spi2_data_clk: qup-spi2-data-clk-state {
2584                                 pins = "gpio8", "gpio9", "gpio10";
2585                                 function = "qup2";
2586                         };
2587
2588                         qup_spi3_cs: qup-spi3-cs-state {
2589                                 pins = "gpio15";
2590                                 function = "qup3";
2591                         };
2592
2593                         qup_spi3_data_clk: qup-spi3-data-clk-state {
2594                                 pins = "gpio12", "gpio13", "gpio14";
2595                                 function = "qup3";
2596                         };
2597
2598                         qup_spi4_cs: qup-spi4-cs-state {
2599                                 pins = "gpio19";
2600                                 function = "qup4";
2601                                 drive-strength = <6>;
2602                                 bias-disable;
2603                         };
2604
2605                         qup_spi4_data_clk: qup-spi4-data-clk-state {
2606                                 pins = "gpio16", "gpio17", "gpio18";
2607                                 function = "qup4";
2608                         };
2609
2610                         qup_spi5_cs: qup-spi5-cs-state {
2611                                 pins = "gpio85";
2612                                 function = "qup5";
2613                         };
2614
2615                         qup_spi5_data_clk: qup-spi5-data-clk-state {
2616                                 pins = "gpio206", "gpio207", "gpio84";
2617                                 function = "qup5";
2618                         };
2619
2620                         qup_spi6_cs: qup-spi6-cs-state {
2621                                 pins = "gpio23";
2622                                 function = "qup6";
2623                         };
2624
2625                         qup_spi6_data_clk: qup-spi6-data-clk-state {
2626                                 pins = "gpio20", "gpio21", "gpio22";
2627                                 function = "qup6";
2628                         };
2629
2630                         qup_spi8_cs: qup-spi8-cs-state {
2631                                 pins = "gpio31";
2632                                 function = "qup8";
2633                         };
2634
2635                         qup_spi8_data_clk: qup-spi8-data-clk-state {
2636                                 pins = "gpio28", "gpio29", "gpio30";
2637                                 function = "qup8";
2638                         };
2639
2640                         qup_spi9_cs: qup-spi9-cs-state {
2641                                 pins = "gpio35";
2642                                 function = "qup9";
2643                         };
2644
2645                         qup_spi9_data_clk: qup-spi9-data-clk-state {
2646                                 pins = "gpio32", "gpio33", "gpio34";
2647                                 function = "qup9";
2648                         };
2649
2650                         qup_spi10_cs: qup-spi10-cs-state {
2651                                 pins = "gpio39";
2652                                 function = "qup10";
2653                         };
2654
2655                         qup_spi10_data_clk: qup-spi10-data-clk-state {
2656                                 pins = "gpio36", "gpio37", "gpio38";
2657                                 function = "qup10";
2658                         };
2659
2660                         qup_spi11_cs: qup-spi11-cs-state {
2661                                 pins = "gpio43";
2662                                 function = "qup11";
2663                         };
2664
2665                         qup_spi11_data_clk: qup-spi11-data-clk-state {
2666                                 pins = "gpio40", "gpio41", "gpio42";
2667                                 function = "qup11";
2668                         };
2669
2670                         qup_spi12_cs: qup-spi12-cs-state {
2671                                 pins = "gpio47";
2672                                 function = "qup12";
2673                         };
2674
2675                         qup_spi12_data_clk: qup-spi12-data-clk-state {
2676                                 pins = "gpio44", "gpio45", "gpio46";
2677                                 function = "qup12";
2678                         };
2679
2680                         qup_spi13_cs: qup-spi13-cs-state {
2681                                 pins = "gpio51";
2682                                 function = "qup13";
2683                         };
2684
2685                         qup_spi13_data_clk: qup-spi13-data-clk-state {
2686                                 pins = "gpio48", "gpio49", "gpio50";
2687                                 function = "qup13";
2688                         };
2689
2690                         qup_spi14_cs: qup-spi14-cs-state {
2691                                 pins = "gpio55";
2692                                 function = "qup14";
2693                         };
2694
2695                         qup_spi14_data_clk: qup-spi14-data-clk-state {
2696                                 pins = "gpio52", "gpio53", "gpio54";
2697                                 function = "qup14";
2698                         };
2699
2700                         qup_spi15_cs: qup-spi15-cs-state {
2701                                 pins = "gpio59";
2702                                 function = "qup15";
2703                         };
2704
2705                         qup_spi15_data_clk: qup-spi15-data-clk-state {
2706                                 pins = "gpio56", "gpio57", "gpio58";
2707                                 function = "qup15";
2708                         };
2709
2710                         qup_spi16_cs: qup-spi16-cs-state {
2711                                 pins = "gpio63";
2712                                 function = "qup16";
2713                         };
2714
2715                         qup_spi16_data_clk: qup-spi16-data-clk-state {
2716                                 pins = "gpio60", "gpio61", "gpio62";
2717                                 function = "qup16";
2718                         };
2719
2720                         qup_spi17_cs: qup-spi17-cs-state {
2721                                 pins = "gpio67";
2722                                 function = "qup17";
2723                         };
2724
2725                         qup_spi17_data_clk: qup-spi17-data-clk-state {
2726                                 pins = "gpio64", "gpio65", "gpio66";
2727                                 function = "qup17";
2728                         };
2729
2730                         qup_spi18_cs: qup-spi18-cs-state {
2731                                 pins = "gpio71";
2732                                 function = "qup18";
2733                                 drive-strength = <6>;
2734                                 bias-disable;
2735                         };
2736
2737                         qup_spi18_data_clk: qup-spi18-data-clk-state {
2738                                 pins = "gpio68", "gpio69", "gpio70";
2739                                 function = "qup18";
2740                                 drive-strength = <6>;
2741                                 bias-disable;
2742                         };
2743
2744                         qup_spi19_cs: qup-spi19-cs-state {
2745                                 pins = "gpio75";
2746                                 function = "qup19";
2747                                 drive-strength = <6>;
2748                                 bias-disable;
2749                         };
2750
2751                         qup_spi19_data_clk: qup-spi19-data-clk-state {
2752                                 pins = "gpio72", "gpio73", "gpio74";
2753                                 function = "qup19";
2754                                 drive-strength = <6>;
2755                                 bias-disable;
2756                         };
2757
2758                         qup_spi20_cs: qup-spi20-cs-state {
2759                                 pins = "gpio79";
2760                                 function = "qup20";
2761                         };
2762
2763                         qup_spi20_data_clk: qup-spi20-data-clk-state {
2764                                 pins = "gpio76", "gpio77", "gpio78";
2765                                 function = "qup20";
2766                         };
2767
2768                         qup_spi21_cs: qup-spi21-cs-state {
2769                                 pins = "gpio83";
2770                                 function = "qup21";
2771                         };
2772
2773                         qup_spi21_data_clk: qup-spi21-data-clk-state {
2774                                 pins = "gpio80", "gpio81", "gpio82";
2775                                 function = "qup21";
2776                         };
2777
2778                         qup_uart7_rx: qup-uart7-rx-state {
2779                                 pins = "gpio26";
2780                                 function = "qup7";
2781                                 drive-strength = <2>;
2782                                 bias-disable;
2783                         };
2784
2785                         qup_uart7_tx: qup-uart7-tx-state {
2786                                 pins = "gpio27";
2787                                 function = "qup7";
2788                                 drive-strength = <2>;
2789                                 bias-disable;
2790                         };
2791
2792                         qup_uart20_default: qup-uart20-default-state {
2793                                 pins = "gpio76", "gpio77", "gpio78", "gpio79";
2794                                 function = "qup20";
2795                         };
2796
2797                 };
2798
2799                 apps_smmu: iommu@15000000 {
2800                         compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
2801                         reg = <0 0x15000000 0 0x100000>;
2802                         #iommu-cells = <2>;
2803                         #global-interrupts = <1>;
2804                         interrupts =    <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2805                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2806                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2807                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2808                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2809                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2810                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2811                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2812                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2813                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2814                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2815                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2816                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2817                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2818                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2819                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2820                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2821                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2822                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2823                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2824                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2825                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2826                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2827                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2828                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2829                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2830                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2831                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2832                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2833                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2834                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2835                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2836                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2837                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2838                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2839                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2840                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2841                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2842                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2843                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2844                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2845                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2846                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2847                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2848                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2849                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2850                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2851                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2852                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2853                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2854                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2855                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2856                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2857                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2858                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2859                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2860                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2861                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2862                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2863                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2864                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2865                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2866                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2867                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2868                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2869                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2870                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2871                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2872                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2873                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2874                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2875                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2876                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2877                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2878                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2879                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2880                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2881                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2882                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2883                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2884                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2885                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2886                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2887                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2888                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2889                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2890                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2891                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2892                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2893                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2894                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2895                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2896                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2897                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2898                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2899                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2900                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
2901                 };
2902
2903                 intc: interrupt-controller@17100000 {
2904                         compatible = "arm,gic-v3";
2905                         #interrupt-cells = <3>;
2906                         interrupt-controller;
2907                         #redistributor-regions = <1>;
2908                         redistributor-stride = <0x0 0x40000>;
2909                         reg = <0x0 0x17100000 0x0 0x10000>,     /* GICD */
2910                               <0x0 0x17180000 0x0 0x200000>;    /* GICR * 8 */
2911                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2912                         #address-cells = <2>;
2913                         #size-cells = <2>;
2914                         ranges;
2915
2916                         gic_its: msi-controller@17140000 {
2917                                 compatible = "arm,gic-v3-its";
2918                                 reg = <0x0 0x17140000 0x0 0x20000>;
2919                                 msi-controller;
2920                                 #msi-cells = <1>;
2921                         };
2922                 };
2923
2924                 timer@17420000 {
2925                         compatible = "arm,armv7-timer-mem";
2926                         #address-cells = <1>;
2927                         #size-cells = <1>;
2928                         ranges = <0 0 0 0x20000000>;
2929                         reg = <0x0 0x17420000 0x0 0x1000>;
2930                         clock-frequency = <19200000>;
2931
2932                         frame@17421000 {
2933                                 frame-number = <0>;
2934                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2935                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2936                                 reg = <0x17421000 0x1000>,
2937                                       <0x17422000 0x1000>;
2938                         };
2939
2940                         frame@17423000 {
2941                                 frame-number = <1>;
2942                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2943                                 reg = <0x17423000 0x1000>;
2944                                 status = "disabled";
2945                         };
2946
2947                         frame@17425000 {
2948                                 frame-number = <2>;
2949                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2950                                 reg = <0x17425000 0x1000>;
2951                                 status = "disabled";
2952                         };
2953
2954                         frame@17427000 {
2955                                 frame-number = <3>;
2956                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2957                                 reg = <0x17427000 0x1000>;
2958                                 status = "disabled";
2959                         };
2960
2961                         frame@17429000 {
2962                                 frame-number = <4>;
2963                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2964                                 reg = <0x17429000 0x1000>;
2965                                 status = "disabled";
2966                         };
2967
2968                         frame@1742b000 {
2969                                 frame-number = <5>;
2970                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2971                                 reg = <0x1742b000 0x1000>;
2972                                 status = "disabled";
2973                         };
2974
2975                         frame@1742d000 {
2976                                 frame-number = <6>;
2977                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2978                                 reg = <0x1742d000 0x1000>;
2979                                 status = "disabled";
2980                         };
2981                 };
2982
2983                 apps_rsc: rsc@17a00000 {
2984                         label = "apps_rsc";
2985                         compatible = "qcom,rpmh-rsc";
2986                         reg = <0x0 0x17a00000 0x0 0x10000>,
2987                               <0x0 0x17a10000 0x0 0x10000>,
2988                               <0x0 0x17a20000 0x0 0x10000>,
2989                               <0x0 0x17a30000 0x0 0x10000>;
2990                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
2991                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2992                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2993                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2994                         qcom,tcs-offset = <0xd00>;
2995                         qcom,drv-id = <2>;
2996                         qcom,tcs-config = <ACTIVE_TCS  3>, <SLEEP_TCS   2>,
2997                                           <WAKE_TCS    2>, <CONTROL_TCS 0>;
2998
2999                         apps_bcm_voter: bcm-voter {
3000                                 compatible = "qcom,bcm-voter";
3001                         };
3002
3003                         rpmhcc: clock-controller {
3004                                 compatible = "qcom,sm8450-rpmh-clk";
3005                                 #clock-cells = <1>;
3006                                 clock-names = "xo";
3007                                 clocks = <&xo_board>;
3008                         };
3009
3010                         rpmhpd: power-controller {
3011                                 compatible = "qcom,sm8450-rpmhpd";
3012                                 #power-domain-cells = <1>;
3013                                 operating-points-v2 = <&rpmhpd_opp_table>;
3014
3015                                 rpmhpd_opp_table: opp-table {
3016                                         compatible = "operating-points-v2";
3017
3018                                         rpmhpd_opp_ret: opp1 {
3019                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3020                                         };
3021
3022                                         rpmhpd_opp_min_svs: opp2 {
3023                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3024                                         };
3025
3026                                         rpmhpd_opp_low_svs: opp3 {
3027                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3028                                         };
3029
3030                                         rpmhpd_opp_svs: opp4 {
3031                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3032                                         };
3033
3034                                         rpmhpd_opp_svs_l1: opp5 {
3035                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3036                                         };
3037
3038                                         rpmhpd_opp_nom: opp6 {
3039                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3040                                         };
3041
3042                                         rpmhpd_opp_nom_l1: opp7 {
3043                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3044                                         };
3045
3046                                         rpmhpd_opp_nom_l2: opp8 {
3047                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3048                                         };
3049
3050                                         rpmhpd_opp_turbo: opp9 {
3051                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3052                                         };
3053
3054                                         rpmhpd_opp_turbo_l1: opp10 {
3055                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3056                                         };
3057                                 };
3058                         };
3059                 };
3060
3061                 cpufreq_hw: cpufreq@17d91000 {
3062                         compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
3063                         reg = <0 0x17d91000 0 0x1000>,
3064                               <0 0x17d92000 0 0x1000>,
3065                               <0 0x17d93000 0 0x1000>;
3066                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3067                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
3068                         clock-names = "xo", "alternate";
3069                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
3070                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3071                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
3072                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3073                         #freq-domain-cells = <1>;
3074                 };
3075
3076                 gem_noc: interconnect@19100000 {
3077                         compatible = "qcom,sm8450-gem-noc";
3078                         reg = <0 0x19100000 0 0xbb800>;
3079                         #interconnect-cells = <2>;
3080                         qcom,bcm-voters = <&apps_bcm_voter>;
3081                 };
3082
3083                 system-cache-controller@19200000 {
3084                         compatible = "qcom,sm8450-llcc";
3085                         reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
3086                         reg-names = "llcc_base", "llcc_broadcast_base";
3087                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3088                 };
3089
3090                 ufs_mem_hc: ufshc@1d84000 {
3091                         compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
3092                                      "jedec,ufs-2.0";
3093                         reg = <0 0x01d84000 0 0x3000>,
3094                               <0 0x01d88000 0 0x8000>;
3095                         reg-names = "std", "ice";
3096                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
3097                         phys = <&ufs_mem_phy_lanes>;
3098                         phy-names = "ufsphy";
3099                         lanes-per-direction = <2>;
3100                         #reset-cells = <1>;
3101                         resets = <&gcc GCC_UFS_PHY_BCR>;
3102                         reset-names = "rst";
3103
3104                         power-domains = <&gcc UFS_PHY_GDSC>;
3105
3106                         iommus = <&apps_smmu 0xe0 0x0>;
3107                         dma-coherent;
3108
3109                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
3110                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
3111                         interconnect-names = "ufs-ddr", "cpu-ufs";
3112                         clock-names =
3113                                 "core_clk",
3114                                 "bus_aggr_clk",
3115                                 "iface_clk",
3116                                 "core_clk_unipro",
3117                                 "ref_clk",
3118                                 "tx_lane0_sync_clk",
3119                                 "rx_lane0_sync_clk",
3120                                 "rx_lane1_sync_clk",
3121                                 "ice_core_clk";
3122                         clocks =
3123                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
3124                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
3125                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
3126                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
3127                                 <&rpmhcc RPMH_CXO_CLK>,
3128                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
3129                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
3130                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
3131                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
3132                         freq-table-hz =
3133                                 <75000000 300000000>,
3134                                 <0 0>,
3135                                 <0 0>,
3136                                 <75000000 300000000>,
3137                                 <75000000 300000000>,
3138                                 <0 0>,
3139                                 <0 0>,
3140                                 <0 0>,
3141                                 <75000000 300000000>;
3142                         status = "disabled";
3143                 };
3144
3145                 ufs_mem_phy: phy@1d87000 {
3146                         compatible = "qcom,sm8450-qmp-ufs-phy";
3147                         reg = <0 0x01d87000 0 0x1c4>;
3148                         #address-cells = <2>;
3149                         #size-cells = <2>;
3150                         ranges;
3151                         clock-names = "ref", "ref_aux", "qref";
3152                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3153                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
3154                                  <&gcc GCC_UFS_0_CLKREF_EN>;
3155
3156                         resets = <&ufs_mem_hc 0>;
3157                         reset-names = "ufsphy";
3158                         status = "disabled";
3159
3160                         ufs_mem_phy_lanes: phy@1d87400 {
3161                                 reg = <0 0x01d87400 0 0x188>,
3162                                       <0 0x01d87600 0 0x200>,
3163                                       <0 0x01d87c00 0 0x200>,
3164                                       <0 0x01d87800 0 0x188>,
3165                                       <0 0x01d87a00 0 0x200>;
3166                                 #phy-cells = <0>;
3167                         };
3168                 };
3169
3170                 sdhc_2: sdhci@8804000 {
3171                         compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
3172                         reg = <0 0x08804000 0 0x1000>;
3173
3174                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3175                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3176                         interrupt-names = "hc_irq", "pwr_irq";
3177
3178                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3179                                  <&gcc GCC_SDCC2_APPS_CLK>,
3180                                  <&rpmhcc RPMH_CXO_CLK>;
3181                         clock-names = "iface", "core", "xo";
3182                         resets = <&gcc GCC_SDCC2_BCR>;
3183                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3184                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3185                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3186                         iommus = <&apps_smmu 0x4a0 0x0>;
3187                         power-domains = <&rpmhpd SM8450_CX>;
3188                         operating-points-v2 = <&sdhc2_opp_table>;
3189                         bus-width = <4>;
3190                         dma-coherent;
3191
3192                         /* Forbid SDR104/SDR50 - broken hw! */
3193                         sdhci-caps-mask = <0x3 0x0>;
3194
3195                         status = "disabled";
3196
3197                         sdhc2_opp_table: opp-table {
3198                                 compatible = "operating-points-v2";
3199
3200                                 opp-100000000 {
3201                                         opp-hz = /bits/ 64 <100000000>;
3202                                         required-opps = <&rpmhpd_opp_low_svs>;
3203                                 };
3204
3205                                 opp-202000000 {
3206                                         opp-hz = /bits/ 64 <202000000>;
3207                                         required-opps = <&rpmhpd_opp_svs_l1>;
3208                                 };
3209                         };
3210                 };
3211
3212                 usb_1: usb@a6f8800 {
3213                         compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
3214                         reg = <0 0x0a6f8800 0 0x400>;
3215                         status = "disabled";
3216                         #address-cells = <2>;
3217                         #size-cells = <2>;
3218                         ranges;
3219
3220                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3221                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3222                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3223                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3224                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3225                                  <&gcc GCC_USB3_0_CLKREF_EN>;
3226                         clock-names = "cfg_noc",
3227                                       "core",
3228                                       "iface",
3229                                       "sleep",
3230                                       "mock_utmi",
3231                                       "xo";
3232
3233                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3234                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3235                         assigned-clock-rates = <19200000>, <200000000>;
3236
3237                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3238                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3239                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3240                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3241                         interrupt-names = "hs_phy_irq",
3242                                           "ss_phy_irq",
3243                                           "dm_hs_phy_irq",
3244                                           "dp_hs_phy_irq";
3245
3246                         power-domains = <&gcc USB30_PRIM_GDSC>;
3247
3248                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3249
3250                         usb_1_dwc3: usb@a600000 {
3251                                 compatible = "snps,dwc3";
3252                                 reg = <0 0x0a600000 0 0xcd00>;
3253                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3254                                 iommus = <&apps_smmu 0x0 0x0>;
3255                                 snps,dis_u2_susphy_quirk;
3256                                 snps,dis_enblslpm_quirk;
3257                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3258                                 phy-names = "usb2-phy", "usb3-phy";
3259                         };
3260                 };
3261
3262                 nsp_noc: interconnect@320c0000 {
3263                         compatible = "qcom,sm8450-nsp-noc";
3264                         reg = <0 0x320c0000 0 0x10000>;
3265                         #interconnect-cells = <2>;
3266                         qcom,bcm-voters = <&apps_bcm_voter>;
3267                 };
3268
3269                 lpass_ag_noc: interconnect@3c40000 {
3270                         compatible = "qcom,sm8450-lpass-ag-noc";
3271                         reg = <0 0x3c40000 0 0x17200>;
3272                         #interconnect-cells = <2>;
3273                         qcom,bcm-voters = <&apps_bcm_voter>;
3274                 };
3275         };
3276
3277         thermal-zones {
3278                 aoss0-thermal {
3279                         polling-delay-passive = <0>;
3280                         polling-delay = <0>;
3281                         thermal-sensors = <&tsens0 0>;
3282
3283                         trips {
3284                                 thermal-engine-config {
3285                                         temperature = <125000>;
3286                                         hysteresis = <1000>;
3287                                         type = "passive";
3288                                 };
3289
3290                                 reset-mon-cfg {
3291                                         temperature = <115000>;
3292                                         hysteresis = <5000>;
3293                                         type = "passive";
3294                                 };
3295                         };
3296                 };
3297
3298                 cpuss0-thermal {
3299                         polling-delay-passive = <0>;
3300                         polling-delay = <0>;
3301                         thermal-sensors = <&tsens0 1>;
3302
3303                         trips {
3304                                 thermal-engine-config {
3305                                         temperature = <125000>;
3306                                         hysteresis = <1000>;
3307                                         type = "passive";
3308                                 };
3309
3310                                 reset-mon-cfg {
3311                                         temperature = <115000>;
3312                                         hysteresis = <5000>;
3313                                         type = "passive";
3314                                 };
3315                         };
3316                 };
3317
3318                 cpuss1-thermal {
3319                         polling-delay-passive = <0>;
3320                         polling-delay = <0>;
3321                         thermal-sensors = <&tsens0 2>;
3322
3323                         trips {
3324                                 thermal-engine-config {
3325                                         temperature = <125000>;
3326                                         hysteresis = <1000>;
3327                                         type = "passive";
3328                                 };
3329
3330                                 reset-mon-cfg {
3331                                         temperature = <115000>;
3332                                         hysteresis = <5000>;
3333                                         type = "passive";
3334                                 };
3335                         };
3336                 };
3337
3338                 cpuss3-thermal {
3339                         polling-delay-passive = <0>;
3340                         polling-delay = <0>;
3341                         thermal-sensors = <&tsens0 3>;
3342
3343                         trips {
3344                                 thermal-engine-config {
3345                                         temperature = <125000>;
3346                                         hysteresis = <1000>;
3347                                         type = "passive";
3348                                 };
3349
3350                                 reset-mon-cfg {
3351                                         temperature = <115000>;
3352                                         hysteresis = <5000>;
3353                                         type = "passive";
3354                                 };
3355                         };
3356                 };
3357
3358                 cpuss4-thermal {
3359                         polling-delay-passive = <0>;
3360                         polling-delay = <0>;
3361                         thermal-sensors = <&tsens0 4>;
3362
3363                         trips {
3364                                 thermal-engine-config {
3365                                         temperature = <125000>;
3366                                         hysteresis = <1000>;
3367                                         type = "passive";
3368                                 };
3369
3370                                 reset-mon-cfg {
3371                                         temperature = <115000>;
3372                                         hysteresis = <5000>;
3373                                         type = "passive";
3374                                 };
3375                         };
3376                 };
3377
3378                 cpu4-top-thermal {
3379                         polling-delay-passive = <0>;
3380                         polling-delay = <0>;
3381                         thermal-sensors = <&tsens0 5>;
3382
3383                         trips {
3384                                 cpu4_top_alert0: trip-point0 {
3385                                         temperature = <90000>;
3386                                         hysteresis = <2000>;
3387                                         type = "passive";
3388                                 };
3389
3390                                 cpu4_top_alert1: trip-point1 {
3391                                         temperature = <95000>;
3392                                         hysteresis = <2000>;
3393                                         type = "passive";
3394                                 };
3395
3396                                 cpu4_top_crit: cpu_crit {
3397                                         temperature = <110000>;
3398                                         hysteresis = <1000>;
3399                                         type = "critical";
3400                                 };
3401                         };
3402                 };
3403
3404                 cpu4-bottom-thermal {
3405                         polling-delay-passive = <0>;
3406                         polling-delay = <0>;
3407                         thermal-sensors = <&tsens0 6>;
3408
3409                         trips {
3410                                 cpu4_bottom_alert0: trip-point0 {
3411                                         temperature = <90000>;
3412                                         hysteresis = <2000>;
3413                                         type = "passive";
3414                                 };
3415
3416                                 cpu4_bottom_alert1: trip-point1 {
3417                                         temperature = <95000>;
3418                                         hysteresis = <2000>;
3419                                         type = "passive";
3420                                 };
3421
3422                                 cpu4_bottom_crit: cpu_crit {
3423                                         temperature = <110000>;
3424                                         hysteresis = <1000>;
3425                                         type = "critical";
3426                                 };
3427                         };
3428                 };
3429
3430                 cpu5-top-thermal {
3431                         polling-delay-passive = <0>;
3432                         polling-delay = <0>;
3433                         thermal-sensors = <&tsens0 7>;
3434
3435                         trips {
3436                                 cpu5_top_alert0: trip-point0 {
3437                                         temperature = <90000>;
3438                                         hysteresis = <2000>;
3439                                         type = "passive";
3440                                 };
3441
3442                                 cpu5_top_alert1: trip-point1 {
3443                                         temperature = <95000>;
3444                                         hysteresis = <2000>;
3445                                         type = "passive";
3446                                 };
3447
3448                                 cpu5_top_crit: cpu_crit {
3449                                         temperature = <110000>;
3450                                         hysteresis = <1000>;
3451                                         type = "critical";
3452                                 };
3453                         };
3454                 };
3455
3456                 cpu5-bottom-thermal {
3457                         polling-delay-passive = <0>;
3458                         polling-delay = <0>;
3459                         thermal-sensors = <&tsens0 8>;
3460
3461                         trips {
3462                                 cpu5_bottom_alert0: trip-point0 {
3463                                         temperature = <90000>;
3464                                         hysteresis = <2000>;
3465                                         type = "passive";
3466                                 };
3467
3468                                 cpu5_bottom_alert1: trip-point1 {
3469                                         temperature = <95000>;
3470                                         hysteresis = <2000>;
3471                                         type = "passive";
3472                                 };
3473
3474                                 cpu5_bottom_crit: cpu_crit {
3475                                         temperature = <110000>;
3476                                         hysteresis = <1000>;
3477                                         type = "critical";
3478                                 };
3479                         };
3480                 };
3481
3482                 cpu6-top-thermal {
3483                         polling-delay-passive = <0>;
3484                         polling-delay = <0>;
3485                         thermal-sensors = <&tsens0 9>;
3486
3487                         trips {
3488                                 cpu6_top_alert0: trip-point0 {
3489                                         temperature = <90000>;
3490                                         hysteresis = <2000>;
3491                                         type = "passive";
3492                                 };
3493
3494                                 cpu6_top_alert1: trip-point1 {
3495                                         temperature = <95000>;
3496                                         hysteresis = <2000>;
3497                                         type = "passive";
3498                                 };
3499
3500                                 cpu6_top_crit: cpu_crit {
3501                                         temperature = <110000>;
3502                                         hysteresis = <1000>;
3503                                         type = "critical";
3504                                 };
3505                         };
3506                 };
3507
3508                 cpu6-bottom-thermal {
3509                         polling-delay-passive = <0>;
3510                         polling-delay = <0>;
3511                         thermal-sensors = <&tsens0 10>;
3512
3513                         trips {
3514                                 cpu6_bottom_alert0: trip-point0 {
3515                                         temperature = <90000>;
3516                                         hysteresis = <2000>;
3517                                         type = "passive";
3518                                 };
3519
3520                                 cpu6_bottom_alert1: trip-point1 {
3521                                         temperature = <95000>;
3522                                         hysteresis = <2000>;
3523                                         type = "passive";
3524                                 };
3525
3526                                 cpu6_bottom_crit: cpu_crit {
3527                                         temperature = <110000>;
3528                                         hysteresis = <1000>;
3529                                         type = "critical";
3530                                 };
3531                         };
3532                 };
3533
3534                 cpu7-top-thermal {
3535                         polling-delay-passive = <0>;
3536                         polling-delay = <0>;
3537                         thermal-sensors = <&tsens0 11>;
3538
3539                         trips {
3540                                 cpu7_top_alert0: trip-point0 {
3541                                         temperature = <90000>;
3542                                         hysteresis = <2000>;
3543                                         type = "passive";
3544                                 };
3545
3546                                 cpu7_top_alert1: trip-point1 {
3547                                         temperature = <95000>;
3548                                         hysteresis = <2000>;
3549                                         type = "passive";
3550                                 };
3551
3552                                 cpu7_top_crit: cpu_crit {
3553                                         temperature = <110000>;
3554                                         hysteresis = <1000>;
3555                                         type = "critical";
3556                                 };
3557                         };
3558                 };
3559
3560                 cpu7-middle-thermal {
3561                         polling-delay-passive = <0>;
3562                         polling-delay = <0>;
3563                         thermal-sensors = <&tsens0 12>;
3564
3565                         trips {
3566                                 cpu7_middle_alert0: trip-point0 {
3567                                         temperature = <90000>;
3568                                         hysteresis = <2000>;
3569                                         type = "passive";
3570                                 };
3571
3572                                 cpu7_middle_alert1: trip-point1 {
3573                                         temperature = <95000>;
3574                                         hysteresis = <2000>;
3575                                         type = "passive";
3576                                 };
3577
3578                                 cpu7_middle_crit: cpu_crit {
3579                                         temperature = <110000>;
3580                                         hysteresis = <1000>;
3581                                         type = "critical";
3582                                 };
3583                         };
3584                 };
3585
3586                 cpu7-bottom-thermal {
3587                         polling-delay-passive = <0>;
3588                         polling-delay = <0>;
3589                         thermal-sensors = <&tsens0 13>;
3590
3591                         trips {
3592                                 cpu7_bottom_alert0: trip-point0 {
3593                                         temperature = <90000>;
3594                                         hysteresis = <2000>;
3595                                         type = "passive";
3596                                 };
3597
3598                                 cpu7_bottom_alert1: trip-point1 {
3599                                         temperature = <95000>;
3600                                         hysteresis = <2000>;
3601                                         type = "passive";
3602                                 };
3603
3604                                 cpu7_bottom_crit: cpu_crit {
3605                                         temperature = <110000>;
3606                                         hysteresis = <1000>;
3607                                         type = "critical";
3608                                 };
3609                         };
3610                 };
3611
3612                 gpu-top-thermal {
3613                         polling-delay-passive = <10>;
3614                         polling-delay = <0>;
3615                         thermal-sensors = <&tsens0 14>;
3616
3617                         trips {
3618                                 thermal-engine-config {
3619                                         temperature = <125000>;
3620                                         hysteresis = <1000>;
3621                                         type = "passive";
3622                                 };
3623
3624                                 thermal-hal-config {
3625                                         temperature = <125000>;
3626                                         hysteresis = <1000>;
3627                                         type = "passive";
3628                                 };
3629
3630                                 reset-mon-cfg {
3631                                         temperature = <115000>;
3632                                         hysteresis = <5000>;
3633                                         type = "passive";
3634                                 };
3635
3636                                 gpu0_tj_cfg: tj_cfg {
3637                                         temperature = <95000>;
3638                                         hysteresis = <5000>;
3639                                         type = "passive";
3640                                 };
3641                         };
3642                 };
3643
3644                 gpu-bottom-thermal {
3645                         polling-delay-passive = <10>;
3646                         polling-delay = <0>;
3647                         thermal-sensors = <&tsens0 15>;
3648
3649                         trips {
3650                                 thermal-engine-config {
3651                                         temperature = <125000>;
3652                                         hysteresis = <1000>;
3653                                         type = "passive";
3654                                 };
3655
3656                                 thermal-hal-config {
3657                                         temperature = <125000>;
3658                                         hysteresis = <1000>;
3659                                         type = "passive";
3660                                 };
3661
3662                                 reset-mon-cfg {
3663                                         temperature = <115000>;
3664                                         hysteresis = <5000>;
3665                                         type = "passive";
3666                                 };
3667
3668                                 gpu1_tj_cfg: tj_cfg {
3669                                         temperature = <95000>;
3670                                         hysteresis = <5000>;
3671                                         type = "passive";
3672                                 };
3673                         };
3674                 };
3675
3676                 aoss1-thermal {
3677                         polling-delay-passive = <0>;
3678                         polling-delay = <0>;
3679                         thermal-sensors = <&tsens1 0>;
3680
3681                         trips {
3682                                 thermal-engine-config {
3683                                         temperature = <125000>;
3684                                         hysteresis = <1000>;
3685                                         type = "passive";
3686                                 };
3687
3688                                 reset-mon-cfg {
3689                                         temperature = <115000>;
3690                                         hysteresis = <5000>;
3691                                         type = "passive";
3692                                 };
3693                         };
3694                 };
3695
3696                 cpu0-thermal {
3697                         polling-delay-passive = <0>;
3698                         polling-delay = <0>;
3699                         thermal-sensors = <&tsens1 1>;
3700
3701                         trips {
3702                                 cpu0_alert0: trip-point0 {
3703                                         temperature = <90000>;
3704                                         hysteresis = <2000>;
3705                                         type = "passive";
3706                                 };
3707
3708                                 cpu0_alert1: trip-point1 {
3709                                         temperature = <95000>;
3710                                         hysteresis = <2000>;
3711                                         type = "passive";
3712                                 };
3713
3714                                 cpu0_crit: cpu_crit {
3715                                         temperature = <110000>;
3716                                         hysteresis = <1000>;
3717                                         type = "critical";
3718                                 };
3719                         };
3720                 };
3721
3722                 cpu1-thermal {
3723                         polling-delay-passive = <0>;
3724                         polling-delay = <0>;
3725                         thermal-sensors = <&tsens1 2>;
3726
3727                         trips {
3728                                 cpu1_alert0: trip-point0 {
3729                                         temperature = <90000>;
3730                                         hysteresis = <2000>;
3731                                         type = "passive";
3732                                 };
3733
3734                                 cpu1_alert1: trip-point1 {
3735                                         temperature = <95000>;
3736                                         hysteresis = <2000>;
3737                                         type = "passive";
3738                                 };
3739
3740                                 cpu1_crit: cpu_crit {
3741                                         temperature = <110000>;
3742                                         hysteresis = <1000>;
3743                                         type = "critical";
3744                                 };
3745                         };
3746                 };
3747
3748                 cpu2-thermal {
3749                         polling-delay-passive = <0>;
3750                         polling-delay = <0>;
3751                         thermal-sensors = <&tsens1 3>;
3752
3753                         trips {
3754                                 cpu2_alert0: trip-point0 {
3755                                         temperature = <90000>;
3756                                         hysteresis = <2000>;
3757                                         type = "passive";
3758                                 };
3759
3760                                 cpu2_alert1: trip-point1 {
3761                                         temperature = <95000>;
3762                                         hysteresis = <2000>;
3763                                         type = "passive";
3764                                 };
3765
3766                                 cpu2_crit: cpu_crit {
3767                                         temperature = <110000>;
3768                                         hysteresis = <1000>;
3769                                         type = "critical";
3770                                 };
3771                         };
3772                 };
3773
3774                 cpu3-thermal {
3775                         polling-delay-passive = <0>;
3776                         polling-delay = <0>;
3777                         thermal-sensors = <&tsens1 4>;
3778
3779                         trips {
3780                                 cpu3_alert0: trip-point0 {
3781                                         temperature = <90000>;
3782                                         hysteresis = <2000>;
3783                                         type = "passive";
3784                                 };
3785
3786                                 cpu3_alert1: trip-point1 {
3787                                         temperature = <95000>;
3788                                         hysteresis = <2000>;
3789                                         type = "passive";
3790                                 };
3791
3792                                 cpu3_crit: cpu_crit {
3793                                         temperature = <110000>;
3794                                         hysteresis = <1000>;
3795                                         type = "critical";
3796                                 };
3797                         };
3798                 };
3799
3800                 cdsp0-thermal {
3801                         polling-delay-passive = <10>;
3802                         polling-delay = <0>;
3803                         thermal-sensors = <&tsens1 5>;
3804
3805                         trips {
3806                                 thermal-engine-config {
3807                                         temperature = <125000>;
3808                                         hysteresis = <1000>;
3809                                         type = "passive";
3810                                 };
3811
3812                                 thermal-hal-config {
3813                                         temperature = <125000>;
3814                                         hysteresis = <1000>;
3815                                         type = "passive";
3816                                 };
3817
3818                                 reset-mon-cfg {
3819                                         temperature = <115000>;
3820                                         hysteresis = <5000>;
3821                                         type = "passive";
3822                                 };
3823
3824                                 cdsp_0_config: junction-config {
3825                                         temperature = <95000>;
3826                                         hysteresis = <5000>;
3827                                         type = "passive";
3828                                 };
3829                         };
3830                 };
3831
3832                 cdsp1-thermal {
3833                         polling-delay-passive = <10>;
3834                         polling-delay = <0>;
3835                         thermal-sensors = <&tsens1 6>;
3836
3837                         trips {
3838                                 thermal-engine-config {
3839                                         temperature = <125000>;
3840                                         hysteresis = <1000>;
3841                                         type = "passive";
3842                                 };
3843
3844                                 thermal-hal-config {
3845                                         temperature = <125000>;
3846                                         hysteresis = <1000>;
3847                                         type = "passive";
3848                                 };
3849
3850                                 reset-mon-cfg {
3851                                         temperature = <115000>;
3852                                         hysteresis = <5000>;
3853                                         type = "passive";
3854                                 };
3855
3856                                 cdsp_1_config: junction-config {
3857                                         temperature = <95000>;
3858                                         hysteresis = <5000>;
3859                                         type = "passive";
3860                                 };
3861                         };
3862                 };
3863
3864                 cdsp2-thermal {
3865                         polling-delay-passive = <10>;
3866                         polling-delay = <0>;
3867                         thermal-sensors = <&tsens1 7>;
3868
3869                         trips {
3870                                 thermal-engine-config {
3871                                         temperature = <125000>;
3872                                         hysteresis = <1000>;
3873                                         type = "passive";
3874                                 };
3875
3876                                 thermal-hal-config {
3877                                         temperature = <125000>;
3878                                         hysteresis = <1000>;
3879                                         type = "passive";
3880                                 };
3881
3882                                 reset-mon-cfg {
3883                                         temperature = <115000>;
3884                                         hysteresis = <5000>;
3885                                         type = "passive";
3886                                 };
3887
3888                                 cdsp_2_config: junction-config {
3889                                         temperature = <95000>;
3890                                         hysteresis = <5000>;
3891                                         type = "passive";
3892                                 };
3893                         };
3894                 };
3895
3896                 video-thermal {
3897                         polling-delay-passive = <0>;
3898                         polling-delay = <0>;
3899                         thermal-sensors = <&tsens1 8>;
3900
3901                         trips {
3902                                 thermal-engine-config {
3903                                         temperature = <125000>;
3904                                         hysteresis = <1000>;
3905                                         type = "passive";
3906                                 };
3907
3908                                 reset-mon-cfg {
3909                                         temperature = <115000>;
3910                                         hysteresis = <5000>;
3911                                         type = "passive";
3912                                 };
3913                         };
3914                 };
3915
3916                 mem-thermal {
3917                         polling-delay-passive = <10>;
3918                         polling-delay = <0>;
3919                         thermal-sensors = <&tsens1 9>;
3920
3921                         trips {
3922                                 thermal-engine-config {
3923                                         temperature = <125000>;
3924                                         hysteresis = <1000>;
3925                                         type = "passive";
3926                                 };
3927
3928                                 ddr_config0: ddr0-config {
3929                                         temperature = <90000>;
3930                                         hysteresis = <5000>;
3931                                         type = "passive";
3932                                 };
3933
3934                                 reset-mon-cfg {
3935                                         temperature = <115000>;
3936                                         hysteresis = <5000>;
3937                                         type = "passive";
3938                                 };
3939                         };
3940                 };
3941
3942                 modem0-thermal {
3943                         polling-delay-passive = <0>;
3944                         polling-delay = <0>;
3945                         thermal-sensors = <&tsens1 10>;
3946
3947                         trips {
3948                                 thermal-engine-config {
3949                                         temperature = <125000>;
3950                                         hysteresis = <1000>;
3951                                         type = "passive";
3952                                 };
3953
3954                                 mdmss0_config0: mdmss0-config0 {
3955                                         temperature = <102000>;
3956                                         hysteresis = <3000>;
3957                                         type = "passive";
3958                                 };
3959
3960                                 mdmss0_config1: mdmss0-config1 {
3961                                         temperature = <105000>;
3962                                         hysteresis = <3000>;
3963                                         type = "passive";
3964                                 };
3965
3966                                 reset-mon-cfg {
3967                                         temperature = <115000>;
3968                                         hysteresis = <5000>;
3969                                         type = "passive";
3970                                 };
3971                         };
3972                 };
3973
3974                 modem1-thermal {
3975                         polling-delay-passive = <0>;
3976                         polling-delay = <0>;
3977                         thermal-sensors = <&tsens1 11>;
3978
3979                         trips {
3980                                 thermal-engine-config {
3981                                         temperature = <125000>;
3982                                         hysteresis = <1000>;
3983                                         type = "passive";
3984                                 };
3985
3986                                 mdmss1_config0: mdmss1-config0 {
3987                                         temperature = <102000>;
3988                                         hysteresis = <3000>;
3989                                         type = "passive";
3990                                 };
3991
3992                                 mdmss1_config1: mdmss1-config1 {
3993                                         temperature = <105000>;
3994                                         hysteresis = <3000>;
3995                                         type = "passive";
3996                                 };
3997
3998                                 reset-mon-cfg {
3999                                         temperature = <115000>;
4000                                         hysteresis = <5000>;
4001                                         type = "passive";
4002                                 };
4003                         };
4004                 };
4005
4006                 modem2-thermal {
4007                         polling-delay-passive = <0>;
4008                         polling-delay = <0>;
4009                         thermal-sensors = <&tsens1 12>;
4010
4011                         trips {
4012                                 thermal-engine-config {
4013                                         temperature = <125000>;
4014                                         hysteresis = <1000>;
4015                                         type = "passive";
4016                                 };
4017
4018                                 mdmss2_config0: mdmss2-config0 {
4019                                         temperature = <102000>;
4020                                         hysteresis = <3000>;
4021                                         type = "passive";
4022                                 };
4023
4024                                 mdmss2_config1: mdmss2-config1 {
4025                                         temperature = <105000>;
4026                                         hysteresis = <3000>;
4027                                         type = "passive";
4028                                 };
4029
4030                                 reset-mon-cfg {
4031                                         temperature = <115000>;
4032                                         hysteresis = <5000>;
4033                                         type = "passive";
4034                                 };
4035                         };
4036                 };
4037
4038                 modem3-thermal {
4039                         polling-delay-passive = <0>;
4040                         polling-delay = <0>;
4041                         thermal-sensors = <&tsens1 13>;
4042
4043                         trips {
4044                                 thermal-engine-config {
4045                                         temperature = <125000>;
4046                                         hysteresis = <1000>;
4047                                         type = "passive";
4048                                 };
4049
4050                                 mdmss3_config0: mdmss3-config0 {
4051                                         temperature = <102000>;
4052                                         hysteresis = <3000>;
4053                                         type = "passive";
4054                                 };
4055
4056                                 mdmss3_config1: mdmss3-config1 {
4057                                         temperature = <105000>;
4058                                         hysteresis = <3000>;
4059                                         type = "passive";
4060                                 };
4061
4062                                 reset-mon-cfg {
4063                                         temperature = <115000>;
4064                                         hysteresis = <5000>;
4065                                         type = "passive";
4066                                 };
4067                         };
4068                 };
4069
4070                 camera0-thermal {
4071                         polling-delay-passive = <0>;
4072                         polling-delay = <0>;
4073                         thermal-sensors = <&tsens1 14>;
4074
4075                         trips {
4076                                 thermal-engine-config {
4077                                         temperature = <125000>;
4078                                         hysteresis = <1000>;
4079                                         type = "passive";
4080                                 };
4081
4082                                 reset-mon-cfg {
4083                                         temperature = <115000>;
4084                                         hysteresis = <5000>;
4085                                         type = "passive";
4086                                 };
4087                         };
4088                 };
4089
4090                 camera1-thermal {
4091                         polling-delay-passive = <0>;
4092                         polling-delay = <0>;
4093                         thermal-sensors = <&tsens1 15>;
4094
4095                         trips {
4096                                 thermal-engine-config {
4097                                         temperature = <125000>;
4098                                         hysteresis = <1000>;
4099                                         type = "passive";
4100                                 };
4101
4102                                 reset-mon-cfg {
4103                                         temperature = <115000>;
4104                                         hysteresis = <5000>;
4105                                         type = "passive";
4106                                 };
4107                         };
4108                 };
4109         };
4110
4111         timer {
4112                 compatible = "arm,armv8-timer";
4113                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4114                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4115                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
4116                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
4117                 clock-frequency = <19200000>;
4118         };
4119 };