arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/dma/qcom-gpi.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interconnect/qcom,sm8350.h>
  13 #include <dt-bindings/mailbox/qcom-ipcc.h>
  14 #include <dt-bindings/power/qcom-rpmpd.h>
  15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17 #include <dt-bindings/interconnect/qcom,sm8350.h>
  18
  19 / {
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         clocks {
  28                 xo_board: xo-board {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                         clock-frequency = <38400000>;
  32                         clock-output-names = "xo_board";
  33                 };
  34
  35                 sleep_clk: sleep-clk {
  36                         compatible = "fixed-clock";
  37                         clock-frequency = <32000>;
  38                         #clock-cells = <0>;
  39                 };
  40
  41                 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <1000>;
  44                         #clock-cells = <0>;
  45                 };
  46
  47                 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
  48                         compatible = "fixed-clock";
  49                         clock-frequency = <1000>;
  50                         #clock-cells = <0>;
  51                 };
  52
  53                 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
  54                         compatible = "fixed-clock";
  55                         clock-frequency = <1000>;
  56                         #clock-cells = <0>;
  57                 };
  58         };
  59
  60         cpus {
  61                 #address-cells = <2>;
  62                 #size-cells = <0>;
  63
  64                 CPU0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a55";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                         next-level-cache = <&L2_0>;
  70                         qcom,freq-domain = <&cpufreq_hw 0>;
  71                         power-domains = <&CPU_PD0>;
  72                         power-domain-names = "psci";
  73                         #cooling-cells = <2>;
  74                         L2_0: l2-cache {
  75                               compatible = "cache";
  76                               next-level-cache = <&L3_0>;
  77                                 L3_0: l3-cache {
  78                                       compatible = "cache";
  79                                 };
  80                         };
  81                 };
  82
  83                 CPU1: cpu@100 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a55";
  86                         reg = <0x0 0x100>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&L2_100>;
  89                         qcom,freq-domain = <&cpufreq_hw 0>;
  90                         power-domains = <&CPU_PD1>;
  91                         power-domain-names = "psci";
  92                         #cooling-cells = <2>;
  93                         L2_100: l2-cache {
  94                               compatible = "cache";
  95                               next-level-cache = <&L3_0>;
  96                         };
  97                 };
  98
  99                 CPU2: cpu@200 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a55";
 102                         reg = <0x0 0x200>;
 103                         enable-method = "psci";
 104                         next-level-cache = <&L2_200>;
 105                         qcom,freq-domain = <&cpufreq_hw 0>;
 106                         power-domains = <&CPU_PD2>;
 107                         power-domain-names = "psci";
 108                         #cooling-cells = <2>;
 109                         L2_200: l2-cache {
 110                               compatible = "cache";
 111                               next-level-cache = <&L3_0>;
 112                         };
 113                 };
 114
 115                 CPU3: cpu@300 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a55";
 118                         reg = <0x0 0x300>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_300>;
 121                         qcom,freq-domain = <&cpufreq_hw 0>;
 122                         power-domains = <&CPU_PD3>;
 123                         power-domain-names = "psci";
 124                         #cooling-cells = <2>;
 125                         L2_300: l2-cache {
 126                               compatible = "cache";
 127                               next-level-cache = <&L3_0>;
 128                         };
 129                 };
 130
 131                 CPU4: cpu@400 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a78";
 134                         reg = <0x0 0x400>;
 135                         enable-method = "psci";
 136                         next-level-cache = <&L2_400>;
 137                         qcom,freq-domain = <&cpufreq_hw 1>;
 138                         power-domains = <&CPU_PD4>;
 139                         power-domain-names = "psci";
 140                         #cooling-cells = <2>;
 141                         L2_400: l2-cache {
 142                               compatible = "cache";
 143                               next-level-cache = <&L3_0>;
 144                         };
 145                 };
 146
 147                 CPU5: cpu@500 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a78";
 150                         reg = <0x0 0x500>;
 151                         enable-method = "psci";
 152                         next-level-cache = <&L2_500>;
 153                         qcom,freq-domain = <&cpufreq_hw 1>;
 154                         power-domains = <&CPU_PD5>;
 155                         power-domain-names = "psci";
 156                         #cooling-cells = <2>;
 157                         L2_500: l2-cache {
 158                               compatible = "cache";
 159                               next-level-cache = <&L3_0>;
 160                         };
 161
 162                 };
 163
 164                 CPU6: cpu@600 {
 165                         device_type = "cpu";
 166                         compatible = "arm,cortex-a78";
 167                         reg = <0x0 0x600>;
 168                         enable-method = "psci";
 169                         next-level-cache = <&L2_600>;
 170                         qcom,freq-domain = <&cpufreq_hw 1>;
 171                         power-domains = <&CPU_PD6>;
 172                         power-domain-names = "psci";
 173                         #cooling-cells = <2>;
 174                         L2_600: l2-cache {
 175                               compatible = "cache";
 176                               next-level-cache = <&L3_0>;
 177                         };
 178                 };
 179
 180                 CPU7: cpu@700 {
 181                         device_type = "cpu";
 182                         compatible = "arm,cortex-x1";
 183                         reg = <0x0 0x700>;
 184                         enable-method = "psci";
 185                         next-level-cache = <&L2_700>;
 186                         qcom,freq-domain = <&cpufreq_hw 2>;
 187                         power-domains = <&CPU_PD7>;
 188                         power-domain-names = "psci";
 189                         #cooling-cells = <2>;
 190                         L2_700: l2-cache {
 191                               compatible = "cache";
 192                               next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 cpu-map {
 197                         cluster0 {
 198                                 core0 {
 199                                         cpu = <&CPU0>;
 200                                 };
 201
 202                                 core1 {
 203                                         cpu = <&CPU1>;
 204                                 };
 205
 206                                 core2 {
 207                                         cpu = <&CPU2>;
 208                                 };
 209
 210                                 core3 {
 211                                         cpu = <&CPU3>;
 212                                 };
 213
 214                                 core4 {
 215                                         cpu = <&CPU4>;
 216                                 };
 217
 218                                 core5 {
 219                                         cpu = <&CPU5>;
 220                                 };
 221
 222                                 core6 {
 223                                         cpu = <&CPU6>;
 224                                 };
 225
 226                                 core7 {
 227                                         cpu = <&CPU7>;
 228                                 };
 229                         };
 230                 };
 231
 232                 idle-states {
 233                         entry-method = "psci";
 234
 235                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 236                                 compatible = "arm,idle-state";
 237                                 idle-state-name = "silver-rail-power-collapse";
 238                                 arm,psci-suspend-param = <0x40000004>;
 239                                 entry-latency-us = <360>;
 240                                 exit-latency-us = <531>;
 241                                 min-residency-us = <3934>;
 242                                 local-timer-stop;
 243                         };
 244
 245                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 246                                 compatible = "arm,idle-state";
 247                                 idle-state-name = "gold-rail-power-collapse";
 248                                 arm,psci-suspend-param = <0x40000004>;
 249                                 entry-latency-us = <702>;
 250                                 exit-latency-us = <1061>;
 251                                 min-residency-us = <4488>;
 252                                 local-timer-stop;
 253                         };
 254                 };
 255
 256                 domain-idle-states {
 257                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 258                                 compatible = "domain-idle-state";
 259                                 idle-state-name = "cluster-power-collapse";
 260                                 arm,psci-suspend-param = <0x4100c344>;
 261                                 entry-latency-us = <3263>;
 262                                 exit-latency-us = <6562>;
 263                                 min-residency-us = <9987>;
 264                                 local-timer-stop;
 265                         };
 266                 };
 267         };
 268
 269         firmware {
 270                 scm: scm {
 271                         compatible = "qcom,scm-sm8350", "qcom,scm";
 272                         #reset-cells = <1>;
 273                 };
 274         };
 275
 276         memory@80000000 {
 277                 device_type = "memory";
 278                 /* We expect the bootloader to fill in the size */
 279                 reg = <0x0 0x80000000 0x0 0x0>;
 280         };
 281
 282         pmu {
 283                 compatible = "arm,armv8-pmuv3";
 284                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 285         };
 286
 287         psci {
 288                 compatible = "arm,psci-1.0";
 289                 method = "smc";
 290
 291                 CPU_PD0: cpu0 {
 292                         #power-domain-cells = <0>;
 293                         power-domains = <&CLUSTER_PD>;
 294                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 295                 };
 296
 297                 CPU_PD1: cpu1 {
 298                         #power-domain-cells = <0>;
 299                         power-domains = <&CLUSTER_PD>;
 300                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 301                 };
 302
 303                 CPU_PD2: cpu2 {
 304                         #power-domain-cells = <0>;
 305                         power-domains = <&CLUSTER_PD>;
 306                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 307                 };
 308
 309                 CPU_PD3: cpu3 {
 310                         #power-domain-cells = <0>;
 311                         power-domains = <&CLUSTER_PD>;
 312                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 313                 };
 314
 315                 CPU_PD4: cpu4 {
 316                         #power-domain-cells = <0>;
 317                         power-domains = <&CLUSTER_PD>;
 318                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 319                 };
 320
 321                 CPU_PD5: cpu5 {
 322                         #power-domain-cells = <0>;
 323                         power-domains = <&CLUSTER_PD>;
 324                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 325                 };
 326
 327                 CPU_PD6: cpu6 {
 328                         #power-domain-cells = <0>;
 329                         power-domains = <&CLUSTER_PD>;
 330                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 331                 };
 332
 333                 CPU_PD7: cpu7 {
 334                         #power-domain-cells = <0>;
 335                         power-domains = <&CLUSTER_PD>;
 336                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 337                 };
 338
 339                 CLUSTER_PD: cpu-cluster0 {
 340                         #power-domain-cells = <0>;
 341                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 342                 };
 343         };
 344
 345         qup_opp_table_100mhz: opp-table-qup100mhz {
 346                 compatible = "operating-points-v2";
 347
 348                 opp-50000000 {
 349                         opp-hz = /bits/ 64 <50000000>;
 350                         required-opps = <&rpmhpd_opp_min_svs>;
 351                 };
 352
 353                 opp-75000000 {
 354                         opp-hz = /bits/ 64 <75000000>;
 355                         required-opps = <&rpmhpd_opp_low_svs>;
 356                 };
 357
 358                 opp-100000000 {
 359                         opp-hz = /bits/ 64 <100000000>;
 360                         required-opps = <&rpmhpd_opp_svs>;
 361                 };
 362         };
 363
 364         qup_opp_table_120mhz: opp-table-qup120mhz {
 365                 compatible = "operating-points-v2";
 366
 367                 opp-50000000 {
 368                         opp-hz = /bits/ 64 <50000000>;
 369                         required-opps = <&rpmhpd_opp_min_svs>;
 370                 };
 371
 372                 opp-75000000 {
 373                         opp-hz = /bits/ 64 <75000000>;
 374                         required-opps = <&rpmhpd_opp_low_svs>;
 375                 };
 376
 377                 opp-120000000 {
 378                         opp-hz = /bits/ 64 <120000000>;
 379                         required-opps = <&rpmhpd_opp_svs>;
 380                 };
 381         };
 382
 383         reserved_memory: reserved-memory {
 384                 #address-cells = <2>;
 385                 #size-cells = <2>;
 386                 ranges;
 387
 388                 hyp_mem: memory@80000000 {
 389                         reg = <0x0 0x80000000 0x0 0x600000>;
 390                         no-map;
 391                 };
 392
 393                 xbl_aop_mem: memory@80700000 {
 394                         no-map;
 395                         reg = <0x0 0x80700000 0x0 0x160000>;
 396                 };
 397
 398                 cmd_db: memory@80860000 {
 399                         compatible = "qcom,cmd-db";
 400                         reg = <0x0 0x80860000 0x0 0x20000>;
 401                         no-map;
 402                 };
 403
 404                 reserved_xbl_uefi_log: memory@80880000 {
 405                         reg = <0x0 0x80880000 0x0 0x14000>;
 406                         no-map;
 407                 };
 408
 409                 smem_mem: memory@80900000 {
 410                         reg = <0x0 0x80900000 0x0 0x200000>;
 411                         no-map;
 412                 };
 413
 414                 cpucp_fw_mem: memory@80b00000 {
 415                         reg = <0x0 0x80b00000 0x0 0x100000>;
 416                         no-map;
 417                 };
 418
 419                 cdsp_secure_heap: memory@80c00000 {
 420                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 421                         no-map;
 422                 };
 423
 424                 pil_camera_mem: mmeory@85200000 {
 425                         reg = <0x0 0x85200000 0x0 0x500000>;
 426                         no-map;
 427                 };
 428
 429                 pil_video_mem: memory@85700000 {
 430                         reg = <0x0 0x85700000 0x0 0x500000>;
 431                         no-map;
 432                 };
 433
 434                 pil_cvp_mem: memory@85c00000 {
 435                         reg = <0x0 0x85c00000 0x0 0x500000>;
 436                         no-map;
 437                 };
 438
 439                 pil_adsp_mem: memory@86100000 {
 440                         reg = <0x0 0x86100000 0x0 0x2100000>;
 441                         no-map;
 442                 };
 443
 444                 pil_slpi_mem: memory@88200000 {
 445                         reg = <0x0 0x88200000 0x0 0x1500000>;
 446                         no-map;
 447                 };
 448
 449                 pil_cdsp_mem: memory@89700000 {
 450                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 451                         no-map;
 452                 };
 453
 454                 pil_ipa_fw_mem: memory@8b500000 {
 455                         reg = <0x0 0x8b500000 0x0 0x10000>;
 456                         no-map;
 457                 };
 458
 459                 pil_ipa_gsi_mem: memory@8b510000 {
 460                         reg = <0x0 0x8b510000 0x0 0xa000>;
 461                         no-map;
 462                 };
 463
 464                 pil_gpu_mem: memory@8b51a000 {
 465                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 466                         no-map;
 467                 };
 468
 469                 pil_spss_mem: memory@8b600000 {
 470                         reg = <0x0 0x8b600000 0x0 0x100000>;
 471                         no-map;
 472                 };
 473
 474                 pil_modem_mem: memory@8b800000 {
 475                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 476                         no-map;
 477                 };
 478
 479                 rmtfs_mem: memory@9b800000 {
 480                         compatible = "qcom,rmtfs-mem";
 481                         reg = <0x0 0x9b800000 0x0 0x280000>;
 482                         no-map;
 483
 484                         qcom,client-id = <1>;
 485                         qcom,vmid = <15>;
 486                 };
 487
 488                 hyp_reserved_mem: memory@d0000000 {
 489                         reg = <0x0 0xd0000000 0x0 0x800000>;
 490                         no-map;
 491                 };
 492
 493                 pil_trustedvm_mem: memory@d0800000 {
 494                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 495                         no-map;
 496                 };
 497
 498                 qrtr_shbuf: memory@d7ef7000 {
 499                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 500                         no-map;
 501                 };
 502
 503                 chan0_shbuf: memory@d7f00000 {
 504                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 505                         no-map;
 506                 };
 507
 508                 chan1_shbuf: memory@d7f80000 {
 509                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 510                         no-map;
 511                 };
 512
 513                 removed_mem: memory@d8800000 {
 514                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 515                         no-map;
 516                 };
 517         };
 518
 519         smem: qcom,smem {
 520                 compatible = "qcom,smem";
 521                 memory-region = <&smem_mem>;
 522                 hwlocks = <&tcsr_mutex 3>;
 523         };
 524
 525         smp2p-adsp {
 526                 compatible = "qcom,smp2p";
 527                 qcom,smem = <443>, <429>;
 528                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 529                                              IPCC_MPROC_SIGNAL_SMP2P
 530                                              IRQ_TYPE_EDGE_RISING>;
 531                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 532                                 IPCC_MPROC_SIGNAL_SMP2P>;
 533
 534                 qcom,local-pid = <0>;
 535                 qcom,remote-pid = <2>;
 536
 537                 smp2p_adsp_out: master-kernel {
 538                         qcom,entry-name = "master-kernel";
 539                         #qcom,smem-state-cells = <1>;
 540                 };
 541
 542                 smp2p_adsp_in: slave-kernel {
 543                         qcom,entry-name = "slave-kernel";
 544                         interrupt-controller;
 545                         #interrupt-cells = <2>;
 546                 };
 547         };
 548
 549         smp2p-cdsp {
 550                 compatible = "qcom,smp2p";
 551                 qcom,smem = <94>, <432>;
 552                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 553                                              IPCC_MPROC_SIGNAL_SMP2P
 554                                              IRQ_TYPE_EDGE_RISING>;
 555                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 556                                 IPCC_MPROC_SIGNAL_SMP2P>;
 557
 558                 qcom,local-pid = <0>;
 559                 qcom,remote-pid = <5>;
 560
 561                 smp2p_cdsp_out: master-kernel {
 562                         qcom,entry-name = "master-kernel";
 563                         #qcom,smem-state-cells = <1>;
 564                 };
 565
 566                 smp2p_cdsp_in: slave-kernel {
 567                         qcom,entry-name = "slave-kernel";
 568                         interrupt-controller;
 569                         #interrupt-cells = <2>;
 570                 };
 571         };
 572
 573         smp2p-modem {
 574                 compatible = "qcom,smp2p";
 575                 qcom,smem = <435>, <428>;
 576                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 577                                              IPCC_MPROC_SIGNAL_SMP2P
 578                                              IRQ_TYPE_EDGE_RISING>;
 579                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 580                                 IPCC_MPROC_SIGNAL_SMP2P>;
 581
 582                 qcom,local-pid = <0>;
 583                 qcom,remote-pid = <1>;
 584
 585                 smp2p_modem_out: master-kernel {
 586                         qcom,entry-name = "master-kernel";
 587                         #qcom,smem-state-cells = <1>;
 588                 };
 589
 590                 smp2p_modem_in: slave-kernel {
 591                         qcom,entry-name = "slave-kernel";
 592                         interrupt-controller;
 593                         #interrupt-cells = <2>;
 594                 };
 595
 596                 ipa_smp2p_out: ipa-ap-to-modem {
 597                         qcom,entry-name = "ipa";
 598                         #qcom,smem-state-cells = <1>;
 599                 };
 600
 601                 ipa_smp2p_in: ipa-modem-to-ap {
 602                         qcom,entry-name = "ipa";
 603                         interrupt-controller;
 604                         #interrupt-cells = <2>;
 605                 };
 606         };
 607
 608         smp2p-slpi {
 609                 compatible = "qcom,smp2p";
 610                 qcom,smem = <481>, <430>;
 611                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 612                                              IPCC_MPROC_SIGNAL_SMP2P
 613                                              IRQ_TYPE_EDGE_RISING>;
 614                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 615                                 IPCC_MPROC_SIGNAL_SMP2P>;
 616
 617                 qcom,local-pid = <0>;
 618                 qcom,remote-pid = <3>;
 619
 620                 smp2p_slpi_out: master-kernel {
 621                         qcom,entry-name = "master-kernel";
 622                         #qcom,smem-state-cells = <1>;
 623                 };
 624
 625                 smp2p_slpi_in: slave-kernel {
 626                         qcom,entry-name = "slave-kernel";
 627                         interrupt-controller;
 628                         #interrupt-cells = <2>;
 629                 };
 630         };
 631
 632         soc: soc@0 {
 633                 #address-cells = <2>;
 634                 #size-cells = <2>;
 635                 ranges = <0 0 0 0 0x10 0>;
 636                 dma-ranges = <0 0 0 0 0x10 0>;
 637                 compatible = "simple-bus";
 638
 639                 gcc: clock-controller@100000 {
 640                         compatible = "qcom,gcc-sm8350";
 641                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 642                         #clock-cells = <1>;
 643                         #reset-cells = <1>;
 644                         #power-domain-cells = <1>;
 645                         clock-names = "bi_tcxo",
 646                                       "sleep_clk",
 647                                       "pcie_0_pipe_clk",
 648                                       "pcie_1_pipe_clk",
 649                                       "ufs_card_rx_symbol_0_clk",
 650                                       "ufs_card_rx_symbol_1_clk",
 651                                       "ufs_card_tx_symbol_0_clk",
 652                                       "ufs_phy_rx_symbol_0_clk",
 653                                       "ufs_phy_rx_symbol_1_clk",
 654                                       "ufs_phy_tx_symbol_0_clk",
 655                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk",
 656                                       "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
 657                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 658                                  <&sleep_clk>,
 659                                  <0>,
 660                                  <0>,
 661                                  <0>,
 662                                  <0>,
 663                                  <0>,
 664                                  <&ufs_phy_rx_symbol_0_clk>,
 665                                  <&ufs_phy_rx_symbol_1_clk>,
 666                                  <&ufs_phy_tx_symbol_0_clk>,
 667                                  <0>,
 668                                  <0>;
 669                 };
 670
 671                 ipcc: mailbox@408000 {
 672                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 673                         reg = <0 0x00408000 0 0x1000>;
 674                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 675                         interrupt-controller;
 676                         #interrupt-cells = <3>;
 677                         #mbox-cells = <2>;
 678                 };
 679
 680                 gpi_dma2: dma-controller@800000 {
 681                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
 682                         reg = <0 0x00800000 0 0x60000>;
 683                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 695                         dma-channels = <12>;
 696                         dma-channel-mask = <0xff>;
 697                         iommus = <&apps_smmu 0x5f6 0x0>;
 698                         #dma-cells = <3>;
 699                         status = "disabled";
 700                 };
 701
 702                 qupv3_id_2: geniqup@8c0000 {
 703                         compatible = "qcom,geni-se-qup";
 704                         reg = <0x0 0x008c0000 0x0 0x6000>;
 705                         clock-names = "m-ahb", "s-ahb";
 706                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 707                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 708                         iommus = <&apps_smmu 0x5e3 0x0>;
 709                         #address-cells = <2>;
 710                         #size-cells = <2>;
 711                         ranges;
 712                         status = "disabled";
 713
 714                         i2c14: i2c@880000 {
 715                                 compatible = "qcom,geni-i2c";
 716                                 reg = <0 0x00880000 0 0x4000>;
 717                                 clock-names = "se";
 718                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 719                                 pinctrl-names = "default";
 720                                 pinctrl-0 = <&qup_i2c14_default>;
 721                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 722                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 723                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 724                                 dma-names = "tx", "rx";
 725                                 #address-cells = <1>;
 726                                 #size-cells = <0>;
 727                                 status = "disabled";
 728                         };
 729
 730                         spi14: spi@880000 {
 731                                 compatible = "qcom,geni-spi";
 732                                 reg = <0 0x00880000 0 0x4000>;
 733                                 clock-names = "se";
 734                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 735                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 736                                 power-domains = <&rpmhpd SM8350_CX>;
 737                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 738                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 739                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 740                                 dma-names = "tx", "rx";
 741                                 #address-cells = <1>;
 742                                 #size-cells = <0>;
 743                                 status = "disabled";
 744                         };
 745
 746                         i2c15: i2c@884000 {
 747                                 compatible = "qcom,geni-i2c";
 748                                 reg = <0 0x00884000 0 0x4000>;
 749                                 clock-names = "se";
 750                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 751                                 pinctrl-names = "default";
 752                                 pinctrl-0 = <&qup_i2c15_default>;
 753                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 754                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 755                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 756                                 dma-names = "tx", "rx";
 757                                 #address-cells = <1>;
 758                                 #size-cells = <0>;
 759                                 status = "disabled";
 760                         };
 761
 762                         spi15: spi@884000 {
 763                                 compatible = "qcom,geni-spi";
 764                                 reg = <0 0x00884000 0 0x4000>;
 765                                 clock-names = "se";
 766                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 767                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 768                                 power-domains = <&rpmhpd SM8350_CX>;
 769                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 770                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 771                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 772                                 dma-names = "tx", "rx";
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 status = "disabled";
 776                         };
 777
 778                         i2c16: i2c@888000 {
 779                                 compatible = "qcom,geni-i2c";
 780                                 reg = <0 0x00888000 0 0x4000>;
 781                                 clock-names = "se";
 782                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 783                                 pinctrl-names = "default";
 784                                 pinctrl-0 = <&qup_i2c16_default>;
 785                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 786                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 787                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 788                                 dma-names = "tx", "rx";
 789                                 #address-cells = <1>;
 790                                 #size-cells = <0>;
 791                                 status = "disabled";
 792                         };
 793
 794                         spi16: spi@888000 {
 795                                 compatible = "qcom,geni-spi";
 796                                 reg = <0 0x00888000 0 0x4000>;
 797                                 clock-names = "se";
 798                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 799                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 800                                 power-domains = <&rpmhpd SM8350_CX>;
 801                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 802                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 803                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 804                                 dma-names = "tx", "rx";
 805                                 #address-cells = <1>;
 806                                 #size-cells = <0>;
 807                                 status = "disabled";
 808                         };
 809
 810                         i2c17: i2c@88c000 {
 811                                 compatible = "qcom,geni-i2c";
 812                                 reg = <0 0x0088c000 0 0x4000>;
 813                                 clock-names = "se";
 814                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 815                                 pinctrl-names = "default";
 816                                 pinctrl-0 = <&qup_i2c17_default>;
 817                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 818                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 819                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 820                                 dma-names = "tx", "rx";
 821                                 #address-cells = <1>;
 822                                 #size-cells = <0>;
 823                                 status = "disabled";
 824                         };
 825
 826                         spi17: spi@88c000 {
 827                                 compatible = "qcom,geni-spi";
 828                                 reg = <0 0x0088c000 0 0x4000>;
 829                                 clock-names = "se";
 830                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 831                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 832                                 power-domains = <&rpmhpd SM8350_CX>;
 833                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 834                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
 835                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
 836                                 dma-names = "tx", "rx";
 837                                 #address-cells = <1>;
 838                                 #size-cells = <0>;
 839                                 status = "disabled";
 840                         };
 841
 842                         /* QUP no. 18 seems to be strictly SPI/UART-only */
 843
 844                         spi18: spi@890000 {
 845                                 compatible = "qcom,geni-spi";
 846                                 reg = <0 0x00890000 0 0x4000>;
 847                                 clock-names = "se";
 848                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 849                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 850                                 power-domains = <&rpmhpd SM8350_CX>;
 851                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 852                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
 853                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
 854                                 dma-names = "tx", "rx";
 855                                 #address-cells = <1>;
 856                                 #size-cells = <0>;
 857                                 status = "disabled";
 858                         };
 859
 860                         uart18: serial@890000 {
 861                                 compatible = "qcom,geni-uart";
 862                                 reg = <0 0x00890000 0 0x4000>;
 863                                 clock-names = "se";
 864                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 865                                 pinctrl-names = "default";
 866                                 pinctrl-0 = <&qup_uart18_default>;
 867                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 868                                 power-domains = <&rpmhpd SM8350_CX>;
 869                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 870                                 status = "disabled";
 871                         };
 872
 873                         i2c19: i2c@894000 {
 874                                 compatible = "qcom,geni-i2c";
 875                                 reg = <0 0x00894000 0 0x4000>;
 876                                 clock-names = "se";
 877                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 878                                 pinctrl-names = "default";
 879                                 pinctrl-0 = <&qup_i2c19_default>;
 880                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 881                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 882                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 883                                 dma-names = "tx", "rx";
 884                                 #address-cells = <1>;
 885                                 #size-cells = <0>;
 886                                 status = "disabled";
 887                         };
 888
 889                         spi19: spi@894000 {
 890                                 compatible = "qcom,geni-spi";
 891                                 reg = <0 0x00894000 0 0x4000>;
 892                                 clock-names = "se";
 893                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 894                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 895                                 power-domains = <&rpmhpd SM8350_CX>;
 896                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 897                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
 898                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
 899                                 dma-names = "tx", "rx";
 900                                 #address-cells = <1>;
 901                                 #size-cells = <0>;
 902                                 status = "disabled";
 903                         };
 904                 };
 905
 906                 gpi_dma0: dma-controller@900000 {
 907                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
 908                         reg = <0 0x00900000 0 0x60000>;
 909                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 911                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 912                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 918                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 921                         dma-channels = <12>;
 922                         dma-channel-mask = <0x7e>;
 923                         iommus = <&apps_smmu 0x5b6 0x0>;
 924                         #dma-cells = <3>;
 925                         status = "disabled";
 926                 };
 927
 928                 qupv3_id_0: geniqup@9c0000 {
 929                         compatible = "qcom,geni-se-qup";
 930                         reg = <0x0 0x009c0000 0x0 0x6000>;
 931                         clock-names = "m-ahb", "s-ahb";
 932                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 933                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 934                         iommus = <&apps_smmu 0x5a3 0>;
 935                         #address-cells = <2>;
 936                         #size-cells = <2>;
 937                         ranges;
 938                         status = "disabled";
 939
 940                         i2c0: i2c@980000 {
 941                                 compatible = "qcom,geni-i2c";
 942                                 reg = <0 0x00980000 0 0x4000>;
 943                                 clock-names = "se";
 944                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 945                                 pinctrl-names = "default";
 946                                 pinctrl-0 = <&qup_i2c0_default>;
 947                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 948                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 949                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 950                                 dma-names = "tx", "rx";
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 status = "disabled";
 954                         };
 955
 956                         spi0: spi@980000 {
 957                                 compatible = "qcom,geni-spi";
 958                                 reg = <0 0x00980000 0 0x4000>;
 959                                 clock-names = "se";
 960                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 961                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 962                                 power-domains = <&rpmhpd SM8350_CX>;
 963                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 964                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 965                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 966                                 dma-names = "tx", "rx";
 967                                 #address-cells = <1>;
 968                                 #size-cells = <0>;
 969                                 status = "disabled";
 970                         };
 971
 972                         i2c1: i2c@984000 {
 973                                 compatible = "qcom,geni-i2c";
 974                                 reg = <0 0x00984000 0 0x4000>;
 975                                 clock-names = "se";
 976                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 977                                 pinctrl-names = "default";
 978                                 pinctrl-0 = <&qup_i2c1_default>;
 979                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 980                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 981                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 982                                 dma-names = "tx", "rx";
 983                                 #address-cells = <1>;
 984                                 #size-cells = <0>;
 985                                 status = "disabled";
 986                         };
 987
 988                         spi1: spi@984000 {
 989                                 compatible = "qcom,geni-spi";
 990                                 reg = <0 0x00984000 0 0x4000>;
 991                                 clock-names = "se";
 992                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 993                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 994                                 power-domains = <&rpmhpd SM8350_CX>;
 995                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 996                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 997                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 998                                 dma-names = "tx", "rx";
 999                                 #address-cells = <1>;
1000                                 #size-cells = <0>;
1001                                 status = "disabled";
1002                         };
1003
1004                         i2c2: i2c@988000 {
1005                                 compatible = "qcom,geni-i2c";
1006                                 reg = <0 0x00988000 0 0x4000>;
1007                                 clock-names = "se";
1008                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1009                                 pinctrl-names = "default";
1010                                 pinctrl-0 = <&qup_i2c2_default>;
1011                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1012                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1013                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1014                                 dma-names = "tx", "rx";
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017                                 status = "disabled";
1018                         };
1019
1020                         spi2: spi@988000 {
1021                                 compatible = "qcom,geni-spi";
1022                                 reg = <0 0x00988000 0 0x4000>;
1023                                 clock-names = "se";
1024                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1025                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1026                                 power-domains = <&rpmhpd SM8350_CX>;
1027                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1028                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1029                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1030                                 dma-names = "tx", "rx";
1031                                 #address-cells = <1>;
1032                                 #size-cells = <0>;
1033                                 status = "disabled";
1034                         };
1035
1036                         uart2: serial@98c000 {
1037                                 compatible = "qcom,geni-debug-uart";
1038                                 reg = <0 0x0098c000 0 0x4000>;
1039                                 clock-names = "se";
1040                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1041                                 pinctrl-names = "default";
1042                                 pinctrl-0 = <&qup_uart3_default_state>;
1043                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1044                                 power-domains = <&rpmhpd SM8350_CX>;
1045                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1046                                 status = "disabled";
1047                         };
1048
1049                         /* QUP no. 3 seems to be strictly SPI-only */
1050
1051                         spi3: spi@98c000 {
1052                                 compatible = "qcom,geni-spi";
1053                                 reg = <0 0x0098c000 0 0x4000>;
1054                                 clock-names = "se";
1055                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1056                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1057                                 power-domains = <&rpmhpd SM8350_CX>;
1058                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1059                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1060                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1061                                 dma-names = "tx", "rx";
1062                                 #address-cells = <1>;
1063                                 #size-cells = <0>;
1064                                 status = "disabled";
1065                         };
1066
1067                         i2c4: i2c@990000 {
1068                                 compatible = "qcom,geni-i2c";
1069                                 reg = <0 0x00990000 0 0x4000>;
1070                                 clock-names = "se";
1071                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1072                                 pinctrl-names = "default";
1073                                 pinctrl-0 = <&qup_i2c4_default>;
1074                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1075                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1076                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1077                                 dma-names = "tx", "rx";
1078                                 #address-cells = <1>;
1079                                 #size-cells = <0>;
1080                                 status = "disabled";
1081                         };
1082
1083                         spi4: spi@990000 {
1084                                 compatible = "qcom,geni-spi";
1085                                 reg = <0 0x00990000 0 0x4000>;
1086                                 clock-names = "se";
1087                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1088                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1089                                 power-domains = <&rpmhpd SM8350_CX>;
1090                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1091                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1092                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1093                                 dma-names = "tx", "rx";
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 status = "disabled";
1097                         };
1098
1099                         i2c5: i2c@994000 {
1100                                 compatible = "qcom,geni-i2c";
1101                                 reg = <0 0x00994000 0 0x4000>;
1102                                 clock-names = "se";
1103                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1104                                 pinctrl-names = "default";
1105                                 pinctrl-0 = <&qup_i2c5_default>;
1106                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1107                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1108                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1109                                 dma-names = "tx", "rx";
1110                                 #address-cells = <1>;
1111                                 #size-cells = <0>;
1112                                 status = "disabled";
1113                         };
1114
1115                         spi5: spi@994000 {
1116                                 compatible = "qcom,geni-spi";
1117                                 reg = <0 0x00994000 0 0x4000>;
1118                                 clock-names = "se";
1119                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1120                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1121                                 power-domains = <&rpmhpd SM8350_CX>;
1122                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1123                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1124                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1125                                 dma-names = "tx", "rx";
1126                                 #address-cells = <1>;
1127                                 #size-cells = <0>;
1128                                 status = "disabled";
1129                         };
1130
1131                         i2c6: i2c@998000 {
1132                                 compatible = "qcom,geni-i2c";
1133                                 reg = <0 0x00998000 0 0x4000>;
1134                                 clock-names = "se";
1135                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1136                                 pinctrl-names = "default";
1137                                 pinctrl-0 = <&qup_i2c6_default>;
1138                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1139                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1140                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1141                                 dma-names = "tx", "rx";
1142                                 #address-cells = <1>;
1143                                 #size-cells = <0>;
1144                                 status = "disabled";
1145                         };
1146
1147                         spi6: spi@998000 {
1148                                 compatible = "qcom,geni-spi";
1149                                 reg = <0 0x00998000 0 0x4000>;
1150                                 clock-names = "se";
1151                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1152                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1153                                 power-domains = <&rpmhpd SM8350_CX>;
1154                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1155                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1156                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1157                                 dma-names = "tx", "rx";
1158                                 #address-cells = <1>;
1159                                 #size-cells = <0>;
1160                                 status = "disabled";
1161                         };
1162
1163                         uart6: serial@998000 {
1164                                 compatible = "qcom,geni-uart";
1165                                 reg = <0 0x00998000 0 0x4000>;
1166                                 clock-names = "se";
1167                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1168                                 pinctrl-names = "default";
1169                                 pinctrl-0 = <&qup_uart6_default>;
1170                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1171                                 power-domains = <&rpmhpd SM8350_CX>;
1172                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1173                                 status = "disabled";
1174                         };
1175
1176                         i2c7: i2c@99c000 {
1177                                 compatible = "qcom,geni-i2c";
1178                                 reg = <0 0x0099c000 0 0x4000>;
1179                                 clock-names = "se";
1180                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1181                                 pinctrl-names = "default";
1182                                 pinctrl-0 = <&qup_i2c7_default>;
1183                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1184                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1185                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1186                                 dma-names = "tx", "rx";
1187                                 #address-cells = <1>;
1188                                 #size-cells = <0>;
1189                                 status = "disabled";
1190                         };
1191
1192                         spi7: spi@99c000 {
1193                                 compatible = "qcom,geni-spi";
1194                                 reg = <0 0x0099c000 0 0x4000>;
1195                                 clock-names = "se";
1196                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1197                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1198                                 power-domains = <&rpmhpd SM8350_CX>;
1199                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1200                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1201                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1202                                 dma-names = "tx", "rx";
1203                                 #address-cells = <1>;
1204                                 #size-cells = <0>;
1205                                 status = "disabled";
1206                         };
1207                 };
1208
1209                 gpi_dma1: dma-controller@a00000 {
1210                         compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma";
1211                         reg = <0 0x00a00000 0 0x60000>;
1212                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1222                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1224                         dma-channels = <12>;
1225                         dma-channel-mask = <0xff>;
1226                         iommus = <&apps_smmu 0x56 0x0>;
1227                         #dma-cells = <3>;
1228                         status = "disabled";
1229                 };
1230
1231                 qupv3_id_1: geniqup@ac0000 {
1232                         compatible = "qcom,geni-se-qup";
1233                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1234                         clock-names = "m-ahb", "s-ahb";
1235                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1236                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1237                         iommus = <&apps_smmu 0x43 0>;
1238                         #address-cells = <2>;
1239                         #size-cells = <2>;
1240                         ranges;
1241                         status = "disabled";
1242
1243                         i2c8: i2c@a80000 {
1244                                 compatible = "qcom,geni-i2c";
1245                                 reg = <0 0x00a80000 0 0x4000>;
1246                                 clock-names = "se";
1247                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1248                                 pinctrl-names = "default";
1249                                 pinctrl-0 = <&qup_i2c8_default>;
1250                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1251                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1252                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1253                                 dma-names = "tx", "rx";
1254                                 #address-cells = <1>;
1255                                 #size-cells = <0>;
1256                                 status = "disabled";
1257                         };
1258
1259                         spi8: spi@a80000 {
1260                                 compatible = "qcom,geni-spi";
1261                                 reg = <0 0x00a80000 0 0x4000>;
1262                                 clock-names = "se";
1263                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1264                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1265                                 power-domains = <&rpmhpd SM8350_CX>;
1266                                 operating-points-v2 = <&qup_opp_table_120mhz>;
1267                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1268                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1269                                 dma-names = "tx", "rx";
1270                                 #address-cells = <1>;
1271                                 #size-cells = <0>;
1272                                 status = "disabled";
1273                         };
1274
1275                         i2c9: i2c@a84000 {
1276                                 compatible = "qcom,geni-i2c";
1277                                 reg = <0 0x00a84000 0 0x4000>;
1278                                 clock-names = "se";
1279                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1280                                 pinctrl-names = "default";
1281                                 pinctrl-0 = <&qup_i2c9_default>;
1282                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1283                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1284                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1285                                 dma-names = "tx", "rx";
1286                                 #address-cells = <1>;
1287                                 #size-cells = <0>;
1288                                 status = "disabled";
1289                         };
1290
1291                         spi9: spi@a84000 {
1292                                 compatible = "qcom,geni-spi";
1293                                 reg = <0 0x00a84000 0 0x4000>;
1294                                 clock-names = "se";
1295                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1296                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1297                                 power-domains = <&rpmhpd SM8350_CX>;
1298                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1299                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1300                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1301                                 dma-names = "tx", "rx";
1302                                 #address-cells = <1>;
1303                                 #size-cells = <0>;
1304                                 status = "disabled";
1305                         };
1306
1307                         i2c10: i2c@a88000 {
1308                                 compatible = "qcom,geni-i2c";
1309                                 reg = <0 0x00a88000 0 0x4000>;
1310                                 clock-names = "se";
1311                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1312                                 pinctrl-names = "default";
1313                                 pinctrl-0 = <&qup_i2c10_default>;
1314                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1315                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1316                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1317                                 dma-names = "tx", "rx";
1318                                 #address-cells = <1>;
1319                                 #size-cells = <0>;
1320                                 status = "disabled";
1321                         };
1322
1323                         spi10: spi@a88000 {
1324                                 compatible = "qcom,geni-spi";
1325                                 reg = <0 0x00a88000 0 0x4000>;
1326                                 clock-names = "se";
1327                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1328                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1329                                 power-domains = <&rpmhpd SM8350_CX>;
1330                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1331                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1332                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1333                                 dma-names = "tx", "rx";
1334                                 #address-cells = <1>;
1335                                 #size-cells = <0>;
1336                                 status = "disabled";
1337                         };
1338
1339                         i2c11: i2c@a8c000 {
1340                                 compatible = "qcom,geni-i2c";
1341                                 reg = <0 0x00a8c000 0 0x4000>;
1342                                 clock-names = "se";
1343                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1344                                 pinctrl-names = "default";
1345                                 pinctrl-0 = <&qup_i2c11_default>;
1346                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1347                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1348                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1349                                 dma-names = "tx", "rx";
1350                                 #address-cells = <1>;
1351                                 #size-cells = <0>;
1352                                 status = "disabled";
1353                         };
1354
1355                         spi11: spi@a8c000 {
1356                                 compatible = "qcom,geni-spi";
1357                                 reg = <0 0x00a8c000 0 0x4000>;
1358                                 clock-names = "se";
1359                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1360                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1361                                 power-domains = <&rpmhpd SM8350_CX>;
1362                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1363                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1364                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1365                                 dma-names = "tx", "rx";
1366                                 #address-cells = <1>;
1367                                 #size-cells = <0>;
1368                                 status = "disabled";
1369                         };
1370
1371                         i2c12: i2c@a90000 {
1372                                 compatible = "qcom,geni-i2c";
1373                                 reg = <0 0x00a90000 0 0x4000>;
1374                                 clock-names = "se";
1375                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1376                                 pinctrl-names = "default";
1377                                 pinctrl-0 = <&qup_i2c12_default>;
1378                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1379                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1380                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1381                                 dma-names = "tx", "rx";
1382                                 #address-cells = <1>;
1383                                 #size-cells = <0>;
1384                                 status = "disabled";
1385                         };
1386
1387                         spi12: spi@a90000 {
1388                                 compatible = "qcom,geni-spi";
1389                                 reg = <0 0x00a90000 0 0x4000>;
1390                                 clock-names = "se";
1391                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1392                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1393                                 power-domains = <&rpmhpd SM8350_CX>;
1394                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1395                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1396                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1397                                 dma-names = "tx", "rx";
1398                                 #address-cells = <1>;
1399                                 #size-cells = <0>;
1400                                 status = "disabled";
1401                         };
1402
1403                         i2c13: i2c@a94000 {
1404                                 compatible = "qcom,geni-i2c";
1405                                 reg = <0 0x00a94000 0 0x4000>;
1406                                 clock-names = "se";
1407                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1408                                 pinctrl-names = "default";
1409                                 pinctrl-0 = <&qup_i2c13_default>;
1410                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1411                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1412                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1413                                 dma-names = "tx", "rx";
1414                                 #address-cells = <1>;
1415                                 #size-cells = <0>;
1416                                 status = "disabled";
1417                         };
1418
1419                         spi13: spi@a94000 {
1420                                 compatible = "qcom,geni-spi";
1421                                 reg = <0 0x00a94000 0 0x4000>;
1422                                 clock-names = "se";
1423                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1424                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1425                                 power-domains = <&rpmhpd SM8350_CX>;
1426                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1427                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1428                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1429                                 dma-names = "tx", "rx";
1430                                 #address-cells = <1>;
1431                                 #size-cells = <0>;
1432                                 status = "disabled";
1433                         };
1434                 };
1435
1436                 apps_smmu: iommu@15000000 {
1437                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1438                         reg = <0 0x15000000 0 0x100000>;
1439                         #iommu-cells = <2>;
1440                         #global-interrupts = <2>;
1441                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1442                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1443                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1444                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1445                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1446                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1447                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1448                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1449                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1450                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1451                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1452                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1453                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1454                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1455                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1456                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1457                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1458                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1459                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1460                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1461                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1462                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1463                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1464                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1465                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1466                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1467                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1468                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1469                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1470                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1471                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1472                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1473                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1474                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1475                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1476                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1477                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1478                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1479                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1480                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1481                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1482                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1483                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1484                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1485                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1486                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1487                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1488                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1489                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1490                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1491                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1492                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1493                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1494                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1495                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1496                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1497                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1498                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1499                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1500                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1501                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1502                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1503                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1504                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1505                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1506                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1507                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1508                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1509                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1510                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1511                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1512                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1513                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1514                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1515                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1516                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1517                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1518                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1519                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1520                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1521                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1522                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1523                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1524                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1525                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1526                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1527                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1528                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1529                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1530                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1531                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1532                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1533                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1534                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1535                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1536                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1537                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
1538                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
1539                 };
1540
1541                 config_noc: interconnect@1500000 {
1542                         compatible = "qcom,sm8350-config-noc";
1543                         reg = <0 0x01500000 0 0xa580>;
1544                         #interconnect-cells = <1>;
1545                         qcom,bcm-voters = <&apps_bcm_voter>;
1546                 };
1547
1548                 mc_virt: interconnect@1580000 {
1549                         compatible = "qcom,sm8350-mc-virt";
1550                         reg = <0 0x01580000 0 0x1000>;
1551                         #interconnect-cells = <1>;
1552                         qcom,bcm-voters = <&apps_bcm_voter>;
1553                 };
1554
1555                 system_noc: interconnect@1680000 {
1556                         compatible = "qcom,sm8350-system-noc";
1557                         reg = <0 0x01680000 0 0x1c200>;
1558                         #interconnect-cells = <1>;
1559                         qcom,bcm-voters = <&apps_bcm_voter>;
1560                 };
1561
1562                 aggre1_noc: interconnect@16e0000 {
1563                         compatible = "qcom,sm8350-aggre1-noc";
1564                         reg = <0 0x016e0000 0 0x1f180>;
1565                         #interconnect-cells = <1>;
1566                         qcom,bcm-voters = <&apps_bcm_voter>;
1567                 };
1568
1569                 aggre2_noc: interconnect@1700000 {
1570                         compatible = "qcom,sm8350-aggre2-noc";
1571                         reg = <0 0x01700000 0 0x33000>;
1572                         #interconnect-cells = <1>;
1573                         qcom,bcm-voters = <&apps_bcm_voter>;
1574                 };
1575
1576                 mmss_noc: interconnect@1740000 {
1577                         compatible = "qcom,sm8350-mmss-noc";
1578                         reg = <0 0x01740000 0 0x1f080>;
1579                         #interconnect-cells = <1>;
1580                         qcom,bcm-voters = <&apps_bcm_voter>;
1581                 };
1582
1583                 lpass_ag_noc: interconnect@3c40000 {
1584                         compatible = "qcom,sm8350-lpass-ag-noc";
1585                         reg = <0 0x03c40000 0 0xf080>;
1586                         #interconnect-cells = <1>;
1587                         qcom,bcm-voters = <&apps_bcm_voter>;
1588                 };
1589
1590                 compute_noc: interconnect@a0c0000{
1591                         compatible = "qcom,sm8350-compute-noc";
1592                         reg = <0 0x0a0c0000 0 0xa180>;
1593                         #interconnect-cells = <1>;
1594                         qcom,bcm-voters = <&apps_bcm_voter>;
1595                 };
1596
1597                 ipa: ipa@1e40000 {
1598                         compatible = "qcom,sm8350-ipa";
1599
1600                         iommus = <&apps_smmu 0x5c0 0x0>,
1601                                  <&apps_smmu 0x5c2 0x0>;
1602                         reg = <0 0x1e40000 0 0x8000>,
1603                               <0 0x1e50000 0 0x4b20>,
1604                               <0 0x1e04000 0 0x23000>;
1605                         reg-names = "ipa-reg",
1606                                     "ipa-shared",
1607                                     "gsi";
1608
1609                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1610                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1611                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1612                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1613                         interrupt-names = "ipa",
1614                                           "gsi",
1615                                           "ipa-clock-query",
1616                                           "ipa-setup-ready";
1617
1618                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1619                         clock-names = "core";
1620
1621                         interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1622                                         <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1623                         interconnect-names = "memory",
1624                                              "config";
1625
1626                         qcom,qmp = <&aoss_qmp>;
1627
1628                         qcom,smem-states = <&ipa_smp2p_out 0>,
1629                                            <&ipa_smp2p_out 1>;
1630                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1631                                                 "ipa-clock-enabled";
1632
1633                         status = "disabled";
1634                 };
1635
1636                 tcsr_mutex: hwlock@1f40000 {
1637                         compatible = "qcom,tcsr-mutex";
1638                         reg = <0x0 0x01f40000 0x0 0x40000>;
1639                         #hwlock-cells = <1>;
1640                 };
1641
1642                 mpss: remoteproc@4080000 {
1643                         compatible = "qcom,sm8350-mpss-pas";
1644                         reg = <0x0 0x04080000 0x0 0x4040>;
1645
1646                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1647                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1648                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1649                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1650                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1651                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1652                         interrupt-names = "wdog", "fatal", "ready", "handover",
1653                                           "stop-ack", "shutdown-ack";
1654
1655                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1656                         clock-names = "xo";
1657
1658                         power-domains = <&rpmhpd SM8350_CX>,
1659                                         <&rpmhpd SM8350_MSS>;
1660                         power-domain-names = "cx", "mss";
1661
1662                         interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
1663
1664                         memory-region = <&pil_modem_mem>;
1665
1666                         qcom,qmp = <&aoss_qmp>;
1667
1668                         qcom,smem-states = <&smp2p_modem_out 0>;
1669                         qcom,smem-state-names = "stop";
1670
1671                         status = "disabled";
1672
1673                         glink-edge {
1674                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1675                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1676                                                              IRQ_TYPE_EDGE_RISING>;
1677                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
1678                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1679                                 label = "modem";
1680                                 qcom,remote-pid = <1>;
1681                         };
1682                 };
1683
1684                 pdc: interrupt-controller@b220000 {
1685                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
1686                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1687                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
1688                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
1689                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
1690                                           <156 716 12>;
1691                         #interrupt-cells = <2>;
1692                         interrupt-parent = <&intc>;
1693                         interrupt-controller;
1694                 };
1695
1696                 tsens0: thermal-sensor@c263000 {
1697                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1698                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1699                               <0 0x0c222000 0 0x8>; /* SROT */
1700                         #qcom,sensors = <15>;
1701                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1702                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1703                         interrupt-names = "uplow", "critical";
1704                         #thermal-sensor-cells = <1>;
1705                 };
1706
1707                 tsens1: thermal-sensor@c265000 {
1708                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1709                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1710                               <0 0x0c223000 0 0x8>; /* SROT */
1711                         #qcom,sensors = <14>;
1712                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1713                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1714                         interrupt-names = "uplow", "critical";
1715                         #thermal-sensor-cells = <1>;
1716                 };
1717
1718                 aoss_qmp: power-controller@c300000 {
1719                         compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp";
1720                         reg = <0 0x0c300000 0 0x400>;
1721                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1722                                                      IRQ_TYPE_EDGE_RISING>;
1723                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1724
1725                         #clock-cells = <0>;
1726                 };
1727
1728                 sram@c3f0000 {
1729                         compatible = "qcom,rpmh-stats";
1730                         reg = <0 0x0c3f0000 0 0x400>;
1731                 };
1732
1733                 spmi_bus: spmi@c440000 {
1734                         compatible = "qcom,spmi-pmic-arb";
1735                         reg = <0x0 0xc440000 0x0 0x1100>,
1736                               <0x0 0xc600000 0x0 0x2000000>,
1737                               <0x0 0xe600000 0x0 0x100000>,
1738                               <0x0 0xe700000 0x0 0xa0000>,
1739                               <0x0 0xc40a000 0x0 0x26000>;
1740                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1741                         interrupt-names = "periph_irq";
1742                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1743                         qcom,ee = <0>;
1744                         qcom,channel = <0>;
1745                         #address-cells = <2>;
1746                         #size-cells = <0>;
1747                         interrupt-controller;
1748                         #interrupt-cells = <4>;
1749                 };
1750
1751                 tlmm: pinctrl@f100000 {
1752                         compatible = "qcom,sm8350-tlmm";
1753                         reg = <0 0x0f100000 0 0x300000>;
1754                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1755                         gpio-controller;
1756                         #gpio-cells = <2>;
1757                         interrupt-controller;
1758                         #interrupt-cells = <2>;
1759                         gpio-ranges = <&tlmm 0 0 204>;
1760                         wakeup-parent = <&pdc>;
1761
1762                         qup_uart3_default_state: qup-uart3-default-state {
1763                                 rx-pins {
1764                                         pins = "gpio18";
1765                                         function = "qup3";
1766                                 };
1767                                 tx-pins {
1768                                         pins = "gpio19";
1769                                         function = "qup3";
1770                                 };
1771                         };
1772
1773                         qup_uart6_default: qup-uart6-default-state {
1774                                 pins = "gpio30", "gpio31";
1775                                 function = "qup6";
1776                                 drive-strength = <2>;
1777                                 bias-disable;
1778                         };
1779
1780                         qup_uart18_default: qup-uart18-default-state {
1781                                 pins = "gpio68", "gpio69";
1782                                 function = "qup18";
1783                                 drive-strength = <2>;
1784                                 bias-disable;
1785                         };
1786
1787                         qup_i2c0_default: qup-i2c0-default-state {
1788                                 pins = "gpio4", "gpio5";
1789                                 function = "qup0";
1790                                 drive-strength = <2>;
1791                                 bias-pull-up;
1792                         };
1793
1794                         qup_i2c1_default: qup-i2c1-default-state {
1795                                 pins = "gpio8", "gpio9";
1796                                 function = "qup1";
1797                                 drive-strength = <2>;
1798                                 bias-pull-up;
1799                         };
1800
1801                         qup_i2c2_default: qup-i2c2-default-state {
1802                                 pins = "gpio12", "gpio13";
1803                                 function = "qup2";
1804                                 drive-strength = <2>;
1805                                 bias-pull-up;
1806                         };
1807
1808                         qup_i2c4_default: qup-i2c4-default-state {
1809                                 pins = "gpio20", "gpio21";
1810                                 function = "qup4";
1811                                 drive-strength = <2>;
1812                                 bias-pull-up;
1813                         };
1814
1815                         qup_i2c5_default: qup-i2c5-default-state {
1816                                 pins = "gpio24", "gpio25";
1817                                 function = "qup5";
1818                                 drive-strength = <2>;
1819                                 bias-pull-up;
1820                         };
1821
1822                         qup_i2c6_default: qup-i2c6-default-state {
1823                                 pins = "gpio28", "gpio29";
1824                                 function = "qup6";
1825                                 drive-strength = <2>;
1826                                 bias-pull-up;
1827                         };
1828
1829                         qup_i2c7_default: qup-i2c7-default-state {
1830                                 pins = "gpio32", "gpio33";
1831                                 function = "qup7";
1832                                 drive-strength = <2>;
1833                                 bias-disable;
1834                         };
1835
1836                         qup_i2c8_default: qup-i2c8-default-state {
1837                                 pins = "gpio36", "gpio37";
1838                                 function = "qup8";
1839                                 drive-strength = <2>;
1840                                 bias-pull-up;
1841                         };
1842
1843                         qup_i2c9_default: qup-i2c9-default-state {
1844                                 pins = "gpio40", "gpio41";
1845                                 function = "qup9";
1846                                 drive-strength = <2>;
1847                                 bias-pull-up;
1848                         };
1849
1850                         qup_i2c10_default: qup-i2c10-default-state {
1851                                 pins = "gpio44", "gpio45";
1852                                 function = "qup10";
1853                                 drive-strength = <2>;
1854                                 bias-pull-up;
1855                         };
1856
1857                         qup_i2c11_default: qup-i2c11-default-state {
1858                                 pins = "gpio48", "gpio49";
1859                                 function = "qup11";
1860                                 drive-strength = <2>;
1861                                 bias-pull-up;
1862                         };
1863
1864                         qup_i2c12_default: qup-i2c12-default-state {
1865                                 pins = "gpio52", "gpio53";
1866                                 function = "qup12";
1867                                 drive-strength = <2>;
1868                                 bias-pull-up;
1869                         };
1870
1871                         qup_i2c13_default: qup-i2c13-default-state {
1872                                 pins = "gpio0", "gpio1";
1873                                 function = "qup13";
1874                                 drive-strength = <2>;
1875                                 bias-pull-up;
1876                         };
1877
1878                         qup_i2c14_default: qup-i2c14-default-state {
1879                                 pins = "gpio56", "gpio57";
1880                                 function = "qup14";
1881                                 drive-strength = <2>;
1882                                 bias-disable;
1883                         };
1884
1885                         qup_i2c15_default: qup-i2c15-default-state {
1886                                 pins = "gpio60", "gpio61";
1887                                 function = "qup15";
1888                                 drive-strength = <2>;
1889                                 bias-disable;
1890                         };
1891
1892                         qup_i2c16_default: qup-i2c16-default-state {
1893                                 pins = "gpio64", "gpio65";
1894                                 function = "qup16";
1895                                 drive-strength = <2>;
1896                                 bias-disable;
1897                         };
1898
1899                         qup_i2c17_default: qup-i2c17-default-state {
1900                                 pins = "gpio72", "gpio73";
1901                                 function = "qup17";
1902                                 drive-strength = <2>;
1903                                 bias-disable;
1904                         };
1905
1906                         qup_i2c19_default: qup-i2c19-default-state {
1907                                 pins = "gpio76", "gpio77";
1908                                 function = "qup19";
1909                                 drive-strength = <2>;
1910                                 bias-disable;
1911                         };
1912                 };
1913
1914                 rng: rng@10d3000 {
1915                         compatible = "qcom,prng-ee";
1916                         reg = <0 0x010d3000 0 0x1000>;
1917                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1918                         clock-names = "core";
1919                 };
1920
1921                 intc: interrupt-controller@17a00000 {
1922                         compatible = "arm,gic-v3";
1923                         #interrupt-cells = <3>;
1924                         interrupt-controller;
1925                         #redistributor-regions = <1>;
1926                         redistributor-stride = <0 0x20000>;
1927                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1928                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1929                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1930                 };
1931
1932                 timer@17c20000 {
1933                         compatible = "arm,armv7-timer-mem";
1934                         #address-cells = <1>;
1935                         #size-cells = <1>;
1936                         ranges = <0 0 0 0x20000000>;
1937                         reg = <0x0 0x17c20000 0x0 0x1000>;
1938                         clock-frequency = <19200000>;
1939
1940                         frame@17c21000 {
1941                                 frame-number = <0>;
1942                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1943                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1944                                 reg = <0x17c21000 0x1000>,
1945                                       <0x17c22000 0x1000>;
1946                         };
1947
1948                         frame@17c23000 {
1949                                 frame-number = <1>;
1950                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1951                                 reg = <0x17c23000 0x1000>;
1952                                 status = "disabled";
1953                         };
1954
1955                         frame@17c25000 {
1956                                 frame-number = <2>;
1957                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1958                                 reg = <0x17c25000 0x1000>;
1959                                 status = "disabled";
1960                         };
1961
1962                         frame@17c27000 {
1963                                 frame-number = <3>;
1964                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1965                                 reg = <0x17c27000 0x1000>;
1966                                 status = "disabled";
1967                         };
1968
1969                         frame@17c29000 {
1970                                 frame-number = <4>;
1971                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1972                                 reg = <0x17c29000 0x1000>;
1973                                 status = "disabled";
1974                         };
1975
1976                         frame@17c2b000 {
1977                                 frame-number = <5>;
1978                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1979                                 reg = <0x17c2b000 0x1000>;
1980                                 status = "disabled";
1981                         };
1982
1983                         frame@17c2d000 {
1984                                 frame-number = <6>;
1985                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1986                                 reg = <0x17c2d000 0x1000>;
1987                                 status = "disabled";
1988                         };
1989                 };
1990
1991                 apps_rsc: rsc@18200000 {
1992                         label = "apps_rsc";
1993                         compatible = "qcom,rpmh-rsc";
1994                         reg = <0x0 0x18200000 0x0 0x10000>,
1995                                 <0x0 0x18210000 0x0 0x10000>,
1996                                 <0x0 0x18220000 0x0 0x10000>;
1997                         reg-names = "drv-0", "drv-1", "drv-2";
1998                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1999                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2000                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2001                         qcom,tcs-offset = <0xd00>;
2002                         qcom,drv-id = <2>;
2003                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2004                                           <WAKE_TCS    3>, <CONTROL_TCS 0>;
2005
2006                         rpmhcc: clock-controller {
2007                                 compatible = "qcom,sm8350-rpmh-clk";
2008                                 #clock-cells = <1>;
2009                                 clock-names = "xo";
2010                                 clocks = <&xo_board>;
2011                         };
2012
2013                         rpmhpd: power-controller {
2014                                 compatible = "qcom,sm8350-rpmhpd";
2015                                 #power-domain-cells = <1>;
2016                                 operating-points-v2 = <&rpmhpd_opp_table>;
2017
2018                                 rpmhpd_opp_table: opp-table {
2019                                         compatible = "operating-points-v2";
2020
2021                                         rpmhpd_opp_ret: opp1 {
2022                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2023                                         };
2024
2025                                         rpmhpd_opp_min_svs: opp2 {
2026                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2027                                         };
2028
2029                                         rpmhpd_opp_low_svs: opp3 {
2030                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2031                                         };
2032
2033                                         rpmhpd_opp_svs: opp4 {
2034                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2035                                         };
2036
2037                                         rpmhpd_opp_svs_l1: opp5 {
2038                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2039                                         };
2040
2041                                         rpmhpd_opp_nom: opp6 {
2042                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2043                                         };
2044
2045                                         rpmhpd_opp_nom_l1: opp7 {
2046                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2047                                         };
2048
2049                                         rpmhpd_opp_nom_l2: opp8 {
2050                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2051                                         };
2052
2053                                         rpmhpd_opp_turbo: opp9 {
2054                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2055                                         };
2056
2057                                         rpmhpd_opp_turbo_l1: opp10 {
2058                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2059                                         };
2060                                 };
2061                         };
2062
2063                         apps_bcm_voter: bcm-voter {
2064                                 compatible = "qcom,bcm-voter";
2065                         };
2066                 };
2067
2068                 cpufreq_hw: cpufreq@18591000 {
2069                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
2070                         reg = <0 0x18591000 0 0x1000>,
2071                               <0 0x18592000 0 0x1000>,
2072                               <0 0x18593000 0 0x1000>;
2073                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
2074
2075                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
2076                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
2077                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
2078                         interrupt-names = "dcvsh-irq-0",
2079                                           "dcvsh-irq-1",
2080                                           "dcvsh-irq-2";
2081
2082                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2083                         clock-names = "xo", "alternate";
2084
2085                         #freq-domain-cells = <1>;
2086                 };
2087
2088                 ufs_mem_hc: ufshc@1d84000 {
2089                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
2090                                      "jedec,ufs-2.0";
2091                         reg = <0 0x01d84000 0 0x3000>;
2092                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2093                         phys = <&ufs_mem_phy_lanes>;
2094                         phy-names = "ufsphy";
2095                         lanes-per-direction = <2>;
2096                         #reset-cells = <1>;
2097                         resets = <&gcc GCC_UFS_PHY_BCR>;
2098                         reset-names = "rst";
2099
2100                         power-domains = <&gcc UFS_PHY_GDSC>;
2101
2102                         iommus = <&apps_smmu 0xe0 0x0>;
2103
2104                         clock-names =
2105                                 "core_clk",
2106                                 "bus_aggr_clk",
2107                                 "iface_clk",
2108                                 "core_clk_unipro",
2109                                 "ref_clk",
2110                                 "tx_lane0_sync_clk",
2111                                 "rx_lane0_sync_clk",
2112                                 "rx_lane1_sync_clk";
2113                         clocks =
2114                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2115                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2116                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2117                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2118                                 <&rpmhcc RPMH_CXO_CLK>,
2119                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2120                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2121                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2122                         freq-table-hz =
2123                                 <75000000 300000000>,
2124                                 <0 0>,
2125                                 <0 0>,
2126                                 <75000000 300000000>,
2127                                 <0 0>,
2128                                 <0 0>,
2129                                 <0 0>,
2130                                 <0 0>;
2131                         status = "disabled";
2132                 };
2133
2134                 ufs_mem_phy: phy@1d87000 {
2135                         compatible = "qcom,sm8350-qmp-ufs-phy";
2136                         reg = <0 0x01d87000 0 0x1c4>;
2137                         #address-cells = <2>;
2138                         #size-cells = <2>;
2139                         ranges;
2140                         clock-names = "ref",
2141                                       "ref_aux";
2142                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2143                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2144
2145                         resets = <&ufs_mem_hc 0>;
2146                         reset-names = "ufsphy";
2147                         status = "disabled";
2148
2149                         ufs_mem_phy_lanes: phy@1d87400 {
2150                                 reg = <0 0x01d87400 0 0x188>,
2151                                       <0 0x01d87600 0 0x200>,
2152                                       <0 0x01d87c00 0 0x200>,
2153                                       <0 0x01d87800 0 0x188>,
2154                                       <0 0x01d87a00 0 0x200>;
2155                                 #phy-cells = <0>;
2156                         };
2157                 };
2158
2159                 slpi: remoteproc@5c00000 {
2160                         compatible = "qcom,sm8350-slpi-pas";
2161                         reg = <0 0x05c00000 0 0x4000>;
2162
2163                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2164                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2165                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2166                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2167                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2168                         interrupt-names = "wdog", "fatal", "ready",
2169                                           "handover", "stop-ack";
2170
2171                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2172                         clock-names = "xo";
2173
2174                         power-domains = <&rpmhpd SM8350_LCX>,
2175                                         <&rpmhpd SM8350_LMX>;
2176                         power-domain-names = "lcx", "lmx";
2177
2178                         memory-region = <&pil_slpi_mem>;
2179
2180                         qcom,qmp = <&aoss_qmp>;
2181
2182                         qcom,smem-states = <&smp2p_slpi_out 0>;
2183                         qcom,smem-state-names = "stop";
2184
2185                         status = "disabled";
2186
2187                         glink-edge {
2188                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2189                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2190                                                              IRQ_TYPE_EDGE_RISING>;
2191                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2192                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2193
2194                                 label = "slpi";
2195                                 qcom,remote-pid = <3>;
2196
2197                                 fastrpc {
2198                                         compatible = "qcom,fastrpc";
2199                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2200                                         label = "sdsp";
2201                                         qcom,non-secure-domain;
2202                                         #address-cells = <1>;
2203                                         #size-cells = <0>;
2204
2205                                         compute-cb@1 {
2206                                                 compatible = "qcom,fastrpc-compute-cb";
2207                                                 reg = <1>;
2208                                                 iommus = <&apps_smmu 0x0541 0x0>;
2209                                         };
2210
2211                                         compute-cb@2 {
2212                                                 compatible = "qcom,fastrpc-compute-cb";
2213                                                 reg = <2>;
2214                                                 iommus = <&apps_smmu 0x0542 0x0>;
2215                                         };
2216
2217                                         compute-cb@3 {
2218                                                 compatible = "qcom,fastrpc-compute-cb";
2219                                                 reg = <3>;
2220                                                 iommus = <&apps_smmu 0x0543 0x0>;
2221                                                 /* note: shared-cb = <4> in downstream */
2222                                         };
2223                                 };
2224                         };
2225                 };
2226
2227                 cdsp: remoteproc@98900000 {
2228                         compatible = "qcom,sm8350-cdsp-pas";
2229                         reg = <0 0x098900000 0 0x1400000>;
2230
2231                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2232                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2233                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2234                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2235                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2236                         interrupt-names = "wdog", "fatal", "ready",
2237                                           "handover", "stop-ack";
2238
2239                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2240                         clock-names = "xo";
2241
2242                         power-domains = <&rpmhpd SM8350_CX>,
2243                                         <&rpmhpd SM8350_MXC>;
2244                         power-domain-names = "cx", "mxc";
2245
2246                         interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
2247
2248                         memory-region = <&pil_cdsp_mem>;
2249
2250                         qcom,qmp = <&aoss_qmp>;
2251
2252                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2253                         qcom,smem-state-names = "stop";
2254
2255                         status = "disabled";
2256
2257                         glink-edge {
2258                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2259                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2260                                                              IRQ_TYPE_EDGE_RISING>;
2261                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2262                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2263
2264                                 label = "cdsp";
2265                                 qcom,remote-pid = <5>;
2266
2267                                 fastrpc {
2268                                         compatible = "qcom,fastrpc";
2269                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2270                                         label = "cdsp";
2271                                         qcom,non-secure-domain;
2272                                         #address-cells = <1>;
2273                                         #size-cells = <0>;
2274
2275                                         compute-cb@1 {
2276                                                 compatible = "qcom,fastrpc-compute-cb";
2277                                                 reg = <1>;
2278                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2279                                                          <&apps_smmu 0x1181 0x0420>;
2280                                         };
2281
2282                                         compute-cb@2 {
2283                                                 compatible = "qcom,fastrpc-compute-cb";
2284                                                 reg = <2>;
2285                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2286                                                          <&apps_smmu 0x1182 0x0420>;
2287                                         };
2288
2289                                         compute-cb@3 {
2290                                                 compatible = "qcom,fastrpc-compute-cb";
2291                                                 reg = <3>;
2292                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2293                                                          <&apps_smmu 0x1183 0x0420>;
2294                                         };
2295
2296                                         compute-cb@4 {
2297                                                 compatible = "qcom,fastrpc-compute-cb";
2298                                                 reg = <4>;
2299                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2300                                                          <&apps_smmu 0x1184 0x0420>;
2301                                         };
2302
2303                                         compute-cb@5 {
2304                                                 compatible = "qcom,fastrpc-compute-cb";
2305                                                 reg = <5>;
2306                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2307                                                          <&apps_smmu 0x1185 0x0420>;
2308                                         };
2309
2310                                         compute-cb@6 {
2311                                                 compatible = "qcom,fastrpc-compute-cb";
2312                                                 reg = <6>;
2313                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2314                                                          <&apps_smmu 0x1186 0x0420>;
2315                                         };
2316
2317                                         compute-cb@7 {
2318                                                 compatible = "qcom,fastrpc-compute-cb";
2319                                                 reg = <7>;
2320                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2321                                                          <&apps_smmu 0x1187 0x0420>;
2322                                         };
2323
2324                                         compute-cb@8 {
2325                                                 compatible = "qcom,fastrpc-compute-cb";
2326                                                 reg = <8>;
2327                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2328                                                          <&apps_smmu 0x1188 0x0420>;
2329                                         };
2330
2331                                         /* note: secure cb9 in downstream */
2332                                 };
2333                         };
2334                 };
2335
2336                 usb_1_hsphy: phy@88e3000 {
2337                         compatible = "qcom,sm8350-usb-hs-phy",
2338                                      "qcom,usb-snps-hs-7nm-phy";
2339                         reg = <0 0x088e3000 0 0x400>;
2340                         status = "disabled";
2341                         #phy-cells = <0>;
2342
2343                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2344                         clock-names = "ref";
2345
2346                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2347                 };
2348
2349                 usb_2_hsphy: phy@88e4000 {
2350                         compatible = "qcom,sm8250-usb-hs-phy",
2351                                      "qcom,usb-snps-hs-7nm-phy";
2352                         reg = <0 0x088e4000 0 0x400>;
2353                         status = "disabled";
2354                         #phy-cells = <0>;
2355
2356                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2357                         clock-names = "ref";
2358
2359                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2360                 };
2361
2362                 usb_1_qmpphy: phy-wrapper@88e9000 {
2363                         compatible = "qcom,sm8350-qmp-usb3-phy";
2364                         reg = <0 0x088e9000 0 0x200>,
2365                               <0 0x088e8000 0 0x20>;
2366                         status = "disabled";
2367                         #address-cells = <2>;
2368                         #size-cells = <2>;
2369                         ranges;
2370
2371                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2372                                  <&rpmhcc RPMH_CXO_CLK>,
2373                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2374                         clock-names = "aux", "ref_clk_src", "com_aux";
2375
2376                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2377                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2378                         reset-names = "phy", "common";
2379
2380                         usb_1_ssphy: phy@88e9200 {
2381                                 reg = <0 0x088e9200 0 0x200>,
2382                                       <0 0x088e9400 0 0x200>,
2383                                       <0 0x088e9c00 0 0x400>,
2384                                       <0 0x088e9600 0 0x200>,
2385                                       <0 0x088e9800 0 0x200>,
2386                                       <0 0x088e9a00 0 0x100>;
2387                                 #phy-cells = <0>;
2388                                 #clock-cells = <0>;
2389                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2390                                 clock-names = "pipe0";
2391                                 clock-output-names = "usb3_phy_pipe_clk_src";
2392                         };
2393                 };
2394
2395                 usb_2_qmpphy: phy-wrapper@88eb000 {
2396                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2397                         reg = <0 0x088eb000 0 0x200>;
2398                         status = "disabled";
2399                         #address-cells = <2>;
2400                         #size-cells = <2>;
2401                         ranges;
2402
2403                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2404                                  <&rpmhcc RPMH_CXO_CLK>,
2405                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2406                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2407                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2408
2409                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2410                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2411                         reset-names = "phy", "common";
2412
2413                         usb_2_ssphy: phy@88ebe00 {
2414                                 reg = <0 0x088ebe00 0 0x200>,
2415                                       <0 0x088ec000 0 0x200>,
2416                                       <0 0x088eb200 0 0x1100>;
2417                                 #phy-cells = <0>;
2418                                 #clock-cells = <0>;
2419                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2420                                 clock-names = "pipe0";
2421                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2422                         };
2423                 };
2424
2425                 dc_noc: interconnect@90c0000 {
2426                         compatible = "qcom,sm8350-dc-noc";
2427                         reg = <0 0x090c0000 0 0x4200>;
2428                         #interconnect-cells = <1>;
2429                         qcom,bcm-voters = <&apps_bcm_voter>;
2430                 };
2431
2432                 gem_noc: interconnect@9100000 {
2433                         compatible = "qcom,sm8350-gem-noc";
2434                         reg = <0 0x09100000 0 0xb4000>;
2435                         #interconnect-cells = <1>;
2436                         qcom,bcm-voters = <&apps_bcm_voter>;
2437                 };
2438
2439                 system-cache-controller@9200000 {
2440                         compatible = "qcom,sm8350-llcc";
2441                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2442                         reg-names = "llcc_base", "llcc_broadcast_base";
2443                 };
2444
2445                 usb_1: usb@a6f8800 {
2446                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2447                         reg = <0 0x0a6f8800 0 0x400>;
2448                         status = "disabled";
2449                         #address-cells = <2>;
2450                         #size-cells = <2>;
2451                         ranges;
2452
2453                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2454                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2455                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2456                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2457                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2458                         clock-names = "cfg_noc",
2459                                       "core",
2460                                       "iface",
2461                                       "sleep",
2462                                       "mock_utmi";
2463
2464                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2465                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2466                         assigned-clock-rates = <19200000>, <200000000>;
2467
2468                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2469                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
2470                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2471                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
2472                         interrupt-names = "hs_phy_irq",
2473                                           "ss_phy_irq",
2474                                           "dm_hs_phy_irq",
2475                                           "dp_hs_phy_irq";
2476
2477                         power-domains = <&gcc USB30_PRIM_GDSC>;
2478
2479                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2480
2481                         usb_1_dwc3: usb@a600000 {
2482                                 compatible = "snps,dwc3";
2483                                 reg = <0 0x0a600000 0 0xcd00>;
2484                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2485                                 iommus = <&apps_smmu 0x0 0x0>;
2486                                 snps,dis_u2_susphy_quirk;
2487                                 snps,dis_enblslpm_quirk;
2488                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2489                                 phy-names = "usb2-phy", "usb3-phy";
2490                         };
2491                 };
2492
2493                 usb_2: usb@a8f8800 {
2494                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2495                         reg = <0 0x0a8f8800 0 0x400>;
2496                         status = "disabled";
2497                         #address-cells = <2>;
2498                         #size-cells = <2>;
2499                         ranges;
2500
2501                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2502                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2503                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2504                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2505                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2506                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2507                         clock-names = "cfg_noc",
2508                                       "core",
2509                                       "iface",
2510                                       "sleep",
2511                                       "mock_utmi",
2512                                       "xo";
2513
2514                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2515                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2516                         assigned-clock-rates = <19200000>, <200000000>;
2517
2518                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2519                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
2520                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2521                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
2522                         interrupt-names = "hs_phy_irq",
2523                                           "ss_phy_irq",
2524                                           "dm_hs_phy_irq",
2525                                           "dp_hs_phy_irq";
2526
2527                         power-domains = <&gcc USB30_SEC_GDSC>;
2528
2529                         resets = <&gcc GCC_USB30_SEC_BCR>;
2530
2531                         usb_2_dwc3: usb@a800000 {
2532                                 compatible = "snps,dwc3";
2533                                 reg = <0 0x0a800000 0 0xcd00>;
2534                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2535                                 iommus = <&apps_smmu 0x20 0x0>;
2536                                 snps,dis_u2_susphy_quirk;
2537                                 snps,dis_enblslpm_quirk;
2538                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2539                                 phy-names = "usb2-phy", "usb3-phy";
2540                         };
2541                 };
2542
2543                 dispcc: clock-controller@af00000 {
2544                         compatible = "qcom,sm8350-dispcc";
2545                         reg = <0 0x0af00000 0 0x10000>;
2546                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2547                                  <0>,
2548                                  <0>,
2549                                  <0>,
2550                                  <0>,
2551                                  <0>,
2552                                  <0>;
2553                         clock-names = "bi_tcxo",
2554                                       "dsi0_phy_pll_out_byteclk",
2555                                       "dsi0_phy_pll_out_dsiclk",
2556                                       "dsi1_phy_pll_out_byteclk",
2557                                       "dsi1_phy_pll_out_dsiclk",
2558                                       "dp_phy_pll_link_clk",
2559                                       "dp_phy_pll_vco_div_clk";
2560                         #clock-cells = <1>;
2561                         #reset-cells = <1>;
2562                         #power-domain-cells = <1>;
2563
2564                         power-domains = <&rpmhpd SM8350_MMCX>;
2565                         power-domain-names = "mmcx";
2566                 };
2567
2568                 adsp: remoteproc@17300000 {
2569                         compatible = "qcom,sm8350-adsp-pas";
2570                         reg = <0 0x17300000 0 0x100>;
2571
2572                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2573                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2574                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2575                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2576                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2577                         interrupt-names = "wdog", "fatal", "ready",
2578                                           "handover", "stop-ack";
2579
2580                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2581                         clock-names = "xo";
2582
2583                         power-domains = <&rpmhpd SM8350_LCX>,
2584                                         <&rpmhpd SM8350_LMX>;
2585                         power-domain-names = "lcx", "lmx";
2586
2587                         memory-region = <&pil_adsp_mem>;
2588
2589                         qcom,qmp = <&aoss_qmp>;
2590
2591                         qcom,smem-states = <&smp2p_adsp_out 0>;
2592                         qcom,smem-state-names = "stop";
2593
2594                         status = "disabled";
2595
2596                         glink-edge {
2597                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2598                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2599                                                              IRQ_TYPE_EDGE_RISING>;
2600                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2601                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2602
2603                                 label = "lpass";
2604                                 qcom,remote-pid = <2>;
2605
2606                                 fastrpc {
2607                                         compatible = "qcom,fastrpc";
2608                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2609                                         label = "adsp";
2610                                         qcom,non-secure-domain;
2611                                         #address-cells = <1>;
2612                                         #size-cells = <0>;
2613
2614                                         compute-cb@3 {
2615                                                 compatible = "qcom,fastrpc-compute-cb";
2616                                                 reg = <3>;
2617                                                 iommus = <&apps_smmu 0x1803 0x0>;
2618                                         };
2619
2620                                         compute-cb@4 {
2621                                                 compatible = "qcom,fastrpc-compute-cb";
2622                                                 reg = <4>;
2623                                                 iommus = <&apps_smmu 0x1804 0x0>;
2624                                         };
2625
2626                                         compute-cb@5 {
2627                                                 compatible = "qcom,fastrpc-compute-cb";
2628                                                 reg = <5>;
2629                                                 iommus = <&apps_smmu 0x1805 0x0>;
2630                                         };
2631                                 };
2632                         };
2633                 };
2634         };
2635
2636         thermal_zones: thermal-zones {
2637                 cpu0-thermal {
2638                         polling-delay-passive = <250>;
2639                         polling-delay = <1000>;
2640
2641                         thermal-sensors = <&tsens0 1>;
2642
2643                         trips {
2644                                 cpu0_alert0: trip-point0 {
2645                                         temperature = <90000>;
2646                                         hysteresis = <2000>;
2647                                         type = "passive";
2648                                 };
2649
2650                                 cpu0_alert1: trip-point1 {
2651                                         temperature = <95000>;
2652                                         hysteresis = <2000>;
2653                                         type = "passive";
2654                                 };
2655
2656                                 cpu0_crit: cpu_crit {
2657                                         temperature = <110000>;
2658                                         hysteresis = <1000>;
2659                                         type = "critical";
2660                                 };
2661                         };
2662
2663                         cooling-maps {
2664                                 map0 {
2665                                         trip = <&cpu0_alert0>;
2666                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2667                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2668                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2669                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2670                                 };
2671                                 map1 {
2672                                         trip = <&cpu0_alert1>;
2673                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2674                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2675                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2676                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2677                                 };
2678                         };
2679                 };
2680
2681                 cpu1-thermal {
2682                         polling-delay-passive = <250>;
2683                         polling-delay = <1000>;
2684
2685                         thermal-sensors = <&tsens0 2>;
2686
2687                         trips {
2688                                 cpu1_alert0: trip-point0 {
2689                                         temperature = <90000>;
2690                                         hysteresis = <2000>;
2691                                         type = "passive";
2692                                 };
2693
2694                                 cpu1_alert1: trip-point1 {
2695                                         temperature = <95000>;
2696                                         hysteresis = <2000>;
2697                                         type = "passive";
2698                                 };
2699
2700                                 cpu1_crit: cpu_crit {
2701                                         temperature = <110000>;
2702                                         hysteresis = <1000>;
2703                                         type = "critical";
2704                                 };
2705                         };
2706
2707                         cooling-maps {
2708                                 map0 {
2709                                         trip = <&cpu1_alert0>;
2710                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2711                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2712                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2713                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2714                                 };
2715                                 map1 {
2716                                         trip = <&cpu1_alert1>;
2717                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2718                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2719                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2720                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2721                                 };
2722                         };
2723                 };
2724
2725                 cpu2-thermal {
2726                         polling-delay-passive = <250>;
2727                         polling-delay = <1000>;
2728
2729                         thermal-sensors = <&tsens0 3>;
2730
2731                         trips {
2732                                 cpu2_alert0: trip-point0 {
2733                                         temperature = <90000>;
2734                                         hysteresis = <2000>;
2735                                         type = "passive";
2736                                 };
2737
2738                                 cpu2_alert1: trip-point1 {
2739                                         temperature = <95000>;
2740                                         hysteresis = <2000>;
2741                                         type = "passive";
2742                                 };
2743
2744                                 cpu2_crit: cpu_crit {
2745                                         temperature = <110000>;
2746                                         hysteresis = <1000>;
2747                                         type = "critical";
2748                                 };
2749                         };
2750
2751                         cooling-maps {
2752                                 map0 {
2753                                         trip = <&cpu2_alert0>;
2754                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2755                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2756                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2757                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2758                                 };
2759                                 map1 {
2760                                         trip = <&cpu2_alert1>;
2761                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2762                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2763                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2764                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2765                                 };
2766                         };
2767                 };
2768
2769                 cpu3-thermal {
2770                         polling-delay-passive = <250>;
2771                         polling-delay = <1000>;
2772
2773                         thermal-sensors = <&tsens0 4>;
2774
2775                         trips {
2776                                 cpu3_alert0: trip-point0 {
2777                                         temperature = <90000>;
2778                                         hysteresis = <2000>;
2779                                         type = "passive";
2780                                 };
2781
2782                                 cpu3_alert1: trip-point1 {
2783                                         temperature = <95000>;
2784                                         hysteresis = <2000>;
2785                                         type = "passive";
2786                                 };
2787
2788                                 cpu3_crit: cpu_crit {
2789                                         temperature = <110000>;
2790                                         hysteresis = <1000>;
2791                                         type = "critical";
2792                                 };
2793                         };
2794
2795                         cooling-maps {
2796                                 map0 {
2797                                         trip = <&cpu3_alert0>;
2798                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2799                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2800                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2801                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2802                                 };
2803                                 map1 {
2804                                         trip = <&cpu3_alert1>;
2805                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2806                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2807                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2808                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2809                                 };
2810                         };
2811                 };
2812
2813                 cpu4-top-thermal {
2814                         polling-delay-passive = <250>;
2815                         polling-delay = <1000>;
2816
2817                         thermal-sensors = <&tsens0 7>;
2818
2819                         trips {
2820                                 cpu4_top_alert0: trip-point0 {
2821                                         temperature = <90000>;
2822                                         hysteresis = <2000>;
2823                                         type = "passive";
2824                                 };
2825
2826                                 cpu4_top_alert1: trip-point1 {
2827                                         temperature = <95000>;
2828                                         hysteresis = <2000>;
2829                                         type = "passive";
2830                                 };
2831
2832                                 cpu4_top_crit: cpu_crit {
2833                                         temperature = <110000>;
2834                                         hysteresis = <1000>;
2835                                         type = "critical";
2836                                 };
2837                         };
2838
2839                         cooling-maps {
2840                                 map0 {
2841                                         trip = <&cpu4_top_alert0>;
2842                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2843                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2844                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2845                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2846                                 };
2847                                 map1 {
2848                                         trip = <&cpu4_top_alert1>;
2849                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2850                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2851                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2852                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2853                                 };
2854                         };
2855                 };
2856
2857                 cpu5-top-thermal {
2858                         polling-delay-passive = <250>;
2859                         polling-delay = <1000>;
2860
2861                         thermal-sensors = <&tsens0 8>;
2862
2863                         trips {
2864                                 cpu5_top_alert0: trip-point0 {
2865                                         temperature = <90000>;
2866                                         hysteresis = <2000>;
2867                                         type = "passive";
2868                                 };
2869
2870                                 cpu5_top_alert1: trip-point1 {
2871                                         temperature = <95000>;
2872                                         hysteresis = <2000>;
2873                                         type = "passive";
2874                                 };
2875
2876                                 cpu5_top_crit: cpu_crit {
2877                                         temperature = <110000>;
2878                                         hysteresis = <1000>;
2879                                         type = "critical";
2880                                 };
2881                         };
2882
2883                         cooling-maps {
2884                                 map0 {
2885                                         trip = <&cpu5_top_alert0>;
2886                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2887                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2888                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2889                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2890                                 };
2891                                 map1 {
2892                                         trip = <&cpu5_top_alert1>;
2893                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2894                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2895                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2896                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2897                                 };
2898                         };
2899                 };
2900
2901                 cpu6-top-thermal {
2902                         polling-delay-passive = <250>;
2903                         polling-delay = <1000>;
2904
2905                         thermal-sensors = <&tsens0 9>;
2906
2907                         trips {
2908                                 cpu6_top_alert0: trip-point0 {
2909                                         temperature = <90000>;
2910                                         hysteresis = <2000>;
2911                                         type = "passive";
2912                                 };
2913
2914                                 cpu6_top_alert1: trip-point1 {
2915                                         temperature = <95000>;
2916                                         hysteresis = <2000>;
2917                                         type = "passive";
2918                                 };
2919
2920                                 cpu6_top_crit: cpu_crit {
2921                                         temperature = <110000>;
2922                                         hysteresis = <1000>;
2923                                         type = "critical";
2924                                 };
2925                         };
2926
2927                         cooling-maps {
2928                                 map0 {
2929                                         trip = <&cpu6_top_alert0>;
2930                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2931                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2932                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2933                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2934                                 };
2935                                 map1 {
2936                                         trip = <&cpu6_top_alert1>;
2937                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2938                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2939                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2940                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2941                                 };
2942                         };
2943                 };
2944
2945                 cpu7-top-thermal {
2946                         polling-delay-passive = <250>;
2947                         polling-delay = <1000>;
2948
2949                         thermal-sensors = <&tsens0 10>;
2950
2951                         trips {
2952                                 cpu7_top_alert0: trip-point0 {
2953                                         temperature = <90000>;
2954                                         hysteresis = <2000>;
2955                                         type = "passive";
2956                                 };
2957
2958                                 cpu7_top_alert1: trip-point1 {
2959                                         temperature = <95000>;
2960                                         hysteresis = <2000>;
2961                                         type = "passive";
2962                                 };
2963
2964                                 cpu7_top_crit: cpu_crit {
2965                                         temperature = <110000>;
2966                                         hysteresis = <1000>;
2967                                         type = "critical";
2968                                 };
2969                         };
2970
2971                         cooling-maps {
2972                                 map0 {
2973                                         trip = <&cpu7_top_alert0>;
2974                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2975                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2976                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2977                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2978                                 };
2979                                 map1 {
2980                                         trip = <&cpu7_top_alert1>;
2981                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2982                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2983                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2984                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2985                                 };
2986                         };
2987                 };
2988
2989                 cpu4-bottom-thermal {
2990                         polling-delay-passive = <250>;
2991                         polling-delay = <1000>;
2992
2993                         thermal-sensors = <&tsens0 11>;
2994
2995                         trips {
2996                                 cpu4_bottom_alert0: trip-point0 {
2997                                         temperature = <90000>;
2998                                         hysteresis = <2000>;
2999                                         type = "passive";
3000                                 };
3001
3002                                 cpu4_bottom_alert1: trip-point1 {
3003                                         temperature = <95000>;
3004                                         hysteresis = <2000>;
3005                                         type = "passive";
3006                                 };
3007
3008                                 cpu4_bottom_crit: cpu_crit {
3009                                         temperature = <110000>;
3010                                         hysteresis = <1000>;
3011                                         type = "critical";
3012                                 };
3013                         };
3014
3015                         cooling-maps {
3016                                 map0 {
3017                                         trip = <&cpu4_bottom_alert0>;
3018                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3019                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3020                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3021                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3022                                 };
3023                                 map1 {
3024                                         trip = <&cpu4_bottom_alert1>;
3025                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3026                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3027                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3028                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3029                                 };
3030                         };
3031                 };
3032
3033                 cpu5-bottom-thermal {
3034                         polling-delay-passive = <250>;
3035                         polling-delay = <1000>;
3036
3037                         thermal-sensors = <&tsens0 12>;
3038
3039                         trips {
3040                                 cpu5_bottom_alert0: trip-point0 {
3041                                         temperature = <90000>;
3042                                         hysteresis = <2000>;
3043                                         type = "passive";
3044                                 };
3045
3046                                 cpu5_bottom_alert1: trip-point1 {
3047                                         temperature = <95000>;
3048                                         hysteresis = <2000>;
3049                                         type = "passive";
3050                                 };
3051
3052                                 cpu5_bottom_crit: cpu_crit {
3053                                         temperature = <110000>;
3054                                         hysteresis = <1000>;
3055                                         type = "critical";
3056                                 };
3057                         };
3058
3059                         cooling-maps {
3060                                 map0 {
3061                                         trip = <&cpu5_bottom_alert0>;
3062                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3063                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3064                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3065                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3066                                 };
3067                                 map1 {
3068                                         trip = <&cpu5_bottom_alert1>;
3069                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3070                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3071                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3072                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3073                                 };
3074                         };
3075                 };
3076
3077                 cpu6-bottom-thermal {
3078                         polling-delay-passive = <250>;
3079                         polling-delay = <1000>;
3080
3081                         thermal-sensors = <&tsens0 13>;
3082
3083                         trips {
3084                                 cpu6_bottom_alert0: trip-point0 {
3085                                         temperature = <90000>;
3086                                         hysteresis = <2000>;
3087                                         type = "passive";
3088                                 };
3089
3090                                 cpu6_bottom_alert1: trip-point1 {
3091                                         temperature = <95000>;
3092                                         hysteresis = <2000>;
3093                                         type = "passive";
3094                                 };
3095
3096                                 cpu6_bottom_crit: cpu_crit {
3097                                         temperature = <110000>;
3098                                         hysteresis = <1000>;
3099                                         type = "critical";
3100                                 };
3101                         };
3102
3103                         cooling-maps {
3104                                 map0 {
3105                                         trip = <&cpu6_bottom_alert0>;
3106                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3107                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3108                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3109                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3110                                 };
3111                                 map1 {
3112                                         trip = <&cpu6_bottom_alert1>;
3113                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3114                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3115                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3116                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3117                                 };
3118                         };
3119                 };
3120
3121                 cpu7-bottom-thermal {
3122                         polling-delay-passive = <250>;
3123                         polling-delay = <1000>;
3124
3125                         thermal-sensors = <&tsens0 14>;
3126
3127                         trips {
3128                                 cpu7_bottom_alert0: trip-point0 {
3129                                         temperature = <90000>;
3130                                         hysteresis = <2000>;
3131                                         type = "passive";
3132                                 };
3133
3134                                 cpu7_bottom_alert1: trip-point1 {
3135                                         temperature = <95000>;
3136                                         hysteresis = <2000>;
3137                                         type = "passive";
3138                                 };
3139
3140                                 cpu7_bottom_crit: cpu_crit {
3141                                         temperature = <110000>;
3142                                         hysteresis = <1000>;
3143                                         type = "critical";
3144                                 };
3145                         };
3146
3147                         cooling-maps {
3148                                 map0 {
3149                                         trip = <&cpu7_bottom_alert0>;
3150                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3151                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3152                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3153                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3154                                 };
3155                                 map1 {
3156                                         trip = <&cpu7_bottom_alert1>;
3157                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3158                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3159                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3160                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3161                                 };
3162                         };
3163                 };
3164
3165                 aoss0-thermal {
3166                         polling-delay-passive = <250>;
3167                         polling-delay = <1000>;
3168
3169                         thermal-sensors = <&tsens0 0>;
3170
3171                         trips {
3172                                 aoss0_alert0: trip-point0 {
3173                                         temperature = <90000>;
3174                                         hysteresis = <2000>;
3175                                         type = "hot";
3176                                 };
3177                         };
3178                 };
3179
3180                 cluster0-thermal {
3181                         polling-delay-passive = <250>;
3182                         polling-delay = <1000>;
3183
3184                         thermal-sensors = <&tsens0 5>;
3185
3186                         trips {
3187                                 cluster0_alert0: trip-point0 {
3188                                         temperature = <90000>;
3189                                         hysteresis = <2000>;
3190                                         type = "hot";
3191                                 };
3192                                 cluster0_crit: cluster0_crit {
3193                                         temperature = <110000>;
3194                                         hysteresis = <2000>;
3195                                         type = "critical";
3196                                 };
3197                         };
3198                 };
3199
3200                 cluster1-thermal {
3201                         polling-delay-passive = <250>;
3202                         polling-delay = <1000>;
3203
3204                         thermal-sensors = <&tsens0 6>;
3205
3206                         trips {
3207                                 cluster1_alert0: trip-point0 {
3208                                         temperature = <90000>;
3209                                         hysteresis = <2000>;
3210                                         type = "hot";
3211                                 };
3212                                 cluster1_crit: cluster1_crit {
3213                                         temperature = <110000>;
3214                                         hysteresis = <2000>;
3215                                         type = "critical";
3216                                 };
3217                         };
3218                 };
3219
3220                 aoss1-thermal {
3221                         polling-delay-passive = <250>;
3222                         polling-delay = <1000>;
3223
3224                         thermal-sensors = <&tsens1 0>;
3225
3226                         trips {
3227                                 aoss1_alert0: trip-point0 {
3228                                         temperature = <90000>;
3229                                         hysteresis = <2000>;
3230                                         type = "hot";
3231                                 };
3232                         };
3233                 };
3234
3235                 gpu-top-thermal {
3236                         polling-delay-passive = <250>;
3237                         polling-delay = <1000>;
3238
3239                         thermal-sensors = <&tsens1 1>;
3240
3241                         trips {
3242                                 gpu1_alert0: trip-point0 {
3243                                         temperature = <90000>;
3244                                         hysteresis = <1000>;
3245                                         type = "hot";
3246                                 };
3247                         };
3248                 };
3249
3250                 gpu-bottom-thermal {
3251                         polling-delay-passive = <250>;
3252                         polling-delay = <1000>;
3253
3254                         thermal-sensors = <&tsens1 2>;
3255
3256                         trips {
3257                                 gpu2_alert0: trip-point0 {
3258                                         temperature = <90000>;
3259                                         hysteresis = <1000>;
3260                                         type = "hot";
3261                                 };
3262                         };
3263                 };
3264
3265                 nspss1-thermal {
3266                         polling-delay-passive = <250>;
3267                         polling-delay = <1000>;
3268
3269                         thermal-sensors = <&tsens1 3>;
3270
3271                         trips {
3272                                 nspss1_alert0: trip-point0 {
3273                                         temperature = <90000>;
3274                                         hysteresis = <1000>;
3275                                         type = "hot";
3276                                 };
3277                         };
3278                 };
3279
3280                 nspss2-thermal {
3281                         polling-delay-passive = <250>;
3282                         polling-delay = <1000>;
3283
3284                         thermal-sensors = <&tsens1 4>;
3285
3286                         trips {
3287                                 nspss2_alert0: trip-point0 {
3288                                         temperature = <90000>;
3289                                         hysteresis = <1000>;
3290                                         type = "hot";
3291                                 };
3292                         };
3293                 };
3294
3295                 nspss3-thermal {
3296                         polling-delay-passive = <250>;
3297                         polling-delay = <1000>;
3298
3299                         thermal-sensors = <&tsens1 5>;
3300
3301                         trips {
3302                                 nspss3_alert0: trip-point0 {
3303                                         temperature = <90000>;
3304                                         hysteresis = <1000>;
3305                                         type = "hot";
3306                                 };
3307                         };
3308                 };
3309
3310                 video-thermal {
3311                         polling-delay-passive = <250>;
3312                         polling-delay = <1000>;
3313
3314                         thermal-sensors = <&tsens1 6>;
3315
3316                         trips {
3317                                 video_alert0: trip-point0 {
3318                                         temperature = <90000>;
3319                                         hysteresis = <2000>;
3320                                         type = "hot";
3321                                 };
3322                         };
3323                 };
3324
3325                 mem-thermal {
3326                         polling-delay-passive = <250>;
3327                         polling-delay = <1000>;
3328
3329                         thermal-sensors = <&tsens1 7>;
3330
3331                         trips {
3332                                 mem_alert0: trip-point0 {
3333                                         temperature = <90000>;
3334                                         hysteresis = <2000>;
3335                                         type = "hot";
3336                                 };
3337                         };
3338                 };
3339
3340                 modem1-top-thermal {
3341                         polling-delay-passive = <250>;
3342                         polling-delay = <1000>;
3343
3344                         thermal-sensors = <&tsens1 8>;
3345
3346                         trips {
3347                                 modem1_alert0: trip-point0 {
3348                                         temperature = <90000>;
3349                                         hysteresis = <2000>;
3350                                         type = "hot";
3351                                 };
3352                         };
3353                 };
3354
3355                 modem2-top-thermal {
3356                         polling-delay-passive = <250>;
3357                         polling-delay = <1000>;
3358
3359                         thermal-sensors = <&tsens1 9>;
3360
3361                         trips {
3362                                 modem2_alert0: trip-point0 {
3363                                         temperature = <90000>;
3364                                         hysteresis = <2000>;
3365                                         type = "hot";
3366                                 };
3367                         };
3368                 };
3369
3370                 modem3-top-thermal {
3371                         polling-delay-passive = <250>;
3372                         polling-delay = <1000>;
3373
3374                         thermal-sensors = <&tsens1 10>;
3375
3376                         trips {
3377                                 modem3_alert0: trip-point0 {
3378                                         temperature = <90000>;
3379                                         hysteresis = <2000>;
3380                                         type = "hot";
3381                                 };
3382                         };
3383                 };
3384
3385                 modem4-top-thermal {
3386                         polling-delay-passive = <250>;
3387                         polling-delay = <1000>;
3388
3389                         thermal-sensors = <&tsens1 11>;
3390
3391                         trips {
3392                                 modem4_alert0: trip-point0 {
3393                                         temperature = <90000>;
3394                                         hysteresis = <2000>;
3395                                         type = "hot";
3396                                 };
3397                         };
3398                 };
3399
3400                 camera-top-thermal {
3401                         polling-delay-passive = <250>;
3402                         polling-delay = <1000>;
3403
3404                         thermal-sensors = <&tsens1 12>;
3405
3406                         trips {
3407                                 camera1_alert0: trip-point0 {
3408                                         temperature = <90000>;
3409                                         hysteresis = <2000>;
3410                                         type = "hot";
3411                                 };
3412                         };
3413                 };
3414
3415                 cam-bottom-thermal {
3416                         polling-delay-passive = <250>;
3417                         polling-delay = <1000>;
3418
3419                         thermal-sensors = <&tsens1 13>;
3420
3421                         trips {
3422                                 camera2_alert0: trip-point0 {
3423                                         temperature = <90000>;
3424                                         hysteresis = <2000>;
3425                                         type = "hot";
3426                                 };
3427                         };
3428                 };
3429         };
3430
3431         timer {
3432                 compatible = "arm,armv8-timer";
3433                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3434                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3435                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3436                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3437         };
3438 };