arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
  12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16 #include <dt-bindings/interconnect/qcom,sm8250.h>
  17 #include <dt-bindings/mailbox/qcom-ipcc.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/soc/qcom,apr.h>
  20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  21 #include <dt-bindings/sound/qcom,q6afe.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
  24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  25
  26 / {
  27         interrupt-parent = <&intc>;
  28
  29         #address-cells = <2>;
  30         #size-cells = <2>;
  31
  32         aliases {
  33                 i2c0 = &i2c0;
  34                 i2c1 = &i2c1;
  35                 i2c2 = &i2c2;
  36                 i2c3 = &i2c3;
  37                 i2c4 = &i2c4;
  38                 i2c5 = &i2c5;
  39                 i2c6 = &i2c6;
  40                 i2c7 = &i2c7;
  41                 i2c8 = &i2c8;
  42                 i2c9 = &i2c9;
  43                 i2c10 = &i2c10;
  44                 i2c11 = &i2c11;
  45                 i2c12 = &i2c12;
  46                 i2c13 = &i2c13;
  47                 i2c14 = &i2c14;
  48                 i2c15 = &i2c15;
  49                 i2c16 = &i2c16;
  50                 i2c17 = &i2c17;
  51                 i2c18 = &i2c18;
  52                 i2c19 = &i2c19;
  53                 spi0 = &spi0;
  54                 spi1 = &spi1;
  55                 spi2 = &spi2;
  56                 spi3 = &spi3;
  57                 spi4 = &spi4;
  58                 spi5 = &spi5;
  59                 spi6 = &spi6;
  60                 spi7 = &spi7;
  61                 spi8 = &spi8;
  62                 spi9 = &spi9;
  63                 spi10 = &spi10;
  64                 spi11 = &spi11;
  65                 spi12 = &spi12;
  66                 spi13 = &spi13;
  67                 spi14 = &spi14;
  68                 spi15 = &spi15;
  69                 spi16 = &spi16;
  70                 spi17 = &spi17;
  71                 spi18 = &spi18;
  72                 spi19 = &spi19;
  73         };
  74
  75         chosen { };
  76
  77         clocks {
  78                 xo_board: xo-board {
  79                         compatible = "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <38400000>;
  82                         clock-output-names = "xo_board";
  83                 };
  84
  85                 sleep_clk: sleep-clk {
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <32768>;
  88                         #clock-cells = <0>;
  89                 };
  90         };
  91
  92         cpus {
  93                 #address-cells = <2>;
  94                 #size-cells = <0>;
  95
  96                 CPU0: cpu@0 {
  97                         device_type = "cpu";
  98                         compatible = "qcom,kryo485";
  99                         reg = <0x0 0x0>;
 100                         enable-method = "psci";
 101                         capacity-dmips-mhz = <448>;
 102                         dynamic-power-coefficient = <105>;
 103                         next-level-cache = <&L2_0>;
 104                         power-domains = <&CPU_PD0>;
 105                         power-domain-names = "psci";
 106                         qcom,freq-domain = <&cpufreq_hw 0>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 109                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 110                         #cooling-cells = <2>;
 111                         L2_0: l2-cache {
 112                                 compatible = "cache";
 113                                 next-level-cache = <&L3_0>;
 114                                 L3_0: l3-cache {
 115                                         compatible = "cache";
 116                                 };
 117                         };
 118                 };
 119
 120                 CPU1: cpu@100 {
 121                         device_type = "cpu";
 122                         compatible = "qcom,kryo485";
 123                         reg = <0x0 0x100>;
 124                         enable-method = "psci";
 125                         capacity-dmips-mhz = <448>;
 126                         dynamic-power-coefficient = <105>;
 127                         next-level-cache = <&L2_100>;
 128                         power-domains = <&CPU_PD1>;
 129                         power-domain-names = "psci";
 130                         qcom,freq-domain = <&cpufreq_hw 0>;
 131                         operating-points-v2 = <&cpu0_opp_table>;
 132                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 133                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 134                         #cooling-cells = <2>;
 135                         L2_100: l2-cache {
 136                                 compatible = "cache";
 137                                 next-level-cache = <&L3_0>;
 138                         };
 139                 };
 140
 141                 CPU2: cpu@200 {
 142                         device_type = "cpu";
 143                         compatible = "qcom,kryo485";
 144                         reg = <0x0 0x200>;
 145                         enable-method = "psci";
 146                         capacity-dmips-mhz = <448>;
 147                         dynamic-power-coefficient = <105>;
 148                         next-level-cache = <&L2_200>;
 149                         power-domains = <&CPU_PD2>;
 150                         power-domain-names = "psci";
 151                         qcom,freq-domain = <&cpufreq_hw 0>;
 152                         operating-points-v2 = <&cpu0_opp_table>;
 153                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 154                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 155                         #cooling-cells = <2>;
 156                         L2_200: l2-cache {
 157                                 compatible = "cache";
 158                                 next-level-cache = <&L3_0>;
 159                         };
 160                 };
 161
 162                 CPU3: cpu@300 {
 163                         device_type = "cpu";
 164                         compatible = "qcom,kryo485";
 165                         reg = <0x0 0x300>;
 166                         enable-method = "psci";
 167                         capacity-dmips-mhz = <448>;
 168                         dynamic-power-coefficient = <105>;
 169                         next-level-cache = <&L2_300>;
 170                         power-domains = <&CPU_PD3>;
 171                         power-domain-names = "psci";
 172                         qcom,freq-domain = <&cpufreq_hw 0>;
 173                         operating-points-v2 = <&cpu0_opp_table>;
 174                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 175                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 176                         #cooling-cells = <2>;
 177                         L2_300: l2-cache {
 178                                 compatible = "cache";
 179                                 next-level-cache = <&L3_0>;
 180                         };
 181                 };
 182
 183                 CPU4: cpu@400 {
 184                         device_type = "cpu";
 185                         compatible = "qcom,kryo485";
 186                         reg = <0x0 0x400>;
 187                         enable-method = "psci";
 188                         capacity-dmips-mhz = <1024>;
 189                         dynamic-power-coefficient = <379>;
 190                         next-level-cache = <&L2_400>;
 191                         power-domains = <&CPU_PD4>;
 192                         power-domain-names = "psci";
 193                         qcom,freq-domain = <&cpufreq_hw 1>;
 194                         operating-points-v2 = <&cpu4_opp_table>;
 195                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 196                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 197                         #cooling-cells = <2>;
 198                         L2_400: l2-cache {
 199                                 compatible = "cache";
 200                                 next-level-cache = <&L3_0>;
 201                         };
 202                 };
 203
 204                 CPU5: cpu@500 {
 205                         device_type = "cpu";
 206                         compatible = "qcom,kryo485";
 207                         reg = <0x0 0x500>;
 208                         enable-method = "psci";
 209                         capacity-dmips-mhz = <1024>;
 210                         dynamic-power-coefficient = <379>;
 211                         next-level-cache = <&L2_500>;
 212                         power-domains = <&CPU_PD5>;
 213                         power-domain-names = "psci";
 214                         qcom,freq-domain = <&cpufreq_hw 1>;
 215                         operating-points-v2 = <&cpu4_opp_table>;
 216                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 217                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 218                         #cooling-cells = <2>;
 219                         L2_500: l2-cache {
 220                                 compatible = "cache";
 221                                 next-level-cache = <&L3_0>;
 222                         };
 223
 224                 };
 225
 226                 CPU6: cpu@600 {
 227                         device_type = "cpu";
 228                         compatible = "qcom,kryo485";
 229                         reg = <0x0 0x600>;
 230                         enable-method = "psci";
 231                         capacity-dmips-mhz = <1024>;
 232                         dynamic-power-coefficient = <379>;
 233                         next-level-cache = <&L2_600>;
 234                         power-domains = <&CPU_PD6>;
 235                         power-domain-names = "psci";
 236                         qcom,freq-domain = <&cpufreq_hw 1>;
 237                         operating-points-v2 = <&cpu4_opp_table>;
 238                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 239                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 240                         #cooling-cells = <2>;
 241                         L2_600: l2-cache {
 242                                 compatible = "cache";
 243                                 next-level-cache = <&L3_0>;
 244                         };
 245                 };
 246
 247                 CPU7: cpu@700 {
 248                         device_type = "cpu";
 249                         compatible = "qcom,kryo485";
 250                         reg = <0x0 0x700>;
 251                         enable-method = "psci";
 252                         capacity-dmips-mhz = <1024>;
 253                         dynamic-power-coefficient = <444>;
 254                         next-level-cache = <&L2_700>;
 255                         power-domains = <&CPU_PD7>;
 256                         power-domain-names = "psci";
 257                         qcom,freq-domain = <&cpufreq_hw 2>;
 258                         operating-points-v2 = <&cpu7_opp_table>;
 259                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 260                                         <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
 261                         #cooling-cells = <2>;
 262                         L2_700: l2-cache {
 263                                 compatible = "cache";
 264                                 next-level-cache = <&L3_0>;
 265                         };
 266                 };
 267
 268                 cpu-map {
 269                         cluster0 {
 270                                 core0 {
 271                                         cpu = <&CPU0>;
 272                                 };
 273
 274                                 core1 {
 275                                         cpu = <&CPU1>;
 276                                 };
 277
 278                                 core2 {
 279                                         cpu = <&CPU2>;
 280                                 };
 281
 282                                 core3 {
 283                                         cpu = <&CPU3>;
 284                                 };
 285
 286                                 core4 {
 287                                         cpu = <&CPU4>;
 288                                 };
 289
 290                                 core5 {
 291                                         cpu = <&CPU5>;
 292                                 };
 293
 294                                 core6 {
 295                                         cpu = <&CPU6>;
 296                                 };
 297
 298                                 core7 {
 299                                         cpu = <&CPU7>;
 300                                 };
 301                         };
 302                 };
 303
 304                 idle-states {
 305                         entry-method = "psci";
 306
 307                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 308                                 compatible = "arm,idle-state";
 309                                 idle-state-name = "silver-rail-power-collapse";
 310                                 arm,psci-suspend-param = <0x40000004>;
 311                                 entry-latency-us = <360>;
 312                                 exit-latency-us = <531>;
 313                                 min-residency-us = <3934>;
 314                                 local-timer-stop;
 315                         };
 316
 317                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 318                                 compatible = "arm,idle-state";
 319                                 idle-state-name = "gold-rail-power-collapse";
 320                                 arm,psci-suspend-param = <0x40000004>;
 321                                 entry-latency-us = <702>;
 322                                 exit-latency-us = <1061>;
 323                                 min-residency-us = <4488>;
 324                                 local-timer-stop;
 325                         };
 326                 };
 327
 328                 domain-idle-states {
 329                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 330                                 compatible = "domain-idle-state";
 331                                 idle-state-name = "cluster-llcc-off";
 332                                 arm,psci-suspend-param = <0x4100c244>;
 333                                 entry-latency-us = <3264>;
 334                                 exit-latency-us = <6562>;
 335                                 min-residency-us = <9987>;
 336                                 local-timer-stop;
 337                                 status = "disabled";
 338                         };
 339                 };
 340         };
 341
 342         cpu0_opp_table: opp-table-cpu0 {
 343                 compatible = "operating-points-v2";
 344                 opp-shared;
 345
 346                 cpu0_opp1: opp-300000000 {
 347                         opp-hz = /bits/ 64 <300000000>;
 348                         opp-peak-kBps = <800000 9600000>;
 349                 };
 350
 351                 cpu0_opp2: opp-403200000 {
 352                         opp-hz = /bits/ 64 <403200000>;
 353                         opp-peak-kBps = <800000 9600000>;
 354                 };
 355
 356                 cpu0_opp3: opp-518400000 {
 357                         opp-hz = /bits/ 64 <518400000>;
 358                         opp-peak-kBps = <800000 16588800>;
 359                 };
 360
 361                 cpu0_opp4: opp-614400000 {
 362                         opp-hz = /bits/ 64 <614400000>;
 363                         opp-peak-kBps = <800000 16588800>;
 364                 };
 365
 366                 cpu0_opp5: opp-691200000 {
 367                         opp-hz = /bits/ 64 <691200000>;
 368                         opp-peak-kBps = <800000 19660800>;
 369                 };
 370
 371                 cpu0_opp6: opp-787200000 {
 372                         opp-hz = /bits/ 64 <787200000>;
 373                         opp-peak-kBps = <1804000 19660800>;
 374                 };
 375
 376                 cpu0_opp7: opp-883200000 {
 377                         opp-hz = /bits/ 64 <883200000>;
 378                         opp-peak-kBps = <1804000 23347200>;
 379                 };
 380
 381                 cpu0_opp8: opp-979200000 {
 382                         opp-hz = /bits/ 64 <979200000>;
 383                         opp-peak-kBps = <1804000 26419200>;
 384                 };
 385
 386                 cpu0_opp9: opp-1075200000 {
 387                         opp-hz = /bits/ 64 <1075200000>;
 388                         opp-peak-kBps = <1804000 29491200>;
 389                 };
 390
 391                 cpu0_opp10: opp-1171200000 {
 392                         opp-hz = /bits/ 64 <1171200000>;
 393                         opp-peak-kBps = <1804000 32563200>;
 394                 };
 395
 396                 cpu0_opp11: opp-1248000000 {
 397                         opp-hz = /bits/ 64 <1248000000>;
 398                         opp-peak-kBps = <1804000 36249600>;
 399                 };
 400
 401                 cpu0_opp12: opp-1344000000 {
 402                         opp-hz = /bits/ 64 <1344000000>;
 403                         opp-peak-kBps = <2188000 36249600>;
 404                 };
 405
 406                 cpu0_opp13: opp-1420800000 {
 407                         opp-hz = /bits/ 64 <1420800000>;
 408                         opp-peak-kBps = <2188000 39321600>;
 409                 };
 410
 411                 cpu0_opp14: opp-1516800000 {
 412                         opp-hz = /bits/ 64 <1516800000>;
 413                         opp-peak-kBps = <3072000 42393600>;
 414                 };
 415
 416                 cpu0_opp15: opp-1612800000 {
 417                         opp-hz = /bits/ 64 <1612800000>;
 418                         opp-peak-kBps = <3072000 42393600>;
 419                 };
 420
 421                 cpu0_opp16: opp-1708800000 {
 422                         opp-hz = /bits/ 64 <1708800000>;
 423                         opp-peak-kBps = <4068000 42393600>;
 424                 };
 425
 426                 cpu0_opp17: opp-1804800000 {
 427                         opp-hz = /bits/ 64 <1804800000>;
 428                         opp-peak-kBps = <4068000 42393600>;
 429                 };
 430         };
 431
 432         cpu4_opp_table: opp-table-cpu4 {
 433                 compatible = "operating-points-v2";
 434                 opp-shared;
 435
 436                 cpu4_opp1: opp-710400000 {
 437                         opp-hz = /bits/ 64 <710400000>;
 438                         opp-peak-kBps = <1804000 19660800>;
 439                 };
 440
 441                 cpu4_opp2: opp-825600000 {
 442                         opp-hz = /bits/ 64 <825600000>;
 443                         opp-peak-kBps = <2188000 23347200>;
 444                 };
 445
 446                 cpu4_opp3: opp-940800000 {
 447                         opp-hz = /bits/ 64 <940800000>;
 448                         opp-peak-kBps = <2188000 26419200>;
 449                 };
 450
 451                 cpu4_opp4: opp-1056000000 {
 452                         opp-hz = /bits/ 64 <1056000000>;
 453                         opp-peak-kBps = <3072000 26419200>;
 454                 };
 455
 456                 cpu4_opp5: opp-1171200000 {
 457                         opp-hz = /bits/ 64 <1171200000>;
 458                         opp-peak-kBps = <3072000 29491200>;
 459                 };
 460
 461                 cpu4_opp6: opp-1286400000 {
 462                         opp-hz = /bits/ 64 <1286400000>;
 463                         opp-peak-kBps = <4068000 29491200>;
 464                 };
 465
 466                 cpu4_opp7: opp-1382400000 {
 467                         opp-hz = /bits/ 64 <1382400000>;
 468                         opp-peak-kBps = <4068000 32563200>;
 469                 };
 470
 471                 cpu4_opp8: opp-1478400000 {
 472                         opp-hz = /bits/ 64 <1478400000>;
 473                         opp-peak-kBps = <4068000 32563200>;
 474                 };
 475
 476                 cpu4_opp9: opp-1574400000 {
 477                         opp-hz = /bits/ 64 <1574400000>;
 478                         opp-peak-kBps = <5412000 39321600>;
 479                 };
 480
 481                 cpu4_opp10: opp-1670400000 {
 482                         opp-hz = /bits/ 64 <1670400000>;
 483                         opp-peak-kBps = <5412000 42393600>;
 484                 };
 485
 486                 cpu4_opp11: opp-1766400000 {
 487                         opp-hz = /bits/ 64 <1766400000>;
 488                         opp-peak-kBps = <5412000 45465600>;
 489                 };
 490
 491                 cpu4_opp12: opp-1862400000 {
 492                         opp-hz = /bits/ 64 <1862400000>;
 493                         opp-peak-kBps = <6220000 45465600>;
 494                 };
 495
 496                 cpu4_opp13: opp-1958400000 {
 497                         opp-hz = /bits/ 64 <1958400000>;
 498                         opp-peak-kBps = <6220000 48537600>;
 499                 };
 500
 501                 cpu4_opp14: opp-2054400000 {
 502                         opp-hz = /bits/ 64 <2054400000>;
 503                         opp-peak-kBps = <7216000 48537600>;
 504                 };
 505
 506                 cpu4_opp15: opp-2150400000 {
 507                         opp-hz = /bits/ 64 <2150400000>;
 508                         opp-peak-kBps = <7216000 51609600>;
 509                 };
 510
 511                 cpu4_opp16: opp-2246400000 {
 512                         opp-hz = /bits/ 64 <2246400000>;
 513                         opp-peak-kBps = <7216000 51609600>;
 514                 };
 515
 516                 cpu4_opp17: opp-2342400000 {
 517                         opp-hz = /bits/ 64 <2342400000>;
 518                         opp-peak-kBps = <8368000 51609600>;
 519                 };
 520
 521                 cpu4_opp18: opp-2419200000 {
 522                         opp-hz = /bits/ 64 <2419200000>;
 523                         opp-peak-kBps = <8368000 51609600>;
 524                 };
 525         };
 526
 527         cpu7_opp_table: opp-table-cpu7 {
 528                 compatible = "operating-points-v2";
 529                 opp-shared;
 530
 531                 cpu7_opp1: opp-844800000 {
 532                         opp-hz = /bits/ 64 <844800000>;
 533                         opp-peak-kBps = <2188000 19660800>;
 534                 };
 535
 536                 cpu7_opp2: opp-960000000 {
 537                         opp-hz = /bits/ 64 <960000000>;
 538                         opp-peak-kBps = <2188000 26419200>;
 539                 };
 540
 541                 cpu7_opp3: opp-1075200000 {
 542                         opp-hz = /bits/ 64 <1075200000>;
 543                         opp-peak-kBps = <3072000 26419200>;
 544                 };
 545
 546                 cpu7_opp4: opp-1190400000 {
 547                         opp-hz = /bits/ 64 <1190400000>;
 548                         opp-peak-kBps = <3072000 29491200>;
 549                 };
 550
 551                 cpu7_opp5: opp-1305600000 {
 552                         opp-hz = /bits/ 64 <1305600000>;
 553                         opp-peak-kBps = <4068000 32563200>;
 554                 };
 555
 556                 cpu7_opp6: opp-1401600000 {
 557                         opp-hz = /bits/ 64 <1401600000>;
 558                         opp-peak-kBps = <4068000 32563200>;
 559                 };
 560
 561                 cpu7_opp7: opp-1516800000 {
 562                         opp-hz = /bits/ 64 <1516800000>;
 563                         opp-peak-kBps = <4068000 36249600>;
 564                 };
 565
 566                 cpu7_opp8: opp-1632000000 {
 567                         opp-hz = /bits/ 64 <1632000000>;
 568                         opp-peak-kBps = <5412000 39321600>;
 569                 };
 570
 571                 cpu7_opp9: opp-1747200000 {
 572                         opp-hz = /bits/ 64 <1708800000>;
 573                         opp-peak-kBps = <5412000 42393600>;
 574                 };
 575
 576                 cpu7_opp10: opp-1862400000 {
 577                         opp-hz = /bits/ 64 <1862400000>;
 578                         opp-peak-kBps = <6220000 45465600>;
 579                 };
 580
 581                 cpu7_opp11: opp-1977600000 {
 582                         opp-hz = /bits/ 64 <1977600000>;
 583                         opp-peak-kBps = <6220000 48537600>;
 584                 };
 585
 586                 cpu7_opp12: opp-2073600000 {
 587                         opp-hz = /bits/ 64 <2073600000>;
 588                         opp-peak-kBps = <7216000 48537600>;
 589                 };
 590
 591                 cpu7_opp13: opp-2169600000 {
 592                         opp-hz = /bits/ 64 <2169600000>;
 593                         opp-peak-kBps = <7216000 51609600>;
 594                 };
 595
 596                 cpu7_opp14: opp-2265600000 {
 597                         opp-hz = /bits/ 64 <2265600000>;
 598                         opp-peak-kBps = <7216000 51609600>;
 599                 };
 600
 601                 cpu7_opp15: opp-2361600000 {
 602                         opp-hz = /bits/ 64 <2361600000>;
 603                         opp-peak-kBps = <8368000 51609600>;
 604                 };
 605
 606                 cpu7_opp16: opp-2457600000 {
 607                         opp-hz = /bits/ 64 <2457600000>;
 608                         opp-peak-kBps = <8368000 51609600>;
 609                 };
 610
 611                 cpu7_opp17: opp-2553600000 {
 612                         opp-hz = /bits/ 64 <2553600000>;
 613                         opp-peak-kBps = <8368000 51609600>;
 614                 };
 615
 616                 cpu7_opp18: opp-2649600000 {
 617                         opp-hz = /bits/ 64 <2649600000>;
 618                         opp-peak-kBps = <8368000 51609600>;
 619                 };
 620
 621                 cpu7_opp19: opp-2745600000 {
 622                         opp-hz = /bits/ 64 <2745600000>;
 623                         opp-peak-kBps = <8368000 51609600>;
 624                 };
 625
 626                 cpu7_opp20: opp-2841600000 {
 627                         opp-hz = /bits/ 64 <2841600000>;
 628                         opp-peak-kBps = <8368000 51609600>;
 629                 };
 630         };
 631
 632         firmware {
 633                 scm: scm {
 634                         compatible = "qcom,scm-sm8250", "qcom,scm";
 635                         #reset-cells = <1>;
 636                 };
 637         };
 638
 639         memory@80000000 {
 640                 device_type = "memory";
 641                 /* We expect the bootloader to fill in the size */
 642                 reg = <0x0 0x80000000 0x0 0x0>;
 643         };
 644
 645         pmu {
 646                 compatible = "arm,armv8-pmuv3";
 647                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 648         };
 649
 650         psci {
 651                 compatible = "arm,psci-1.0";
 652                 method = "smc";
 653
 654                 CPU_PD0: cpu0 {
 655                         #power-domain-cells = <0>;
 656                         power-domains = <&CLUSTER_PD>;
 657                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 658                 };
 659
 660                 CPU_PD1: cpu1 {
 661                         #power-domain-cells = <0>;
 662                         power-domains = <&CLUSTER_PD>;
 663                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 664                 };
 665
 666                 CPU_PD2: cpu2 {
 667                         #power-domain-cells = <0>;
 668                         power-domains = <&CLUSTER_PD>;
 669                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 670                 };
 671
 672                 CPU_PD3: cpu3 {
 673                         #power-domain-cells = <0>;
 674                         power-domains = <&CLUSTER_PD>;
 675                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 676                 };
 677
 678                 CPU_PD4: cpu4 {
 679                         #power-domain-cells = <0>;
 680                         power-domains = <&CLUSTER_PD>;
 681                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 682                 };
 683
 684                 CPU_PD5: cpu5 {
 685                         #power-domain-cells = <0>;
 686                         power-domains = <&CLUSTER_PD>;
 687                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 688                 };
 689
 690                 CPU_PD6: cpu6 {
 691                         #power-domain-cells = <0>;
 692                         power-domains = <&CLUSTER_PD>;
 693                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 694                 };
 695
 696                 CPU_PD7: cpu7 {
 697                         #power-domain-cells = <0>;
 698                         power-domains = <&CLUSTER_PD>;
 699                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 700                 };
 701
 702                 CLUSTER_PD: cpu-cluster0 {
 703                         #power-domain-cells = <0>;
 704                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 705                 };
 706         };
 707
 708         qup_opp_table: opp-table-qup {
 709                 compatible = "operating-points-v2";
 710
 711                 opp-50000000 {
 712                         opp-hz = /bits/ 64 <50000000>;
 713                         required-opps = <&rpmhpd_opp_min_svs>;
 714                 };
 715
 716                 opp-75000000 {
 717                         opp-hz = /bits/ 64 <75000000>;
 718                         required-opps = <&rpmhpd_opp_low_svs>;
 719                 };
 720
 721                 opp-120000000 {
 722                         opp-hz = /bits/ 64 <120000000>;
 723                         required-opps = <&rpmhpd_opp_svs>;
 724                 };
 725         };
 726
 727         reserved-memory {
 728                 #address-cells = <2>;
 729                 #size-cells = <2>;
 730                 ranges;
 731
 732                 hyp_mem: memory@80000000 {
 733                         reg = <0x0 0x80000000 0x0 0x600000>;
 734                         no-map;
 735                 };
 736
 737                 xbl_aop_mem: memory@80700000 {
 738                         reg = <0x0 0x80700000 0x0 0x160000>;
 739                         no-map;
 740                 };
 741
 742                 cmd_db: memory@80860000 {
 743                         compatible = "qcom,cmd-db";
 744                         reg = <0x0 0x80860000 0x0 0x20000>;
 745                         no-map;
 746                 };
 747
 748                 smem_mem: memory@80900000 {
 749                         reg = <0x0 0x80900000 0x0 0x200000>;
 750                         no-map;
 751                 };
 752
 753                 removed_mem: memory@80b00000 {
 754                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 755                         no-map;
 756                 };
 757
 758                 camera_mem: memory@86200000 {
 759                         reg = <0x0 0x86200000 0x0 0x500000>;
 760                         no-map;
 761                 };
 762
 763                 wlan_mem: memory@86700000 {
 764                         reg = <0x0 0x86700000 0x0 0x100000>;
 765                         no-map;
 766                 };
 767
 768                 ipa_fw_mem: memory@86800000 {
 769                         reg = <0x0 0x86800000 0x0 0x10000>;
 770                         no-map;
 771                 };
 772
 773                 ipa_gsi_mem: memory@86810000 {
 774                         reg = <0x0 0x86810000 0x0 0xa000>;
 775                         no-map;
 776                 };
 777
 778                 gpu_mem: memory@8681a000 {
 779                         reg = <0x0 0x8681a000 0x0 0x2000>;
 780                         no-map;
 781                 };
 782
 783                 npu_mem: memory@86900000 {
 784                         reg = <0x0 0x86900000 0x0 0x500000>;
 785                         no-map;
 786                 };
 787
 788                 video_mem: memory@86e00000 {
 789                         reg = <0x0 0x86e00000 0x0 0x500000>;
 790                         no-map;
 791                 };
 792
 793                 cvp_mem: memory@87300000 {
 794                         reg = <0x0 0x87300000 0x0 0x500000>;
 795                         no-map;
 796                 };
 797
 798                 cdsp_mem: memory@87800000 {
 799                         reg = <0x0 0x87800000 0x0 0x1400000>;
 800                         no-map;
 801                 };
 802
 803                 slpi_mem: memory@88c00000 {
 804                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 805                         no-map;
 806                 };
 807
 808                 adsp_mem: memory@8a100000 {
 809                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 810                         no-map;
 811                 };
 812
 813                 spss_mem: memory@8be00000 {
 814                         reg = <0x0 0x8be00000 0x0 0x100000>;
 815                         no-map;
 816                 };
 817
 818                 cdsp_secure_heap: memory@8bf00000 {
 819                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 820                         no-map;
 821                 };
 822         };
 823
 824         smem {
 825                 compatible = "qcom,smem";
 826                 memory-region = <&smem_mem>;
 827                 hwlocks = <&tcsr_mutex 3>;
 828         };
 829
 830         smp2p-adsp {
 831                 compatible = "qcom,smp2p";
 832                 qcom,smem = <443>, <429>;
 833                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 834                                              IPCC_MPROC_SIGNAL_SMP2P
 835                                              IRQ_TYPE_EDGE_RISING>;
 836                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 837                                 IPCC_MPROC_SIGNAL_SMP2P>;
 838
 839                 qcom,local-pid = <0>;
 840                 qcom,remote-pid = <2>;
 841
 842                 smp2p_adsp_out: master-kernel {
 843                         qcom,entry-name = "master-kernel";
 844                         #qcom,smem-state-cells = <1>;
 845                 };
 846
 847                 smp2p_adsp_in: slave-kernel {
 848                         qcom,entry-name = "slave-kernel";
 849                         interrupt-controller;
 850                         #interrupt-cells = <2>;
 851                 };
 852         };
 853
 854         smp2p-cdsp {
 855                 compatible = "qcom,smp2p";
 856                 qcom,smem = <94>, <432>;
 857                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 858                                              IPCC_MPROC_SIGNAL_SMP2P
 859                                              IRQ_TYPE_EDGE_RISING>;
 860                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 861                                 IPCC_MPROC_SIGNAL_SMP2P>;
 862
 863                 qcom,local-pid = <0>;
 864                 qcom,remote-pid = <5>;
 865
 866                 smp2p_cdsp_out: master-kernel {
 867                         qcom,entry-name = "master-kernel";
 868                         #qcom,smem-state-cells = <1>;
 869                 };
 870
 871                 smp2p_cdsp_in: slave-kernel {
 872                         qcom,entry-name = "slave-kernel";
 873                         interrupt-controller;
 874                         #interrupt-cells = <2>;
 875                 };
 876         };
 877
 878         smp2p-slpi {
 879                 compatible = "qcom,smp2p";
 880                 qcom,smem = <481>, <430>;
 881                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 882                                              IPCC_MPROC_SIGNAL_SMP2P
 883                                              IRQ_TYPE_EDGE_RISING>;
 884                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 885                                 IPCC_MPROC_SIGNAL_SMP2P>;
 886
 887                 qcom,local-pid = <0>;
 888                 qcom,remote-pid = <3>;
 889
 890                 smp2p_slpi_out: master-kernel {
 891                         qcom,entry-name = "master-kernel";
 892                         #qcom,smem-state-cells = <1>;
 893                 };
 894
 895                 smp2p_slpi_in: slave-kernel {
 896                         qcom,entry-name = "slave-kernel";
 897                         interrupt-controller;
 898                         #interrupt-cells = <2>;
 899                 };
 900         };
 901
 902         soc: soc@0 {
 903                 #address-cells = <2>;
 904                 #size-cells = <2>;
 905                 ranges = <0 0 0 0 0x10 0>;
 906                 dma-ranges = <0 0 0 0 0x10 0>;
 907                 compatible = "simple-bus";
 908
 909                 gcc: clock-controller@100000 {
 910                         compatible = "qcom,gcc-sm8250";
 911                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 912                         #clock-cells = <1>;
 913                         #reset-cells = <1>;
 914                         #power-domain-cells = <1>;
 915                         clock-names = "bi_tcxo",
 916                                       "bi_tcxo_ao",
 917                                       "sleep_clk";
 918                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 919                                  <&rpmhcc RPMH_CXO_CLK_A>,
 920                                  <&sleep_clk>;
 921                 };
 922
 923                 ipcc: mailbox@408000 {
 924                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 925                         reg = <0 0x00408000 0 0x1000>;
 926                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 927                         interrupt-controller;
 928                         #interrupt-cells = <3>;
 929                         #mbox-cells = <2>;
 930                 };
 931
 932                 rng: rng@793000 {
 933                         compatible = "qcom,prng-ee";
 934                         reg = <0 0x00793000 0 0x1000>;
 935                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 936                         clock-names = "core";
 937                 };
 938
 939                 gpi_dma2: dma-controller@800000 {
 940                         compatible = "qcom,sm8250-gpi-dma";
 941                         reg = <0 0x00800000 0 0x70000>;
 942                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 943                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 944                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 945                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 946                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 947                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 950                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 951                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
 952                         dma-channels = <10>;
 953                         dma-channel-mask = <0x3f>;
 954                         iommus = <&apps_smmu 0x76 0x0>;
 955                         #dma-cells = <3>;
 956                         status = "disabled";
 957                 };
 958
 959                 qupv3_id_2: geniqup@8c0000 {
 960                         compatible = "qcom,geni-se-qup";
 961                         reg = <0x0 0x008c0000 0x0 0x6000>;
 962                         clock-names = "m-ahb", "s-ahb";
 963                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 964                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 965                         #address-cells = <2>;
 966                         #size-cells = <2>;
 967                         iommus = <&apps_smmu 0x63 0x0>;
 968                         ranges;
 969                         status = "disabled";
 970
 971                         i2c14: i2c@880000 {
 972                                 compatible = "qcom,geni-i2c";
 973                                 reg = <0 0x00880000 0 0x4000>;
 974                                 clock-names = "se";
 975                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_i2c14_default>;
 978                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 979                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 980                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 981                                 dma-names = "tx", "rx";
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984                                 status = "disabled";
 985                         };
 986
 987                         spi14: spi@880000 {
 988                                 compatible = "qcom,geni-spi";
 989                                 reg = <0 0x00880000 0 0x4000>;
 990                                 clock-names = "se";
 991                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 992                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 993                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 994                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 995                                 dma-names = "tx", "rx";
 996                                 power-domains = <&rpmhpd SM8250_CX>;
 997                                 operating-points-v2 = <&qup_opp_table>;
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c15: i2c@884000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0 0x00884000 0 0x4000>;
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&qup_i2c15_default>;
1010                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1011                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1012                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1013                                 dma-names = "tx", "rx";
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 status = "disabled";
1017                         };
1018
1019                         spi15: spi@884000 {
1020                                 compatible = "qcom,geni-spi";
1021                                 reg = <0 0x00884000 0 0x4000>;
1022                                 clock-names = "se";
1023                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1024                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1025                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1026                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1027                                 dma-names = "tx", "rx";
1028                                 power-domains = <&rpmhpd SM8250_CX>;
1029                                 operating-points-v2 = <&qup_opp_table>;
1030                                 #address-cells = <1>;
1031                                 #size-cells = <0>;
1032                                 status = "disabled";
1033                         };
1034
1035                         i2c16: i2c@888000 {
1036                                 compatible = "qcom,geni-i2c";
1037                                 reg = <0 0x00888000 0 0x4000>;
1038                                 clock-names = "se";
1039                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_i2c16_default>;
1042                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1043                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1044                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1045                                 dma-names = "tx", "rx";
1046                                 #address-cells = <1>;
1047                                 #size-cells = <0>;
1048                                 status = "disabled";
1049                         };
1050
1051                         spi16: spi@888000 {
1052                                 compatible = "qcom,geni-spi";
1053                                 reg = <0 0x00888000 0 0x4000>;
1054                                 clock-names = "se";
1055                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1056                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1057                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1058                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1059                                 dma-names = "tx", "rx";
1060                                 power-domains = <&rpmhpd SM8250_CX>;
1061                                 operating-points-v2 = <&qup_opp_table>;
1062                                 #address-cells = <1>;
1063                                 #size-cells = <0>;
1064                                 status = "disabled";
1065                         };
1066
1067                         i2c17: i2c@88c000 {
1068                                 compatible = "qcom,geni-i2c";
1069                                 reg = <0 0x0088c000 0 0x4000>;
1070                                 clock-names = "se";
1071                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1072                                 pinctrl-names = "default";
1073                                 pinctrl-0 = <&qup_i2c17_default>;
1074                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1075                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1076                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1077                                 dma-names = "tx", "rx";
1078                                 #address-cells = <1>;
1079                                 #size-cells = <0>;
1080                                 status = "disabled";
1081                         };
1082
1083                         spi17: spi@88c000 {
1084                                 compatible = "qcom,geni-spi";
1085                                 reg = <0 0x0088c000 0 0x4000>;
1086                                 clock-names = "se";
1087                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1088                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1089                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1090                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1091                                 dma-names = "tx", "rx";
1092                                 power-domains = <&rpmhpd SM8250_CX>;
1093                                 operating-points-v2 = <&qup_opp_table>;
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 status = "disabled";
1097                         };
1098
1099                         uart17: serial@88c000 {
1100                                 compatible = "qcom,geni-uart";
1101                                 reg = <0 0x0088c000 0 0x4000>;
1102                                 clock-names = "se";
1103                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1104                                 pinctrl-names = "default";
1105                                 pinctrl-0 = <&qup_uart17_default>;
1106                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1107                                 power-domains = <&rpmhpd SM8250_CX>;
1108                                 operating-points-v2 = <&qup_opp_table>;
1109                                 status = "disabled";
1110                         };
1111
1112                         i2c18: i2c@890000 {
1113                                 compatible = "qcom,geni-i2c";
1114                                 reg = <0 0x00890000 0 0x4000>;
1115                                 clock-names = "se";
1116                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1117                                 pinctrl-names = "default";
1118                                 pinctrl-0 = <&qup_i2c18_default>;
1119                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1120                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1121                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1122                                 dma-names = "tx", "rx";
1123                                 #address-cells = <1>;
1124                                 #size-cells = <0>;
1125                                 status = "disabled";
1126                         };
1127
1128                         spi18: spi@890000 {
1129                                 compatible = "qcom,geni-spi";
1130                                 reg = <0 0x00890000 0 0x4000>;
1131                                 clock-names = "se";
1132                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1133                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1134                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1135                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1136                                 dma-names = "tx", "rx";
1137                                 power-domains = <&rpmhpd SM8250_CX>;
1138                                 operating-points-v2 = <&qup_opp_table>;
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 status = "disabled";
1142                         };
1143
1144                         uart18: serial@890000 {
1145                                 compatible = "qcom,geni-uart";
1146                                 reg = <0 0x00890000 0 0x4000>;
1147                                 clock-names = "se";
1148                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1149                                 pinctrl-names = "default";
1150                                 pinctrl-0 = <&qup_uart18_default>;
1151                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1152                                 power-domains = <&rpmhpd SM8250_CX>;
1153                                 operating-points-v2 = <&qup_opp_table>;
1154                                 status = "disabled";
1155                         };
1156
1157                         i2c19: i2c@894000 {
1158                                 compatible = "qcom,geni-i2c";
1159                                 reg = <0 0x00894000 0 0x4000>;
1160                                 clock-names = "se";
1161                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1162                                 pinctrl-names = "default";
1163                                 pinctrl-0 = <&qup_i2c19_default>;
1164                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1165                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1166                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1167                                 dma-names = "tx", "rx";
1168                                 #address-cells = <1>;
1169                                 #size-cells = <0>;
1170                                 status = "disabled";
1171                         };
1172
1173                         spi19: spi@894000 {
1174                                 compatible = "qcom,geni-spi";
1175                                 reg = <0 0x00894000 0 0x4000>;
1176                                 clock-names = "se";
1177                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1178                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1179                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1180                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1181                                 dma-names = "tx", "rx";
1182                                 power-domains = <&rpmhpd SM8250_CX>;
1183                                 operating-points-v2 = <&qup_opp_table>;
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186                                 status = "disabled";
1187                         };
1188                 };
1189
1190                 gpi_dma0: dma-controller@900000 {
1191                         compatible = "qcom,sm8250-gpi-dma";
1192                         reg = <0 0x00900000 0 0x70000>;
1193                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1206                         dma-channels = <15>;
1207                         dma-channel-mask = <0x7ff>;
1208                         iommus = <&apps_smmu 0x5b6 0x0>;
1209                         #dma-cells = <3>;
1210                         status = "disabled";
1211                 };
1212
1213                 qupv3_id_0: geniqup@9c0000 {
1214                         compatible = "qcom,geni-se-qup";
1215                         reg = <0x0 0x009c0000 0x0 0x6000>;
1216                         clock-names = "m-ahb", "s-ahb";
1217                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1218                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1219                         #address-cells = <2>;
1220                         #size-cells = <2>;
1221                         iommus = <&apps_smmu 0x5a3 0x0>;
1222                         ranges;
1223                         status = "disabled";
1224
1225                         i2c0: i2c@980000 {
1226                                 compatible = "qcom,geni-i2c";
1227                                 reg = <0 0x00980000 0 0x4000>;
1228                                 clock-names = "se";
1229                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1230                                 pinctrl-names = "default";
1231                                 pinctrl-0 = <&qup_i2c0_default>;
1232                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1233                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1234                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1235                                 dma-names = "tx", "rx";
1236                                 #address-cells = <1>;
1237                                 #size-cells = <0>;
1238                                 status = "disabled";
1239                         };
1240
1241                         spi0: spi@980000 {
1242                                 compatible = "qcom,geni-spi";
1243                                 reg = <0 0x00980000 0 0x4000>;
1244                                 clock-names = "se";
1245                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1246                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1247                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1248                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1249                                 dma-names = "tx", "rx";
1250                                 power-domains = <&rpmhpd SM8250_CX>;
1251                                 operating-points-v2 = <&qup_opp_table>;
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 status = "disabled";
1255                         };
1256
1257                         i2c1: i2c@984000 {
1258                                 compatible = "qcom,geni-i2c";
1259                                 reg = <0 0x00984000 0 0x4000>;
1260                                 clock-names = "se";
1261                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1262                                 pinctrl-names = "default";
1263                                 pinctrl-0 = <&qup_i2c1_default>;
1264                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1265                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1266                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1267                                 dma-names = "tx", "rx";
1268                                 #address-cells = <1>;
1269                                 #size-cells = <0>;
1270                                 status = "disabled";
1271                         };
1272
1273                         spi1: spi@984000 {
1274                                 compatible = "qcom,geni-spi";
1275                                 reg = <0 0x00984000 0 0x4000>;
1276                                 clock-names = "se";
1277                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1278                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1279                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1280                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1281                                 dma-names = "tx", "rx";
1282                                 power-domains = <&rpmhpd SM8250_CX>;
1283                                 operating-points-v2 = <&qup_opp_table>;
1284                                 #address-cells = <1>;
1285                                 #size-cells = <0>;
1286                                 status = "disabled";
1287                         };
1288
1289                         i2c2: i2c@988000 {
1290                                 compatible = "qcom,geni-i2c";
1291                                 reg = <0 0x00988000 0 0x4000>;
1292                                 clock-names = "se";
1293                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1294                                 pinctrl-names = "default";
1295                                 pinctrl-0 = <&qup_i2c2_default>;
1296                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1297                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1298                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1299                                 dma-names = "tx", "rx";
1300                                 #address-cells = <1>;
1301                                 #size-cells = <0>;
1302                                 status = "disabled";
1303                         };
1304
1305                         spi2: spi@988000 {
1306                                 compatible = "qcom,geni-spi";
1307                                 reg = <0 0x00988000 0 0x4000>;
1308                                 clock-names = "se";
1309                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1310                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1311                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1312                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1313                                 dma-names = "tx", "rx";
1314                                 power-domains = <&rpmhpd SM8250_CX>;
1315                                 operating-points-v2 = <&qup_opp_table>;
1316                                 #address-cells = <1>;
1317                                 #size-cells = <0>;
1318                                 status = "disabled";
1319                         };
1320
1321                         uart2: serial@988000 {
1322                                 compatible = "qcom,geni-debug-uart";
1323                                 reg = <0 0x00988000 0 0x4000>;
1324                                 clock-names = "se";
1325                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1326                                 pinctrl-names = "default";
1327                                 pinctrl-0 = <&qup_uart2_default>;
1328                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1329                                 power-domains = <&rpmhpd SM8250_CX>;
1330                                 operating-points-v2 = <&qup_opp_table>;
1331                                 status = "disabled";
1332                         };
1333
1334                         i2c3: i2c@98c000 {
1335                                 compatible = "qcom,geni-i2c";
1336                                 reg = <0 0x0098c000 0 0x4000>;
1337                                 clock-names = "se";
1338                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1339                                 pinctrl-names = "default";
1340                                 pinctrl-0 = <&qup_i2c3_default>;
1341                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1342                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1343                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1344                                 dma-names = "tx", "rx";
1345                                 #address-cells = <1>;
1346                                 #size-cells = <0>;
1347                                 status = "disabled";
1348                         };
1349
1350                         spi3: spi@98c000 {
1351                                 compatible = "qcom,geni-spi";
1352                                 reg = <0 0x0098c000 0 0x4000>;
1353                                 clock-names = "se";
1354                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1355                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1356                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1357                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1358                                 dma-names = "tx", "rx";
1359                                 power-domains = <&rpmhpd SM8250_CX>;
1360                                 operating-points-v2 = <&qup_opp_table>;
1361                                 #address-cells = <1>;
1362                                 #size-cells = <0>;
1363                                 status = "disabled";
1364                         };
1365
1366                         i2c4: i2c@990000 {
1367                                 compatible = "qcom,geni-i2c";
1368                                 reg = <0 0x00990000 0 0x4000>;
1369                                 clock-names = "se";
1370                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1371                                 pinctrl-names = "default";
1372                                 pinctrl-0 = <&qup_i2c4_default>;
1373                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1374                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1375                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1376                                 dma-names = "tx", "rx";
1377                                 #address-cells = <1>;
1378                                 #size-cells = <0>;
1379                                 status = "disabled";
1380                         };
1381
1382                         spi4: spi@990000 {
1383                                 compatible = "qcom,geni-spi";
1384                                 reg = <0 0x00990000 0 0x4000>;
1385                                 clock-names = "se";
1386                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1387                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1388                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1389                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1390                                 dma-names = "tx", "rx";
1391                                 power-domains = <&rpmhpd SM8250_CX>;
1392                                 operating-points-v2 = <&qup_opp_table>;
1393                                 #address-cells = <1>;
1394                                 #size-cells = <0>;
1395                                 status = "disabled";
1396                         };
1397
1398                         i2c5: i2c@994000 {
1399                                 compatible = "qcom,geni-i2c";
1400                                 reg = <0 0x00994000 0 0x4000>;
1401                                 clock-names = "se";
1402                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1403                                 pinctrl-names = "default";
1404                                 pinctrl-0 = <&qup_i2c5_default>;
1405                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1406                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1407                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1408                                 dma-names = "tx", "rx";
1409                                 #address-cells = <1>;
1410                                 #size-cells = <0>;
1411                                 status = "disabled";
1412                         };
1413
1414                         spi5: spi@994000 {
1415                                 compatible = "qcom,geni-spi";
1416                                 reg = <0 0x00994000 0 0x4000>;
1417                                 clock-names = "se";
1418                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1419                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1420                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1421                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1422                                 dma-names = "tx", "rx";
1423                                 power-domains = <&rpmhpd SM8250_CX>;
1424                                 operating-points-v2 = <&qup_opp_table>;
1425                                 #address-cells = <1>;
1426                                 #size-cells = <0>;
1427                                 status = "disabled";
1428                         };
1429
1430                         i2c6: i2c@998000 {
1431                                 compatible = "qcom,geni-i2c";
1432                                 reg = <0 0x00998000 0 0x4000>;
1433                                 clock-names = "se";
1434                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1435                                 pinctrl-names = "default";
1436                                 pinctrl-0 = <&qup_i2c6_default>;
1437                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1438                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1439                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1440                                 dma-names = "tx", "rx";
1441                                 #address-cells = <1>;
1442                                 #size-cells = <0>;
1443                                 status = "disabled";
1444                         };
1445
1446                         spi6: spi@998000 {
1447                                 compatible = "qcom,geni-spi";
1448                                 reg = <0 0x00998000 0 0x4000>;
1449                                 clock-names = "se";
1450                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1451                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1452                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1453                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1454                                 dma-names = "tx", "rx";
1455                                 power-domains = <&rpmhpd SM8250_CX>;
1456                                 operating-points-v2 = <&qup_opp_table>;
1457                                 #address-cells = <1>;
1458                                 #size-cells = <0>;
1459                                 status = "disabled";
1460                         };
1461
1462                         uart6: serial@998000 {
1463                                 compatible = "qcom,geni-uart";
1464                                 reg = <0 0x00998000 0 0x4000>;
1465                                 clock-names = "se";
1466                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1467                                 pinctrl-names = "default";
1468                                 pinctrl-0 = <&qup_uart6_default>;
1469                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1470                                 power-domains = <&rpmhpd SM8250_CX>;
1471                                 operating-points-v2 = <&qup_opp_table>;
1472                                 status = "disabled";
1473                         };
1474
1475                         i2c7: i2c@99c000 {
1476                                 compatible = "qcom,geni-i2c";
1477                                 reg = <0 0x0099c000 0 0x4000>;
1478                                 clock-names = "se";
1479                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1480                                 pinctrl-names = "default";
1481                                 pinctrl-0 = <&qup_i2c7_default>;
1482                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1483                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1484                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1485                                 dma-names = "tx", "rx";
1486                                 #address-cells = <1>;
1487                                 #size-cells = <0>;
1488                                 status = "disabled";
1489                         };
1490
1491                         spi7: spi@99c000 {
1492                                 compatible = "qcom,geni-spi";
1493                                 reg = <0 0x0099c000 0 0x4000>;
1494                                 clock-names = "se";
1495                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1496                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1497                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1498                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1499                                 dma-names = "tx", "rx";
1500                                 power-domains = <&rpmhpd SM8250_CX>;
1501                                 operating-points-v2 = <&qup_opp_table>;
1502                                 #address-cells = <1>;
1503                                 #size-cells = <0>;
1504                                 status = "disabled";
1505                         };
1506                 };
1507
1508                 gpi_dma1: dma-controller@a00000 {
1509                         compatible = "qcom,sm8250-gpi-dma";
1510                         reg = <0 0x00a00000 0 0x70000>;
1511                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1516                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1517                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1518                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1519                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1520                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1521                         dma-channels = <10>;
1522                         dma-channel-mask = <0x3f>;
1523                         iommus = <&apps_smmu 0x56 0x0>;
1524                         #dma-cells = <3>;
1525                         status = "disabled";
1526                 };
1527
1528                 qupv3_id_1: geniqup@ac0000 {
1529                         compatible = "qcom,geni-se-qup";
1530                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1531                         clock-names = "m-ahb", "s-ahb";
1532                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1533                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1534                         #address-cells = <2>;
1535                         #size-cells = <2>;
1536                         iommus = <&apps_smmu 0x43 0x0>;
1537                         ranges;
1538                         status = "disabled";
1539
1540                         i2c8: i2c@a80000 {
1541                                 compatible = "qcom,geni-i2c";
1542                                 reg = <0 0x00a80000 0 0x4000>;
1543                                 clock-names = "se";
1544                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1545                                 pinctrl-names = "default";
1546                                 pinctrl-0 = <&qup_i2c8_default>;
1547                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1548                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1549                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1550                                 dma-names = "tx", "rx";
1551                                 #address-cells = <1>;
1552                                 #size-cells = <0>;
1553                                 status = "disabled";
1554                         };
1555
1556                         spi8: spi@a80000 {
1557                                 compatible = "qcom,geni-spi";
1558                                 reg = <0 0x00a80000 0 0x4000>;
1559                                 clock-names = "se";
1560                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1561                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1562                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1563                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1564                                 dma-names = "tx", "rx";
1565                                 power-domains = <&rpmhpd SM8250_CX>;
1566                                 operating-points-v2 = <&qup_opp_table>;
1567                                 #address-cells = <1>;
1568                                 #size-cells = <0>;
1569                                 status = "disabled";
1570                         };
1571
1572                         i2c9: i2c@a84000 {
1573                                 compatible = "qcom,geni-i2c";
1574                                 reg = <0 0x00a84000 0 0x4000>;
1575                                 clock-names = "se";
1576                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1577                                 pinctrl-names = "default";
1578                                 pinctrl-0 = <&qup_i2c9_default>;
1579                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1580                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1581                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1582                                 dma-names = "tx", "rx";
1583                                 #address-cells = <1>;
1584                                 #size-cells = <0>;
1585                                 status = "disabled";
1586                         };
1587
1588                         spi9: spi@a84000 {
1589                                 compatible = "qcom,geni-spi";
1590                                 reg = <0 0x00a84000 0 0x4000>;
1591                                 clock-names = "se";
1592                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1593                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1594                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1595                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1596                                 dma-names = "tx", "rx";
1597                                 power-domains = <&rpmhpd SM8250_CX>;
1598                                 operating-points-v2 = <&qup_opp_table>;
1599                                 #address-cells = <1>;
1600                                 #size-cells = <0>;
1601                                 status = "disabled";
1602                         };
1603
1604                         i2c10: i2c@a88000 {
1605                                 compatible = "qcom,geni-i2c";
1606                                 reg = <0 0x00a88000 0 0x4000>;
1607                                 clock-names = "se";
1608                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1609                                 pinctrl-names = "default";
1610                                 pinctrl-0 = <&qup_i2c10_default>;
1611                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1612                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1613                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1614                                 dma-names = "tx", "rx";
1615                                 #address-cells = <1>;
1616                                 #size-cells = <0>;
1617                                 status = "disabled";
1618                         };
1619
1620                         spi10: spi@a88000 {
1621                                 compatible = "qcom,geni-spi";
1622                                 reg = <0 0x00a88000 0 0x4000>;
1623                                 clock-names = "se";
1624                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1625                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1626                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1627                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1628                                 dma-names = "tx", "rx";
1629                                 power-domains = <&rpmhpd SM8250_CX>;
1630                                 operating-points-v2 = <&qup_opp_table>;
1631                                 #address-cells = <1>;
1632                                 #size-cells = <0>;
1633                                 status = "disabled";
1634                         };
1635
1636                         i2c11: i2c@a8c000 {
1637                                 compatible = "qcom,geni-i2c";
1638                                 reg = <0 0x00a8c000 0 0x4000>;
1639                                 clock-names = "se";
1640                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1641                                 pinctrl-names = "default";
1642                                 pinctrl-0 = <&qup_i2c11_default>;
1643                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1644                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1645                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1646                                 dma-names = "tx", "rx";
1647                                 #address-cells = <1>;
1648                                 #size-cells = <0>;
1649                                 status = "disabled";
1650                         };
1651
1652                         spi11: spi@a8c000 {
1653                                 compatible = "qcom,geni-spi";
1654                                 reg = <0 0x00a8c000 0 0x4000>;
1655                                 clock-names = "se";
1656                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1657                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1658                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1659                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1660                                 dma-names = "tx", "rx";
1661                                 power-domains = <&rpmhpd SM8250_CX>;
1662                                 operating-points-v2 = <&qup_opp_table>;
1663                                 #address-cells = <1>;
1664                                 #size-cells = <0>;
1665                                 status = "disabled";
1666                         };
1667
1668                         i2c12: i2c@a90000 {
1669                                 compatible = "qcom,geni-i2c";
1670                                 reg = <0 0x00a90000 0 0x4000>;
1671                                 clock-names = "se";
1672                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1673                                 pinctrl-names = "default";
1674                                 pinctrl-0 = <&qup_i2c12_default>;
1675                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1676                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1677                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1678                                 dma-names = "tx", "rx";
1679                                 #address-cells = <1>;
1680                                 #size-cells = <0>;
1681                                 status = "disabled";
1682                         };
1683
1684                         spi12: spi@a90000 {
1685                                 compatible = "qcom,geni-spi";
1686                                 reg = <0 0x00a90000 0 0x4000>;
1687                                 clock-names = "se";
1688                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1689                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1690                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1691                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1692                                 dma-names = "tx", "rx";
1693                                 power-domains = <&rpmhpd SM8250_CX>;
1694                                 operating-points-v2 = <&qup_opp_table>;
1695                                 #address-cells = <1>;
1696                                 #size-cells = <0>;
1697                                 status = "disabled";
1698                         };
1699
1700                         uart12: serial@a90000 {
1701                                 compatible = "qcom,geni-debug-uart";
1702                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1703                                 clock-names = "se";
1704                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1705                                 pinctrl-names = "default";
1706                                 pinctrl-0 = <&qup_uart12_default>;
1707                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1708                                 power-domains = <&rpmhpd SM8250_CX>;
1709                                 operating-points-v2 = <&qup_opp_table>;
1710                                 status = "disabled";
1711                         };
1712
1713                         i2c13: i2c@a94000 {
1714                                 compatible = "qcom,geni-i2c";
1715                                 reg = <0 0x00a94000 0 0x4000>;
1716                                 clock-names = "se";
1717                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1718                                 pinctrl-names = "default";
1719                                 pinctrl-0 = <&qup_i2c13_default>;
1720                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1721                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1722                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1723                                 dma-names = "tx", "rx";
1724                                 #address-cells = <1>;
1725                                 #size-cells = <0>;
1726                                 status = "disabled";
1727                         };
1728
1729                         spi13: spi@a94000 {
1730                                 compatible = "qcom,geni-spi";
1731                                 reg = <0 0x00a94000 0 0x4000>;
1732                                 clock-names = "se";
1733                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1734                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1735                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1736                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1737                                 dma-names = "tx", "rx";
1738                                 power-domains = <&rpmhpd SM8250_CX>;
1739                                 operating-points-v2 = <&qup_opp_table>;
1740                                 #address-cells = <1>;
1741                                 #size-cells = <0>;
1742                                 status = "disabled";
1743                         };
1744                 };
1745
1746                 config_noc: interconnect@1500000 {
1747                         compatible = "qcom,sm8250-config-noc";
1748                         reg = <0 0x01500000 0 0xa580>;
1749                         #interconnect-cells = <1>;
1750                         qcom,bcm-voters = <&apps_bcm_voter>;
1751                 };
1752
1753                 system_noc: interconnect@1620000 {
1754                         compatible = "qcom,sm8250-system-noc";
1755                         reg = <0 0x01620000 0 0x1c200>;
1756                         #interconnect-cells = <1>;
1757                         qcom,bcm-voters = <&apps_bcm_voter>;
1758                 };
1759
1760                 mc_virt: interconnect@163d000 {
1761                         compatible = "qcom,sm8250-mc-virt";
1762                         reg = <0 0x0163d000 0 0x1000>;
1763                         #interconnect-cells = <1>;
1764                         qcom,bcm-voters = <&apps_bcm_voter>;
1765                 };
1766
1767                 aggre1_noc: interconnect@16e0000 {
1768                         compatible = "qcom,sm8250-aggre1-noc";
1769                         reg = <0 0x016e0000 0 0x1f180>;
1770                         #interconnect-cells = <1>;
1771                         qcom,bcm-voters = <&apps_bcm_voter>;
1772                 };
1773
1774                 aggre2_noc: interconnect@1700000 {
1775                         compatible = "qcom,sm8250-aggre2-noc";
1776                         reg = <0 0x01700000 0 0x33000>;
1777                         #interconnect-cells = <1>;
1778                         qcom,bcm-voters = <&apps_bcm_voter>;
1779                 };
1780
1781                 compute_noc: interconnect@1733000 {
1782                         compatible = "qcom,sm8250-compute-noc";
1783                         reg = <0 0x01733000 0 0xa180>;
1784                         #interconnect-cells = <1>;
1785                         qcom,bcm-voters = <&apps_bcm_voter>;
1786                 };
1787
1788                 mmss_noc: interconnect@1740000 {
1789                         compatible = "qcom,sm8250-mmss-noc";
1790                         reg = <0 0x01740000 0 0x1f080>;
1791                         #interconnect-cells = <1>;
1792                         qcom,bcm-voters = <&apps_bcm_voter>;
1793                 };
1794
1795                 pcie0: pci@1c00000 {
1796                         compatible = "qcom,pcie-sm8250";
1797                         reg = <0 0x01c00000 0 0x3000>,
1798                               <0 0x60000000 0 0xf1d>,
1799                               <0 0x60000f20 0 0xa8>,
1800                               <0 0x60001000 0 0x1000>,
1801                               <0 0x60100000 0 0x100000>;
1802                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1803                         device_type = "pci";
1804                         linux,pci-domain = <0>;
1805                         bus-range = <0x00 0xff>;
1806                         num-lanes = <1>;
1807
1808                         #address-cells = <3>;
1809                         #size-cells = <2>;
1810
1811                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1812                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1813
1814                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1815                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1816                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1817                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1818                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1819                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1820                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1821                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1822                         interrupt-names = "msi0", "msi1", "msi2", "msi3",
1823                                           "msi4", "msi5", "msi6", "msi7";
1824                         #interrupt-cells = <1>;
1825                         interrupt-map-mask = <0 0 0 0x7>;
1826                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1827                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1828                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1829                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1830
1831                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1832                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1833                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1834                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1835                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1836                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1837                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1838                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1839                         clock-names = "pipe",
1840                                       "aux",
1841                                       "cfg",
1842                                       "bus_master",
1843                                       "bus_slave",
1844                                       "slave_q2a",
1845                                       "tbu",
1846                                       "ddrss_sf_tbu";
1847
1848                         iommus = <&apps_smmu 0x1c00 0x7f>;
1849                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
1850                                     <0x100 &apps_smmu 0x1c01 0x1>;
1851
1852                         resets = <&gcc GCC_PCIE_0_BCR>;
1853                         reset-names = "pci";
1854
1855                         power-domains = <&gcc PCIE_0_GDSC>;
1856
1857                         phys = <&pcie0_lane>;
1858                         phy-names = "pciephy";
1859
1860                         perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1861                         wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1862
1863                         pinctrl-names = "default";
1864                         pinctrl-0 = <&pcie0_default_state>;
1865                         dma-coherent;
1866
1867                         status = "disabled";
1868                 };
1869
1870                 pcie0_phy: phy@1c06000 {
1871                         compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1872                         reg = <0 0x01c06000 0 0x1c0>;
1873                         #address-cells = <2>;
1874                         #size-cells = <2>;
1875                         ranges;
1876                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1877                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1878                                  <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
1879                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1880                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1881
1882                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1883                         reset-names = "phy";
1884
1885                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1886                         assigned-clock-rates = <100000000>;
1887
1888                         status = "disabled";
1889
1890                         pcie0_lane: phy@1c06200 {
1891                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1892                                       <0 0x1c06400 0 0x200>, /* rx */
1893                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1894                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1895                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1896                                 clock-names = "pipe0";
1897
1898                                 #phy-cells = <0>;
1899
1900                                 #clock-cells = <0>;
1901                                 clock-output-names = "pcie_0_pipe_clk";
1902                         };
1903                 };
1904
1905                 pcie1: pci@1c08000 {
1906                         compatible = "qcom,pcie-sm8250";
1907                         reg = <0 0x01c08000 0 0x3000>,
1908                               <0 0x40000000 0 0xf1d>,
1909                               <0 0x40000f20 0 0xa8>,
1910                               <0 0x40001000 0 0x1000>,
1911                               <0 0x40100000 0 0x100000>;
1912                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1913                         device_type = "pci";
1914                         linux,pci-domain = <1>;
1915                         bus-range = <0x00 0xff>;
1916                         num-lanes = <2>;
1917
1918                         #address-cells = <3>;
1919                         #size-cells = <2>;
1920
1921                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1922                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1923
1924                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1925                         interrupt-names = "msi";
1926                         #interrupt-cells = <1>;
1927                         interrupt-map-mask = <0 0 0 0x7>;
1928                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1929                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1930                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1931                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1932
1933                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1934                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1935                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1936                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1937                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1938                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1939                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1940                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1941                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
1942                         clock-names = "pipe",
1943                                       "aux",
1944                                       "cfg",
1945                                       "bus_master",
1946                                       "bus_slave",
1947                                       "slave_q2a",
1948                                       "ref",
1949                                       "tbu",
1950                                       "ddrss_sf_tbu";
1951
1952                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1953                         assigned-clock-rates = <19200000>;
1954
1955                         iommus = <&apps_smmu 0x1c80 0x7f>;
1956                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1957                                     <0x100 &apps_smmu 0x1c81 0x1>;
1958
1959                         resets = <&gcc GCC_PCIE_1_BCR>;
1960                         reset-names = "pci";
1961
1962                         power-domains = <&gcc PCIE_1_GDSC>;
1963
1964                         phys = <&pcie1_lane>;
1965                         phy-names = "pciephy";
1966
1967                         perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
1968                         wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
1969
1970                         pinctrl-names = "default";
1971                         pinctrl-0 = <&pcie1_default_state>;
1972                         dma-coherent;
1973
1974                         status = "disabled";
1975                 };
1976
1977                 pcie1_phy: phy@1c0e000 {
1978                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
1979                         reg = <0 0x01c0e000 0 0x1c0>;
1980                         #address-cells = <2>;
1981                         #size-cells = <2>;
1982                         ranges;
1983                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1984                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1985                                  <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
1986                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1987                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1988
1989                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1990                         reset-names = "phy";
1991
1992                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1993                         assigned-clock-rates = <100000000>;
1994
1995                         status = "disabled";
1996
1997                         pcie1_lane: phy@1c0e200 {
1998                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1999                                       <0 0x1c0e400 0 0x200>, /* rx0 */
2000                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
2001                                       <0 0x1c0e600 0 0x170>, /* tx1 */
2002                                       <0 0x1c0e800 0 0x200>, /* rx1 */
2003                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2004                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2005                                 clock-names = "pipe0";
2006
2007                                 #phy-cells = <0>;
2008
2009                                 #clock-cells = <0>;
2010                                 clock-output-names = "pcie_1_pipe_clk";
2011                         };
2012                 };
2013
2014                 pcie2: pci@1c10000 {
2015                         compatible = "qcom,pcie-sm8250";
2016                         reg = <0 0x01c10000 0 0x3000>,
2017                               <0 0x64000000 0 0xf1d>,
2018                               <0 0x64000f20 0 0xa8>,
2019                               <0 0x64001000 0 0x1000>,
2020                               <0 0x64100000 0 0x100000>;
2021                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2022                         device_type = "pci";
2023                         linux,pci-domain = <2>;
2024                         bus-range = <0x00 0xff>;
2025                         num-lanes = <2>;
2026
2027                         #address-cells = <3>;
2028                         #size-cells = <2>;
2029
2030                         ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2031                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2032
2033                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2034                         interrupt-names = "msi";
2035                         #interrupt-cells = <1>;
2036                         interrupt-map-mask = <0 0 0 0x7>;
2037                         interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2038                                         <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2039                                         <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2040                                         <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2041
2042                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2043                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2044                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2045                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2046                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2047                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2048                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2049                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2050                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2051                         clock-names = "pipe",
2052                                       "aux",
2053                                       "cfg",
2054                                       "bus_master",
2055                                       "bus_slave",
2056                                       "slave_q2a",
2057                                       "ref",
2058                                       "tbu",
2059                                       "ddrss_sf_tbu";
2060
2061                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2062                         assigned-clock-rates = <19200000>;
2063
2064                         iommus = <&apps_smmu 0x1d00 0x7f>;
2065                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2066                                     <0x100 &apps_smmu 0x1d01 0x1>;
2067
2068                         resets = <&gcc GCC_PCIE_2_BCR>;
2069                         reset-names = "pci";
2070
2071                         power-domains = <&gcc PCIE_2_GDSC>;
2072
2073                         phys = <&pcie2_lane>;
2074                         phy-names = "pciephy";
2075
2076                         perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2077                         wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2078
2079                         pinctrl-names = "default";
2080                         pinctrl-0 = <&pcie2_default_state>;
2081                         dma-coherent;
2082
2083                         status = "disabled";
2084                 };
2085
2086                 pcie2_phy: phy@1c16000 {
2087                         compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2088                         reg = <0 0x1c16000 0 0x1c0>;
2089                         #address-cells = <2>;
2090                         #size-cells = <2>;
2091                         ranges;
2092                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2093                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2094                                  <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2095                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2096                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2097
2098                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2099                         reset-names = "phy";
2100
2101                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2102                         assigned-clock-rates = <100000000>;
2103
2104                         status = "disabled";
2105
2106                         pcie2_lane: phy@1c16200 {
2107                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
2108                                       <0 0x1c16400 0 0x200>, /* rx0 */
2109                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
2110                                       <0 0x1c16600 0 0x170>, /* tx1 */
2111                                       <0 0x1c16800 0 0x200>, /* rx1 */
2112                                       <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
2113                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2114                                 clock-names = "pipe0";
2115
2116                                 #phy-cells = <0>;
2117
2118                                 #clock-cells = <0>;
2119                                 clock-output-names = "pcie_2_pipe_clk";
2120                         };
2121                 };
2122
2123                 ufs_mem_hc: ufshc@1d84000 {
2124                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2125                                      "jedec,ufs-2.0";
2126                         reg = <0 0x01d84000 0 0x3000>;
2127                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2128                         phys = <&ufs_mem_phy_lanes>;
2129                         phy-names = "ufsphy";
2130                         lanes-per-direction = <2>;
2131                         #reset-cells = <1>;
2132                         resets = <&gcc GCC_UFS_PHY_BCR>;
2133                         reset-names = "rst";
2134
2135                         power-domains = <&gcc UFS_PHY_GDSC>;
2136
2137                         iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2138
2139                         clock-names =
2140                                 "core_clk",
2141                                 "bus_aggr_clk",
2142                                 "iface_clk",
2143                                 "core_clk_unipro",
2144                                 "ref_clk",
2145                                 "tx_lane0_sync_clk",
2146                                 "rx_lane0_sync_clk",
2147                                 "rx_lane1_sync_clk";
2148                         clocks =
2149                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2150                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2151                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2152                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2153                                 <&rpmhcc RPMH_CXO_CLK>,
2154                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2155                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2156                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2157                         freq-table-hz =
2158                                 <37500000 300000000>,
2159                                 <0 0>,
2160                                 <0 0>,
2161                                 <37500000 300000000>,
2162                                 <0 0>,
2163                                 <0 0>,
2164                                 <0 0>,
2165                                 <0 0>;
2166
2167                         status = "disabled";
2168                 };
2169
2170                 ufs_mem_phy: phy@1d87000 {
2171                         compatible = "qcom,sm8250-qmp-ufs-phy";
2172                         reg = <0 0x01d87000 0 0x1c0>;
2173                         #address-cells = <2>;
2174                         #size-cells = <2>;
2175                         ranges;
2176                         clock-names = "ref",
2177                                       "ref_aux";
2178                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2179                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2180
2181                         resets = <&ufs_mem_hc 0>;
2182                         reset-names = "ufsphy";
2183                         status = "disabled";
2184
2185                         ufs_mem_phy_lanes: phy@1d87400 {
2186                                 reg = <0 0x01d87400 0 0x16c>,
2187                                       <0 0x01d87600 0 0x200>,
2188                                       <0 0x01d87c00 0 0x200>,
2189                                       <0 0x01d87800 0 0x16c>,
2190                                       <0 0x01d87a00 0 0x200>;
2191                                 #phy-cells = <0>;
2192                         };
2193                 };
2194
2195                 ipa_virt: interconnect@1e00000 {
2196                         compatible = "qcom,sm8250-ipa-virt";
2197                         reg = <0 0x01e00000 0 0x1000>;
2198                         #interconnect-cells = <1>;
2199                         qcom,bcm-voters = <&apps_bcm_voter>;
2200                 };
2201
2202                 tcsr_mutex: hwlock@1f40000 {
2203                         compatible = "qcom,tcsr-mutex";
2204                         reg = <0x0 0x01f40000 0x0 0x40000>;
2205                         #hwlock-cells = <1>;
2206                 };
2207
2208                 wsamacro: codec@3240000 {
2209                         compatible = "qcom,sm8250-lpass-wsa-macro";
2210                         reg = <0 0x03240000 0 0x1000>;
2211                         clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2212                                  <&audiocc LPASS_CDC_WSA_NPL>,
2213                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2214                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2215                                  <&aoncc LPASS_CDC_VA_MCLK>,
2216                                  <&vamacro>;
2217
2218                         clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2219
2220                         #clock-cells = <0>;
2221                         clock-frequency = <9600000>;
2222                         clock-output-names = "mclk";
2223                         #sound-dai-cells = <1>;
2224
2225                         pinctrl-names = "default";
2226                         pinctrl-0 = <&wsa_swr_active>;
2227                 };
2228
2229                 swr0: soundwire-controller@3250000 {
2230                         reg = <0 0x03250000 0 0x2000>;
2231                         compatible = "qcom,soundwire-v1.5.1";
2232                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2233                         clocks = <&wsamacro>;
2234                         clock-names = "iface";
2235
2236                         qcom,din-ports = <2>;
2237                         qcom,dout-ports = <6>;
2238
2239                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2240                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2241                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2242                         qcom,ports-block-pack-mode =    /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2243
2244                         #sound-dai-cells = <1>;
2245                         #address-cells = <2>;
2246                         #size-cells = <0>;
2247                 };
2248
2249                 audiocc: clock-controller@3300000 {
2250                         compatible = "qcom,sm8250-lpass-audiocc";
2251                         reg = <0 0x03300000 0 0x30000>;
2252                         #clock-cells = <1>;
2253                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2254                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2255                                 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2256                         clock-names = "core", "audio", "bus";
2257                 };
2258
2259                 vamacro: codec@3370000 {
2260                         compatible = "qcom,sm8250-lpass-va-macro";
2261                         reg = <0 0x03370000 0 0x1000>;
2262                         clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2263                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2264                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2265
2266                         clock-names = "mclk", "macro", "dcodec";
2267
2268                         #clock-cells = <0>;
2269                         clock-frequency = <9600000>;
2270                         clock-output-names = "fsgen";
2271                         #sound-dai-cells = <1>;
2272                 };
2273
2274                 rxmacro: rxmacro@3200000 {
2275                         pinctrl-names = "default";
2276                         pinctrl-0 = <&rx_swr_active>;
2277                         compatible = "qcom,sm8250-lpass-rx-macro";
2278                         reg = <0 0x3200000 0 0x1000>;
2279                         status = "disabled";
2280
2281                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2282                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2283                                 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2284                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2285                                 <&vamacro>;
2286
2287                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2288
2289                         #clock-cells = <0>;
2290                         clock-frequency = <9600000>;
2291                         clock-output-names = "mclk";
2292                         #sound-dai-cells = <1>;
2293                 };
2294
2295                 swr1: soundwire-controller@3210000 {
2296                         reg = <0 0x3210000 0 0x2000>;
2297                         compatible = "qcom,soundwire-v1.5.1";
2298                         status = "disabled";
2299                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2300                         clocks = <&rxmacro>;
2301                         clock-names = "iface";
2302                         label = "RX";
2303                         qcom,din-ports = <0>;
2304                         qcom,dout-ports = <5>;
2305
2306                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2307                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2308                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2309                         qcom,ports-hstart =             /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2310                         qcom,ports-hstop =              /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2311                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2312                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2313                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2314                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2315
2316                         #sound-dai-cells = <1>;
2317                         #address-cells = <2>;
2318                         #size-cells = <0>;
2319                 };
2320
2321                 txmacro: txmacro@3220000 {
2322                         pinctrl-names = "default";
2323                         pinctrl-0 = <&tx_swr_active>;
2324                         compatible = "qcom,sm8250-lpass-tx-macro";
2325                         reg = <0 0x3220000 0 0x1000>;
2326                         status = "disabled";
2327
2328                         clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2329                                  <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2330                                  <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2331                                  <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2332                                  <&vamacro>;
2333
2334                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2335
2336                         #clock-cells = <0>;
2337                         clock-frequency = <9600000>;
2338                         clock-output-names = "mclk";
2339                         #address-cells = <2>;
2340                         #size-cells = <2>;
2341                         #sound-dai-cells = <1>;
2342                 };
2343
2344                 /* tx macro */
2345                 swr2: soundwire-controller@3230000 {
2346                         reg = <0 0x3230000 0 0x2000>;
2347                         compatible = "qcom,soundwire-v1.5.1";
2348                         interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2349                         interrupt-names = "core";
2350                         status = "disabled";
2351
2352                         clocks = <&txmacro>;
2353                         clock-names = "iface";
2354                         label = "TX";
2355
2356                         qcom,din-ports = <5>;
2357                         qcom,dout-ports = <0>;
2358                         qcom,ports-sinterval-low =      /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2359                         qcom,ports-offset1 =            /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2360                         qcom,ports-offset2 =            /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2361                         qcom,ports-block-pack-mode =    /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2362                         qcom,ports-hstart =             /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2363                         qcom,ports-hstop =              /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2364                         qcom,ports-word-length =        /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2365                         qcom,ports-block-group-count =  /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2366                         qcom,ports-lane-control =       /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2367                         qcom,port-offset = <1>;
2368                         #sound-dai-cells = <1>;
2369                         #address-cells = <2>;
2370                         #size-cells = <0>;
2371                 };
2372
2373                 aoncc: clock-controller@3380000 {
2374                         compatible = "qcom,sm8250-lpass-aoncc";
2375                         reg = <0 0x03380000 0 0x40000>;
2376                         #clock-cells = <1>;
2377                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2378                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2379                                 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2380                         clock-names = "core", "audio", "bus";
2381                 };
2382
2383                 lpass_tlmm: pinctrl@33c0000{
2384                         compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2385                         reg = <0 0x033c0000 0x0 0x20000>,
2386                               <0 0x03550000 0x0 0x10000>;
2387                         gpio-controller;
2388                         #gpio-cells = <2>;
2389                         gpio-ranges = <&lpass_tlmm 0 0 14>;
2390
2391                         clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2392                                 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2393                         clock-names = "core", "audio";
2394
2395                         wsa_swr_active: wsa-swr-active-pins {
2396                                 clk {
2397                                         pins = "gpio10";
2398                                         function = "wsa_swr_clk";
2399                                         drive-strength = <2>;
2400                                         slew-rate = <1>;
2401                                         bias-disable;
2402                                 };
2403
2404                                 data {
2405                                         pins = "gpio11";
2406                                         function = "wsa_swr_data";
2407                                         drive-strength = <2>;
2408                                         slew-rate = <1>;
2409                                         bias-bus-hold;
2410
2411                                 };
2412                         };
2413
2414                         wsa_swr_sleep: wsa-swr-sleep-pins {
2415                                 clk {
2416                                         pins = "gpio10";
2417                                         function = "wsa_swr_clk";
2418                                         drive-strength = <2>;
2419                                         input-enable;
2420                                         bias-pull-down;
2421                                 };
2422
2423                                 data {
2424                                         pins = "gpio11";
2425                                         function = "wsa_swr_data";
2426                                         drive-strength = <2>;
2427                                         input-enable;
2428                                         bias-pull-down;
2429
2430                                 };
2431                         };
2432
2433                         dmic01_active: dmic01-active-pins {
2434                                 clk {
2435                                         pins = "gpio6";
2436                                         function = "dmic1_clk";
2437                                         drive-strength = <8>;
2438                                         output-high;
2439                                 };
2440                                 data {
2441                                         pins = "gpio7";
2442                                         function = "dmic1_data";
2443                                         drive-strength = <8>;
2444                                         input-enable;
2445                                 };
2446                         };
2447
2448                         dmic01_sleep: dmic01-sleep-pins {
2449                                 clk {
2450                                         pins = "gpio6";
2451                                         function = "dmic1_clk";
2452                                         drive-strength = <2>;
2453                                         bias-disable;
2454                                         output-low;
2455                                 };
2456
2457                                 data {
2458                                         pins = "gpio7";
2459                                         function = "dmic1_data";
2460                                         drive-strength = <2>;
2461                                         bias-pull-down;
2462                                         input-enable;
2463                                 };
2464                         };
2465
2466                         rx_swr_active: rx_swr-active-pins {
2467                                 clk {
2468                                         pins = "gpio3";
2469                                         function = "swr_rx_clk";
2470                                         drive-strength = <2>;
2471                                         slew-rate = <1>;
2472                                         bias-disable;
2473                                 };
2474
2475                                 data {
2476                                         pins = "gpio4", "gpio5";
2477                                         function = "swr_rx_data";
2478                                         drive-strength = <2>;
2479                                         slew-rate = <1>;
2480                                         bias-bus-hold;
2481                                 };
2482                         };
2483
2484                         tx_swr_active: tx_swr-active-pins {
2485                                 clk {
2486                                         pins = "gpio0";
2487                                         function = "swr_tx_clk";
2488                                         drive-strength = <2>;
2489                                         slew-rate = <1>;
2490                                         bias-disable;
2491                                 };
2492
2493                                 data {
2494                                         pins = "gpio1", "gpio2";
2495                                         function = "swr_tx_data";
2496                                         drive-strength = <2>;
2497                                         slew-rate = <1>;
2498                                         bias-bus-hold;
2499                                 };
2500                         };
2501
2502                         tx_swr_sleep: tx_swr-sleep-pins {
2503                                 clk {
2504                                         pins = "gpio0";
2505                                         function = "swr_tx_clk";
2506                                         drive-strength = <2>;
2507                                         input-enable;
2508                                         bias-pull-down;
2509                                 };
2510
2511                                 data1 {
2512                                         pins = "gpio1";
2513                                         function = "swr_tx_data";
2514                                         drive-strength = <2>;
2515                                         input-enable;
2516                                         bias-bus-hold;
2517                                 };
2518
2519                                 data2 {
2520                                         pins = "gpio2";
2521                                         function = "swr_tx_data";
2522                                         drive-strength = <2>;
2523                                         input-enable;
2524                                         bias-pull-down;
2525                                 };
2526                         };
2527                 };
2528
2529                 gpu: gpu@3d00000 {
2530                         compatible = "qcom,adreno-650.2",
2531                                      "qcom,adreno";
2532
2533                         reg = <0 0x03d00000 0 0x40000>;
2534                         reg-names = "kgsl_3d0_reg_memory";
2535
2536                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2537
2538                         iommus = <&adreno_smmu 0 0x401>;
2539
2540                         operating-points-v2 = <&gpu_opp_table>;
2541
2542                         qcom,gmu = <&gmu>;
2543
2544                         status = "disabled";
2545
2546                         zap-shader {
2547                                 memory-region = <&gpu_mem>;
2548                         };
2549
2550                         /* note: downstream checks gpu binning for 670 Mhz */
2551                         gpu_opp_table: opp-table {
2552                                 compatible = "operating-points-v2";
2553
2554                                 opp-670000000 {
2555                                         opp-hz = /bits/ 64 <670000000>;
2556                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2557                                 };
2558
2559                                 opp-587000000 {
2560                                         opp-hz = /bits/ 64 <587000000>;
2561                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2562                                 };
2563
2564                                 opp-525000000 {
2565                                         opp-hz = /bits/ 64 <525000000>;
2566                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2567                                 };
2568
2569                                 opp-490000000 {
2570                                         opp-hz = /bits/ 64 <490000000>;
2571                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2572                                 };
2573
2574                                 opp-441600000 {
2575                                         opp-hz = /bits/ 64 <441600000>;
2576                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2577                                 };
2578
2579                                 opp-400000000 {
2580                                         opp-hz = /bits/ 64 <400000000>;
2581                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2582                                 };
2583
2584                                 opp-305000000 {
2585                                         opp-hz = /bits/ 64 <305000000>;
2586                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2587                                 };
2588                         };
2589                 };
2590
2591                 gmu: gmu@3d6a000 {
2592                         compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2593
2594                         reg = <0 0x03d6a000 0 0x30000>,
2595                               <0 0x3de0000 0 0x10000>,
2596                               <0 0xb290000 0 0x10000>,
2597                               <0 0xb490000 0 0x10000>;
2598                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2599
2600                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2601                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2602                         interrupt-names = "hfi", "gmu";
2603
2604                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2605                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2606                                  <&gpucc GPU_CC_CXO_CLK>,
2607                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2608                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2609                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2610
2611                         power-domains = <&gpucc GPU_CX_GDSC>,
2612                                         <&gpucc GPU_GX_GDSC>;
2613                         power-domain-names = "cx", "gx";
2614
2615                         iommus = <&adreno_smmu 5 0x400>;
2616
2617                         operating-points-v2 = <&gmu_opp_table>;
2618
2619                         status = "disabled";
2620
2621                         gmu_opp_table: opp-table {
2622                                 compatible = "operating-points-v2";
2623
2624                                 opp-200000000 {
2625                                         opp-hz = /bits/ 64 <200000000>;
2626                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2627                                 };
2628                         };
2629                 };
2630
2631                 gpucc: clock-controller@3d90000 {
2632                         compatible = "qcom,sm8250-gpucc";
2633                         reg = <0 0x03d90000 0 0x9000>;
2634                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2635                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2636                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2637                         clock-names = "bi_tcxo",
2638                                       "gcc_gpu_gpll0_clk_src",
2639                                       "gcc_gpu_gpll0_div_clk_src";
2640                         #clock-cells = <1>;
2641                         #reset-cells = <1>;
2642                         #power-domain-cells = <1>;
2643                 };
2644
2645                 adreno_smmu: iommu@3da0000 {
2646                         compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2647                         reg = <0 0x03da0000 0 0x10000>;
2648                         #iommu-cells = <2>;
2649                         #global-interrupts = <2>;
2650                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2651                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2652                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2653                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2654                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2655                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2656                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2657                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2658                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2659                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
2660                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2661                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2662                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2663                         clock-names = "ahb", "bus", "iface";
2664
2665                         power-domains = <&gpucc GPU_CX_GDSC>;
2666                 };
2667
2668                 slpi: remoteproc@5c00000 {
2669                         compatible = "qcom,sm8250-slpi-pas";
2670                         reg = <0 0x05c00000 0 0x4000>;
2671
2672                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2673                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2674                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2675                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2676                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2677                         interrupt-names = "wdog", "fatal", "ready",
2678                                           "handover", "stop-ack";
2679
2680                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2681                         clock-names = "xo";
2682
2683                         power-domains = <&rpmhpd SM8250_LCX>,
2684                                         <&rpmhpd SM8250_LMX>;
2685                         power-domain-names = "lcx", "lmx";
2686
2687                         memory-region = <&slpi_mem>;
2688
2689                         qcom,qmp = <&aoss_qmp>;
2690
2691                         qcom,smem-states = <&smp2p_slpi_out 0>;
2692                         qcom,smem-state-names = "stop";
2693
2694                         status = "disabled";
2695
2696                         glink-edge {
2697                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2698                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2699                                                              IRQ_TYPE_EDGE_RISING>;
2700                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2701                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2702
2703                                 label = "slpi";
2704                                 qcom,remote-pid = <3>;
2705
2706                                 fastrpc {
2707                                         compatible = "qcom,fastrpc";
2708                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2709                                         label = "sdsp";
2710                                         qcom,non-secure-domain;
2711                                         #address-cells = <1>;
2712                                         #size-cells = <0>;
2713
2714                                         compute-cb@1 {
2715                                                 compatible = "qcom,fastrpc-compute-cb";
2716                                                 reg = <1>;
2717                                                 iommus = <&apps_smmu 0x0541 0x0>;
2718                                         };
2719
2720                                         compute-cb@2 {
2721                                                 compatible = "qcom,fastrpc-compute-cb";
2722                                                 reg = <2>;
2723                                                 iommus = <&apps_smmu 0x0542 0x0>;
2724                                         };
2725
2726                                         compute-cb@3 {
2727                                                 compatible = "qcom,fastrpc-compute-cb";
2728                                                 reg = <3>;
2729                                                 iommus = <&apps_smmu 0x0543 0x0>;
2730                                                 /* note: shared-cb = <4> in downstream */
2731                                         };
2732                                 };
2733                         };
2734                 };
2735
2736                 cdsp: remoteproc@8300000 {
2737                         compatible = "qcom,sm8250-cdsp-pas";
2738                         reg = <0 0x08300000 0 0x10000>;
2739
2740                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2741                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2742                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2743                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2744                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2745                         interrupt-names = "wdog", "fatal", "ready",
2746                                           "handover", "stop-ack";
2747
2748                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2749                         clock-names = "xo";
2750
2751                         power-domains = <&rpmhpd SM8250_CX>;
2752
2753                         memory-region = <&cdsp_mem>;
2754
2755                         qcom,qmp = <&aoss_qmp>;
2756
2757                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2758                         qcom,smem-state-names = "stop";
2759
2760                         status = "disabled";
2761
2762                         glink-edge {
2763                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2764                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2765                                                              IRQ_TYPE_EDGE_RISING>;
2766                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2767                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2768
2769                                 label = "cdsp";
2770                                 qcom,remote-pid = <5>;
2771
2772                                 fastrpc {
2773                                         compatible = "qcom,fastrpc";
2774                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2775                                         label = "cdsp";
2776                                         qcom,non-secure-domain;
2777                                         #address-cells = <1>;
2778                                         #size-cells = <0>;
2779
2780                                         compute-cb@1 {
2781                                                 compatible = "qcom,fastrpc-compute-cb";
2782                                                 reg = <1>;
2783                                                 iommus = <&apps_smmu 0x1001 0x0460>;
2784                                         };
2785
2786                                         compute-cb@2 {
2787                                                 compatible = "qcom,fastrpc-compute-cb";
2788                                                 reg = <2>;
2789                                                 iommus = <&apps_smmu 0x1002 0x0460>;
2790                                         };
2791
2792                                         compute-cb@3 {
2793                                                 compatible = "qcom,fastrpc-compute-cb";
2794                                                 reg = <3>;
2795                                                 iommus = <&apps_smmu 0x1003 0x0460>;
2796                                         };
2797
2798                                         compute-cb@4 {
2799                                                 compatible = "qcom,fastrpc-compute-cb";
2800                                                 reg = <4>;
2801                                                 iommus = <&apps_smmu 0x1004 0x0460>;
2802                                         };
2803
2804                                         compute-cb@5 {
2805                                                 compatible = "qcom,fastrpc-compute-cb";
2806                                                 reg = <5>;
2807                                                 iommus = <&apps_smmu 0x1005 0x0460>;
2808                                         };
2809
2810                                         compute-cb@6 {
2811                                                 compatible = "qcom,fastrpc-compute-cb";
2812                                                 reg = <6>;
2813                                                 iommus = <&apps_smmu 0x1006 0x0460>;
2814                                         };
2815
2816                                         compute-cb@7 {
2817                                                 compatible = "qcom,fastrpc-compute-cb";
2818                                                 reg = <7>;
2819                                                 iommus = <&apps_smmu 0x1007 0x0460>;
2820                                         };
2821
2822                                         compute-cb@8 {
2823                                                 compatible = "qcom,fastrpc-compute-cb";
2824                                                 reg = <8>;
2825                                                 iommus = <&apps_smmu 0x1008 0x0460>;
2826                                         };
2827
2828                                         /* note: secure cb9 in downstream */
2829                                 };
2830                         };
2831                 };
2832
2833                 sound: sound {
2834                 };
2835
2836                 usb_1_hsphy: phy@88e3000 {
2837                         compatible = "qcom,sm8250-usb-hs-phy",
2838                                      "qcom,usb-snps-hs-7nm-phy";
2839                         reg = <0 0x088e3000 0 0x400>;
2840                         status = "disabled";
2841                         #phy-cells = <0>;
2842
2843                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2844                         clock-names = "ref";
2845
2846                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2847                 };
2848
2849                 usb_2_hsphy: phy@88e4000 {
2850                         compatible = "qcom,sm8250-usb-hs-phy",
2851                                      "qcom,usb-snps-hs-7nm-phy";
2852                         reg = <0 0x088e4000 0 0x400>;
2853                         status = "disabled";
2854                         #phy-cells = <0>;
2855
2856                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2857                         clock-names = "ref";
2858
2859                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2860                 };
2861
2862                 usb_1_qmpphy: phy@88e9000 {
2863                         compatible = "qcom,sm8250-qmp-usb3-dp-phy";
2864                         reg = <0 0x088e9000 0 0x200>,
2865                               <0 0x088e8000 0 0x40>,
2866                               <0 0x088ea000 0 0x200>;
2867                         status = "disabled";
2868                         #address-cells = <2>;
2869                         #size-cells = <2>;
2870                         ranges;
2871
2872                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2873                                  <&rpmhcc RPMH_CXO_CLK>,
2874                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2875                         clock-names = "aux", "ref_clk_src", "com_aux";
2876
2877                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2878                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2879                         reset-names = "phy", "common";
2880
2881                         usb_1_ssphy: usb3-phy@88e9200 {
2882                                 reg = <0 0x088e9200 0 0x200>,
2883                                       <0 0x088e9400 0 0x200>,
2884                                       <0 0x088e9c00 0 0x400>,
2885                                       <0 0x088e9600 0 0x200>,
2886                                       <0 0x088e9800 0 0x200>,
2887                                       <0 0x088e9a00 0 0x100>;
2888                                 #clock-cells = <0>;
2889                                 #phy-cells = <0>;
2890                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2891                                 clock-names = "pipe0";
2892                                 clock-output-names = "usb3_phy_pipe_clk_src";
2893                         };
2894
2895                         dp_phy: dp-phy@88ea200 {
2896                                 reg = <0 0x088ea200 0 0x200>,
2897                                       <0 0x088ea400 0 0x200>,
2898                                       <0 0x088eaa00 0 0x200>,
2899                                       <0 0x088ea600 0 0x200>,
2900                                       <0 0x088ea800 0 0x200>;
2901                                 #phy-cells = <0>;
2902                                 #clock-cells = <1>;
2903                         };
2904                 };
2905
2906                 usb_2_qmpphy: phy@88eb000 {
2907                         compatible = "qcom,sm8250-qmp-usb3-uni-phy";
2908                         reg = <0 0x088eb000 0 0x200>;
2909                         status = "disabled";
2910                         #address-cells = <2>;
2911                         #size-cells = <2>;
2912                         ranges;
2913
2914                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2915                                  <&rpmhcc RPMH_CXO_CLK>,
2916                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2917                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2918                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2919
2920                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2921                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2922                         reset-names = "phy", "common";
2923
2924                         usb_2_ssphy: phy@88eb200 {
2925                                 reg = <0 0x088eb200 0 0x200>,
2926                                       <0 0x088eb400 0 0x200>,
2927                                       <0 0x088eb800 0 0x800>;
2928                                 #clock-cells = <0>;
2929                                 #phy-cells = <0>;
2930                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2931                                 clock-names = "pipe0";
2932                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2933                         };
2934                 };
2935
2936                 sdhc_2: mmc@8804000 {
2937                         compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
2938                         reg = <0 0x08804000 0 0x1000>;
2939
2940                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2941                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2942                         interrupt-names = "hc_irq", "pwr_irq";
2943
2944                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2945                                  <&gcc GCC_SDCC2_APPS_CLK>,
2946                                  <&rpmhcc RPMH_CXO_CLK>;
2947                         clock-names = "iface", "core", "xo";
2948                         iommus = <&apps_smmu 0x4a0 0x0>;
2949                         qcom,dll-config = <0x0007642c>;
2950                         qcom,ddr-config = <0x80040868>;
2951                         power-domains = <&rpmhpd SM8250_CX>;
2952                         operating-points-v2 = <&sdhc2_opp_table>;
2953
2954                         status = "disabled";
2955
2956                         sdhc2_opp_table: opp-table {
2957                                 compatible = "operating-points-v2";
2958
2959                                 opp-19200000 {
2960                                         opp-hz = /bits/ 64 <19200000>;
2961                                         required-opps = <&rpmhpd_opp_min_svs>;
2962                                 };
2963
2964                                 opp-50000000 {
2965                                         opp-hz = /bits/ 64 <50000000>;
2966                                         required-opps = <&rpmhpd_opp_low_svs>;
2967                                 };
2968
2969                                 opp-100000000 {
2970                                         opp-hz = /bits/ 64 <100000000>;
2971                                         required-opps = <&rpmhpd_opp_svs>;
2972                                 };
2973
2974                                 opp-202000000 {
2975                                         opp-hz = /bits/ 64 <202000000>;
2976                                         required-opps = <&rpmhpd_opp_svs_l1>;
2977                                 };
2978                         };
2979                 };
2980
2981                 dc_noc: interconnect@90c0000 {
2982                         compatible = "qcom,sm8250-dc-noc";
2983                         reg = <0 0x090c0000 0 0x4200>;
2984                         #interconnect-cells = <1>;
2985                         qcom,bcm-voters = <&apps_bcm_voter>;
2986                 };
2987
2988                 gem_noc: interconnect@9100000 {
2989                         compatible = "qcom,sm8250-gem-noc";
2990                         reg = <0 0x09100000 0 0xb4000>;
2991                         #interconnect-cells = <1>;
2992                         qcom,bcm-voters = <&apps_bcm_voter>;
2993                 };
2994
2995                 npu_noc: interconnect@9990000 {
2996                         compatible = "qcom,sm8250-npu-noc";
2997                         reg = <0 0x09990000 0 0x1600>;
2998                         #interconnect-cells = <1>;
2999                         qcom,bcm-voters = <&apps_bcm_voter>;
3000                 };
3001
3002                 usb_1: usb@a6f8800 {
3003                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3004                         reg = <0 0x0a6f8800 0 0x400>;
3005                         status = "disabled";
3006                         #address-cells = <2>;
3007                         #size-cells = <2>;
3008                         ranges;
3009                         dma-ranges;
3010
3011                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3012                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3013                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3014                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3015                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3016                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3017                         clock-names = "cfg_noc",
3018                                       "core",
3019                                       "iface",
3020                                       "sleep",
3021                                       "mock_utmi",
3022                                       "xo";
3023
3024                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3025                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3026                         assigned-clock-rates = <19200000>, <200000000>;
3027
3028                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3029                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3030                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3031                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3032                         interrupt-names = "hs_phy_irq",
3033                                           "ss_phy_irq",
3034                                           "dm_hs_phy_irq",
3035                                           "dp_hs_phy_irq";
3036
3037                         power-domains = <&gcc USB30_PRIM_GDSC>;
3038
3039                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3040
3041                         usb_1_dwc3: usb@a600000 {
3042                                 compatible = "snps,dwc3";
3043                                 reg = <0 0x0a600000 0 0xcd00>;
3044                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3045                                 iommus = <&apps_smmu 0x0 0x0>;
3046                                 snps,dis_u2_susphy_quirk;
3047                                 snps,dis_enblslpm_quirk;
3048                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3049                                 phy-names = "usb2-phy", "usb3-phy";
3050                         };
3051                 };
3052
3053                 system-cache-controller@9200000 {
3054                         compatible = "qcom,sm8250-llcc";
3055                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
3056                         reg-names = "llcc_base", "llcc_broadcast_base";
3057                 };
3058
3059                 usb_2: usb@a8f8800 {
3060                         compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3061                         reg = <0 0x0a8f8800 0 0x400>;
3062                         status = "disabled";
3063                         #address-cells = <2>;
3064                         #size-cells = <2>;
3065                         ranges;
3066                         dma-ranges;
3067
3068                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3069                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3070                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3071                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3072                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3073                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
3074                         clock-names = "cfg_noc",
3075                                       "core",
3076                                       "iface",
3077                                       "sleep",
3078                                       "mock_utmi",
3079                                       "xo";
3080
3081                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3082                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3083                         assigned-clock-rates = <19200000>, <200000000>;
3084
3085                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3086                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
3087                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3088                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
3089                         interrupt-names = "hs_phy_irq",
3090                                           "ss_phy_irq",
3091                                           "dm_hs_phy_irq",
3092                                           "dp_hs_phy_irq";
3093
3094                         power-domains = <&gcc USB30_SEC_GDSC>;
3095
3096                         resets = <&gcc GCC_USB30_SEC_BCR>;
3097
3098                         usb_2_dwc3: usb@a800000 {
3099                                 compatible = "snps,dwc3";
3100                                 reg = <0 0x0a800000 0 0xcd00>;
3101                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3102                                 iommus = <&apps_smmu 0x20 0>;
3103                                 snps,dis_u2_susphy_quirk;
3104                                 snps,dis_enblslpm_quirk;
3105                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3106                                 phy-names = "usb2-phy", "usb3-phy";
3107                         };
3108                 };
3109
3110                 venus: video-codec@aa00000 {
3111                         compatible = "qcom,sm8250-venus";
3112                         reg = <0 0x0aa00000 0 0x100000>;
3113                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3114                         power-domains = <&videocc MVS0C_GDSC>,
3115                                         <&videocc MVS0_GDSC>,
3116                                         <&rpmhpd SM8250_MX>;
3117                         power-domain-names = "venus", "vcodec0", "mx";
3118                         operating-points-v2 = <&venus_opp_table>;
3119
3120                         clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
3121                                  <&videocc VIDEO_CC_MVS0C_CLK>,
3122                                  <&videocc VIDEO_CC_MVS0_CLK>;
3123                         clock-names = "iface", "core", "vcodec0_core";
3124
3125                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
3126                                         <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
3127                         interconnect-names = "cpu-cfg", "video-mem";
3128
3129                         iommus = <&apps_smmu 0x2100 0x0400>;
3130                         memory-region = <&video_mem>;
3131
3132                         resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
3133                                  <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
3134                         reset-names = "bus", "core";
3135
3136                         status = "disabled";
3137
3138                         video-decoder {
3139                                 compatible = "venus-decoder";
3140                         };
3141
3142                         video-encoder {
3143                                 compatible = "venus-encoder";
3144                         };
3145
3146                         venus_opp_table: opp-table {
3147                                 compatible = "operating-points-v2";
3148
3149                                 opp-720000000 {
3150                                         opp-hz = /bits/ 64 <720000000>;
3151                                         required-opps = <&rpmhpd_opp_low_svs>;
3152                                 };
3153
3154                                 opp-1014000000 {
3155                                         opp-hz = /bits/ 64 <1014000000>;
3156                                         required-opps = <&rpmhpd_opp_svs>;
3157                                 };
3158
3159                                 opp-1098000000 {
3160                                         opp-hz = /bits/ 64 <1098000000>;
3161                                         required-opps = <&rpmhpd_opp_svs_l1>;
3162                                 };
3163
3164                                 opp-1332000000 {
3165                                         opp-hz = /bits/ 64 <1332000000>;
3166                                         required-opps = <&rpmhpd_opp_nom>;
3167                                 };
3168                         };
3169                 };
3170
3171                 videocc: clock-controller@abf0000 {
3172                         compatible = "qcom,sm8250-videocc";
3173                         reg = <0 0x0abf0000 0 0x10000>;
3174                         clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3175                                  <&rpmhcc RPMH_CXO_CLK>,
3176                                  <&rpmhcc RPMH_CXO_CLK_A>;
3177                         power-domains = <&rpmhpd SM8250_MMCX>;
3178                         required-opps = <&rpmhpd_opp_low_svs>;
3179                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
3180                         #clock-cells = <1>;
3181                         #reset-cells = <1>;
3182                         #power-domain-cells = <1>;
3183                 };
3184
3185                 cci0: cci@ac4f000 {
3186                         compatible = "qcom,sm8250-cci";
3187                         #address-cells = <1>;
3188                         #size-cells = <0>;
3189
3190                         reg = <0 0x0ac4f000 0 0x1000>;
3191                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3192                         power-domains = <&camcc TITAN_TOP_GDSC>;
3193
3194                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3195                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3196                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3197                                  <&camcc CAM_CC_CCI_0_CLK>,
3198                                  <&camcc CAM_CC_CCI_0_CLK_SRC>;
3199                         clock-names = "camnoc_axi",
3200                                       "slow_ahb_src",
3201                                       "cpas_ahb",
3202                                       "cci",
3203                                       "cci_src";
3204
3205                         pinctrl-0 = <&cci0_default>;
3206                         pinctrl-1 = <&cci0_sleep>;
3207                         pinctrl-names = "default", "sleep";
3208
3209                         status = "disabled";
3210
3211                         cci0_i2c0: i2c-bus@0 {
3212                                 reg = <0>;
3213                                 clock-frequency = <1000000>;
3214                                 #address-cells = <1>;
3215                                 #size-cells = <0>;
3216                         };
3217
3218                         cci0_i2c1: i2c-bus@1 {
3219                                 reg = <1>;
3220                                 clock-frequency = <1000000>;
3221                                 #address-cells = <1>;
3222                                 #size-cells = <0>;
3223                         };
3224                 };
3225
3226                 cci1: cci@ac50000 {
3227                         compatible = "qcom,sm8250-cci";
3228                         #address-cells = <1>;
3229                         #size-cells = <0>;
3230
3231                         reg = <0 0x0ac50000 0 0x1000>;
3232                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3233                         power-domains = <&camcc TITAN_TOP_GDSC>;
3234
3235                         clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3236                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3237                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3238                                  <&camcc CAM_CC_CCI_1_CLK>,
3239                                  <&camcc CAM_CC_CCI_1_CLK_SRC>;
3240                         clock-names = "camnoc_axi",
3241                                       "slow_ahb_src",
3242                                       "cpas_ahb",
3243                                       "cci",
3244                                       "cci_src";
3245
3246                         pinctrl-0 = <&cci1_default>;
3247                         pinctrl-1 = <&cci1_sleep>;
3248                         pinctrl-names = "default", "sleep";
3249
3250                         status = "disabled";
3251
3252                         cci1_i2c0: i2c-bus@0 {
3253                                 reg = <0>;
3254                                 clock-frequency = <1000000>;
3255                                 #address-cells = <1>;
3256                                 #size-cells = <0>;
3257                         };
3258
3259                         cci1_i2c1: i2c-bus@1 {
3260                                 reg = <1>;
3261                                 clock-frequency = <1000000>;
3262                                 #address-cells = <1>;
3263                                 #size-cells = <0>;
3264                         };
3265                 };
3266
3267                 camss: camss@ac6a000 {
3268                         compatible = "qcom,sm8250-camss";
3269                         status = "disabled";
3270
3271                         reg = <0 0xac6a000 0 0x2000>,
3272                               <0 0xac6c000 0 0x2000>,
3273                               <0 0xac6e000 0 0x1000>,
3274                               <0 0xac70000 0 0x1000>,
3275                               <0 0xac72000 0 0x1000>,
3276                               <0 0xac74000 0 0x1000>,
3277                               <0 0xacb4000 0 0xd000>,
3278                               <0 0xacc3000 0 0xd000>,
3279                               <0 0xacd9000 0 0x2200>,
3280                               <0 0xacdb200 0 0x2200>;
3281                         reg-names = "csiphy0",
3282                                     "csiphy1",
3283                                     "csiphy2",
3284                                     "csiphy3",
3285                                     "csiphy4",
3286                                     "csiphy5",
3287                                     "vfe0",
3288                                     "vfe1",
3289                                     "vfe_lite0",
3290                                     "vfe_lite1";
3291
3292                         interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3293                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3294                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3295                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3298                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3299                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3300                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3301                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3302                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3303                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
3306                         interrupt-names = "csiphy0",
3307                                           "csiphy1",
3308                                           "csiphy2",
3309                                           "csiphy3",
3310                                           "csiphy4",
3311                                           "csiphy5",
3312                                           "csid0",
3313                                           "csid1",
3314                                           "csid2",
3315                                           "csid3",
3316                                           "vfe0",
3317                                           "vfe1",
3318                                           "vfe_lite0",
3319                                           "vfe_lite1";
3320
3321                         power-domains = <&camcc IFE_0_GDSC>,
3322                                         <&camcc IFE_1_GDSC>,
3323                                         <&camcc TITAN_TOP_GDSC>;
3324
3325                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3326                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
3327                                  <&gcc GCC_CAMERA_SF_AXI_CLK>,
3328                                  <&camcc CAM_CC_CAMNOC_AXI_CLK>,
3329                                  <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
3330                                  <&camcc CAM_CC_CORE_AHB_CLK>,
3331                                  <&camcc CAM_CC_CPAS_AHB_CLK>,
3332                                  <&camcc CAM_CC_CSIPHY0_CLK>,
3333                                  <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
3334                                  <&camcc CAM_CC_CSIPHY1_CLK>,
3335                                  <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
3336                                  <&camcc CAM_CC_CSIPHY2_CLK>,
3337                                  <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
3338                                  <&camcc CAM_CC_CSIPHY3_CLK>,
3339                                  <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
3340                                  <&camcc CAM_CC_CSIPHY4_CLK>,
3341                                  <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
3342                                  <&camcc CAM_CC_CSIPHY5_CLK>,
3343                                  <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
3344                                  <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
3345                                  <&camcc CAM_CC_IFE_0_AHB_CLK>,
3346                                  <&camcc CAM_CC_IFE_0_AXI_CLK>,
3347                                  <&camcc CAM_CC_IFE_0_CLK>,
3348                                  <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
3349                                  <&camcc CAM_CC_IFE_0_CSID_CLK>,
3350                                  <&camcc CAM_CC_IFE_0_AREG_CLK>,
3351                                  <&camcc CAM_CC_IFE_1_AHB_CLK>,
3352                                  <&camcc CAM_CC_IFE_1_AXI_CLK>,
3353                                  <&camcc CAM_CC_IFE_1_CLK>,
3354                                  <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
3355                                  <&camcc CAM_CC_IFE_1_CSID_CLK>,
3356                                  <&camcc CAM_CC_IFE_1_AREG_CLK>,
3357                                  <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
3358                                  <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
3359                                  <&camcc CAM_CC_IFE_LITE_CLK>,
3360                                  <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
3361                                  <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
3362
3363                         clock-names = "cam_ahb_clk",
3364                                       "cam_hf_axi",
3365                                       "cam_sf_axi",
3366                                       "camnoc_axi",
3367                                       "camnoc_axi_src",
3368                                       "core_ahb",
3369                                       "cpas_ahb",
3370                                       "csiphy0",
3371                                       "csiphy0_timer",
3372                                       "csiphy1",
3373                                       "csiphy1_timer",
3374                                       "csiphy2",
3375                                       "csiphy2_timer",
3376                                       "csiphy3",
3377                                       "csiphy3_timer",
3378                                       "csiphy4",
3379                                       "csiphy4_timer",
3380                                       "csiphy5",
3381                                       "csiphy5_timer",
3382                                       "slow_ahb_src",
3383                                       "vfe0_ahb",
3384                                       "vfe0_axi",
3385                                       "vfe0",
3386                                       "vfe0_cphy_rx",
3387                                       "vfe0_csid",
3388                                       "vfe0_areg",
3389                                       "vfe1_ahb",
3390                                       "vfe1_axi",
3391                                       "vfe1",
3392                                       "vfe1_cphy_rx",
3393                                       "vfe1_csid",
3394                                       "vfe1_areg",
3395                                       "vfe_lite_ahb",
3396                                       "vfe_lite_axi",
3397                                       "vfe_lite",
3398                                       "vfe_lite_cphy_rx",
3399                                       "vfe_lite_csid";
3400
3401                         iommus = <&apps_smmu 0x800 0x400>,
3402                                  <&apps_smmu 0x801 0x400>,
3403                                  <&apps_smmu 0x840 0x400>,
3404                                  <&apps_smmu 0x841 0x400>,
3405                                  <&apps_smmu 0xc00 0x400>,
3406                                  <&apps_smmu 0xc01 0x400>,
3407                                  <&apps_smmu 0xc40 0x400>,
3408                                  <&apps_smmu 0xc41 0x400>;
3409
3410                         interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
3411                                         <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
3412                                         <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
3413                                         <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
3414                         interconnect-names = "cam_ahb",
3415                                              "cam_hf_0_mnoc",
3416                                              "cam_sf_0_mnoc",
3417                                              "cam_sf_icp_mnoc";
3418                 };
3419
3420                 camcc: clock-controller@ad00000 {
3421                         compatible = "qcom,sm8250-camcc";
3422                         reg = <0 0x0ad00000 0 0x10000>;
3423                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3424                                  <&rpmhcc RPMH_CXO_CLK>,
3425                                  <&rpmhcc RPMH_CXO_CLK_A>,
3426                                  <&sleep_clk>;
3427                         clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3428                         power-domains = <&rpmhpd SM8250_MMCX>;
3429                         required-opps = <&rpmhpd_opp_low_svs>;
3430                         status = "disabled";
3431                         #clock-cells = <1>;
3432                         #reset-cells = <1>;
3433                         #power-domain-cells = <1>;
3434                 };
3435
3436                 mdss: mdss@ae00000 {
3437                         compatible = "qcom,sm8250-mdss";
3438                         reg = <0 0x0ae00000 0 0x1000>;
3439                         reg-names = "mdss";
3440
3441                         interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3442                                         <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3443                         interconnect-names = "mdp0-mem", "mdp1-mem";
3444
3445                         power-domains = <&dispcc MDSS_GDSC>;
3446
3447                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3448                                  <&gcc GCC_DISP_HF_AXI_CLK>,
3449                                  <&gcc GCC_DISP_SF_AXI_CLK>,
3450                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3451                         clock-names = "iface", "bus", "nrt_bus", "core";
3452
3453                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3454                         interrupt-controller;
3455                         #interrupt-cells = <1>;
3456
3457                         iommus = <&apps_smmu 0x820 0x402>;
3458
3459                         status = "disabled";
3460
3461                         #address-cells = <2>;
3462                         #size-cells = <2>;
3463                         ranges;
3464
3465                         mdss_mdp: display-controller@ae01000 {
3466                                 compatible = "qcom,sm8250-dpu";
3467                                 reg = <0 0x0ae01000 0 0x8f000>,
3468                                       <0 0x0aeb0000 0 0x2008>;
3469                                 reg-names = "mdp", "vbif";
3470
3471                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3472                                          <&gcc GCC_DISP_HF_AXI_CLK>,
3473                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3474                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3475                                 clock-names = "iface", "bus", "core", "vsync";
3476
3477                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3478                                 assigned-clock-rates = <19200000>;
3479
3480                                 operating-points-v2 = <&mdp_opp_table>;
3481                                 power-domains = <&rpmhpd SM8250_MMCX>;
3482
3483                                 interrupt-parent = <&mdss>;
3484                                 interrupts = <0>;
3485
3486                                 ports {
3487                                         #address-cells = <1>;
3488                                         #size-cells = <0>;
3489
3490                                         port@0 {
3491                                                 reg = <0>;
3492                                                 dpu_intf1_out: endpoint {
3493                                                         remote-endpoint = <&dsi0_in>;
3494                                                 };
3495                                         };
3496
3497                                         port@1 {
3498                                                 reg = <1>;
3499                                                 dpu_intf2_out: endpoint {
3500                                                         remote-endpoint = <&dsi1_in>;
3501                                                 };
3502                                         };
3503                                 };
3504
3505                                 mdp_opp_table: opp-table {
3506                                         compatible = "operating-points-v2";
3507
3508                                         opp-200000000 {
3509                                                 opp-hz = /bits/ 64 <200000000>;
3510                                                 required-opps = <&rpmhpd_opp_low_svs>;
3511                                         };
3512
3513                                         opp-300000000 {
3514                                                 opp-hz = /bits/ 64 <300000000>;
3515                                                 required-opps = <&rpmhpd_opp_svs>;
3516                                         };
3517
3518                                         opp-345000000 {
3519                                                 opp-hz = /bits/ 64 <345000000>;
3520                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3521                                         };
3522
3523                                         opp-460000000 {
3524                                                 opp-hz = /bits/ 64 <460000000>;
3525                                                 required-opps = <&rpmhpd_opp_nom>;
3526                                         };
3527                                 };
3528                         };
3529
3530                         dsi0: dsi@ae94000 {
3531                                 compatible = "qcom,mdss-dsi-ctrl";
3532                                 reg = <0 0x0ae94000 0 0x400>;
3533                                 reg-names = "dsi_ctrl";
3534
3535                                 interrupt-parent = <&mdss>;
3536                                 interrupts = <4>;
3537
3538                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3539                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3540                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3541                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3542                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3543                                         <&gcc GCC_DISP_HF_AXI_CLK>;
3544                                 clock-names = "byte",
3545                                               "byte_intf",
3546                                               "pixel",
3547                                               "core",
3548                                               "iface",
3549                                               "bus";
3550
3551                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3552                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
3553
3554                                 operating-points-v2 = <&dsi_opp_table>;
3555                                 power-domains = <&rpmhpd SM8250_MMCX>;
3556
3557                                 phys = <&dsi0_phy>;
3558                                 phy-names = "dsi";
3559
3560                                 status = "disabled";
3561
3562                                 #address-cells = <1>;
3563                                 #size-cells = <0>;
3564
3565                                 ports {
3566                                         #address-cells = <1>;
3567                                         #size-cells = <0>;
3568
3569                                         port@0 {
3570                                                 reg = <0>;
3571                                                 dsi0_in: endpoint {
3572                                                         remote-endpoint = <&dpu_intf1_out>;
3573                                                 };
3574                                         };
3575
3576                                         port@1 {
3577                                                 reg = <1>;
3578                                                 dsi0_out: endpoint {
3579                                                 };
3580                                         };
3581                                 };
3582
3583                                 dsi_opp_table: opp-table {
3584                                         compatible = "operating-points-v2";
3585
3586                                         opp-187500000 {
3587                                                 opp-hz = /bits/ 64 <187500000>;
3588                                                 required-opps = <&rpmhpd_opp_low_svs>;
3589                                         };
3590
3591                                         opp-300000000 {
3592                                                 opp-hz = /bits/ 64 <300000000>;
3593                                                 required-opps = <&rpmhpd_opp_svs>;
3594                                         };
3595
3596                                         opp-358000000 {
3597                                                 opp-hz = /bits/ 64 <358000000>;
3598                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3599                                         };
3600                                 };
3601                         };
3602
3603                         dsi0_phy: dsi-phy@ae94400 {
3604                                 compatible = "qcom,dsi-phy-7nm";
3605                                 reg = <0 0x0ae94400 0 0x200>,
3606                                       <0 0x0ae94600 0 0x280>,
3607                                       <0 0x0ae94900 0 0x260>;
3608                                 reg-names = "dsi_phy",
3609                                             "dsi_phy_lane",
3610                                             "dsi_pll";
3611
3612                                 #clock-cells = <1>;
3613                                 #phy-cells = <0>;
3614
3615                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3616                                          <&rpmhcc RPMH_CXO_CLK>;
3617                                 clock-names = "iface", "ref";
3618
3619                                 status = "disabled";
3620                         };
3621
3622                         dsi1: dsi@ae96000 {
3623                                 compatible = "qcom,mdss-dsi-ctrl";
3624                                 reg = <0 0x0ae96000 0 0x400>;
3625                                 reg-names = "dsi_ctrl";
3626
3627                                 interrupt-parent = <&mdss>;
3628                                 interrupts = <5>;
3629
3630                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3631                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3632                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3633                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3634                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3635                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3636                                 clock-names = "byte",
3637                                               "byte_intf",
3638                                               "pixel",
3639                                               "core",
3640                                               "iface",
3641                                               "bus";
3642
3643                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3644                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
3645
3646                                 operating-points-v2 = <&dsi_opp_table>;
3647                                 power-domains = <&rpmhpd SM8250_MMCX>;
3648
3649                                 phys = <&dsi1_phy>;
3650                                 phy-names = "dsi";
3651
3652                                 status = "disabled";
3653
3654                                 #address-cells = <1>;
3655                                 #size-cells = <0>;
3656
3657                                 ports {
3658                                         #address-cells = <1>;
3659                                         #size-cells = <0>;
3660
3661                                         port@0 {
3662                                                 reg = <0>;
3663                                                 dsi1_in: endpoint {
3664                                                         remote-endpoint = <&dpu_intf2_out>;
3665                                                 };
3666                                         };
3667
3668                                         port@1 {
3669                                                 reg = <1>;
3670                                                 dsi1_out: endpoint {
3671                                                 };
3672                                         };
3673                                 };
3674                         };
3675
3676                         dsi1_phy: dsi-phy@ae96400 {
3677                                 compatible = "qcom,dsi-phy-7nm";
3678                                 reg = <0 0x0ae96400 0 0x200>,
3679                                       <0 0x0ae96600 0 0x280>,
3680                                       <0 0x0ae96900 0 0x260>;
3681                                 reg-names = "dsi_phy",
3682                                             "dsi_phy_lane",
3683                                             "dsi_pll";
3684
3685                                 #clock-cells = <1>;
3686                                 #phy-cells = <0>;
3687
3688                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3689                                          <&rpmhcc RPMH_CXO_CLK>;
3690                                 clock-names = "iface", "ref";
3691
3692                                 status = "disabled";
3693                         };
3694                 };
3695
3696                 dispcc: clock-controller@af00000 {
3697                         compatible = "qcom,sm8250-dispcc";
3698                         reg = <0 0x0af00000 0 0x10000>;
3699                         power-domains = <&rpmhpd SM8250_MMCX>;
3700                         required-opps = <&rpmhpd_opp_low_svs>;
3701                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3702                                  <&dsi0_phy 0>,
3703                                  <&dsi0_phy 1>,
3704                                  <&dsi1_phy 0>,
3705                                  <&dsi1_phy 1>,
3706                                  <&dp_phy 0>,
3707                                  <&dp_phy 1>;
3708                         clock-names = "bi_tcxo",
3709                                       "dsi0_phy_pll_out_byteclk",
3710                                       "dsi0_phy_pll_out_dsiclk",
3711                                       "dsi1_phy_pll_out_byteclk",
3712                                       "dsi1_phy_pll_out_dsiclk",
3713                                       "dp_phy_pll_link_clk",
3714                                       "dp_phy_pll_vco_div_clk";
3715                         #clock-cells = <1>;
3716                         #reset-cells = <1>;
3717                         #power-domain-cells = <1>;
3718                 };
3719
3720                 pdc: interrupt-controller@b220000 {
3721                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
3722                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3723                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3724                                           <125 63 1>, <126 716 12>;
3725                         #interrupt-cells = <2>;
3726                         interrupt-parent = <&intc>;
3727                         interrupt-controller;
3728                 };
3729
3730                 tsens0: thermal-sensor@c263000 {
3731                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3732                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3733                               <0 0x0c222000 0 0x1ff>; /* SROT */
3734                         #qcom,sensors = <16>;
3735                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3736                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3737                         interrupt-names = "uplow", "critical";
3738                         #thermal-sensor-cells = <1>;
3739                 };
3740
3741                 tsens1: thermal-sensor@c265000 {
3742                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
3743                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3744                               <0 0x0c223000 0 0x1ff>; /* SROT */
3745                         #qcom,sensors = <9>;
3746                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3747                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3748                         interrupt-names = "uplow", "critical";
3749                         #thermal-sensor-cells = <1>;
3750                 };
3751
3752                 aoss_qmp: power-controller@c300000 {
3753                         compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
3754                         reg = <0 0x0c300000 0 0x400>;
3755                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3756                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
3757                                                      IRQ_TYPE_EDGE_RISING>;
3758                         mboxes = <&ipcc IPCC_CLIENT_AOP
3759                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
3760
3761                         #clock-cells = <0>;
3762                 };
3763
3764                 sram@c3f0000 {
3765                         compatible = "qcom,rpmh-stats";
3766                         reg = <0 0x0c3f0000 0 0x400>;
3767                 };
3768
3769                 spmi_bus: spmi@c440000 {
3770                         compatible = "qcom,spmi-pmic-arb";
3771                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3772                               <0x0 0x0c600000 0x0 0x2000000>,
3773                               <0x0 0x0e600000 0x0 0x0100000>,
3774                               <0x0 0x0e700000 0x0 0x00a0000>,
3775                               <0x0 0x0c40a000 0x0 0x0026000>;
3776                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3777                         interrupt-names = "periph_irq";
3778                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3779                         qcom,ee = <0>;
3780                         qcom,channel = <0>;
3781                         #address-cells = <2>;
3782                         #size-cells = <0>;
3783                         interrupt-controller;
3784                         #interrupt-cells = <4>;
3785                 };
3786
3787                 tlmm: pinctrl@f100000 {
3788                         compatible = "qcom,sm8250-pinctrl";
3789                         reg = <0 0x0f100000 0 0x300000>,
3790                               <0 0x0f500000 0 0x300000>,
3791                               <0 0x0f900000 0 0x300000>;
3792                         reg-names = "west", "south", "north";
3793                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3794                         gpio-controller;
3795                         #gpio-cells = <2>;
3796                         interrupt-controller;
3797                         #interrupt-cells = <2>;
3798                         gpio-ranges = <&tlmm 0 0 181>;
3799                         wakeup-parent = <&pdc>;
3800
3801                         cci0_default: cci0-default {
3802                                 cci0_i2c0_default: cci0-i2c0-default {
3803                                         /* SDA, SCL */
3804                                         pins = "gpio101", "gpio102";
3805                                         function = "cci_i2c";
3806
3807                                         bias-pull-up;
3808                                         drive-strength = <2>; /* 2 mA */
3809                                 };
3810
3811                                 cci0_i2c1_default: cci0-i2c1-default {
3812                                         /* SDA, SCL */
3813                                         pins = "gpio103", "gpio104";
3814                                         function = "cci_i2c";
3815
3816                                         bias-pull-up;
3817                                         drive-strength = <2>; /* 2 mA */
3818                                 };
3819                         };
3820
3821                         cci0_sleep: cci0-sleep {
3822                                 cci0_i2c0_sleep: cci0-i2c0-sleep {
3823                                         /* SDA, SCL */
3824                                         pins = "gpio101", "gpio102";
3825                                         function = "cci_i2c";
3826
3827                                         drive-strength = <2>; /* 2 mA */
3828                                         bias-pull-down;
3829                                 };
3830
3831                                 cci0_i2c1_sleep: cci0-i2c1-sleep {
3832                                         /* SDA, SCL */
3833                                         pins = "gpio103", "gpio104";
3834                                         function = "cci_i2c";
3835
3836                                         drive-strength = <2>; /* 2 mA */
3837                                         bias-pull-down;
3838                                 };
3839                         };
3840
3841                         cci1_default: cci1-default {
3842                                 cci1_i2c0_default: cci1-i2c0-default {
3843                                         /* SDA, SCL */
3844                                         pins = "gpio105","gpio106";
3845                                         function = "cci_i2c";
3846
3847                                         bias-pull-up;
3848                                         drive-strength = <2>; /* 2 mA */
3849                                 };
3850
3851                                 cci1_i2c1_default: cci1-i2c1-default {
3852                                         /* SDA, SCL */
3853                                         pins = "gpio107","gpio108";
3854                                         function = "cci_i2c";
3855
3856                                         bias-pull-up;
3857                                         drive-strength = <2>; /* 2 mA */
3858                                 };
3859                         };
3860
3861                         cci1_sleep: cci1-sleep {
3862                                 cci1_i2c0_sleep: cci1-i2c0-sleep {
3863                                         /* SDA, SCL */
3864                                         pins = "gpio105","gpio106";
3865                                         function = "cci_i2c";
3866
3867                                         bias-pull-down;
3868                                         drive-strength = <2>; /* 2 mA */
3869                                 };
3870
3871                                 cci1_i2c1_sleep: cci1-i2c1-sleep {
3872                                         /* SDA, SCL */
3873                                         pins = "gpio107","gpio108";
3874                                         function = "cci_i2c";
3875
3876                                         bias-pull-down;
3877                                         drive-strength = <2>; /* 2 mA */
3878                                 };
3879                         };
3880
3881                         pri_mi2s_active: pri-mi2s-active {
3882                                 sclk {
3883                                         pins = "gpio138";
3884                                         function = "mi2s0_sck";
3885                                         drive-strength = <8>;
3886                                         bias-disable;
3887                                 };
3888
3889                                 ws {
3890                                         pins = "gpio141";
3891                                         function = "mi2s0_ws";
3892                                         drive-strength = <8>;
3893                                         output-high;
3894                                 };
3895
3896                                 data0 {
3897                                         pins = "gpio139";
3898                                         function = "mi2s0_data0";
3899                                         drive-strength = <8>;
3900                                         bias-disable;
3901                                         output-high;
3902                                 };
3903
3904                                 data1 {
3905                                         pins = "gpio140";
3906                                         function = "mi2s0_data1";
3907                                         drive-strength = <8>;
3908                                         output-high;
3909                                 };
3910                         };
3911
3912                         qup_i2c0_default: qup-i2c0-default {
3913                                 mux {
3914                                         pins = "gpio28", "gpio29";
3915                                         function = "qup0";
3916                                 };
3917
3918                                 config {
3919                                         pins = "gpio28", "gpio29";
3920                                         drive-strength = <2>;
3921                                         bias-disable;
3922                                 };
3923                         };
3924
3925                         qup_i2c1_default: qup-i2c1-default {
3926                                 pinmux {
3927                                         pins = "gpio4", "gpio5";
3928                                         function = "qup1";
3929                                 };
3930
3931                                 config {
3932                                         pins = "gpio4", "gpio5";
3933                                         drive-strength = <2>;
3934                                         bias-disable;
3935                                 };
3936                         };
3937
3938                         qup_i2c2_default: qup-i2c2-default {
3939                                 mux {
3940                                         pins = "gpio115", "gpio116";
3941                                         function = "qup2";
3942                                 };
3943
3944                                 config {
3945                                         pins = "gpio115", "gpio116";
3946                                         drive-strength = <2>;
3947                                         bias-disable;
3948                                 };
3949                         };
3950
3951                         qup_i2c3_default: qup-i2c3-default {
3952                                 mux {
3953                                         pins = "gpio119", "gpio120";
3954                                         function = "qup3";
3955                                 };
3956
3957                                 config {
3958                                         pins = "gpio119", "gpio120";
3959                                         drive-strength = <2>;
3960                                         bias-disable;
3961                                 };
3962                         };
3963
3964                         qup_i2c4_default: qup-i2c4-default {
3965                                 mux {
3966                                         pins = "gpio8", "gpio9";
3967                                         function = "qup4";
3968                                 };
3969
3970                                 config {
3971                                         pins = "gpio8", "gpio9";
3972                                         drive-strength = <2>;
3973                                         bias-disable;
3974                                 };
3975                         };
3976
3977                         qup_i2c5_default: qup-i2c5-default {
3978                                 mux {
3979                                         pins = "gpio12", "gpio13";
3980                                         function = "qup5";
3981                                 };
3982
3983                                 config {
3984                                         pins = "gpio12", "gpio13";
3985                                         drive-strength = <2>;
3986                                         bias-disable;
3987                                 };
3988                         };
3989
3990                         qup_i2c6_default: qup-i2c6-default {
3991                                 mux {
3992                                         pins = "gpio16", "gpio17";
3993                                         function = "qup6";
3994                                 };
3995
3996                                 config {
3997                                         pins = "gpio16", "gpio17";
3998                                         drive-strength = <2>;
3999                                         bias-disable;
4000                                 };
4001                         };
4002
4003                         qup_i2c7_default: qup-i2c7-default {
4004                                 mux {
4005                                         pins = "gpio20", "gpio21";
4006                                         function = "qup7";
4007                                 };
4008
4009                                 config {
4010                                         pins = "gpio20", "gpio21";
4011                                         drive-strength = <2>;
4012                                         bias-disable;
4013                                 };
4014                         };
4015
4016                         qup_i2c8_default: qup-i2c8-default {
4017                                 mux {
4018                                         pins = "gpio24", "gpio25";
4019                                         function = "qup8";
4020                                 };
4021
4022                                 config {
4023                                         pins = "gpio24", "gpio25";
4024                                         drive-strength = <2>;
4025                                         bias-disable;
4026                                 };
4027                         };
4028
4029                         qup_i2c9_default: qup-i2c9-default {
4030                                 mux {
4031                                         pins = "gpio125", "gpio126";
4032                                         function = "qup9";
4033                                 };
4034
4035                                 config {
4036                                         pins = "gpio125", "gpio126";
4037                                         drive-strength = <2>;
4038                                         bias-disable;
4039                                 };
4040                         };
4041
4042                         qup_i2c10_default: qup-i2c10-default {
4043                                 mux {
4044                                         pins = "gpio129", "gpio130";
4045                                         function = "qup10";
4046                                 };
4047
4048                                 config {
4049                                         pins = "gpio129", "gpio130";
4050                                         drive-strength = <2>;
4051                                         bias-disable;
4052                                 };
4053                         };
4054
4055                         qup_i2c11_default: qup-i2c11-default {
4056                                 mux {
4057                                         pins = "gpio60", "gpio61";
4058                                         function = "qup11";
4059                                 };
4060
4061                                 config {
4062                                         pins = "gpio60", "gpio61";
4063                                         drive-strength = <2>;
4064                                         bias-disable;
4065                                 };
4066                         };
4067
4068                         qup_i2c12_default: qup-i2c12-default {
4069                                 mux {
4070                                         pins = "gpio32", "gpio33";
4071                                         function = "qup12";
4072                                 };
4073
4074                                 config {
4075                                         pins = "gpio32", "gpio33";
4076                                         drive-strength = <2>;
4077                                         bias-disable;
4078                                 };
4079                         };
4080
4081                         qup_i2c13_default: qup-i2c13-default {
4082                                 mux {
4083                                         pins = "gpio36", "gpio37";
4084                                         function = "qup13";
4085                                 };
4086
4087                                 config {
4088                                         pins = "gpio36", "gpio37";
4089                                         drive-strength = <2>;
4090                                         bias-disable;
4091                                 };
4092                         };
4093
4094                         qup_i2c14_default: qup-i2c14-default {
4095                                 mux {
4096                                         pins = "gpio40", "gpio41";
4097                                         function = "qup14";
4098                                 };
4099
4100                                 config {
4101                                         pins = "gpio40", "gpio41";
4102                                         drive-strength = <2>;
4103                                         bias-disable;
4104                                 };
4105                         };
4106
4107                         qup_i2c15_default: qup-i2c15-default {
4108                                 mux {
4109                                         pins = "gpio44", "gpio45";
4110                                         function = "qup15";
4111                                 };
4112
4113                                 config {
4114                                         pins = "gpio44", "gpio45";
4115                                         drive-strength = <2>;
4116                                         bias-disable;
4117                                 };
4118                         };
4119
4120                         qup_i2c16_default: qup-i2c16-default {
4121                                 mux {
4122                                         pins = "gpio48", "gpio49";
4123                                         function = "qup16";
4124                                 };
4125
4126                                 config {
4127                                         pins = "gpio48", "gpio49";
4128                                         drive-strength = <2>;
4129                                         bias-disable;
4130                                 };
4131                         };
4132
4133                         qup_i2c17_default: qup-i2c17-default {
4134                                 mux {
4135                                         pins = "gpio52", "gpio53";
4136                                         function = "qup17";
4137                                 };
4138
4139                                 config {
4140                                         pins = "gpio52", "gpio53";
4141                                         drive-strength = <2>;
4142                                         bias-disable;
4143                                 };
4144                         };
4145
4146                         qup_i2c18_default: qup-i2c18-default {
4147                                 mux {
4148                                         pins = "gpio56", "gpio57";
4149                                         function = "qup18";
4150                                 };
4151
4152                                 config {
4153                                         pins = "gpio56", "gpio57";
4154                                         drive-strength = <2>;
4155                                         bias-disable;
4156                                 };
4157                         };
4158
4159                         qup_i2c19_default: qup-i2c19-default {
4160                                 mux {
4161                                         pins = "gpio0", "gpio1";
4162                                         function = "qup19";
4163                                 };
4164
4165                                 config {
4166                                         pins = "gpio0", "gpio1";
4167                                         drive-strength = <2>;
4168                                         bias-disable;
4169                                 };
4170                         };
4171
4172                         qup_spi0_cs: qup-spi0-cs {
4173                                 pins = "gpio31";
4174                                 function = "qup0";
4175                         };
4176
4177                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
4178                                 pins = "gpio31";
4179                                 function = "gpio";
4180                         };
4181
4182                         qup_spi0_data_clk: qup-spi0-data-clk {
4183                                 pins = "gpio28", "gpio29",
4184                                        "gpio30";
4185                                 function = "qup0";
4186                         };
4187
4188                         qup_spi1_cs: qup-spi1-cs {
4189                                 pins = "gpio7";
4190                                 function = "qup1";
4191                         };
4192
4193                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
4194                                 pins = "gpio7";
4195                                 function = "gpio";
4196                         };
4197
4198                         qup_spi1_data_clk: qup-spi1-data-clk {
4199                                 pins = "gpio4", "gpio5",
4200                                        "gpio6";
4201                                 function = "qup1";
4202                         };
4203
4204                         qup_spi2_cs: qup-spi2-cs {
4205                                 pins = "gpio118";
4206                                 function = "qup2";
4207                         };
4208
4209                         qup_spi2_cs_gpio: qup-spi2-cs-gpio {
4210                                 pins = "gpio118";
4211                                 function = "gpio";
4212                         };
4213
4214                         qup_spi2_data_clk: qup-spi2-data-clk {
4215                                 pins = "gpio115", "gpio116",
4216                                        "gpio117";
4217                                 function = "qup2";
4218                         };
4219
4220                         qup_spi3_cs: qup-spi3-cs {
4221                                 pins = "gpio122";
4222                                 function = "qup3";
4223                         };
4224
4225                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
4226                                 pins = "gpio122";
4227                                 function = "gpio";
4228                         };
4229
4230                         qup_spi3_data_clk: qup-spi3-data-clk {
4231                                 pins = "gpio119", "gpio120",
4232                                        "gpio121";
4233                                 function = "qup3";
4234                         };
4235
4236                         qup_spi4_cs: qup-spi4-cs {
4237                                 pins = "gpio11";
4238                                 function = "qup4";
4239                         };
4240
4241                         qup_spi4_cs_gpio: qup-spi4-cs-gpio {
4242                                 pins = "gpio11";
4243                                 function = "gpio";
4244                         };
4245
4246                         qup_spi4_data_clk: qup-spi4-data-clk {
4247                                 pins = "gpio8", "gpio9",
4248                                        "gpio10";
4249                                 function = "qup4";
4250                         };
4251
4252                         qup_spi5_cs: qup-spi5-cs {
4253                                 pins = "gpio15";
4254                                 function = "qup5";
4255                         };
4256
4257                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
4258                                 pins = "gpio15";
4259                                 function = "gpio";
4260                         };
4261
4262                         qup_spi5_data_clk: qup-spi5-data-clk {
4263                                 pins = "gpio12", "gpio13",
4264                                        "gpio14";
4265                                 function = "qup5";
4266                         };
4267
4268                         qup_spi6_cs: qup-spi6-cs {
4269                                 pins = "gpio19";
4270                                 function = "qup6";
4271                         };
4272
4273                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
4274                                 pins = "gpio19";
4275                                 function = "gpio";
4276                         };
4277
4278                         qup_spi6_data_clk: qup-spi6-data-clk {
4279                                 pins = "gpio16", "gpio17",
4280                                        "gpio18";
4281                                 function = "qup6";
4282                         };
4283
4284                         qup_spi7_cs: qup-spi7-cs {
4285                                 pins = "gpio23";
4286                                 function = "qup7";
4287                         };
4288
4289                         qup_spi7_cs_gpio: qup-spi7-cs-gpio {
4290                                 pins = "gpio23";
4291                                 function = "gpio";
4292                         };
4293
4294                         qup_spi7_data_clk: qup-spi7-data-clk {
4295                                 pins = "gpio20", "gpio21",
4296                                        "gpio22";
4297                                 function = "qup7";
4298                         };
4299
4300                         qup_spi8_cs: qup-spi8-cs {
4301                                 pins = "gpio27";
4302                                 function = "qup8";
4303                         };
4304
4305                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
4306                                 pins = "gpio27";
4307                                 function = "gpio";
4308                         };
4309
4310                         qup_spi8_data_clk: qup-spi8-data-clk {
4311                                 pins = "gpio24", "gpio25",
4312                                        "gpio26";
4313                                 function = "qup8";
4314                         };
4315
4316                         qup_spi9_cs: qup-spi9-cs {
4317                                 pins = "gpio128";
4318                                 function = "qup9";
4319                         };
4320
4321                         qup_spi9_cs_gpio: qup-spi9-cs-gpio {
4322                                 pins = "gpio128";
4323                                 function = "gpio";
4324                         };
4325
4326                         qup_spi9_data_clk: qup-spi9-data-clk {
4327                                 pins = "gpio125", "gpio126",
4328                                        "gpio127";
4329                                 function = "qup9";
4330                         };
4331
4332                         qup_spi10_cs: qup-spi10-cs {
4333                                 pins = "gpio132";
4334                                 function = "qup10";
4335                         };
4336
4337                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
4338                                 pins = "gpio132";
4339                                 function = "gpio";
4340                         };
4341
4342                         qup_spi10_data_clk: qup-spi10-data-clk {
4343                                 pins = "gpio129", "gpio130",
4344                                        "gpio131";
4345                                 function = "qup10";
4346                         };
4347
4348                         qup_spi11_cs: qup-spi11-cs {
4349                                 pins = "gpio63";
4350                                 function = "qup11";
4351                         };
4352
4353                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
4354                                 pins = "gpio63";
4355                                 function = "gpio";
4356                         };
4357
4358                         qup_spi11_data_clk: qup-spi11-data-clk {
4359                                 pins = "gpio60", "gpio61",
4360                                        "gpio62";
4361                                 function = "qup11";
4362                         };
4363
4364                         qup_spi12_cs: qup-spi12-cs {
4365                                 pins = "gpio35";
4366                                 function = "qup12";
4367                         };
4368
4369                         qup_spi12_cs_gpio: qup-spi12-cs-gpio {
4370                                 pins = "gpio35";
4371                                 function = "gpio";
4372                         };
4373
4374                         qup_spi12_data_clk: qup-spi12-data-clk {
4375                                 pins = "gpio32", "gpio33",
4376                                        "gpio34";
4377                                 function = "qup12";
4378                         };
4379
4380                         qup_spi13_cs: qup-spi13-cs {
4381                                 pins = "gpio39";
4382                                 function = "qup13";
4383                         };
4384
4385                         qup_spi13_cs_gpio: qup-spi13-cs-gpio {
4386                                 pins = "gpio39";
4387                                 function = "gpio";
4388                         };
4389
4390                         qup_spi13_data_clk: qup-spi13-data-clk {
4391                                 pins = "gpio36", "gpio37",
4392                                        "gpio38";
4393                                 function = "qup13";
4394                         };
4395
4396                         qup_spi14_cs: qup-spi14-cs {
4397                                 pins = "gpio43";
4398                                 function = "qup14";
4399                         };
4400
4401                         qup_spi14_cs_gpio: qup-spi14-cs-gpio {
4402                                 pins = "gpio43";
4403                                 function = "gpio";
4404                         };
4405
4406                         qup_spi14_data_clk: qup-spi14-data-clk {
4407                                 pins = "gpio40", "gpio41",
4408                                        "gpio42";
4409                                 function = "qup14";
4410                         };
4411
4412                         qup_spi15_cs: qup-spi15-cs {
4413                                 pins = "gpio47";
4414                                 function = "qup15";
4415                         };
4416
4417                         qup_spi15_cs_gpio: qup-spi15-cs-gpio {
4418                                 pins = "gpio47";
4419                                 function = "gpio";
4420                         };
4421
4422                         qup_spi15_data_clk: qup-spi15-data-clk {
4423                                 pins = "gpio44", "gpio45",
4424                                        "gpio46";
4425                                 function = "qup15";
4426                         };
4427
4428                         qup_spi16_cs: qup-spi16-cs {
4429                                 pins = "gpio51";
4430                                 function = "qup16";
4431                         };
4432
4433                         qup_spi16_cs_gpio: qup-spi16-cs-gpio {
4434                                 pins = "gpio51";
4435                                 function = "gpio";
4436                         };
4437
4438                         qup_spi16_data_clk: qup-spi16-data-clk {
4439                                 pins = "gpio48", "gpio49",
4440                                        "gpio50";
4441                                 function = "qup16";
4442                         };
4443
4444                         qup_spi17_cs: qup-spi17-cs {
4445                                 pins = "gpio55";
4446                                 function = "qup17";
4447                         };
4448
4449                         qup_spi17_cs_gpio: qup-spi17-cs-gpio {
4450                                 pins = "gpio55";
4451                                 function = "gpio";
4452                         };
4453
4454                         qup_spi17_data_clk: qup-spi17-data-clk {
4455                                 pins = "gpio52", "gpio53",
4456                                        "gpio54";
4457                                 function = "qup17";
4458                         };
4459
4460                         qup_spi18_cs: qup-spi18-cs {
4461                                 pins = "gpio59";
4462                                 function = "qup18";
4463                         };
4464
4465                         qup_spi18_cs_gpio: qup-spi18-cs-gpio {
4466                                 pins = "gpio59";
4467                                 function = "gpio";
4468                         };
4469
4470                         qup_spi18_data_clk: qup-spi18-data-clk {
4471                                 pins = "gpio56", "gpio57",
4472                                        "gpio58";
4473                                 function = "qup18";
4474                         };
4475
4476                         qup_spi19_cs: qup-spi19-cs {
4477                                 pins = "gpio3";
4478                                 function = "qup19";
4479                         };
4480
4481                         qup_spi19_cs_gpio: qup-spi19-cs-gpio {
4482                                 pins = "gpio3";
4483                                 function = "gpio";
4484                         };
4485
4486                         qup_spi19_data_clk: qup-spi19-data-clk {
4487                                 pins = "gpio0", "gpio1",
4488                                        "gpio2";
4489                                 function = "qup19";
4490                         };
4491
4492                         qup_uart2_default: qup-uart2-default {
4493                                 mux {
4494                                         pins = "gpio117", "gpio118";
4495                                         function = "qup2";
4496                                 };
4497                         };
4498
4499                         qup_uart6_default: qup-uart6-default {
4500                                 mux {
4501                                         pins = "gpio16", "gpio17",
4502                                                 "gpio18", "gpio19";
4503                                         function = "qup6";
4504                                 };
4505                         };
4506
4507                         qup_uart12_default: qup-uart12-default {
4508                                 mux {
4509                                         pins = "gpio34", "gpio35";
4510                                         function = "qup12";
4511                                 };
4512                         };
4513
4514                         qup_uart17_default: qup-uart17-default {
4515                                 mux {
4516                                         pins = "gpio52", "gpio53",
4517                                                 "gpio54", "gpio55";
4518                                         function = "qup17";
4519                                 };
4520                         };
4521
4522                         qup_uart18_default: qup-uart18-default {
4523                                 mux {
4524                                         pins = "gpio58", "gpio59";
4525                                         function = "qup18";
4526                                 };
4527                         };
4528
4529                         tert_mi2s_active: tert-mi2s-active {
4530                                 sck {
4531                                         pins = "gpio133";
4532                                         function = "mi2s2_sck";
4533                                         drive-strength = <8>;
4534                                         bias-disable;
4535                                 };
4536
4537                                 data0 {
4538                                         pins = "gpio134";
4539                                         function = "mi2s2_data0";
4540                                         drive-strength = <8>;
4541                                         bias-disable;
4542                                         output-high;
4543                                 };
4544
4545                                 ws {
4546                                         pins = "gpio135";
4547                                         function = "mi2s2_ws";
4548                                         drive-strength = <8>;
4549                                         output-high;
4550                                 };
4551                         };
4552
4553                         sdc2_sleep_state: sdc2-sleep {
4554                                 clk {
4555                                         pins = "sdc2_clk";
4556                                         drive-strength = <2>;
4557                                         bias-disable;
4558                                 };
4559
4560                                 cmd {
4561                                         pins = "sdc2_cmd";
4562                                         drive-strength = <2>;
4563                                         bias-pull-up;
4564                                 };
4565
4566                                 data {
4567                                         pins = "sdc2_data";
4568                                         drive-strength = <2>;
4569                                         bias-pull-up;
4570                                 };
4571                         };
4572
4573                         pcie0_default_state: pcie0-default {
4574                                 perst {
4575                                         pins = "gpio79";
4576                                         function = "gpio";
4577                                         drive-strength = <2>;
4578                                         bias-pull-down;
4579                                 };
4580
4581                                 clkreq {
4582                                         pins = "gpio80";
4583                                         function = "pci_e0";
4584                                         drive-strength = <2>;
4585                                         bias-pull-up;
4586                                 };
4587
4588                                 wake {
4589                                         pins = "gpio81";
4590                                         function = "gpio";
4591                                         drive-strength = <2>;
4592                                         bias-pull-up;
4593                                 };
4594                         };
4595
4596                         pcie1_default_state: pcie1-default {
4597                                 perst {
4598                                         pins = "gpio82";
4599                                         function = "gpio";
4600                                         drive-strength = <2>;
4601                                         bias-pull-down;
4602                                 };
4603
4604                                 clkreq {
4605                                         pins = "gpio83";
4606                                         function = "pci_e1";
4607                                         drive-strength = <2>;
4608                                         bias-pull-up;
4609                                 };
4610
4611                                 wake {
4612                                         pins = "gpio84";
4613                                         function = "gpio";
4614                                         drive-strength = <2>;
4615                                         bias-pull-up;
4616                                 };
4617                         };
4618
4619                         pcie2_default_state: pcie2-default {
4620                                 perst {
4621                                         pins = "gpio85";
4622                                         function = "gpio";
4623                                         drive-strength = <2>;
4624                                         bias-pull-down;
4625                                 };
4626
4627                                 clkreq {
4628                                         pins = "gpio86";
4629                                         function = "pci_e2";
4630                                         drive-strength = <2>;
4631                                         bias-pull-up;
4632                                 };
4633
4634                                 wake {
4635                                         pins = "gpio87";
4636                                         function = "gpio";
4637                                         drive-strength = <2>;
4638                                         bias-pull-up;
4639                                 };
4640                         };
4641                 };
4642
4643                 apps_smmu: iommu@15000000 {
4644                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
4645                         reg = <0 0x15000000 0 0x100000>;
4646                         #iommu-cells = <2>;
4647                         #global-interrupts = <2>;
4648                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4649                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4650                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4651                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4652                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4653                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4654                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4655                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4656                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4657                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4658                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4659                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4660                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4661                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4662                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4663                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4664                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4665                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4666                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4667                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4668                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4669                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4670                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4671                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4672                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4673                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4674                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4675                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4676                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4677                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4678                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4679                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4680                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4681                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4682                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4683                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4684                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4685                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4686                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4687                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4688                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4689                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4690                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4691                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4692                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4693                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4694                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4695                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4696                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4697                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4698                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4699                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4700                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4701                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4702                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4703                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4704                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4705                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4706                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4707                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4708                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4709                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4710                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4711                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4712                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4713                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4714                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4715                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4716                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4717                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4718                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4719                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4720                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4721                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4722                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4723                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4724                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4725                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4726                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4727                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4728                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4729                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4730                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4731                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4732                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4733                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4734                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4735                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4736                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4737                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4738                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4739                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4740                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4741                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4742                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4743                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4744                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
4745                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
4746                 };
4747
4748                 adsp: remoteproc@17300000 {
4749                         compatible = "qcom,sm8250-adsp-pas";
4750                         reg = <0 0x17300000 0 0x100>;
4751
4752                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
4753                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4754                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4755                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4756                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4757                         interrupt-names = "wdog", "fatal", "ready",
4758                                           "handover", "stop-ack";
4759
4760                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4761                         clock-names = "xo";
4762
4763                         power-domains = <&rpmhpd SM8250_LCX>,
4764                                         <&rpmhpd SM8250_LMX>;
4765                         power-domain-names = "lcx", "lmx";
4766
4767                         memory-region = <&adsp_mem>;
4768
4769                         qcom,qmp = <&aoss_qmp>;
4770
4771                         qcom,smem-states = <&smp2p_adsp_out 0>;
4772                         qcom,smem-state-names = "stop";
4773
4774                         status = "disabled";
4775
4776                         glink-edge {
4777                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4778                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4779                                                              IRQ_TYPE_EDGE_RISING>;
4780                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
4781                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4782
4783                                 label = "lpass";
4784                                 qcom,remote-pid = <2>;
4785
4786                                 apr {
4787                                         compatible = "qcom,apr-v2";
4788                                         qcom,glink-channels = "apr_audio_svc";
4789                                         qcom,domain = <APR_DOMAIN_ADSP>;
4790                                         #address-cells = <1>;
4791                                         #size-cells = <0>;
4792
4793                                         apr-service@3 {
4794                                                 reg = <APR_SVC_ADSP_CORE>;
4795                                                 compatible = "qcom,q6core";
4796                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4797                                         };
4798
4799                                         q6afe: apr-service@4 {
4800                                                 compatible = "qcom,q6afe";
4801                                                 reg = <APR_SVC_AFE>;
4802                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4803                                                 q6afedai: dais {
4804                                                         compatible = "qcom,q6afe-dais";
4805                                                         #address-cells = <1>;
4806                                                         #size-cells = <0>;
4807                                                         #sound-dai-cells = <1>;
4808                                                 };
4809
4810                                                 q6afecc: cc {
4811                                                         compatible = "qcom,q6afe-clocks";
4812                                                         #clock-cells = <2>;
4813                                                 };
4814                                         };
4815
4816                                         q6asm: apr-service@7 {
4817                                                 compatible = "qcom,q6asm";
4818                                                 reg = <APR_SVC_ASM>;
4819                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4820                                                 q6asmdai: dais {
4821                                                         compatible = "qcom,q6asm-dais";
4822                                                         #address-cells = <1>;
4823                                                         #size-cells = <0>;
4824                                                         #sound-dai-cells = <1>;
4825                                                         iommus = <&apps_smmu 0x1801 0x0>;
4826                                                 };
4827                                         };
4828
4829                                         q6adm: apr-service@8 {
4830                                                 compatible = "qcom,q6adm";
4831                                                 reg = <APR_SVC_ADM>;
4832                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
4833                                                 q6routing: routing {
4834                                                         compatible = "qcom,q6adm-routing";
4835                                                         #sound-dai-cells = <0>;
4836                                                 };
4837                                         };
4838                                 };
4839
4840                                 fastrpc {
4841                                         compatible = "qcom,fastrpc";
4842                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4843                                         label = "adsp";
4844                                         qcom,non-secure-domain;
4845                                         #address-cells = <1>;
4846                                         #size-cells = <0>;
4847
4848                                         compute-cb@3 {
4849                                                 compatible = "qcom,fastrpc-compute-cb";
4850                                                 reg = <3>;
4851                                                 iommus = <&apps_smmu 0x1803 0x0>;
4852                                         };
4853
4854                                         compute-cb@4 {
4855                                                 compatible = "qcom,fastrpc-compute-cb";
4856                                                 reg = <4>;
4857                                                 iommus = <&apps_smmu 0x1804 0x0>;
4858                                         };
4859
4860                                         compute-cb@5 {
4861                                                 compatible = "qcom,fastrpc-compute-cb";
4862                                                 reg = <5>;
4863                                                 iommus = <&apps_smmu 0x1805 0x0>;
4864                                         };
4865                                 };
4866                         };
4867                 };
4868
4869                 intc: interrupt-controller@17a00000 {
4870                         compatible = "arm,gic-v3";
4871                         #interrupt-cells = <3>;
4872                         interrupt-controller;
4873                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4874                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4875                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4876                 };
4877
4878                 watchdog@17c10000 {
4879                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
4880                         reg = <0 0x17c10000 0 0x1000>;
4881                         clocks = <&sleep_clk>;
4882                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4883                 };
4884
4885                 timer@17c20000 {
4886                         #address-cells = <1>;
4887                         #size-cells = <1>;
4888                         ranges = <0 0 0 0x20000000>;
4889                         compatible = "arm,armv7-timer-mem";
4890                         reg = <0x0 0x17c20000 0x0 0x1000>;
4891                         clock-frequency = <19200000>;
4892
4893                         frame@17c21000 {
4894                                 frame-number = <0>;
4895                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4896                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4897                                 reg = <0x17c21000 0x1000>,
4898                                       <0x17c22000 0x1000>;
4899                         };
4900
4901                         frame@17c23000 {
4902                                 frame-number = <1>;
4903                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4904                                 reg = <0x17c23000 0x1000>;
4905                                 status = "disabled";
4906                         };
4907
4908                         frame@17c25000 {
4909                                 frame-number = <2>;
4910                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4911                                 reg = <0x17c25000 0x1000>;
4912                                 status = "disabled";
4913                         };
4914
4915                         frame@17c27000 {
4916                                 frame-number = <3>;
4917                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4918                                 reg = <0x17c27000 0x1000>;
4919                                 status = "disabled";
4920                         };
4921
4922                         frame@17c29000 {
4923                                 frame-number = <4>;
4924                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4925                                 reg = <0x17c29000 0x1000>;
4926                                 status = "disabled";
4927                         };
4928
4929                         frame@17c2b000 {
4930                                 frame-number = <5>;
4931                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4932                                 reg = <0x17c2b000 0x1000>;
4933                                 status = "disabled";
4934                         };
4935
4936                         frame@17c2d000 {
4937                                 frame-number = <6>;
4938                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4939                                 reg = <0x17c2d000 0x1000>;
4940                                 status = "disabled";
4941                         };
4942                 };
4943
4944                 apps_rsc: rsc@18200000 {
4945                         label = "apps_rsc";
4946                         compatible = "qcom,rpmh-rsc";
4947                         reg = <0x0 0x18200000 0x0 0x10000>,
4948                                 <0x0 0x18210000 0x0 0x10000>,
4949                                 <0x0 0x18220000 0x0 0x10000>;
4950                         reg-names = "drv-0", "drv-1", "drv-2";
4951                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4952                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4953                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4954                         qcom,tcs-offset = <0xd00>;
4955                         qcom,drv-id = <2>;
4956                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
4957                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
4958
4959                         rpmhcc: clock-controller {
4960                                 compatible = "qcom,sm8250-rpmh-clk";
4961                                 #clock-cells = <1>;
4962                                 clock-names = "xo";
4963                                 clocks = <&xo_board>;
4964                         };
4965
4966                         rpmhpd: power-controller {
4967                                 compatible = "qcom,sm8250-rpmhpd";
4968                                 #power-domain-cells = <1>;
4969                                 operating-points-v2 = <&rpmhpd_opp_table>;
4970
4971                                 rpmhpd_opp_table: opp-table {
4972                                         compatible = "operating-points-v2";
4973
4974                                         rpmhpd_opp_ret: opp1 {
4975                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4976                                         };
4977
4978                                         rpmhpd_opp_min_svs: opp2 {
4979                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4980                                         };
4981
4982                                         rpmhpd_opp_low_svs: opp3 {
4983                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4984                                         };
4985
4986                                         rpmhpd_opp_svs: opp4 {
4987                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4988                                         };
4989
4990                                         rpmhpd_opp_svs_l1: opp5 {
4991                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4992                                         };
4993
4994                                         rpmhpd_opp_nom: opp6 {
4995                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4996                                         };
4997
4998                                         rpmhpd_opp_nom_l1: opp7 {
4999                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5000                                         };
5001
5002                                         rpmhpd_opp_nom_l2: opp8 {
5003                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5004                                         };
5005
5006                                         rpmhpd_opp_turbo: opp9 {
5007                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5008                                         };
5009
5010                                         rpmhpd_opp_turbo_l1: opp10 {
5011                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5012                                         };
5013                                 };
5014                         };
5015
5016                         apps_bcm_voter: bcm-voter {
5017                                 compatible = "qcom,bcm-voter";
5018                         };
5019                 };
5020
5021                 epss_l3: interconnect@18590000 {
5022                         compatible = "qcom,sm8250-epss-l3";
5023                         reg = <0 0x18590000 0 0x1000>;
5024
5025                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5026                         clock-names = "xo", "alternate";
5027
5028                         #interconnect-cells = <1>;
5029                 };
5030
5031                 cpufreq_hw: cpufreq@18591000 {
5032                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5033                         reg = <0 0x18591000 0 0x1000>,
5034                               <0 0x18592000 0 0x1000>,
5035                               <0 0x18593000 0 0x1000>;
5036                         reg-names = "freq-domain0", "freq-domain1",
5037                                     "freq-domain2";
5038
5039                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5040                         clock-names = "xo", "alternate";
5041                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5042                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5043                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5044                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5045                         #freq-domain-cells = <1>;
5046                 };
5047         };
5048
5049         timer {
5050                 compatible = "arm,armv8-timer";
5051                 interrupts = <GIC_PPI 13
5052                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5053                              <GIC_PPI 14
5054                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5055                              <GIC_PPI 11
5056                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5057                              <GIC_PPI 10
5058                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5059         };
5060
5061         thermal-zones {
5062                 cpu0-thermal {
5063                         polling-delay-passive = <250>;
5064                         polling-delay = <1000>;
5065
5066                         thermal-sensors = <&tsens0 1>;
5067
5068                         trips {
5069                                 cpu0_alert0: trip-point0 {
5070                                         temperature = <90000>;
5071                                         hysteresis = <2000>;
5072                                         type = "passive";
5073                                 };
5074
5075                                 cpu0_alert1: trip-point1 {
5076                                         temperature = <95000>;
5077                                         hysteresis = <2000>;
5078                                         type = "passive";
5079                                 };
5080
5081                                 cpu0_crit: cpu_crit {
5082                                         temperature = <110000>;
5083                                         hysteresis = <1000>;
5084                                         type = "critical";
5085                                 };
5086                         };
5087
5088                         cooling-maps {
5089                                 map0 {
5090                                         trip = <&cpu0_alert0>;
5091                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5092                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5093                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5094                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5095                                 };
5096                                 map1 {
5097                                         trip = <&cpu0_alert1>;
5098                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5099                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5100                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5101                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5102                                 };
5103                         };
5104                 };
5105
5106                 cpu1-thermal {
5107                         polling-delay-passive = <250>;
5108                         polling-delay = <1000>;
5109
5110                         thermal-sensors = <&tsens0 2>;
5111
5112                         trips {
5113                                 cpu1_alert0: trip-point0 {
5114                                         temperature = <90000>;
5115                                         hysteresis = <2000>;
5116                                         type = "passive";
5117                                 };
5118
5119                                 cpu1_alert1: trip-point1 {
5120                                         temperature = <95000>;
5121                                         hysteresis = <2000>;
5122                                         type = "passive";
5123                                 };
5124
5125                                 cpu1_crit: cpu_crit {
5126                                         temperature = <110000>;
5127                                         hysteresis = <1000>;
5128                                         type = "critical";
5129                                 };
5130                         };
5131
5132                         cooling-maps {
5133                                 map0 {
5134                                         trip = <&cpu1_alert0>;
5135                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5136                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5137                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5138                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5139                                 };
5140                                 map1 {
5141                                         trip = <&cpu1_alert1>;
5142                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5143                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5144                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5145                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5146                                 };
5147                         };
5148                 };
5149
5150                 cpu2-thermal {
5151                         polling-delay-passive = <250>;
5152                         polling-delay = <1000>;
5153
5154                         thermal-sensors = <&tsens0 3>;
5155
5156                         trips {
5157                                 cpu2_alert0: trip-point0 {
5158                                         temperature = <90000>;
5159                                         hysteresis = <2000>;
5160                                         type = "passive";
5161                                 };
5162
5163                                 cpu2_alert1: trip-point1 {
5164                                         temperature = <95000>;
5165                                         hysteresis = <2000>;
5166                                         type = "passive";
5167                                 };
5168
5169                                 cpu2_crit: cpu_crit {
5170                                         temperature = <110000>;
5171                                         hysteresis = <1000>;
5172                                         type = "critical";
5173                                 };
5174                         };
5175
5176                         cooling-maps {
5177                                 map0 {
5178                                         trip = <&cpu2_alert0>;
5179                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5180                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5181                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5182                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5183                                 };
5184                                 map1 {
5185                                         trip = <&cpu2_alert1>;
5186                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5187                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5188                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5189                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5190                                 };
5191                         };
5192                 };
5193
5194                 cpu3-thermal {
5195                         polling-delay-passive = <250>;
5196                         polling-delay = <1000>;
5197
5198                         thermal-sensors = <&tsens0 4>;
5199
5200                         trips {
5201                                 cpu3_alert0: trip-point0 {
5202                                         temperature = <90000>;
5203                                         hysteresis = <2000>;
5204                                         type = "passive";
5205                                 };
5206
5207                                 cpu3_alert1: trip-point1 {
5208                                         temperature = <95000>;
5209                                         hysteresis = <2000>;
5210                                         type = "passive";
5211                                 };
5212
5213                                 cpu3_crit: cpu_crit {
5214                                         temperature = <110000>;
5215                                         hysteresis = <1000>;
5216                                         type = "critical";
5217                                 };
5218                         };
5219
5220                         cooling-maps {
5221                                 map0 {
5222                                         trip = <&cpu3_alert0>;
5223                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5224                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5225                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5226                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5227                                 };
5228                                 map1 {
5229                                         trip = <&cpu3_alert1>;
5230                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5231                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5232                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5233                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5234                                 };
5235                         };
5236                 };
5237
5238                 cpu4-top-thermal {
5239                         polling-delay-passive = <250>;
5240                         polling-delay = <1000>;
5241
5242                         thermal-sensors = <&tsens0 7>;
5243
5244                         trips {
5245                                 cpu4_top_alert0: trip-point0 {
5246                                         temperature = <90000>;
5247                                         hysteresis = <2000>;
5248                                         type = "passive";
5249                                 };
5250
5251                                 cpu4_top_alert1: trip-point1 {
5252                                         temperature = <95000>;
5253                                         hysteresis = <2000>;
5254                                         type = "passive";
5255                                 };
5256
5257                                 cpu4_top_crit: cpu_crit {
5258                                         temperature = <110000>;
5259                                         hysteresis = <1000>;
5260                                         type = "critical";
5261                                 };
5262                         };
5263
5264                         cooling-maps {
5265                                 map0 {
5266                                         trip = <&cpu4_top_alert0>;
5267                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5268                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5269                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5270                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5271                                 };
5272                                 map1 {
5273                                         trip = <&cpu4_top_alert1>;
5274                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5275                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5276                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5277                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5278                                 };
5279                         };
5280                 };
5281
5282                 cpu5-top-thermal {
5283                         polling-delay-passive = <250>;
5284                         polling-delay = <1000>;
5285
5286                         thermal-sensors = <&tsens0 8>;
5287
5288                         trips {
5289                                 cpu5_top_alert0: trip-point0 {
5290                                         temperature = <90000>;
5291                                         hysteresis = <2000>;
5292                                         type = "passive";
5293                                 };
5294
5295                                 cpu5_top_alert1: trip-point1 {
5296                                         temperature = <95000>;
5297                                         hysteresis = <2000>;
5298                                         type = "passive";
5299                                 };
5300
5301                                 cpu5_top_crit: cpu_crit {
5302                                         temperature = <110000>;
5303                                         hysteresis = <1000>;
5304                                         type = "critical";
5305                                 };
5306                         };
5307
5308                         cooling-maps {
5309                                 map0 {
5310                                         trip = <&cpu5_top_alert0>;
5311                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5312                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5313                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5314                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5315                                 };
5316                                 map1 {
5317                                         trip = <&cpu5_top_alert1>;
5318                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5319                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5320                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5321                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5322                                 };
5323                         };
5324                 };
5325
5326                 cpu6-top-thermal {
5327                         polling-delay-passive = <250>;
5328                         polling-delay = <1000>;
5329
5330                         thermal-sensors = <&tsens0 9>;
5331
5332                         trips {
5333                                 cpu6_top_alert0: trip-point0 {
5334                                         temperature = <90000>;
5335                                         hysteresis = <2000>;
5336                                         type = "passive";
5337                                 };
5338
5339                                 cpu6_top_alert1: trip-point1 {
5340                                         temperature = <95000>;
5341                                         hysteresis = <2000>;
5342                                         type = "passive";
5343                                 };
5344
5345                                 cpu6_top_crit: cpu_crit {
5346                                         temperature = <110000>;
5347                                         hysteresis = <1000>;
5348                                         type = "critical";
5349                                 };
5350                         };
5351
5352                         cooling-maps {
5353                                 map0 {
5354                                         trip = <&cpu6_top_alert0>;
5355                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5356                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5357                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5358                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5359                                 };
5360                                 map1 {
5361                                         trip = <&cpu6_top_alert1>;
5362                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5363                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5364                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5365                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5366                                 };
5367                         };
5368                 };
5369
5370                 cpu7-top-thermal {
5371                         polling-delay-passive = <250>;
5372                         polling-delay = <1000>;
5373
5374                         thermal-sensors = <&tsens0 10>;
5375
5376                         trips {
5377                                 cpu7_top_alert0: trip-point0 {
5378                                         temperature = <90000>;
5379                                         hysteresis = <2000>;
5380                                         type = "passive";
5381                                 };
5382
5383                                 cpu7_top_alert1: trip-point1 {
5384                                         temperature = <95000>;
5385                                         hysteresis = <2000>;
5386                                         type = "passive";
5387                                 };
5388
5389                                 cpu7_top_crit: cpu_crit {
5390                                         temperature = <110000>;
5391                                         hysteresis = <1000>;
5392                                         type = "critical";
5393                                 };
5394                         };
5395
5396                         cooling-maps {
5397                                 map0 {
5398                                         trip = <&cpu7_top_alert0>;
5399                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5400                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5401                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5402                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5403                                 };
5404                                 map1 {
5405                                         trip = <&cpu7_top_alert1>;
5406                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5407                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5408                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5409                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5410                                 };
5411                         };
5412                 };
5413
5414                 cpu4-bottom-thermal {
5415                         polling-delay-passive = <250>;
5416                         polling-delay = <1000>;
5417
5418                         thermal-sensors = <&tsens0 11>;
5419
5420                         trips {
5421                                 cpu4_bottom_alert0: trip-point0 {
5422                                         temperature = <90000>;
5423                                         hysteresis = <2000>;
5424                                         type = "passive";
5425                                 };
5426
5427                                 cpu4_bottom_alert1: trip-point1 {
5428                                         temperature = <95000>;
5429                                         hysteresis = <2000>;
5430                                         type = "passive";
5431                                 };
5432
5433                                 cpu4_bottom_crit: cpu_crit {
5434                                         temperature = <110000>;
5435                                         hysteresis = <1000>;
5436                                         type = "critical";
5437                                 };
5438                         };
5439
5440                         cooling-maps {
5441                                 map0 {
5442                                         trip = <&cpu4_bottom_alert0>;
5443                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5444                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5445                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5446                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5447                                 };
5448                                 map1 {
5449                                         trip = <&cpu4_bottom_alert1>;
5450                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5451                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5452                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5453                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5454                                 };
5455                         };
5456                 };
5457
5458                 cpu5-bottom-thermal {
5459                         polling-delay-passive = <250>;
5460                         polling-delay = <1000>;
5461
5462                         thermal-sensors = <&tsens0 12>;
5463
5464                         trips {
5465                                 cpu5_bottom_alert0: trip-point0 {
5466                                         temperature = <90000>;
5467                                         hysteresis = <2000>;
5468                                         type = "passive";
5469                                 };
5470
5471                                 cpu5_bottom_alert1: trip-point1 {
5472                                         temperature = <95000>;
5473                                         hysteresis = <2000>;
5474                                         type = "passive";
5475                                 };
5476
5477                                 cpu5_bottom_crit: cpu_crit {
5478                                         temperature = <110000>;
5479                                         hysteresis = <1000>;
5480                                         type = "critical";
5481                                 };
5482                         };
5483
5484                         cooling-maps {
5485                                 map0 {
5486                                         trip = <&cpu5_bottom_alert0>;
5487                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5488                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5489                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5490                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5491                                 };
5492                                 map1 {
5493                                         trip = <&cpu5_bottom_alert1>;
5494                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5495                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5496                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5497                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5498                                 };
5499                         };
5500                 };
5501
5502                 cpu6-bottom-thermal {
5503                         polling-delay-passive = <250>;
5504                         polling-delay = <1000>;
5505
5506                         thermal-sensors = <&tsens0 13>;
5507
5508                         trips {
5509                                 cpu6_bottom_alert0: trip-point0 {
5510                                         temperature = <90000>;
5511                                         hysteresis = <2000>;
5512                                         type = "passive";
5513                                 };
5514
5515                                 cpu6_bottom_alert1: trip-point1 {
5516                                         temperature = <95000>;
5517                                         hysteresis = <2000>;
5518                                         type = "passive";
5519                                 };
5520
5521                                 cpu6_bottom_crit: cpu_crit {
5522                                         temperature = <110000>;
5523                                         hysteresis = <1000>;
5524                                         type = "critical";
5525                                 };
5526                         };
5527
5528                         cooling-maps {
5529                                 map0 {
5530                                         trip = <&cpu6_bottom_alert0>;
5531                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5532                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5533                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5534                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5535                                 };
5536                                 map1 {
5537                                         trip = <&cpu6_bottom_alert1>;
5538                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5539                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5540                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5541                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5542                                 };
5543                         };
5544                 };
5545
5546                 cpu7-bottom-thermal {
5547                         polling-delay-passive = <250>;
5548                         polling-delay = <1000>;
5549
5550                         thermal-sensors = <&tsens0 14>;
5551
5552                         trips {
5553                                 cpu7_bottom_alert0: trip-point0 {
5554                                         temperature = <90000>;
5555                                         hysteresis = <2000>;
5556                                         type = "passive";
5557                                 };
5558
5559                                 cpu7_bottom_alert1: trip-point1 {
5560                                         temperature = <95000>;
5561                                         hysteresis = <2000>;
5562                                         type = "passive";
5563                                 };
5564
5565                                 cpu7_bottom_crit: cpu_crit {
5566                                         temperature = <110000>;
5567                                         hysteresis = <1000>;
5568                                         type = "critical";
5569                                 };
5570                         };
5571
5572                         cooling-maps {
5573                                 map0 {
5574                                         trip = <&cpu7_bottom_alert0>;
5575                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5576                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5577                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5578                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5579                                 };
5580                                 map1 {
5581                                         trip = <&cpu7_bottom_alert1>;
5582                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5583                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5584                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5585                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5586                                 };
5587                         };
5588                 };
5589
5590                 aoss0-thermal {
5591                         polling-delay-passive = <250>;
5592                         polling-delay = <1000>;
5593
5594                         thermal-sensors = <&tsens0 0>;
5595
5596                         trips {
5597                                 aoss0_alert0: trip-point0 {
5598                                         temperature = <90000>;
5599                                         hysteresis = <2000>;
5600                                         type = "hot";
5601                                 };
5602                         };
5603                 };
5604
5605                 cluster0-thermal {
5606                         polling-delay-passive = <250>;
5607                         polling-delay = <1000>;
5608
5609                         thermal-sensors = <&tsens0 5>;
5610
5611                         trips {
5612                                 cluster0_alert0: trip-point0 {
5613                                         temperature = <90000>;
5614                                         hysteresis = <2000>;
5615                                         type = "hot";
5616                                 };
5617                                 cluster0_crit: cluster0_crit {
5618                                         temperature = <110000>;
5619                                         hysteresis = <2000>;
5620                                         type = "critical";
5621                                 };
5622                         };
5623                 };
5624
5625                 cluster1-thermal {
5626                         polling-delay-passive = <250>;
5627                         polling-delay = <1000>;
5628
5629                         thermal-sensors = <&tsens0 6>;
5630
5631                         trips {
5632                                 cluster1_alert0: trip-point0 {
5633                                         temperature = <90000>;
5634                                         hysteresis = <2000>;
5635                                         type = "hot";
5636                                 };
5637                                 cluster1_crit: cluster1_crit {
5638                                         temperature = <110000>;
5639                                         hysteresis = <2000>;
5640                                         type = "critical";
5641                                 };
5642                         };
5643                 };
5644
5645                 gpu-top-thermal {
5646                         polling-delay-passive = <250>;
5647                         polling-delay = <1000>;
5648
5649                         thermal-sensors = <&tsens0 15>;
5650
5651                         trips {
5652                                 gpu1_alert0: trip-point0 {
5653                                         temperature = <90000>;
5654                                         hysteresis = <2000>;
5655                                         type = "hot";
5656                                 };
5657                         };
5658                 };
5659
5660                 aoss1-thermal {
5661                         polling-delay-passive = <250>;
5662                         polling-delay = <1000>;
5663
5664                         thermal-sensors = <&tsens1 0>;
5665
5666                         trips {
5667                                 aoss1_alert0: trip-point0 {
5668                                         temperature = <90000>;
5669                                         hysteresis = <2000>;
5670                                         type = "hot";
5671                                 };
5672                         };
5673                 };
5674
5675                 wlan-thermal {
5676                         polling-delay-passive = <250>;
5677                         polling-delay = <1000>;
5678
5679                         thermal-sensors = <&tsens1 1>;
5680
5681                         trips {
5682                                 wlan_alert0: trip-point0 {
5683                                         temperature = <90000>;
5684                                         hysteresis = <2000>;
5685                                         type = "hot";
5686                                 };
5687                         };
5688                 };
5689
5690                 video-thermal {
5691                         polling-delay-passive = <250>;
5692                         polling-delay = <1000>;
5693
5694                         thermal-sensors = <&tsens1 2>;
5695
5696                         trips {
5697                                 video_alert0: trip-point0 {
5698                                         temperature = <90000>;
5699                                         hysteresis = <2000>;
5700                                         type = "hot";
5701                                 };
5702                         };
5703                 };
5704
5705                 mem-thermal {
5706                         polling-delay-passive = <250>;
5707                         polling-delay = <1000>;
5708
5709                         thermal-sensors = <&tsens1 3>;
5710
5711                         trips {
5712                                 mem_alert0: trip-point0 {
5713                                         temperature = <90000>;
5714                                         hysteresis = <2000>;
5715                                         type = "hot";
5716                                 };
5717                         };
5718                 };
5719
5720                 q6-hvx-thermal {
5721                         polling-delay-passive = <250>;
5722                         polling-delay = <1000>;
5723
5724                         thermal-sensors = <&tsens1 4>;
5725
5726                         trips {
5727                                 q6_hvx_alert0: trip-point0 {
5728                                         temperature = <90000>;
5729                                         hysteresis = <2000>;
5730                                         type = "hot";
5731                                 };
5732                         };
5733                 };
5734
5735                 camera-thermal {
5736                         polling-delay-passive = <250>;
5737                         polling-delay = <1000>;
5738
5739                         thermal-sensors = <&tsens1 5>;
5740
5741                         trips {
5742                                 camera_alert0: trip-point0 {
5743                                         temperature = <90000>;
5744                                         hysteresis = <2000>;
5745                                         type = "hot";
5746                                 };
5747                         };
5748                 };
5749
5750                 compute-thermal {
5751                         polling-delay-passive = <250>;
5752                         polling-delay = <1000>;
5753
5754                         thermal-sensors = <&tsens1 6>;
5755
5756                         trips {
5757                                 compute_alert0: trip-point0 {
5758                                         temperature = <90000>;
5759                                         hysteresis = <2000>;
5760                                         type = "hot";
5761                                 };
5762                         };
5763                 };
5764
5765                 npu-thermal {
5766                         polling-delay-passive = <250>;
5767                         polling-delay = <1000>;
5768
5769                         thermal-sensors = <&tsens1 7>;
5770
5771                         trips {
5772                                 npu_alert0: trip-point0 {
5773                                         temperature = <90000>;
5774                                         hysteresis = <2000>;
5775                                         type = "hot";
5776                                 };
5777                         };
5778                 };
5779
5780                 gpu-bottom-thermal {
5781                         polling-delay-passive = <250>;
5782                         polling-delay = <1000>;
5783
5784                         thermal-sensors = <&tsens1 8>;
5785
5786                         trips {
5787                                 gpu2_alert0: trip-point0 {
5788                                         temperature = <90000>;
5789                                         hysteresis = <2000>;
5790                                         type = "hot";
5791                                 };
5792                         };
5793                 };
5794         };
5795 };