arch/arm64/boot/dts/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/dma/qcom-gpi.h>
   8 #include <dt-bindings/firmware/qcom,scm.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/phy/phy-qcom-qmp.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
  15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  18 #include <dt-bindings/interconnect/qcom,sm8150.h>
  19 #include <dt-bindings/thermal/thermal.h>
  20
  21 / {
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         chosen { };
  28
  29         clocks {
  30                 xo_board: xo-board {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <38400000>;
  34                         clock-output-names = "xo_board";
  35                 };
  36
  37                 sleep_clk: sleep-clk {
  38                         compatible = "fixed-clock";
  39                         #clock-cells = <0>;
  40                         clock-frequency = <32764>;
  41                         clock-output-names = "sleep_clk";
  42                 };
  43         };
  44
  45         cpus {
  46                 #address-cells = <2>;
  47                 #size-cells = <0>;
  48
  49                 CPU0: cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "qcom,kryo485";
  52                         reg = <0x0 0x0>;
  53                         clocks = <&cpufreq_hw 0>;
  54                         enable-method = "psci";
  55                         capacity-dmips-mhz = <488>;
  56                         dynamic-power-coefficient = <232>;
  57                         next-level-cache = <&L2_0>;
  58                         qcom,freq-domain = <&cpufreq_hw 0>;
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
  61                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  62                         power-domains = <&CPU_PD0>;
  63                         power-domain-names = "psci";
  64                         #cooling-cells = <2>;
  65                         L2_0: l2-cache {
  66                                 compatible = "cache";
  67                                 cache-level = <2>;
  68                                 cache-unified;
  69                                 next-level-cache = <&L3_0>;
  70                                 L3_0: l3-cache {
  71                                         compatible = "cache";
  72                                         cache-level = <3>;
  73                                         cache-unified;
  74                                 };
  75                         };
  76                 };
  77
  78                 CPU1: cpu@100 {
  79                         device_type = "cpu";
  80                         compatible = "qcom,kryo485";
  81                         reg = <0x0 0x100>;
  82                         clocks = <&cpufreq_hw 0>;
  83                         enable-method = "psci";
  84                         capacity-dmips-mhz = <488>;
  85                         dynamic-power-coefficient = <232>;
  86                         next-level-cache = <&L2_100>;
  87                         qcom,freq-domain = <&cpufreq_hw 0>;
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
  90                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  91                         power-domains = <&CPU_PD1>;
  92                         power-domain-names = "psci";
  93                         #cooling-cells = <2>;
  94                         L2_100: l2-cache {
  95                                 compatible = "cache";
  96                                 cache-level = <2>;
  97                                 cache-unified;
  98                                 next-level-cache = <&L3_0>;
  99                         };
 100                 };
 101
 102                 CPU2: cpu@200 {
 103                         device_type = "cpu";
 104                         compatible = "qcom,kryo485";
 105                         reg = <0x0 0x200>;
 106                         clocks = <&cpufreq_hw 0>;
 107                         enable-method = "psci";
 108                         capacity-dmips-mhz = <488>;
 109                         dynamic-power-coefficient = <232>;
 110                         next-level-cache = <&L2_200>;
 111                         qcom,freq-domain = <&cpufreq_hw 0>;
 112                         operating-points-v2 = <&cpu0_opp_table>;
 113                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 114                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 115                         power-domains = <&CPU_PD2>;
 116                         power-domain-names = "psci";
 117                         #cooling-cells = <2>;
 118                         L2_200: l2-cache {
 119                                 compatible = "cache";
 120                                 cache-level = <2>;
 121                                 cache-unified;
 122                                 next-level-cache = <&L3_0>;
 123                         };
 124                 };
 125
 126                 CPU3: cpu@300 {
 127                         device_type = "cpu";
 128                         compatible = "qcom,kryo485";
 129                         reg = <0x0 0x300>;
 130                         clocks = <&cpufreq_hw 0>;
 131                         enable-method = "psci";
 132                         capacity-dmips-mhz = <488>;
 133                         dynamic-power-coefficient = <232>;
 134                         next-level-cache = <&L2_300>;
 135                         qcom,freq-domain = <&cpufreq_hw 0>;
 136                         operating-points-v2 = <&cpu0_opp_table>;
 137                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 138                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 139                         power-domains = <&CPU_PD3>;
 140                         power-domain-names = "psci";
 141                         #cooling-cells = <2>;
 142                         L2_300: l2-cache {
 143                                 compatible = "cache";
 144                                 cache-level = <2>;
 145                                 cache-unified;
 146                                 next-level-cache = <&L3_0>;
 147                         };
 148                 };
 149
 150                 CPU4: cpu@400 {
 151                         device_type = "cpu";
 152                         compatible = "qcom,kryo485";
 153                         reg = <0x0 0x400>;
 154                         clocks = <&cpufreq_hw 1>;
 155                         enable-method = "psci";
 156                         capacity-dmips-mhz = <1024>;
 157                         dynamic-power-coefficient = <369>;
 158                         next-level-cache = <&L2_400>;
 159                         qcom,freq-domain = <&cpufreq_hw 1>;
 160                         operating-points-v2 = <&cpu4_opp_table>;
 161                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 162                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 163                         power-domains = <&CPU_PD4>;
 164                         power-domain-names = "psci";
 165                         #cooling-cells = <2>;
 166                         L2_400: l2-cache {
 167                                 compatible = "cache";
 168                                 cache-level = <2>;
 169                                 cache-unified;
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU5: cpu@500 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo485";
 177                         reg = <0x0 0x500>;
 178                         clocks = <&cpufreq_hw 1>;
 179                         enable-method = "psci";
 180                         capacity-dmips-mhz = <1024>;
 181                         dynamic-power-coefficient = <369>;
 182                         next-level-cache = <&L2_500>;
 183                         qcom,freq-domain = <&cpufreq_hw 1>;
 184                         operating-points-v2 = <&cpu4_opp_table>;
 185                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 186                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 187                         power-domains = <&CPU_PD5>;
 188                         power-domain-names = "psci";
 189                         #cooling-cells = <2>;
 190                         L2_500: l2-cache {
 191                                 compatible = "cache";
 192                                 cache-level = <2>;
 193                                 cache-unified;
 194                                 next-level-cache = <&L3_0>;
 195                         };
 196                 };
 197
 198                 CPU6: cpu@600 {
 199                         device_type = "cpu";
 200                         compatible = "qcom,kryo485";
 201                         reg = <0x0 0x600>;
 202                         clocks = <&cpufreq_hw 1>;
 203                         enable-method = "psci";
 204                         capacity-dmips-mhz = <1024>;
 205                         dynamic-power-coefficient = <369>;
 206                         next-level-cache = <&L2_600>;
 207                         qcom,freq-domain = <&cpufreq_hw 1>;
 208                         operating-points-v2 = <&cpu4_opp_table>;
 209                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 210                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 211                         power-domains = <&CPU_PD6>;
 212                         power-domain-names = "psci";
 213                         #cooling-cells = <2>;
 214                         L2_600: l2-cache {
 215                                 compatible = "cache";
 216                                 cache-level = <2>;
 217                                 cache-unified;
 218                                 next-level-cache = <&L3_0>;
 219                         };
 220                 };
 221
 222                 CPU7: cpu@700 {
 223                         device_type = "cpu";
 224                         compatible = "qcom,kryo485";
 225                         reg = <0x0 0x700>;
 226                         clocks = <&cpufreq_hw 2>;
 227                         enable-method = "psci";
 228                         capacity-dmips-mhz = <1024>;
 229                         dynamic-power-coefficient = <421>;
 230                         next-level-cache = <&L2_700>;
 231                         qcom,freq-domain = <&cpufreq_hw 2>;
 232                         operating-points-v2 = <&cpu7_opp_table>;
 233                         interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
 234                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 235                         power-domains = <&CPU_PD7>;
 236                         power-domain-names = "psci";
 237                         #cooling-cells = <2>;
 238                         L2_700: l2-cache {
 239                                 compatible = "cache";
 240                                 cache-level = <2>;
 241                                 cache-unified;
 242                                 next-level-cache = <&L3_0>;
 243                         };
 244                 };
 245
 246                 cpu-map {
 247                         cluster0 {
 248                                 core0 {
 249                                         cpu = <&CPU0>;
 250                                 };
 251
 252                                 core1 {
 253                                         cpu = <&CPU1>;
 254                                 };
 255
 256                                 core2 {
 257                                         cpu = <&CPU2>;
 258                                 };
 259
 260                                 core3 {
 261                                         cpu = <&CPU3>;
 262                                 };
 263
 264                                 core4 {
 265                                         cpu = <&CPU4>;
 266                                 };
 267
 268                                 core5 {
 269                                         cpu = <&CPU5>;
 270                                 };
 271
 272                                 core6 {
 273                                         cpu = <&CPU6>;
 274                                 };
 275
 276                                 core7 {
 277                                         cpu = <&CPU7>;
 278                                 };
 279                         };
 280                 };
 281
 282                 idle-states {
 283                         entry-method = "psci";
 284
 285                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 286                                 compatible = "arm,idle-state";
 287                                 idle-state-name = "little-rail-power-collapse";
 288                                 arm,psci-suspend-param = <0x40000004>;
 289                                 entry-latency-us = <355>;
 290                                 exit-latency-us = <909>;
 291                                 min-residency-us = <3934>;
 292                                 local-timer-stop;
 293                         };
 294
 295                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 296                                 compatible = "arm,idle-state";
 297                                 idle-state-name = "big-rail-power-collapse";
 298                                 arm,psci-suspend-param = <0x40000004>;
 299                                 entry-latency-us = <241>;
 300                                 exit-latency-us = <1461>;
 301                                 min-residency-us = <4488>;
 302                                 local-timer-stop;
 303                         };
 304                 };
 305
 306                 domain-idle-states {
 307                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 308                                 compatible = "domain-idle-state";
 309                                 arm,psci-suspend-param = <0x4100c244>;
 310                                 entry-latency-us = <3263>;
 311                                 exit-latency-us = <6562>;
 312                                 min-residency-us = <9987>;
 313                         };
 314                 };
 315         };
 316
 317         cpu0_opp_table: opp-table-cpu0 {
 318                 compatible = "operating-points-v2";
 319                 opp-shared;
 320
 321                 cpu0_opp1: opp-300000000 {
 322                         opp-hz = /bits/ 64 <300000000>;
 323                         opp-peak-kBps = <800000 9600000>;
 324                 };
 325
 326                 cpu0_opp2: opp-403200000 {
 327                         opp-hz = /bits/ 64 <403200000>;
 328                         opp-peak-kBps = <800000 9600000>;
 329                 };
 330
 331                 cpu0_opp3: opp-499200000 {
 332                         opp-hz = /bits/ 64 <499200000>;
 333                         opp-peak-kBps = <800000 12902400>;
 334                 };
 335
 336                 cpu0_opp4: opp-576000000 {
 337                         opp-hz = /bits/ 64 <576000000>;
 338                         opp-peak-kBps = <800000 12902400>;
 339                 };
 340
 341                 cpu0_opp5: opp-672000000 {
 342                         opp-hz = /bits/ 64 <672000000>;
 343                         opp-peak-kBps = <800000 15974400>;
 344                 };
 345
 346                 cpu0_opp6: opp-768000000 {
 347                         opp-hz = /bits/ 64 <768000000>;
 348                         opp-peak-kBps = <1804000 19660800>;
 349                 };
 350
 351                 cpu0_opp7: opp-844800000 {
 352                         opp-hz = /bits/ 64 <844800000>;
 353                         opp-peak-kBps = <1804000 19660800>;
 354                 };
 355
 356                 cpu0_opp8: opp-940800000 {
 357                         opp-hz = /bits/ 64 <940800000>;
 358                         opp-peak-kBps = <1804000 22732800>;
 359                 };
 360
 361                 cpu0_opp9: opp-1036800000 {
 362                         opp-hz = /bits/ 64 <1036800000>;
 363                         opp-peak-kBps = <1804000 22732800>;
 364                 };
 365
 366                 cpu0_opp10: opp-1113600000 {
 367                         opp-hz = /bits/ 64 <1113600000>;
 368                         opp-peak-kBps = <2188000 25804800>;
 369                 };
 370
 371                 cpu0_opp11: opp-1209600000 {
 372                         opp-hz = /bits/ 64 <1209600000>;
 373                         opp-peak-kBps = <2188000 31948800>;
 374                 };
 375
 376                 cpu0_opp12: opp-1305600000 {
 377                         opp-hz = /bits/ 64 <1305600000>;
 378                         opp-peak-kBps = <3072000 31948800>;
 379                 };
 380
 381                 cpu0_opp13: opp-1382400000 {
 382                         opp-hz = /bits/ 64 <1382400000>;
 383                         opp-peak-kBps = <3072000 31948800>;
 384                 };
 385
 386                 cpu0_opp14: opp-1478400000 {
 387                         opp-hz = /bits/ 64 <1478400000>;
 388                         opp-peak-kBps = <3072000 31948800>;
 389                 };
 390
 391                 cpu0_opp15: opp-1555200000 {
 392                         opp-hz = /bits/ 64 <1555200000>;
 393                         opp-peak-kBps = <3072000 40550400>;
 394                 };
 395
 396                 cpu0_opp16: opp-1632000000 {
 397                         opp-hz = /bits/ 64 <1632000000>;
 398                         opp-peak-kBps = <3072000 40550400>;
 399                 };
 400
 401                 cpu0_opp17: opp-1708800000 {
 402                         opp-hz = /bits/ 64 <1708800000>;
 403                         opp-peak-kBps = <3072000 43008000>;
 404                 };
 405
 406                 cpu0_opp18: opp-1785600000 {
 407                         opp-hz = /bits/ 64 <1785600000>;
 408                         opp-peak-kBps = <3072000 43008000>;
 409                 };
 410         };
 411
 412         cpu4_opp_table: opp-table-cpu4 {
 413                 compatible = "operating-points-v2";
 414                 opp-shared;
 415
 416                 cpu4_opp1: opp-710400000 {
 417                         opp-hz = /bits/ 64 <710400000>;
 418                         opp-peak-kBps = <1804000 15974400>;
 419                 };
 420
 421                 cpu4_opp2: opp-825600000 {
 422                         opp-hz = /bits/ 64 <825600000>;
 423                         opp-peak-kBps = <2188000 19660800>;
 424                 };
 425
 426                 cpu4_opp3: opp-940800000 {
 427                         opp-hz = /bits/ 64 <940800000>;
 428                         opp-peak-kBps = <2188000 22732800>;
 429                 };
 430
 431                 cpu4_opp4: opp-1056000000 {
 432                         opp-hz = /bits/ 64 <1056000000>;
 433                         opp-peak-kBps = <3072000 25804800>;
 434                 };
 435
 436                 cpu4_opp5: opp-1171200000 {
 437                         opp-hz = /bits/ 64 <1171200000>;
 438                         opp-peak-kBps = <3072000 31948800>;
 439                 };
 440
 441                 cpu4_opp6: opp-1286400000 {
 442                         opp-hz = /bits/ 64 <1286400000>;
 443                         opp-peak-kBps = <4068000 31948800>;
 444                 };
 445
 446                 cpu4_opp7: opp-1401600000 {
 447                         opp-hz = /bits/ 64 <1401600000>;
 448                         opp-peak-kBps = <4068000 31948800>;
 449                 };
 450
 451                 cpu4_opp8: opp-1497600000 {
 452                         opp-hz = /bits/ 64 <1497600000>;
 453                         opp-peak-kBps = <4068000 40550400>;
 454                 };
 455
 456                 cpu4_opp9: opp-1612800000 {
 457                         opp-hz = /bits/ 64 <1612800000>;
 458                         opp-peak-kBps = <4068000 40550400>;
 459                 };
 460
 461                 cpu4_opp10: opp-1708800000 {
 462                         opp-hz = /bits/ 64 <1708800000>;
 463                         opp-peak-kBps = <4068000 43008000>;
 464                 };
 465
 466                 cpu4_opp11: opp-1804800000 {
 467                         opp-hz = /bits/ 64 <1804800000>;
 468                         opp-peak-kBps = <6220000 43008000>;
 469                 };
 470
 471                 cpu4_opp12: opp-1920000000 {
 472                         opp-hz = /bits/ 64 <1920000000>;
 473                         opp-peak-kBps = <6220000 49152000>;
 474                 };
 475
 476                 cpu4_opp13: opp-2016000000 {
 477                         opp-hz = /bits/ 64 <2016000000>;
 478                         opp-peak-kBps = <7216000 49152000>;
 479                 };
 480
 481                 cpu4_opp14: opp-2131200000 {
 482                         opp-hz = /bits/ 64 <2131200000>;
 483                         opp-peak-kBps = <8368000 49152000>;
 484                 };
 485
 486                 cpu4_opp15: opp-2227200000 {
 487                         opp-hz = /bits/ 64 <2227200000>;
 488                         opp-peak-kBps = <8368000 51609600>;
 489                 };
 490
 491                 cpu4_opp16: opp-2323200000 {
 492                         opp-hz = /bits/ 64 <2323200000>;
 493                         opp-peak-kBps = <8368000 51609600>;
 494                 };
 495
 496                 cpu4_opp17: opp-2419200000 {
 497                         opp-hz = /bits/ 64 <2419200000>;
 498                         opp-peak-kBps = <8368000 51609600>;
 499                 };
 500         };
 501
 502         cpu7_opp_table: opp-table-cpu7 {
 503                 compatible = "operating-points-v2";
 504                 opp-shared;
 505
 506                 cpu7_opp1: opp-825600000 {
 507                         opp-hz = /bits/ 64 <825600000>;
 508                         opp-peak-kBps = <2188000 19660800>;
 509                 };
 510
 511                 cpu7_opp2: opp-940800000 {
 512                         opp-hz = /bits/ 64 <940800000>;
 513                         opp-peak-kBps = <2188000 22732800>;
 514                 };
 515
 516                 cpu7_opp3: opp-1056000000 {
 517                         opp-hz = /bits/ 64 <1056000000>;
 518                         opp-peak-kBps = <3072000 25804800>;
 519                 };
 520
 521                 cpu7_opp4: opp-1171200000 {
 522                         opp-hz = /bits/ 64 <1171200000>;
 523                         opp-peak-kBps = <3072000 31948800>;
 524                 };
 525
 526                 cpu7_opp5: opp-1286400000 {
 527                         opp-hz = /bits/ 64 <1286400000>;
 528                         opp-peak-kBps = <4068000 31948800>;
 529                 };
 530
 531                 cpu7_opp6: opp-1401600000 {
 532                         opp-hz = /bits/ 64 <1401600000>;
 533                         opp-peak-kBps = <4068000 31948800>;
 534                 };
 535
 536                 cpu7_opp7: opp-1497600000 {
 537                         opp-hz = /bits/ 64 <1497600000>;
 538                         opp-peak-kBps = <4068000 40550400>;
 539                 };
 540
 541                 cpu7_opp8: opp-1612800000 {
 542                         opp-hz = /bits/ 64 <1612800000>;
 543                         opp-peak-kBps = <4068000 40550400>;
 544                 };
 545
 546                 cpu7_opp9: opp-1708800000 {
 547                         opp-hz = /bits/ 64 <1708800000>;
 548                         opp-peak-kBps = <4068000 43008000>;
 549                 };
 550
 551                 cpu7_opp10: opp-1804800000 {
 552                         opp-hz = /bits/ 64 <1804800000>;
 553                         opp-peak-kBps = <6220000 43008000>;
 554                 };
 555
 556                 cpu7_opp11: opp-1920000000 {
 557                         opp-hz = /bits/ 64 <1920000000>;
 558                         opp-peak-kBps = <6220000 49152000>;
 559                 };
 560
 561                 cpu7_opp12: opp-2016000000 {
 562                         opp-hz = /bits/ 64 <2016000000>;
 563                         opp-peak-kBps = <7216000 49152000>;
 564                 };
 565
 566                 cpu7_opp13: opp-2131200000 {
 567                         opp-hz = /bits/ 64 <2131200000>;
 568                         opp-peak-kBps = <8368000 49152000>;
 569                 };
 570
 571                 cpu7_opp14: opp-2227200000 {
 572                         opp-hz = /bits/ 64 <2227200000>;
 573                         opp-peak-kBps = <8368000 51609600>;
 574                 };
 575
 576                 cpu7_opp15: opp-2323200000 {
 577                         opp-hz = /bits/ 64 <2323200000>;
 578                         opp-peak-kBps = <8368000 51609600>;
 579                 };
 580
 581                 cpu7_opp16: opp-2419200000 {
 582                         opp-hz = /bits/ 64 <2419200000>;
 583                         opp-peak-kBps = <8368000 51609600>;
 584                 };
 585
 586                 cpu7_opp17: opp-2534400000 {
 587                         opp-hz = /bits/ 64 <2534400000>;
 588                         opp-peak-kBps = <8368000 51609600>;
 589                 };
 590
 591                 cpu7_opp18: opp-2649600000 {
 592                         opp-hz = /bits/ 64 <2649600000>;
 593                         opp-peak-kBps = <8368000 51609600>;
 594                 };
 595
 596                 cpu7_opp19: opp-2745600000 {
 597                         opp-hz = /bits/ 64 <2745600000>;
 598                         opp-peak-kBps = <8368000 51609600>;
 599                 };
 600
 601                 cpu7_opp20: opp-2841600000 {
 602                         opp-hz = /bits/ 64 <2841600000>;
 603                         opp-peak-kBps = <8368000 51609600>;
 604                 };
 605         };
 606
 607         firmware {
 608                 scm: scm {
 609                         compatible = "qcom,scm-sm8150", "qcom,scm";
 610                         #reset-cells = <1>;
 611                 };
 612         };
 613
 614         memory@80000000 {
 615                 device_type = "memory";
 616                 /* We expect the bootloader to fill in the size */
 617                 reg = <0x0 0x80000000 0x0 0x0>;
 618         };
 619
 620         pmu {
 621                 compatible = "arm,armv8-pmuv3";
 622                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 623         };
 624
 625         psci {
 626                 compatible = "arm,psci-1.0";
 627                 method = "smc";
 628
 629                 CPU_PD0: power-domain-cpu0 {
 630                         #power-domain-cells = <0>;
 631                         power-domains = <&CLUSTER_PD>;
 632                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 633                 };
 634
 635                 CPU_PD1: power-domain-cpu1 {
 636                         #power-domain-cells = <0>;
 637                         power-domains = <&CLUSTER_PD>;
 638                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 639                 };
 640
 641                 CPU_PD2: power-domain-cpu2 {
 642                         #power-domain-cells = <0>;
 643                         power-domains = <&CLUSTER_PD>;
 644                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 645                 };
 646
 647                 CPU_PD3: power-domain-cpu3 {
 648                         #power-domain-cells = <0>;
 649                         power-domains = <&CLUSTER_PD>;
 650                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 651                 };
 652
 653                 CPU_PD4: power-domain-cpu4 {
 654                         #power-domain-cells = <0>;
 655                         power-domains = <&CLUSTER_PD>;
 656                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 657                 };
 658
 659                 CPU_PD5: power-domain-cpu5 {
 660                         #power-domain-cells = <0>;
 661                         power-domains = <&CLUSTER_PD>;
 662                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 663                 };
 664
 665                 CPU_PD6: power-domain-cpu6 {
 666                         #power-domain-cells = <0>;
 667                         power-domains = <&CLUSTER_PD>;
 668                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 669                 };
 670
 671                 CPU_PD7: power-domain-cpu7 {
 672                         #power-domain-cells = <0>;
 673                         power-domains = <&CLUSTER_PD>;
 674                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 675                 };
 676
 677                 CLUSTER_PD: power-domain-cpu-cluster0 {
 678                         #power-domain-cells = <0>;
 679                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 680                 };
 681         };
 682
 683         reserved-memory {
 684                 #address-cells = <2>;
 685                 #size-cells = <2>;
 686                 ranges;
 687
 688                 hyp_mem: memory@85700000 {
 689                         reg = <0x0 0x85700000 0x0 0x600000>;
 690                         no-map;
 691                 };
 692
 693                 xbl_mem: memory@85d00000 {
 694                         reg = <0x0 0x85d00000 0x0 0x140000>;
 695                         no-map;
 696                 };
 697
 698                 aop_mem: memory@85f00000 {
 699                         reg = <0x0 0x85f00000 0x0 0x20000>;
 700                         no-map;
 701                 };
 702
 703                 aop_cmd_db: memory@85f20000 {
 704                         compatible = "qcom,cmd-db";
 705                         reg = <0x0 0x85f20000 0x0 0x20000>;
 706                         no-map;
 707                 };
 708
 709                 smem_mem: memory@86000000 {
 710                         reg = <0x0 0x86000000 0x0 0x200000>;
 711                         no-map;
 712                 };
 713
 714                 tz_mem: memory@86200000 {
 715                         reg = <0x0 0x86200000 0x0 0x3900000>;
 716                         no-map;
 717                 };
 718
 719                 rmtfs_mem: memory@89b00000 {
 720                         compatible = "qcom,rmtfs-mem";
 721                         reg = <0x0 0x89b00000 0x0 0x200000>;
 722                         no-map;
 723
 724                         qcom,client-id = <1>;
 725                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 726                 };
 727
 728                 camera_mem: memory@8b700000 {
 729                         reg = <0x0 0x8b700000 0x0 0x500000>;
 730                         no-map;
 731                 };
 732
 733                 wlan_mem: memory@8bc00000 {
 734                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 735                         no-map;
 736                 };
 737
 738                 npu_mem: memory@8bd80000 {
 739                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 740                         no-map;
 741                 };
 742
 743                 adsp_mem: memory@8be00000 {
 744                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 745                         no-map;
 746                 };
 747
 748                 mpss_mem: memory@8d800000 {
 749                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 750                         no-map;
 751                 };
 752
 753                 venus_mem: memory@96e00000 {
 754                         reg = <0x0 0x96e00000 0x0 0x500000>;
 755                         no-map;
 756                 };
 757
 758                 slpi_mem: memory@97300000 {
 759                         reg = <0x0 0x97300000 0x0 0x1400000>;
 760                         no-map;
 761                 };
 762
 763                 ipa_fw_mem: memory@98700000 {
 764                         reg = <0x0 0x98700000 0x0 0x10000>;
 765                         no-map;
 766                 };
 767
 768                 ipa_gsi_mem: memory@98710000 {
 769                         reg = <0x0 0x98710000 0x0 0x5000>;
 770                         no-map;
 771                 };
 772
 773                 gpu_mem: memory@98715000 {
 774                         reg = <0x0 0x98715000 0x0 0x2000>;
 775                         no-map;
 776                 };
 777
 778                 spss_mem: memory@98800000 {
 779                         reg = <0x0 0x98800000 0x0 0x100000>;
 780                         no-map;
 781                 };
 782
 783                 cdsp_mem: memory@98900000 {
 784                         reg = <0x0 0x98900000 0x0 0x1400000>;
 785                         no-map;
 786                 };
 787
 788                 qseecom_mem: memory@9e400000 {
 789                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 790                         no-map;
 791                 };
 792         };
 793
 794         smem {
 795                 compatible = "qcom,smem";
 796                 memory-region = <&smem_mem>;
 797                 hwlocks = <&tcsr_mutex 3>;
 798         };
 799
 800         smp2p-cdsp {
 801                 compatible = "qcom,smp2p";
 802                 qcom,smem = <94>, <432>;
 803
 804                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 805
 806                 mboxes = <&apss_shared 6>;
 807
 808                 qcom,local-pid = <0>;
 809                 qcom,remote-pid = <5>;
 810
 811                 cdsp_smp2p_out: master-kernel {
 812                         qcom,entry-name = "master-kernel";
 813                         #qcom,smem-state-cells = <1>;
 814                 };
 815
 816                 cdsp_smp2p_in: slave-kernel {
 817                         qcom,entry-name = "slave-kernel";
 818
 819                         interrupt-controller;
 820                         #interrupt-cells = <2>;
 821                 };
 822         };
 823
 824         smp2p-lpass {
 825                 compatible = "qcom,smp2p";
 826                 qcom,smem = <443>, <429>;
 827
 828                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 829
 830                 mboxes = <&apss_shared 10>;
 831
 832                 qcom,local-pid = <0>;
 833                 qcom,remote-pid = <2>;
 834
 835                 adsp_smp2p_out: master-kernel {
 836                         qcom,entry-name = "master-kernel";
 837                         #qcom,smem-state-cells = <1>;
 838                 };
 839
 840                 adsp_smp2p_in: slave-kernel {
 841                         qcom,entry-name = "slave-kernel";
 842
 843                         interrupt-controller;
 844                         #interrupt-cells = <2>;
 845                 };
 846         };
 847
 848         smp2p-mpss {
 849                 compatible = "qcom,smp2p";
 850                 qcom,smem = <435>, <428>;
 851
 852                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 853
 854                 mboxes = <&apss_shared 14>;
 855
 856                 qcom,local-pid = <0>;
 857                 qcom,remote-pid = <1>;
 858
 859                 modem_smp2p_out: master-kernel {
 860                         qcom,entry-name = "master-kernel";
 861                         #qcom,smem-state-cells = <1>;
 862                 };
 863
 864                 modem_smp2p_in: slave-kernel {
 865                         qcom,entry-name = "slave-kernel";
 866
 867                         interrupt-controller;
 868                         #interrupt-cells = <2>;
 869                 };
 870         };
 871
 872         smp2p-slpi {
 873                 compatible = "qcom,smp2p";
 874                 qcom,smem = <481>, <430>;
 875
 876                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 877
 878                 mboxes = <&apss_shared 26>;
 879
 880                 qcom,local-pid = <0>;
 881                 qcom,remote-pid = <3>;
 882
 883                 slpi_smp2p_out: master-kernel {
 884                         qcom,entry-name = "master-kernel";
 885                         #qcom,smem-state-cells = <1>;
 886                 };
 887
 888                 slpi_smp2p_in: slave-kernel {
 889                         qcom,entry-name = "slave-kernel";
 890
 891                         interrupt-controller;
 892                         #interrupt-cells = <2>;
 893                 };
 894         };
 895
 896         soc: soc@0 {
 897                 #address-cells = <2>;
 898                 #size-cells = <2>;
 899                 ranges = <0 0 0 0 0x10 0>;
 900                 dma-ranges = <0 0 0 0 0x10 0>;
 901                 compatible = "simple-bus";
 902
 903                 gcc: clock-controller@100000 {
 904                         compatible = "qcom,gcc-sm8150";
 905                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 906                         #clock-cells = <1>;
 907                         #reset-cells = <1>;
 908                         #power-domain-cells = <1>;
 909                         clock-names = "bi_tcxo",
 910                                       "sleep_clk";
 911                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 912                                  <&sleep_clk>;
 913                 };
 914
 915                 gpi_dma0: dma-controller@800000 {
 916                         compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
 917                         reg = <0 0x00800000 0 0x60000>;
 918                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 920                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 921                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 922                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 925                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 926                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 931                         dma-channels = <13>;
 932                         dma-channel-mask = <0xfa>;
 933                         iommus = <&apps_smmu 0x00d6 0x0>;
 934                         #dma-cells = <3>;
 935                         status = "disabled";
 936                 };
 937
 938                 ethernet: ethernet@20000 {
 939                         compatible = "qcom,sm8150-ethqos";
 940                         reg = <0x0 0x00020000 0x0 0x10000>,
 941                               <0x0 0x00036000 0x0 0x100>;
 942                         reg-names = "stmmaceth", "rgmii";
 943                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
 944                         clocks = <&gcc GCC_EMAC_AXI_CLK>,
 945                                 <&gcc GCC_EMAC_SLV_AHB_CLK>,
 946                                 <&gcc GCC_EMAC_PTP_CLK>,
 947                                 <&gcc GCC_EMAC_RGMII_CLK>;
 948                         interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
 949                                      <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
 950                         interrupt-names = "macirq", "eth_lpi";
 951
 952                         power-domains = <&gcc EMAC_GDSC>;
 953                         resets = <&gcc GCC_EMAC_BCR>;
 954
 955                         iommus = <&apps_smmu 0x3c0 0x0>;
 956
 957                         snps,tso;
 958                         rx-fifo-depth = <4096>;
 959                         tx-fifo-depth = <4096>;
 960
 961                         status = "disabled";
 962                 };
 963
 964                 qfprom: efuse@784000 {
 965                         compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
 966                         reg = <0 0x00784000 0 0x8ff>;
 967                         #address-cells = <1>;
 968                         #size-cells = <1>;
 969
 970                         gpu_speed_bin: gpu_speed_bin@133 {
 971                                 reg = <0x133 0x1>;
 972                                 bits = <5 3>;
 973                         };
 974                 };
 975
 976                 qupv3_id_0: geniqup@8c0000 {
 977                         compatible = "qcom,geni-se-qup";
 978                         reg = <0x0 0x008c0000 0x0 0x6000>;
 979                         clock-names = "m-ahb", "s-ahb";
 980                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 981                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 982                         iommus = <&apps_smmu 0xc3 0x0>;
 983                         #address-cells = <2>;
 984                         #size-cells = <2>;
 985                         ranges;
 986                         status = "disabled";
 987
 988                         i2c0: i2c@880000 {
 989                                 compatible = "qcom,geni-i2c";
 990                                 reg = <0 0x00880000 0 0x4000>;
 991                                 clock-names = "se";
 992                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 993                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 994                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 995                                 dma-names = "tx", "rx";
 996                                 pinctrl-names = "default";
 997                                 pinctrl-0 = <&qup_i2c0_default>;
 998                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 999                                 #address-cells = <1>;
1000                                 #size-cells = <0>;
1001                                 status = "disabled";
1002                         };
1003
1004                         spi0: spi@880000 {
1005                                 compatible = "qcom,geni-spi";
1006                                 reg = <0 0x00880000 0 0x4000>;
1007                                 reg-names = "se";
1008                                 clock-names = "se";
1009                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1010                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1011                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1012                                 dma-names = "tx", "rx";
1013                                 pinctrl-names = "default";
1014                                 pinctrl-0 = <&qup_spi0_default>;
1015                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1016                                 spi-max-frequency = <50000000>;
1017                                 #address-cells = <1>;
1018                                 #size-cells = <0>;
1019                                 status = "disabled";
1020                         };
1021
1022                         i2c1: i2c@884000 {
1023                                 compatible = "qcom,geni-i2c";
1024                                 reg = <0 0x00884000 0 0x4000>;
1025                                 clock-names = "se";
1026                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1027                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1028                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1029                                 dma-names = "tx", "rx";
1030                                 pinctrl-names = "default";
1031                                 pinctrl-0 = <&qup_i2c1_default>;
1032                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1033                                 #address-cells = <1>;
1034                                 #size-cells = <0>;
1035                                 status = "disabled";
1036                         };
1037
1038                         spi1: spi@884000 {
1039                                 compatible = "qcom,geni-spi";
1040                                 reg = <0 0x00884000 0 0x4000>;
1041                                 reg-names = "se";
1042                                 clock-names = "se";
1043                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1044                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1045                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1046                                 dma-names = "tx", "rx";
1047                                 pinctrl-names = "default";
1048                                 pinctrl-0 = <&qup_spi1_default>;
1049                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1050                                 spi-max-frequency = <50000000>;
1051                                 #address-cells = <1>;
1052                                 #size-cells = <0>;
1053                                 status = "disabled";
1054                         };
1055
1056                         i2c2: i2c@888000 {
1057                                 compatible = "qcom,geni-i2c";
1058                                 reg = <0 0x00888000 0 0x4000>;
1059                                 clock-names = "se";
1060                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1061                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1062                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1063                                 dma-names = "tx", "rx";
1064                                 pinctrl-names = "default";
1065                                 pinctrl-0 = <&qup_i2c2_default>;
1066                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1067                                 #address-cells = <1>;
1068                                 #size-cells = <0>;
1069                                 status = "disabled";
1070                         };
1071
1072                         spi2: spi@888000 {
1073                                 compatible = "qcom,geni-spi";
1074                                 reg = <0 0x00888000 0 0x4000>;
1075                                 reg-names = "se";
1076                                 clock-names = "se";
1077                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1078                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1079                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1080                                 dma-names = "tx", "rx";
1081                                 pinctrl-names = "default";
1082                                 pinctrl-0 = <&qup_spi2_default>;
1083                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1084                                 spi-max-frequency = <50000000>;
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087                                 status = "disabled";
1088                         };
1089
1090                         i2c3: i2c@88c000 {
1091                                 compatible = "qcom,geni-i2c";
1092                                 reg = <0 0x0088c000 0 0x4000>;
1093                                 clock-names = "se";
1094                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1095                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1096                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1097                                 dma-names = "tx", "rx";
1098                                 pinctrl-names = "default";
1099                                 pinctrl-0 = <&qup_i2c3_default>;
1100                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1101                                 #address-cells = <1>;
1102                                 #size-cells = <0>;
1103                                 status = "disabled";
1104                         };
1105
1106                         spi3: spi@88c000 {
1107                                 compatible = "qcom,geni-spi";
1108                                 reg = <0 0x0088c000 0 0x4000>;
1109                                 reg-names = "se";
1110                                 clock-names = "se";
1111                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1112                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1113                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1114                                 dma-names = "tx", "rx";
1115                                 pinctrl-names = "default";
1116                                 pinctrl-0 = <&qup_spi3_default>;
1117                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1118                                 spi-max-frequency = <50000000>;
1119                                 #address-cells = <1>;
1120                                 #size-cells = <0>;
1121                                 status = "disabled";
1122                         };
1123
1124                         i2c4: i2c@890000 {
1125                                 compatible = "qcom,geni-i2c";
1126                                 reg = <0 0x00890000 0 0x4000>;
1127                                 clock-names = "se";
1128                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1129                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1130                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1131                                 dma-names = "tx", "rx";
1132                                 pinctrl-names = "default";
1133                                 pinctrl-0 = <&qup_i2c4_default>;
1134                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1135                                 #address-cells = <1>;
1136                                 #size-cells = <0>;
1137                                 status = "disabled";
1138                         };
1139
1140                         spi4: spi@890000 {
1141                                 compatible = "qcom,geni-spi";
1142                                 reg = <0 0x00890000 0 0x4000>;
1143                                 reg-names = "se";
1144                                 clock-names = "se";
1145                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1146                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1147                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1148                                 dma-names = "tx", "rx";
1149                                 pinctrl-names = "default";
1150                                 pinctrl-0 = <&qup_spi4_default>;
1151                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1152                                 spi-max-frequency = <50000000>;
1153                                 #address-cells = <1>;
1154                                 #size-cells = <0>;
1155                                 status = "disabled";
1156                         };
1157
1158                         i2c5: i2c@894000 {
1159                                 compatible = "qcom,geni-i2c";
1160                                 reg = <0 0x00894000 0 0x4000>;
1161                                 clock-names = "se";
1162                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1163                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1164                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1165                                 dma-names = "tx", "rx";
1166                                 pinctrl-names = "default";
1167                                 pinctrl-0 = <&qup_i2c5_default>;
1168                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169                                 #address-cells = <1>;
1170                                 #size-cells = <0>;
1171                                 status = "disabled";
1172                         };
1173
1174                         spi5: spi@894000 {
1175                                 compatible = "qcom,geni-spi";
1176                                 reg = <0 0x00894000 0 0x4000>;
1177                                 reg-names = "se";
1178                                 clock-names = "se";
1179                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1180                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1181                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1182                                 dma-names = "tx", "rx";
1183                                 pinctrl-names = "default";
1184                                 pinctrl-0 = <&qup_spi5_default>;
1185                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1186                                 spi-max-frequency = <50000000>;
1187                                 #address-cells = <1>;
1188                                 #size-cells = <0>;
1189                                 status = "disabled";
1190                         };
1191
1192                         i2c6: i2c@898000 {
1193                                 compatible = "qcom,geni-i2c";
1194                                 reg = <0 0x00898000 0 0x4000>;
1195                                 clock-names = "se";
1196                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1197                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1198                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1199                                 dma-names = "tx", "rx";
1200                                 pinctrl-names = "default";
1201                                 pinctrl-0 = <&qup_i2c6_default>;
1202                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1203                                 #address-cells = <1>;
1204                                 #size-cells = <0>;
1205                                 status = "disabled";
1206                         };
1207
1208                         spi6: spi@898000 {
1209                                 compatible = "qcom,geni-spi";
1210                                 reg = <0 0x00898000 0 0x4000>;
1211                                 reg-names = "se";
1212                                 clock-names = "se";
1213                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1214                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1215                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1216                                 dma-names = "tx", "rx";
1217                                 pinctrl-names = "default";
1218                                 pinctrl-0 = <&qup_spi6_default>;
1219                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1220                                 spi-max-frequency = <50000000>;
1221                                 #address-cells = <1>;
1222                                 #size-cells = <0>;
1223                                 status = "disabled";
1224                         };
1225
1226                         i2c7: i2c@89c000 {
1227                                 compatible = "qcom,geni-i2c";
1228                                 reg = <0 0x0089c000 0 0x4000>;
1229                                 clock-names = "se";
1230                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1231                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1232                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1233                                 dma-names = "tx", "rx";
1234                                 pinctrl-names = "default";
1235                                 pinctrl-0 = <&qup_i2c7_default>;
1236                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1237                                 #address-cells = <1>;
1238                                 #size-cells = <0>;
1239                                 status = "disabled";
1240                         };
1241
1242                         spi7: spi@89c000 {
1243                                 compatible = "qcom,geni-spi";
1244                                 reg = <0 0x0089c000 0 0x4000>;
1245                                 reg-names = "se";
1246                                 clock-names = "se";
1247                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1248                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1249                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1250                                 dma-names = "tx", "rx";
1251                                 pinctrl-names = "default";
1252                                 pinctrl-0 = <&qup_spi7_default>;
1253                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1254                                 spi-max-frequency = <50000000>;
1255                                 #address-cells = <1>;
1256                                 #size-cells = <0>;
1257                                 status = "disabled";
1258                         };
1259                 };
1260
1261                 gpi_dma1: dma-controller@a00000 {
1262                         compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1263                         reg = <0 0x00a00000 0 0x60000>;
1264                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1267                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1269                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1270                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1271                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1272                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1273                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1274                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1275                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1276                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1277                         dma-channels = <13>;
1278                         dma-channel-mask = <0xfa>;
1279                         iommus = <&apps_smmu 0x0616 0x0>;
1280                         #dma-cells = <3>;
1281                         status = "disabled";
1282                 };
1283
1284                 qupv3_id_1: geniqup@ac0000 {
1285                         compatible = "qcom,geni-se-qup";
1286                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1287                         clock-names = "m-ahb", "s-ahb";
1288                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1289                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1290                         iommus = <&apps_smmu 0x603 0x0>;
1291                         #address-cells = <2>;
1292                         #size-cells = <2>;
1293                         ranges;
1294                         status = "disabled";
1295
1296                         i2c8: i2c@a80000 {
1297                                 compatible = "qcom,geni-i2c";
1298                                 reg = <0 0x00a80000 0 0x4000>;
1299                                 clock-names = "se";
1300                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1301                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1302                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1303                                 dma-names = "tx", "rx";
1304                                 pinctrl-names = "default";
1305                                 pinctrl-0 = <&qup_i2c8_default>;
1306                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1307                                 #address-cells = <1>;
1308                                 #size-cells = <0>;
1309                                 status = "disabled";
1310                         };
1311
1312                         spi8: spi@a80000 {
1313                                 compatible = "qcom,geni-spi";
1314                                 reg = <0 0x00a80000 0 0x4000>;
1315                                 reg-names = "se";
1316                                 clock-names = "se";
1317                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1318                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1319                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1320                                 dma-names = "tx", "rx";
1321                                 pinctrl-names = "default";
1322                                 pinctrl-0 = <&qup_spi8_default>;
1323                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1324                                 spi-max-frequency = <50000000>;
1325                                 #address-cells = <1>;
1326                                 #size-cells = <0>;
1327                                 status = "disabled";
1328                         };
1329
1330                         i2c9: i2c@a84000 {
1331                                 compatible = "qcom,geni-i2c";
1332                                 reg = <0 0x00a84000 0 0x4000>;
1333                                 clock-names = "se";
1334                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1335                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1336                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1337                                 dma-names = "tx", "rx";
1338                                 pinctrl-names = "default";
1339                                 pinctrl-0 = <&qup_i2c9_default>;
1340                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1341                                 #address-cells = <1>;
1342                                 #size-cells = <0>;
1343                                 status = "disabled";
1344                         };
1345
1346                         spi9: spi@a84000 {
1347                                 compatible = "qcom,geni-spi";
1348                                 reg = <0 0x00a84000 0 0x4000>;
1349                                 reg-names = "se";
1350                                 clock-names = "se";
1351                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1352                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1353                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1354                                 dma-names = "tx", "rx";
1355                                 pinctrl-names = "default";
1356                                 pinctrl-0 = <&qup_spi9_default>;
1357                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1358                                 spi-max-frequency = <50000000>;
1359                                 #address-cells = <1>;
1360                                 #size-cells = <0>;
1361                                 status = "disabled";
1362                         };
1363
1364                         uart9: serial@a84000 {
1365                                 compatible = "qcom,geni-uart";
1366                                 reg = <0x0 0x00a84000 0x0 0x4000>;
1367                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1368                                 clock-names = "se";
1369                                 pinctrl-0 = <&qup_uart9_default>;
1370                                 pinctrl-names = "default";
1371                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1372                                 status = "disabled";
1373                         };
1374
1375                         i2c10: i2c@a88000 {
1376                                 compatible = "qcom,geni-i2c";
1377                                 reg = <0 0x00a88000 0 0x4000>;
1378                                 clock-names = "se";
1379                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1380                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1381                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1382                                 dma-names = "tx", "rx";
1383                                 pinctrl-names = "default";
1384                                 pinctrl-0 = <&qup_i2c10_default>;
1385                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1386                                 #address-cells = <1>;
1387                                 #size-cells = <0>;
1388                                 status = "disabled";
1389                         };
1390
1391                         spi10: spi@a88000 {
1392                                 compatible = "qcom,geni-spi";
1393                                 reg = <0 0x00a88000 0 0x4000>;
1394                                 reg-names = "se";
1395                                 clock-names = "se";
1396                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1397                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1398                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1399                                 dma-names = "tx", "rx";
1400                                 pinctrl-names = "default";
1401                                 pinctrl-0 = <&qup_spi10_default>;
1402                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1403                                 spi-max-frequency = <50000000>;
1404                                 #address-cells = <1>;
1405                                 #size-cells = <0>;
1406                                 status = "disabled";
1407                         };
1408
1409                         i2c11: i2c@a8c000 {
1410                                 compatible = "qcom,geni-i2c";
1411                                 reg = <0 0x00a8c000 0 0x4000>;
1412                                 clock-names = "se";
1413                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1414                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1415                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1416                                 dma-names = "tx", "rx";
1417                                 pinctrl-names = "default";
1418                                 pinctrl-0 = <&qup_i2c11_default>;
1419                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1420                                 #address-cells = <1>;
1421                                 #size-cells = <0>;
1422                                 status = "disabled";
1423                         };
1424
1425                         spi11: spi@a8c000 {
1426                                 compatible = "qcom,geni-spi";
1427                                 reg = <0 0x00a8c000 0 0x4000>;
1428                                 reg-names = "se";
1429                                 clock-names = "se";
1430                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1431                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1432                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1433                                 dma-names = "tx", "rx";
1434                                 pinctrl-names = "default";
1435                                 pinctrl-0 = <&qup_spi11_default>;
1436                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1437                                 spi-max-frequency = <50000000>;
1438                                 #address-cells = <1>;
1439                                 #size-cells = <0>;
1440                                 status = "disabled";
1441                         };
1442
1443                         uart2: serial@a90000 {
1444                                 compatible = "qcom,geni-debug-uart";
1445                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1446                                 clock-names = "se";
1447                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1448                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1449                                 status = "disabled";
1450                         };
1451
1452                         i2c12: i2c@a90000 {
1453                                 compatible = "qcom,geni-i2c";
1454                                 reg = <0 0x00a90000 0 0x4000>;
1455                                 clock-names = "se";
1456                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1457                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1458                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1459                                 dma-names = "tx", "rx";
1460                                 pinctrl-names = "default";
1461                                 pinctrl-0 = <&qup_i2c12_default>;
1462                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1463                                 #address-cells = <1>;
1464                                 #size-cells = <0>;
1465                                 status = "disabled";
1466                         };
1467
1468                         spi12: spi@a90000 {
1469                                 compatible = "qcom,geni-spi";
1470                                 reg = <0 0x00a90000 0 0x4000>;
1471                                 reg-names = "se";
1472                                 clock-names = "se";
1473                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1474                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1475                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1476                                 dma-names = "tx", "rx";
1477                                 pinctrl-names = "default";
1478                                 pinctrl-0 = <&qup_spi12_default>;
1479                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1480                                 spi-max-frequency = <50000000>;
1481                                 #address-cells = <1>;
1482                                 #size-cells = <0>;
1483                                 status = "disabled";
1484                         };
1485
1486                         i2c16: i2c@94000 {
1487                                 compatible = "qcom,geni-i2c";
1488                                 reg = <0 0x00094000 0 0x4000>;
1489                                 clock-names = "se";
1490                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1491                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1492                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1493                                 dma-names = "tx", "rx";
1494                                 pinctrl-names = "default";
1495                                 pinctrl-0 = <&qup_i2c16_default>;
1496                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1497                                 #address-cells = <1>;
1498                                 #size-cells = <0>;
1499                                 status = "disabled";
1500                         };
1501
1502                         spi16: spi@a94000 {
1503                                 compatible = "qcom,geni-spi";
1504                                 reg = <0 0x00a94000 0 0x4000>;
1505                                 reg-names = "se";
1506                                 clock-names = "se";
1507                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1508                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1509                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1510                                 dma-names = "tx", "rx";
1511                                 pinctrl-names = "default";
1512                                 pinctrl-0 = <&qup_spi16_default>;
1513                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1514                                 spi-max-frequency = <50000000>;
1515                                 #address-cells = <1>;
1516                                 #size-cells = <0>;
1517                                 status = "disabled";
1518                         };
1519                 };
1520
1521                 gpi_dma2: dma-controller@c00000 {
1522                         compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1523                         reg = <0 0x00c00000 0 0x60000>;
1524                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1525                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1526                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1527                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1528                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1529                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1530                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1531                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1532                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1533                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1534                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1535                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1536                                      <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1537                         dma-channels = <13>;
1538                         dma-channel-mask = <0xfa>;
1539                         iommus = <&apps_smmu 0x07b6 0x0>;
1540                         #dma-cells = <3>;
1541                         status = "disabled";
1542                 };
1543
1544                 qupv3_id_2: geniqup@cc0000 {
1545                         compatible = "qcom,geni-se-qup";
1546                         reg = <0x0 0x00cc0000 0x0 0x6000>;
1547
1548                         clock-names = "m-ahb", "s-ahb";
1549                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1550                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1551                         iommus = <&apps_smmu 0x7a3 0x0>;
1552                         #address-cells = <2>;
1553                         #size-cells = <2>;
1554                         ranges;
1555                         status = "disabled";
1556
1557                         i2c17: i2c@c80000 {
1558                                 compatible = "qcom,geni-i2c";
1559                                 reg = <0 0x00c80000 0 0x4000>;
1560                                 clock-names = "se";
1561                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1562                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1563                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1564                                 dma-names = "tx", "rx";
1565                                 pinctrl-names = "default";
1566                                 pinctrl-0 = <&qup_i2c17_default>;
1567                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1568                                 #address-cells = <1>;
1569                                 #size-cells = <0>;
1570                                 status = "disabled";
1571                         };
1572
1573                         spi17: spi@c80000 {
1574                                 compatible = "qcom,geni-spi";
1575                                 reg = <0 0x00c80000 0 0x4000>;
1576                                 reg-names = "se";
1577                                 clock-names = "se";
1578                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1579                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1580                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1581                                 dma-names = "tx", "rx";
1582                                 pinctrl-names = "default";
1583                                 pinctrl-0 = <&qup_spi17_default>;
1584                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1585                                 spi-max-frequency = <50000000>;
1586                                 #address-cells = <1>;
1587                                 #size-cells = <0>;
1588                                 status = "disabled";
1589                         };
1590
1591                         i2c18: i2c@c84000 {
1592                                 compatible = "qcom,geni-i2c";
1593                                 reg = <0 0x00c84000 0 0x4000>;
1594                                 clock-names = "se";
1595                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1596                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1597                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1598                                 dma-names = "tx", "rx";
1599                                 pinctrl-names = "default";
1600                                 pinctrl-0 = <&qup_i2c18_default>;
1601                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1602                                 #address-cells = <1>;
1603                                 #size-cells = <0>;
1604                                 status = "disabled";
1605                         };
1606
1607                         spi18: spi@c84000 {
1608                                 compatible = "qcom,geni-spi";
1609                                 reg = <0 0x00c84000 0 0x4000>;
1610                                 reg-names = "se";
1611                                 clock-names = "se";
1612                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1613                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1614                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1615                                 dma-names = "tx", "rx";
1616                                 pinctrl-names = "default";
1617                                 pinctrl-0 = <&qup_spi18_default>;
1618                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1619                                 spi-max-frequency = <50000000>;
1620                                 #address-cells = <1>;
1621                                 #size-cells = <0>;
1622                                 status = "disabled";
1623                         };
1624
1625                         i2c19: i2c@c88000 {
1626                                 compatible = "qcom,geni-i2c";
1627                                 reg = <0 0x00c88000 0 0x4000>;
1628                                 clock-names = "se";
1629                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1630                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1631                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1632                                 dma-names = "tx", "rx";
1633                                 pinctrl-names = "default";
1634                                 pinctrl-0 = <&qup_i2c19_default>;
1635                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1636                                 #address-cells = <1>;
1637                                 #size-cells = <0>;
1638                                 status = "disabled";
1639                         };
1640
1641                         spi19: spi@c88000 {
1642                                 compatible = "qcom,geni-spi";
1643                                 reg = <0 0x00c88000 0 0x4000>;
1644                                 reg-names = "se";
1645                                 clock-names = "se";
1646                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1647                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1648                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1649                                 dma-names = "tx", "rx";
1650                                 pinctrl-names = "default";
1651                                 pinctrl-0 = <&qup_spi19_default>;
1652                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1653                                 spi-max-frequency = <50000000>;
1654                                 #address-cells = <1>;
1655                                 #size-cells = <0>;
1656                                 status = "disabled";
1657                         };
1658
1659                         i2c13: i2c@c8c000 {
1660                                 compatible = "qcom,geni-i2c";
1661                                 reg = <0 0x00c8c000 0 0x4000>;
1662                                 clock-names = "se";
1663                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1664                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1665                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1666                                 dma-names = "tx", "rx";
1667                                 pinctrl-names = "default";
1668                                 pinctrl-0 = <&qup_i2c13_default>;
1669                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1670                                 #address-cells = <1>;
1671                                 #size-cells = <0>;
1672                                 status = "disabled";
1673                         };
1674
1675                         spi13: spi@c8c000 {
1676                                 compatible = "qcom,geni-spi";
1677                                 reg = <0 0x00c8c000 0 0x4000>;
1678                                 reg-names = "se";
1679                                 clock-names = "se";
1680                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1681                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1682                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1683                                 dma-names = "tx", "rx";
1684                                 pinctrl-names = "default";
1685                                 pinctrl-0 = <&qup_spi13_default>;
1686                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1687                                 spi-max-frequency = <50000000>;
1688                                 #address-cells = <1>;
1689                                 #size-cells = <0>;
1690                                 status = "disabled";
1691                         };
1692
1693                         i2c14: i2c@c90000 {
1694                                 compatible = "qcom,geni-i2c";
1695                                 reg = <0 0x00c90000 0 0x4000>;
1696                                 clock-names = "se";
1697                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1698                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1699                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1700                                 dma-names = "tx", "rx";
1701                                 pinctrl-names = "default";
1702                                 pinctrl-0 = <&qup_i2c14_default>;
1703                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1704                                 #address-cells = <1>;
1705                                 #size-cells = <0>;
1706                                 status = "disabled";
1707                         };
1708
1709                         spi14: spi@c90000 {
1710                                 compatible = "qcom,geni-spi";
1711                                 reg = <0 0x00c90000 0 0x4000>;
1712                                 reg-names = "se";
1713                                 clock-names = "se";
1714                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1715                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1716                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1717                                 dma-names = "tx", "rx";
1718                                 pinctrl-names = "default";
1719                                 pinctrl-0 = <&qup_spi14_default>;
1720                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1721                                 spi-max-frequency = <50000000>;
1722                                 #address-cells = <1>;
1723                                 #size-cells = <0>;
1724                                 status = "disabled";
1725                         };
1726
1727                         i2c15: i2c@c94000 {
1728                                 compatible = "qcom,geni-i2c";
1729                                 reg = <0 0x00c94000 0 0x4000>;
1730                                 clock-names = "se";
1731                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1732                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1733                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1734                                 dma-names = "tx", "rx";
1735                                 pinctrl-names = "default";
1736                                 pinctrl-0 = <&qup_i2c15_default>;
1737                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1738                                 #address-cells = <1>;
1739                                 #size-cells = <0>;
1740                                 status = "disabled";
1741                         };
1742
1743                         spi15: spi@c94000 {
1744                                 compatible = "qcom,geni-spi";
1745                                 reg = <0 0x00c94000 0 0x4000>;
1746                                 reg-names = "se";
1747                                 clock-names = "se";
1748                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1749                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1750                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1751                                 dma-names = "tx", "rx";
1752                                 pinctrl-names = "default";
1753                                 pinctrl-0 = <&qup_spi15_default>;
1754                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1755                                 spi-max-frequency = <50000000>;
1756                                 #address-cells = <1>;
1757                                 #size-cells = <0>;
1758                                 status = "disabled";
1759                         };
1760                 };
1761
1762                 config_noc: interconnect@1500000 {
1763                         compatible = "qcom,sm8150-config-noc";
1764                         reg = <0 0x01500000 0 0x7400>;
1765                         #interconnect-cells = <2>;
1766                         qcom,bcm-voters = <&apps_bcm_voter>;
1767                 };
1768
1769                 system_noc: interconnect@1620000 {
1770                         compatible = "qcom,sm8150-system-noc";
1771                         reg = <0 0x01620000 0 0x19400>;
1772                         #interconnect-cells = <2>;
1773                         qcom,bcm-voters = <&apps_bcm_voter>;
1774                 };
1775
1776                 mc_virt: interconnect@163a000 {
1777                         compatible = "qcom,sm8150-mc-virt";
1778                         reg = <0 0x0163a000 0 0x1000>;
1779                         #interconnect-cells = <2>;
1780                         qcom,bcm-voters = <&apps_bcm_voter>;
1781                 };
1782
1783                 aggre1_noc: interconnect@16e0000 {
1784                         compatible = "qcom,sm8150-aggre1-noc";
1785                         reg = <0 0x016e0000 0 0xd080>;
1786                         #interconnect-cells = <2>;
1787                         qcom,bcm-voters = <&apps_bcm_voter>;
1788                 };
1789
1790                 aggre2_noc: interconnect@1700000 {
1791                         compatible = "qcom,sm8150-aggre2-noc";
1792                         reg = <0 0x01700000 0 0x20000>;
1793                         #interconnect-cells = <2>;
1794                         qcom,bcm-voters = <&apps_bcm_voter>;
1795                 };
1796
1797                 compute_noc: interconnect@1720000 {
1798                         compatible = "qcom,sm8150-compute-noc";
1799                         reg = <0 0x01720000 0 0x7000>;
1800                         #interconnect-cells = <2>;
1801                         qcom,bcm-voters = <&apps_bcm_voter>;
1802                 };
1803
1804                 mmss_noc: interconnect@1740000 {
1805                         compatible = "qcom,sm8150-mmss-noc";
1806                         reg = <0 0x01740000 0 0x1c100>;
1807                         #interconnect-cells = <2>;
1808                         qcom,bcm-voters = <&apps_bcm_voter>;
1809                 };
1810
1811                 system-cache-controller@9200000 {
1812                         compatible = "qcom,sm8150-llcc";
1813                         reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1814                               <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1815                               <0 0x09600000 0 0x50000>;
1816                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1817                                     "llcc3_base", "llcc_broadcast_base";
1818                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1819                 };
1820
1821                 dma@10a2000 {
1822                         compatible = "qcom,sm8150-dcc", "qcom,dcc";
1823                         reg = <0x0 0x010a2000 0x0 0x1000>,
1824                               <0x0 0x010ad000 0x0 0x3000>;
1825                 };
1826
1827                 pcie0: pci@1c00000 {
1828                         compatible = "qcom,pcie-sm8150";
1829                         reg = <0 0x01c00000 0 0x3000>,
1830                               <0 0x60000000 0 0xf1d>,
1831                               <0 0x60000f20 0 0xa8>,
1832                               <0 0x60001000 0 0x1000>,
1833                               <0 0x60100000 0 0x100000>;
1834                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1835                         device_type = "pci";
1836                         linux,pci-domain = <0>;
1837                         bus-range = <0x00 0xff>;
1838                         num-lanes = <1>;
1839
1840                         #address-cells = <3>;
1841                         #size-cells = <2>;
1842
1843                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1844                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1845
1846                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1847                         interrupt-names = "msi";
1848                         #interrupt-cells = <1>;
1849                         interrupt-map-mask = <0 0 0 0x7>;
1850                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1851                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1852                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1853                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1854
1855                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1856                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1857                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1858                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1859                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1860                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1861                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1862                         clock-names = "pipe",
1863                                       "aux",
1864                                       "cfg",
1865                                       "bus_master",
1866                                       "bus_slave",
1867                                       "slave_q2a",
1868                                       "tbu";
1869
1870                         iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
1871                                     <0x100 &apps_smmu 0x1d81 0x1>;
1872
1873                         resets = <&gcc GCC_PCIE_0_BCR>;
1874                         reset-names = "pci";
1875
1876                         power-domains = <&gcc PCIE_0_GDSC>;
1877
1878                         phys = <&pcie0_phy>;
1879                         phy-names = "pciephy";
1880
1881                         perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1882                         enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1883
1884                         pinctrl-names = "default";
1885                         pinctrl-0 = <&pcie0_default_state>;
1886
1887                         status = "disabled";
1888                 };
1889
1890                 pcie0_phy: phy@1c06000 {
1891                         compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1892                         reg = <0 0x01c06000 0 0x1000>;
1893                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1894                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1895                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1896                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1897                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1898                         clock-names = "aux",
1899                                       "cfg_ahb",
1900                                       "ref",
1901                                       "refgen",
1902                                       "pipe";
1903
1904                         clock-output-names = "pcie_0_pipe_clk";
1905                         #clock-cells = <0>;
1906
1907                         #phy-cells = <0>;
1908
1909                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1910                         reset-names = "phy";
1911
1912                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1913                         assigned-clock-rates = <100000000>;
1914
1915                         status = "disabled";
1916                 };
1917
1918                 pcie1: pci@1c08000 {
1919                         compatible = "qcom,pcie-sm8150";
1920                         reg = <0 0x01c08000 0 0x3000>,
1921                               <0 0x40000000 0 0xf1d>,
1922                               <0 0x40000f20 0 0xa8>,
1923                               <0 0x40001000 0 0x1000>,
1924                               <0 0x40100000 0 0x100000>;
1925                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1926                         device_type = "pci";
1927                         linux,pci-domain = <1>;
1928                         bus-range = <0x00 0xff>;
1929                         num-lanes = <2>;
1930
1931                         #address-cells = <3>;
1932                         #size-cells = <2>;
1933
1934                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1935                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1936
1937                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1938                         interrupt-names = "msi";
1939                         #interrupt-cells = <1>;
1940                         interrupt-map-mask = <0 0 0 0x7>;
1941                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1942                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1943                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1944                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1945
1946                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1947                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1948                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1949                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1950                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1951                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1952                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1953                         clock-names = "pipe",
1954                                       "aux",
1955                                       "cfg",
1956                                       "bus_master",
1957                                       "bus_slave",
1958                                       "slave_q2a",
1959                                       "tbu";
1960
1961                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1962                         assigned-clock-rates = <19200000>;
1963
1964                         iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
1965                                     <0x100 &apps_smmu 0x1e01 0x1>;
1966
1967                         resets = <&gcc GCC_PCIE_1_BCR>;
1968                         reset-names = "pci";
1969
1970                         power-domains = <&gcc PCIE_1_GDSC>;
1971
1972                         phys = <&pcie1_phy>;
1973                         phy-names = "pciephy";
1974
1975                         perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1976                         enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1977
1978                         pinctrl-names = "default";
1979                         pinctrl-0 = <&pcie1_default_state>;
1980
1981                         status = "disabled";
1982                 };
1983
1984                 pcie1_phy: phy@1c0e000 {
1985                         compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1986                         reg = <0 0x01c0e000 0 0x1000>;
1987                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1988                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1989                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1990                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
1991                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1992                         clock-names = "aux",
1993                                       "cfg_ahb",
1994                                       "ref",
1995                                       "refgen",
1996                                       "pipe";
1997
1998                         clock-output-names = "pcie_1_pipe_clk";
1999                         #clock-cells = <0>;
2000
2001                         #phy-cells = <0>;
2002
2003                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2004                         reset-names = "phy";
2005
2006                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2007                         assigned-clock-rates = <100000000>;
2008
2009                         status = "disabled";
2010                 };
2011
2012                 ufs_mem_hc: ufshc@1d84000 {
2013                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2014                                      "jedec,ufs-2.0";
2015                         reg = <0 0x01d84000 0 0x2500>,
2016                               <0 0x01d90000 0 0x8000>;
2017                         reg-names = "std", "ice";
2018                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2019                         phys = <&ufs_mem_phy_lanes>;
2020                         phy-names = "ufsphy";
2021                         lanes-per-direction = <2>;
2022                         #reset-cells = <1>;
2023                         resets = <&gcc GCC_UFS_PHY_BCR>;
2024                         reset-names = "rst";
2025
2026                         iommus = <&apps_smmu 0x300 0>;
2027
2028                         clock-names =
2029                                 "core_clk",
2030                                 "bus_aggr_clk",
2031                                 "iface_clk",
2032                                 "core_clk_unipro",
2033                                 "ref_clk",
2034                                 "tx_lane0_sync_clk",
2035                                 "rx_lane0_sync_clk",
2036                                 "rx_lane1_sync_clk",
2037                                 "ice_core_clk";
2038                         clocks =
2039                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2040                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2041                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2042                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2043                                 <&rpmhcc RPMH_CXO_CLK>,
2044                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2045                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2046                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2047                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2048                         freq-table-hz =
2049                                 <37500000 300000000>,
2050                                 <0 0>,
2051                                 <0 0>,
2052                                 <37500000 300000000>,
2053                                 <0 0>,
2054                                 <0 0>,
2055                                 <0 0>,
2056                                 <0 0>,
2057                                 <0 300000000>;
2058
2059                         status = "disabled";
2060                 };
2061
2062                 ufs_mem_phy: phy@1d87000 {
2063                         compatible = "qcom,sm8150-qmp-ufs-phy";
2064                         reg = <0 0x01d87000 0 0x1c0>;
2065                         #address-cells = <2>;
2066                         #size-cells = <2>;
2067                         ranges;
2068                         clock-names = "ref",
2069                                       "ref_aux";
2070                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2071                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2072
2073                         power-domains = <&gcc UFS_PHY_GDSC>;
2074
2075                         resets = <&ufs_mem_hc 0>;
2076                         reset-names = "ufsphy";
2077                         status = "disabled";
2078
2079                         ufs_mem_phy_lanes: phy@1d87400 {
2080                                 reg = <0 0x01d87400 0 0x16c>,
2081                                       <0 0x01d87600 0 0x200>,
2082                                       <0 0x01d87c00 0 0x200>,
2083                                       <0 0x01d87800 0 0x16c>,
2084                                       <0 0x01d87a00 0 0x200>;
2085                                 #phy-cells = <0>;
2086                         };
2087                 };
2088
2089                 cryptobam: dma-controller@1dc4000 {
2090                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2091                         reg = <0 0x01dc4000 0 0x24000>;
2092                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2093                         #dma-cells = <1>;
2094                         qcom,ee = <0>;
2095                         qcom,controlled-remotely;
2096                         num-channels = <8>;
2097                         qcom,num-ees = <2>;
2098                         iommus = <&apps_smmu 0x502 0x0641>,
2099                                  <&apps_smmu 0x504 0x0011>,
2100                                  <&apps_smmu 0x506 0x0011>,
2101                                  <&apps_smmu 0x508 0x0011>,
2102                                  <&apps_smmu 0x512 0x0000>;
2103                 };
2104
2105                 crypto: crypto@1dfa000 {
2106                         compatible = "qcom,sm8150-qce", "qcom,qce";
2107                         reg = <0 0x01dfa000 0 0x6000>;
2108                         dmas = <&cryptobam 4>, <&cryptobam 5>;
2109                         dma-names = "rx", "tx";
2110                         iommus = <&apps_smmu 0x502 0x0641>,
2111                                  <&apps_smmu 0x504 0x0011>,
2112                                  <&apps_smmu 0x506 0x0011>,
2113                                  <&apps_smmu 0x508 0x0011>,
2114                                  <&apps_smmu 0x512 0x0000>;
2115                         interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2116                         interconnect-names = "memory";
2117                 };
2118
2119                 tcsr_mutex: hwlock@1f40000 {
2120                         compatible = "qcom,tcsr-mutex";
2121                         reg = <0x0 0x01f40000 0x0 0x20000>;
2122                         #hwlock-cells = <1>;
2123                 };
2124
2125                 tcsr_regs_1: syscon@1f60000 {
2126                         compatible = "qcom,sm8150-tcsr", "syscon";
2127                         reg = <0x0 0x01f60000 0x0 0x20000>;
2128                 };
2129
2130                 remoteproc_slpi: remoteproc@2400000 {
2131                         compatible = "qcom,sm8150-slpi-pas";
2132                         reg = <0x0 0x02400000 0x0 0x4040>;
2133
2134                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2135                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2136                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2137                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2138                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2139                         interrupt-names = "wdog", "fatal", "ready",
2140                                           "handover", "stop-ack";
2141
2142                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2143                         clock-names = "xo";
2144
2145                         power-domains = <&rpmhpd SM8150_LCX>,
2146                                         <&rpmhpd SM8150_LMX>;
2147                         power-domain-names = "lcx", "lmx";
2148
2149                         memory-region = <&slpi_mem>;
2150
2151                         qcom,qmp = <&aoss_qmp>;
2152
2153                         qcom,smem-states = <&slpi_smp2p_out 0>;
2154                         qcom,smem-state-names = "stop";
2155
2156                         status = "disabled";
2157
2158                         glink-edge {
2159                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2160                                 label = "dsps";
2161                                 qcom,remote-pid = <3>;
2162                                 mboxes = <&apss_shared 24>;
2163
2164                                 fastrpc {
2165                                         compatible = "qcom,fastrpc";
2166                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2167                                         label = "sdsp";
2168                                         qcom,non-secure-domain;
2169                                         #address-cells = <1>;
2170                                         #size-cells = <0>;
2171
2172                                         compute-cb@1 {
2173                                                 compatible = "qcom,fastrpc-compute-cb";
2174                                                 reg = <1>;
2175                                                 iommus = <&apps_smmu 0x05a1 0x0>;
2176                                         };
2177
2178                                         compute-cb@2 {
2179                                                 compatible = "qcom,fastrpc-compute-cb";
2180                                                 reg = <2>;
2181                                                 iommus = <&apps_smmu 0x05a2 0x0>;
2182                                         };
2183
2184                                         compute-cb@3 {
2185                                                 compatible = "qcom,fastrpc-compute-cb";
2186                                                 reg = <3>;
2187                                                 iommus = <&apps_smmu 0x05a3 0x0>;
2188                                                 /* note: shared-cb = <4> in downstream */
2189                                         };
2190                                 };
2191                         };
2192                 };
2193
2194                 gpu: gpu@2c00000 {
2195                         compatible = "qcom,adreno-640.1", "qcom,adreno";
2196                         reg = <0 0x02c00000 0 0x40000>;
2197                         reg-names = "kgsl_3d0_reg_memory";
2198
2199                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2200
2201                         iommus = <&adreno_smmu 0 0x401>;
2202
2203                         operating-points-v2 = <&gpu_opp_table>;
2204
2205                         qcom,gmu = <&gmu>;
2206
2207                         nvmem-cells = <&gpu_speed_bin>;
2208                         nvmem-cell-names = "speed_bin";
2209
2210                         status = "disabled";
2211
2212                         zap-shader {
2213                                 memory-region = <&gpu_mem>;
2214                         };
2215
2216                         gpu_opp_table: opp-table {
2217                                 compatible = "operating-points-v2";
2218
2219                                 opp-675000000 {
2220                                         opp-hz = /bits/ 64 <675000000>;
2221                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2222                                         opp-supported-hw = <0x2>;
2223                                 };
2224
2225                                 opp-585000000 {
2226                                         opp-hz = /bits/ 64 <585000000>;
2227                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2228                                         opp-supported-hw = <0x3>;
2229                                 };
2230
2231                                 opp-499200000 {
2232                                         opp-hz = /bits/ 64 <499200000>;
2233                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2234                                         opp-supported-hw = <0x3>;
2235                                 };
2236
2237                                 opp-427000000 {
2238                                         opp-hz = /bits/ 64 <427000000>;
2239                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2240                                         opp-supported-hw = <0x3>;
2241                                 };
2242
2243                                 opp-345000000 {
2244                                         opp-hz = /bits/ 64 <345000000>;
2245                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2246                                         opp-supported-hw = <0x3>;
2247                                 };
2248
2249                                 opp-257000000 {
2250                                         opp-hz = /bits/ 64 <257000000>;
2251                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2252                                         opp-supported-hw = <0x3>;
2253                                 };
2254                         };
2255                 };
2256
2257                 gmu: gmu@2c6a000 {
2258                         compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2259
2260                         reg = <0 0x02c6a000 0 0x30000>,
2261                               <0 0x0b290000 0 0x10000>,
2262                               <0 0x0b490000 0 0x10000>;
2263                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2264
2265                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2266                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2267                         interrupt-names = "hfi", "gmu";
2268
2269                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2270                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2271                                  <&gpucc GPU_CC_CXO_CLK>,
2272                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2273                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2274                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2275
2276                         power-domains = <&gpucc GPU_CX_GDSC>,
2277                                         <&gpucc GPU_GX_GDSC>;
2278                         power-domain-names = "cx", "gx";
2279
2280                         iommus = <&adreno_smmu 5 0x400>;
2281
2282                         operating-points-v2 = <&gmu_opp_table>;
2283
2284                         status = "disabled";
2285
2286                         gmu_opp_table: opp-table {
2287                                 compatible = "operating-points-v2";
2288
2289                                 opp-200000000 {
2290                                         opp-hz = /bits/ 64 <200000000>;
2291                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292                                 };
2293                         };
2294                 };
2295
2296                 gpucc: clock-controller@2c90000 {
2297                         compatible = "qcom,sm8150-gpucc";
2298                         reg = <0 0x02c90000 0 0x9000>;
2299                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2300                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2301                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2302                         clock-names = "bi_tcxo",
2303                                       "gcc_gpu_gpll0_clk_src",
2304                                       "gcc_gpu_gpll0_div_clk_src";
2305                         #clock-cells = <1>;
2306                         #reset-cells = <1>;
2307                         #power-domain-cells = <1>;
2308                 };
2309
2310                 adreno_smmu: iommu@2ca0000 {
2311                         compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2312                                      "qcom,smmu-500", "arm,mmu-500";
2313                         reg = <0 0x02ca0000 0 0x10000>;
2314                         #iommu-cells = <2>;
2315                         #global-interrupts = <1>;
2316                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2317                                 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2318                                 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2319                                 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2320                                 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2321                                 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2322                                 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2323                                 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2324                                 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2325                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2326                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2327                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2328                         clock-names = "ahb", "bus", "iface";
2329
2330                         power-domains = <&gpucc GPU_CX_GDSC>;
2331                 };
2332
2333                 tlmm: pinctrl@3100000 {
2334                         compatible = "qcom,sm8150-pinctrl";
2335                         reg = <0x0 0x03100000 0x0 0x300000>,
2336                               <0x0 0x03500000 0x0 0x300000>,
2337                               <0x0 0x03900000 0x0 0x300000>,
2338                               <0x0 0x03D00000 0x0 0x300000>;
2339                         reg-names = "west", "east", "north", "south";
2340                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2341                         gpio-ranges = <&tlmm 0 0 176>;
2342                         gpio-controller;
2343                         #gpio-cells = <2>;
2344                         interrupt-controller;
2345                         #interrupt-cells = <2>;
2346                         wakeup-parent = <&pdc>;
2347
2348                         qup_i2c0_default: qup-i2c0-default-state {
2349                                 pins = "gpio0", "gpio1";
2350                                 function = "qup0";
2351                                 drive-strength = <0x02>;
2352                                 bias-disable;
2353                         };
2354
2355                         qup_spi0_default: qup-spi0-default-state {
2356                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2357                                 function = "qup0";
2358                                 drive-strength = <6>;
2359                                 bias-disable;
2360                         };
2361
2362                         qup_i2c1_default: qup-i2c1-default-state {
2363                                 pins = "gpio114", "gpio115";
2364                                 function = "qup1";
2365                                 drive-strength = <2>;
2366                                 bias-disable;
2367                         };
2368
2369                         qup_spi1_default: qup-spi1-default-state {
2370                                 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2371                                 function = "qup1";
2372                                 drive-strength = <6>;
2373                                 bias-disable;
2374                         };
2375
2376                         qup_i2c2_default: qup-i2c2-default-state {
2377                                 pins = "gpio126", "gpio127";
2378                                 function = "qup2";
2379                                 drive-strength = <2>;
2380                                 bias-disable;
2381                         };
2382
2383                         qup_spi2_default: qup-spi2-default-state {
2384                                 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2385                                 function = "qup2";
2386                                 drive-strength = <6>;
2387                                 bias-disable;
2388                         };
2389
2390                         qup_i2c3_default: qup-i2c3-default-state {
2391                                 pins = "gpio144", "gpio145";
2392                                 function = "qup3";
2393                                 drive-strength = <2>;
2394                                 bias-disable;
2395                         };
2396
2397                         qup_spi3_default: qup-spi3-default-state {
2398                                 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2399                                 function = "qup3";
2400                                 drive-strength = <6>;
2401                                 bias-disable;
2402                         };
2403
2404                         qup_i2c4_default: qup-i2c4-default-state {
2405                                 pins = "gpio51", "gpio52";
2406                                 function = "qup4";
2407                                 drive-strength = <2>;
2408                                 bias-disable;
2409                         };
2410
2411                         qup_spi4_default: qup-spi4-default-state {
2412                                 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2413                                 function = "qup4";
2414                                 drive-strength = <6>;
2415                                 bias-disable;
2416                         };
2417
2418                         qup_i2c5_default: qup-i2c5-default-state {
2419                                 pins = "gpio121", "gpio122";
2420                                 function = "qup5";
2421                                 drive-strength = <2>;
2422                                 bias-disable;
2423                         };
2424
2425                         qup_spi5_default: qup-spi5-default-state {
2426                                 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2427                                 function = "qup5";
2428                                 drive-strength = <6>;
2429                                 bias-disable;
2430                         };
2431
2432                         qup_i2c6_default: qup-i2c6-default-state {
2433                                 pins = "gpio6", "gpio7";
2434                                 function = "qup6";
2435                                 drive-strength = <2>;
2436                                 bias-disable;
2437                         };
2438
2439                         qup_spi6_default: qup-spi6_default-state {
2440                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2441                                 function = "qup6";
2442                                 drive-strength = <6>;
2443                                 bias-disable;
2444                         };
2445
2446                         qup_i2c7_default: qup-i2c7-default-state {
2447                                 pins = "gpio98", "gpio99";
2448                                 function = "qup7";
2449                                 drive-strength = <2>;
2450                                 bias-disable;
2451                         };
2452
2453                         qup_spi7_default: qup-spi7_default-state {
2454                                 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2455                                 function = "qup7";
2456                                 drive-strength = <6>;
2457                                 bias-disable;
2458                         };
2459
2460                         qup_i2c8_default: qup-i2c8-default-state {
2461                                 pins = "gpio88", "gpio89";
2462                                 function = "qup8";
2463                                 drive-strength = <2>;
2464                                 bias-disable;
2465                         };
2466
2467                         qup_spi8_default: qup-spi8-default-state {
2468                                 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2469                                 function = "qup8";
2470                                 drive-strength = <6>;
2471                                 bias-disable;
2472                         };
2473
2474                         qup_i2c9_default: qup-i2c9-default-state {
2475                                 pins = "gpio39", "gpio40";
2476                                 function = "qup9";
2477                                 drive-strength = <2>;
2478                                 bias-disable;
2479                         };
2480
2481                         qup_spi9_default: qup-spi9-default-state {
2482                                 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2483                                 function = "qup9";
2484                                 drive-strength = <6>;
2485                                 bias-disable;
2486                         };
2487
2488                         qup_uart9_default: qup-uart9-default-state {
2489                                 pins = "gpio41", "gpio42";
2490                                 function = "qup9";
2491                                 drive-strength = <2>;
2492                                 bias-disable;
2493                         };
2494
2495                         qup_i2c10_default: qup-i2c10-default-state {
2496                                 pins = "gpio9", "gpio10";
2497                                 function = "qup10";
2498                                 drive-strength = <2>;
2499                                 bias-disable;
2500                         };
2501
2502                         qup_spi10_default: qup-spi10-default-state {
2503                                 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2504                                 function = "qup10";
2505                                 drive-strength = <6>;
2506                                 bias-disable;
2507                         };
2508
2509                         qup_i2c11_default: qup-i2c11-default-state {
2510                                 pins = "gpio94", "gpio95";
2511                                 function = "qup11";
2512                                 drive-strength = <2>;
2513                                 bias-disable;
2514                         };
2515
2516                         qup_spi11_default: qup-spi11-default-state {
2517                                 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2518                                 function = "qup11";
2519                                 drive-strength = <6>;
2520                                 bias-disable;
2521                         };
2522
2523                         qup_i2c12_default: qup-i2c12-default-state {
2524                                 pins = "gpio83", "gpio84";
2525                                 function = "qup12";
2526                                 drive-strength = <2>;
2527                                 bias-disable;
2528                         };
2529
2530                         qup_spi12_default: qup-spi12-default-state {
2531                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2532                                 function = "qup12";
2533                                 drive-strength = <6>;
2534                                 bias-disable;
2535                         };
2536
2537                         qup_i2c13_default: qup-i2c13-default-state {
2538                                 pins = "gpio43", "gpio44";
2539                                 function = "qup13";
2540                                 drive-strength = <2>;
2541                                 bias-disable;
2542                         };
2543
2544                         qup_spi13_default: qup-spi13-default-state {
2545                                 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2546                                 function = "qup13";
2547                                 drive-strength = <6>;
2548                                 bias-disable;
2549                         };
2550
2551                         qup_i2c14_default: qup-i2c14-default-state {
2552                                 pins = "gpio47", "gpio48";
2553                                 function = "qup14";
2554                                 drive-strength = <2>;
2555                                 bias-disable;
2556                         };
2557
2558                         qup_spi14_default: qup-spi14-default-state {
2559                                 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2560                                 function = "qup14";
2561                                 drive-strength = <6>;
2562                                 bias-disable;
2563                         };
2564
2565                         qup_i2c15_default: qup-i2c15-default-state {
2566                                 pins = "gpio27", "gpio28";
2567                                 function = "qup15";
2568                                 drive-strength = <2>;
2569                                 bias-disable;
2570                         };
2571
2572                         qup_spi15_default: qup-spi15-default-state {
2573                                 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2574                                 function = "qup15";
2575                                 drive-strength = <6>;
2576                                 bias-disable;
2577                         };
2578
2579                         qup_i2c16_default: qup-i2c16-default-state {
2580                                 pins = "gpio86", "gpio85";
2581                                 function = "qup16";
2582                                 drive-strength = <2>;
2583                                 bias-disable;
2584                         };
2585
2586                         qup_spi16_default: qup-spi16-default-state {
2587                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2588                                 function = "qup16";
2589                                 drive-strength = <6>;
2590                                 bias-disable;
2591                         };
2592
2593                         qup_i2c17_default: qup-i2c17-default-state {
2594                                 pins = "gpio55", "gpio56";
2595                                 function = "qup17";
2596                                 drive-strength = <2>;
2597                                 bias-disable;
2598                         };
2599
2600                         qup_spi17_default: qup-spi17-default-state {
2601                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2602                                 function = "qup17";
2603                                 drive-strength = <6>;
2604                                 bias-disable;
2605                         };
2606
2607                         qup_i2c18_default: qup-i2c18-default-state {
2608                                 pins = "gpio23", "gpio24";
2609                                 function = "qup18";
2610                                 drive-strength = <2>;
2611                                 bias-disable;
2612                         };
2613
2614                         qup_spi18_default: qup-spi18-default-state {
2615                                 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2616                                 function = "qup18";
2617                                 drive-strength = <6>;
2618                                 bias-disable;
2619                         };
2620
2621                         qup_i2c19_default: qup-i2c19-default-state {
2622                                 pins = "gpio57", "gpio58";
2623                                 function = "qup19";
2624                                 drive-strength = <2>;
2625                                 bias-disable;
2626                         };
2627
2628                         qup_spi19_default: qup-spi19-default-state {
2629                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2630                                 function = "qup19";
2631                                 drive-strength = <6>;
2632                                 bias-disable;
2633                         };
2634
2635                         pcie0_default_state: pcie0-default-state {
2636                                 perst-pins {
2637                                         pins = "gpio35";
2638                                         function = "gpio";
2639                                         drive-strength = <2>;
2640                                         bias-pull-down;
2641                                 };
2642
2643                                 clkreq-pins {
2644                                         pins = "gpio36";
2645                                         function = "pci_e0";
2646                                         drive-strength = <2>;
2647                                         bias-pull-up;
2648                                 };
2649
2650                                 wake-pins {
2651                                         pins = "gpio37";
2652                                         function = "gpio";
2653                                         drive-strength = <2>;
2654                                         bias-pull-up;
2655                                 };
2656                         };
2657
2658                         pcie1_default_state: pcie1-default-state {
2659                                 perst-pins {
2660                                         pins = "gpio102";
2661                                         function = "gpio";
2662                                         drive-strength = <2>;
2663                                         bias-pull-down;
2664                                 };
2665
2666                                 clkreq-pins {
2667                                         pins = "gpio103";
2668                                         function = "pci_e1";
2669                                         drive-strength = <2>;
2670                                         bias-pull-up;
2671                                 };
2672
2673                                 wake-pins {
2674                                         pins = "gpio104";
2675                                         function = "gpio";
2676                                         drive-strength = <2>;
2677                                         bias-pull-up;
2678                                 };
2679                         };
2680                 };
2681
2682                 remoteproc_mpss: remoteproc@4080000 {
2683                         compatible = "qcom,sm8150-mpss-pas";
2684                         reg = <0x0 0x04080000 0x0 0x4040>;
2685
2686                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2687                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2688                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2689                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2690                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2691                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2692                         interrupt-names = "wdog", "fatal", "ready", "handover",
2693                                           "stop-ack", "shutdown-ack";
2694
2695                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2696                         clock-names = "xo";
2697
2698                         power-domains = <&rpmhpd SM8150_CX>,
2699                                         <&rpmhpd SM8150_MSS>;
2700                         power-domain-names = "cx", "mss";
2701
2702                         memory-region = <&mpss_mem>;
2703
2704                         qcom,qmp = <&aoss_qmp>;
2705
2706                         qcom,smem-states = <&modem_smp2p_out 0>;
2707                         qcom,smem-state-names = "stop";
2708
2709                         status = "disabled";
2710
2711                         glink-edge {
2712                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2713                                 label = "modem";
2714                                 qcom,remote-pid = <1>;
2715                                 mboxes = <&apss_shared 12>;
2716                         };
2717                 };
2718
2719                 stm@6002000 {
2720                         compatible = "arm,coresight-stm", "arm,primecell";
2721                         reg = <0 0x06002000 0 0x1000>,
2722                               <0 0x16280000 0 0x180000>;
2723                         reg-names = "stm-base", "stm-stimulus-base";
2724
2725                         clocks = <&aoss_qmp>;
2726                         clock-names = "apb_pclk";
2727
2728                         out-ports {
2729                                 port {
2730                                         stm_out: endpoint {
2731                                                 remote-endpoint = <&funnel0_in7>;
2732                                         };
2733                                 };
2734                         };
2735                 };
2736
2737                 funnel@6041000 {
2738                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2739                         reg = <0 0x06041000 0 0x1000>;
2740
2741                         clocks = <&aoss_qmp>;
2742                         clock-names = "apb_pclk";
2743
2744                         out-ports {
2745                                 port {
2746                                         funnel0_out: endpoint {
2747                                                 remote-endpoint = <&merge_funnel_in0>;
2748                                         };
2749                                 };
2750                         };
2751
2752                         in-ports {
2753                                 #address-cells = <1>;
2754                                 #size-cells = <0>;
2755
2756                                 port@7 {
2757                                         reg = <7>;
2758                                         funnel0_in7: endpoint {
2759                                                 remote-endpoint = <&stm_out>;
2760                                         };
2761                                 };
2762                         };
2763                 };
2764
2765                 funnel@6042000 {
2766                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2767                         reg = <0 0x06042000 0 0x1000>;
2768
2769                         clocks = <&aoss_qmp>;
2770                         clock-names = "apb_pclk";
2771
2772                         out-ports {
2773                                 port {
2774                                         funnel1_out: endpoint {
2775                                                 remote-endpoint = <&merge_funnel_in1>;
2776                                         };
2777                                 };
2778                         };
2779
2780                         in-ports {
2781                                 #address-cells = <1>;
2782                                 #size-cells = <0>;
2783
2784                                 port@4 {
2785                                         reg = <4>;
2786                                         funnel1_in4: endpoint {
2787                                                 remote-endpoint = <&swao_replicator_out>;
2788                                         };
2789                                 };
2790                         };
2791                 };
2792
2793                 funnel@6043000 {
2794                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2795                         reg = <0 0x06043000 0 0x1000>;
2796
2797                         clocks = <&aoss_qmp>;
2798                         clock-names = "apb_pclk";
2799
2800                         out-ports {
2801                                 port {
2802                                         funnel2_out: endpoint {
2803                                                 remote-endpoint = <&merge_funnel_in2>;
2804                                         };
2805                                 };
2806                         };
2807
2808                         in-ports {
2809                                 #address-cells = <1>;
2810                                 #size-cells = <0>;
2811
2812                                 port@2 {
2813                                         reg = <2>;
2814                                         funnel2_in2: endpoint {
2815                                                 remote-endpoint = <&apss_merge_funnel_out>;
2816                                         };
2817                                 };
2818                         };
2819                 };
2820
2821                 funnel@6045000 {
2822                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2823                         reg = <0 0x06045000 0 0x1000>;
2824
2825                         clocks = <&aoss_qmp>;
2826                         clock-names = "apb_pclk";
2827
2828                         out-ports {
2829                                 port {
2830                                         merge_funnel_out: endpoint {
2831                                                 remote-endpoint = <&etf_in>;
2832                                         };
2833                                 };
2834                         };
2835
2836                         in-ports {
2837                                 #address-cells = <1>;
2838                                 #size-cells = <0>;
2839
2840                                 port@0 {
2841                                         reg = <0>;
2842                                         merge_funnel_in0: endpoint {
2843                                                 remote-endpoint = <&funnel0_out>;
2844                                         };
2845                                 };
2846
2847                                 port@1 {
2848                                         reg = <1>;
2849                                         merge_funnel_in1: endpoint {
2850                                                 remote-endpoint = <&funnel1_out>;
2851                                         };
2852                                 };
2853
2854                                 port@2 {
2855                                         reg = <2>;
2856                                         merge_funnel_in2: endpoint {
2857                                                 remote-endpoint = <&funnel2_out>;
2858                                         };
2859                                 };
2860                         };
2861                 };
2862
2863                 replicator@6046000 {
2864                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2865                         reg = <0 0x06046000 0 0x1000>;
2866
2867                         clocks = <&aoss_qmp>;
2868                         clock-names = "apb_pclk";
2869
2870                         out-ports {
2871                                 #address-cells = <1>;
2872                                 #size-cells = <0>;
2873
2874                                 port@0 {
2875                                         reg = <0>;
2876                                         replicator_out0: endpoint {
2877                                                 remote-endpoint = <&etr_in>;
2878                                         };
2879                                 };
2880
2881                                 port@1 {
2882                                         reg = <1>;
2883                                         replicator_out1: endpoint {
2884                                                 remote-endpoint = <&replicator1_in>;
2885                                         };
2886                                 };
2887                         };
2888
2889                         in-ports {
2890                                 port {
2891                                         replicator_in0: endpoint {
2892                                                 remote-endpoint = <&etf_out>;
2893                                         };
2894                                 };
2895                         };
2896                 };
2897
2898                 etf@6047000 {
2899                         compatible = "arm,coresight-tmc", "arm,primecell";
2900                         reg = <0 0x06047000 0 0x1000>;
2901
2902                         clocks = <&aoss_qmp>;
2903                         clock-names = "apb_pclk";
2904
2905                         out-ports {
2906                                 port {
2907                                         etf_out: endpoint {
2908                                                 remote-endpoint = <&replicator_in0>;
2909                                         };
2910                                 };
2911                         };
2912
2913                         in-ports {
2914                                 port {
2915                                         etf_in: endpoint {
2916                                                 remote-endpoint = <&merge_funnel_out>;
2917                                         };
2918                                 };
2919                         };
2920                 };
2921
2922                 etr@6048000 {
2923                         compatible = "arm,coresight-tmc", "arm,primecell";
2924                         reg = <0 0x06048000 0 0x1000>;
2925                         iommus = <&apps_smmu 0x05e0 0x0>;
2926
2927                         clocks = <&aoss_qmp>;
2928                         clock-names = "apb_pclk";
2929                         arm,scatter-gather;
2930
2931                         in-ports {
2932                                 port {
2933                                         etr_in: endpoint {
2934                                                 remote-endpoint = <&replicator_out0>;
2935                                         };
2936                                 };
2937                         };
2938                 };
2939
2940                 replicator@604a000 {
2941                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2942                         reg = <0 0x0604a000 0 0x1000>;
2943
2944                         clocks = <&aoss_qmp>;
2945                         clock-names = "apb_pclk";
2946
2947                         out-ports {
2948                                 #address-cells = <1>;
2949                                 #size-cells = <0>;
2950
2951                                 port@1 {
2952                                         reg = <1>;
2953                                         replicator1_out: endpoint {
2954                                                 remote-endpoint = <&swao_funnel_in>;
2955                                         };
2956                                 };
2957                         };
2958
2959                         in-ports {
2960                                 #address-cells = <1>;
2961                                 #size-cells = <0>;
2962
2963                                 port@1 {
2964                                         reg = <1>;
2965                                         replicator1_in: endpoint {
2966                                                 remote-endpoint = <&replicator_out1>;
2967                                         };
2968                                 };
2969                         };
2970                 };
2971
2972                 funnel@6b08000 {
2973                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2974                         reg = <0 0x06b08000 0 0x1000>;
2975
2976                         clocks = <&aoss_qmp>;
2977                         clock-names = "apb_pclk";
2978
2979                         out-ports {
2980                                 port {
2981                                         swao_funnel_out: endpoint {
2982                                                 remote-endpoint = <&swao_etf_in>;
2983                                         };
2984                                 };
2985                         };
2986
2987                         in-ports {
2988                                 #address-cells = <1>;
2989                                 #size-cells = <0>;
2990
2991                                 port@6 {
2992                                         reg = <6>;
2993                                         swao_funnel_in: endpoint {
2994                                                 remote-endpoint = <&replicator1_out>;
2995                                         };
2996                                 };
2997                         };
2998                 };
2999
3000                 etf@6b09000 {
3001                         compatible = "arm,coresight-tmc", "arm,primecell";
3002                         reg = <0 0x06b09000 0 0x1000>;
3003
3004                         clocks = <&aoss_qmp>;
3005                         clock-names = "apb_pclk";
3006
3007                         out-ports {
3008                                 port {
3009                                         swao_etf_out: endpoint {
3010                                                 remote-endpoint = <&swao_replicator_in>;
3011                                         };
3012                                 };
3013                         };
3014
3015                         in-ports {
3016                                 port {
3017                                         swao_etf_in: endpoint {
3018                                                 remote-endpoint = <&swao_funnel_out>;
3019                                         };
3020                                 };
3021                         };
3022                 };
3023
3024                 replicator@6b0a000 {
3025                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3026                         reg = <0 0x06b0a000 0 0x1000>;
3027
3028                         clocks = <&aoss_qmp>;
3029                         clock-names = "apb_pclk";
3030                         qcom,replicator-loses-context;
3031
3032                         out-ports {
3033                                 port {
3034                                         swao_replicator_out: endpoint {
3035                                                 remote-endpoint = <&funnel1_in4>;
3036                                         };
3037                                 };
3038                         };
3039
3040                         in-ports {
3041                                 port {
3042                                         swao_replicator_in: endpoint {
3043                                                 remote-endpoint = <&swao_etf_out>;
3044                                         };
3045                                 };
3046                         };
3047                 };
3048
3049                 etm@7040000 {
3050                         compatible = "arm,coresight-etm4x", "arm,primecell";
3051                         reg = <0 0x07040000 0 0x1000>;
3052
3053                         cpu = <&CPU0>;
3054
3055                         clocks = <&aoss_qmp>;
3056                         clock-names = "apb_pclk";
3057                         arm,coresight-loses-context-with-cpu;
3058                         qcom,skip-power-up;
3059
3060                         out-ports {
3061                                 port {
3062                                         etm0_out: endpoint {
3063                                                 remote-endpoint = <&apss_funnel_in0>;
3064                                         };
3065                                 };
3066                         };
3067                 };
3068
3069                 etm@7140000 {
3070                         compatible = "arm,coresight-etm4x", "arm,primecell";
3071                         reg = <0 0x07140000 0 0x1000>;
3072
3073                         cpu = <&CPU1>;
3074
3075                         clocks = <&aoss_qmp>;
3076                         clock-names = "apb_pclk";
3077                         arm,coresight-loses-context-with-cpu;
3078                         qcom,skip-power-up;
3079
3080                         out-ports {
3081                                 port {
3082                                         etm1_out: endpoint {
3083                                                 remote-endpoint = <&apss_funnel_in1>;
3084                                         };
3085                                 };
3086                         };
3087                 };
3088
3089                 etm@7240000 {
3090                         compatible = "arm,coresight-etm4x", "arm,primecell";
3091                         reg = <0 0x07240000 0 0x1000>;
3092
3093                         cpu = <&CPU2>;
3094
3095                         clocks = <&aoss_qmp>;
3096                         clock-names = "apb_pclk";
3097                         arm,coresight-loses-context-with-cpu;
3098                         qcom,skip-power-up;
3099
3100                         out-ports {
3101                                 port {
3102                                         etm2_out: endpoint {
3103                                                 remote-endpoint = <&apss_funnel_in2>;
3104                                         };
3105                                 };
3106                         };
3107                 };
3108
3109                 etm@7340000 {
3110                         compatible = "arm,coresight-etm4x", "arm,primecell";
3111                         reg = <0 0x07340000 0 0x1000>;
3112
3113                         cpu = <&CPU3>;
3114
3115                         clocks = <&aoss_qmp>;
3116                         clock-names = "apb_pclk";
3117                         arm,coresight-loses-context-with-cpu;
3118                         qcom,skip-power-up;
3119
3120                         out-ports {
3121                                 port {
3122                                         etm3_out: endpoint {
3123                                                 remote-endpoint = <&apss_funnel_in3>;
3124                                         };
3125                                 };
3126                         };
3127                 };
3128
3129                 etm@7440000 {
3130                         compatible = "arm,coresight-etm4x", "arm,primecell";
3131                         reg = <0 0x07440000 0 0x1000>;
3132
3133                         cpu = <&CPU4>;
3134
3135                         clocks = <&aoss_qmp>;
3136                         clock-names = "apb_pclk";
3137                         arm,coresight-loses-context-with-cpu;
3138                         qcom,skip-power-up;
3139
3140                         out-ports {
3141                                 port {
3142                                         etm4_out: endpoint {
3143                                                 remote-endpoint = <&apss_funnel_in4>;
3144                                         };
3145                                 };
3146                         };
3147                 };
3148
3149                 etm@7540000 {
3150                         compatible = "arm,coresight-etm4x", "arm,primecell";
3151                         reg = <0 0x07540000 0 0x1000>;
3152
3153                         cpu = <&CPU5>;
3154
3155                         clocks = <&aoss_qmp>;
3156                         clock-names = "apb_pclk";
3157                         arm,coresight-loses-context-with-cpu;
3158                         qcom,skip-power-up;
3159
3160                         out-ports {
3161                                 port {
3162                                         etm5_out: endpoint {
3163                                                 remote-endpoint = <&apss_funnel_in5>;
3164                                         };
3165                                 };
3166                         };
3167                 };
3168
3169                 etm@7640000 {
3170                         compatible = "arm,coresight-etm4x", "arm,primecell";
3171                         reg = <0 0x07640000 0 0x1000>;
3172
3173                         cpu = <&CPU6>;
3174
3175                         clocks = <&aoss_qmp>;
3176                         clock-names = "apb_pclk";
3177                         arm,coresight-loses-context-with-cpu;
3178                         qcom,skip-power-up;
3179
3180                         out-ports {
3181                                 port {
3182                                         etm6_out: endpoint {
3183                                                 remote-endpoint = <&apss_funnel_in6>;
3184                                         };
3185                                 };
3186                         };
3187                 };
3188
3189                 etm@7740000 {
3190                         compatible = "arm,coresight-etm4x", "arm,primecell";
3191                         reg = <0 0x07740000 0 0x1000>;
3192
3193                         cpu = <&CPU7>;
3194
3195                         clocks = <&aoss_qmp>;
3196                         clock-names = "apb_pclk";
3197                         arm,coresight-loses-context-with-cpu;
3198                         qcom,skip-power-up;
3199
3200                         out-ports {
3201                                 port {
3202                                         etm7_out: endpoint {
3203                                                 remote-endpoint = <&apss_funnel_in7>;
3204                                         };
3205                                 };
3206                         };
3207                 };
3208
3209                 funnel@7800000 { /* APSS Funnel */
3210                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3211                         reg = <0 0x07800000 0 0x1000>;
3212
3213                         clocks = <&aoss_qmp>;
3214                         clock-names = "apb_pclk";
3215
3216                         out-ports {
3217                                 port {
3218                                         apss_funnel_out: endpoint {
3219                                                 remote-endpoint = <&apss_merge_funnel_in>;
3220                                         };
3221                                 };
3222                         };
3223
3224                         in-ports {
3225                                 #address-cells = <1>;
3226                                 #size-cells = <0>;
3227
3228                                 port@0 {
3229                                         reg = <0>;
3230                                         apss_funnel_in0: endpoint {
3231                                                 remote-endpoint = <&etm0_out>;
3232                                         };
3233                                 };
3234
3235                                 port@1 {
3236                                         reg = <1>;
3237                                         apss_funnel_in1: endpoint {
3238                                                 remote-endpoint = <&etm1_out>;
3239                                         };
3240                                 };
3241
3242                                 port@2 {
3243                                         reg = <2>;
3244                                         apss_funnel_in2: endpoint {
3245                                                 remote-endpoint = <&etm2_out>;
3246                                         };
3247                                 };
3248
3249                                 port@3 {
3250                                         reg = <3>;
3251                                         apss_funnel_in3: endpoint {
3252                                                 remote-endpoint = <&etm3_out>;
3253                                         };
3254                                 };
3255
3256                                 port@4 {
3257                                         reg = <4>;
3258                                         apss_funnel_in4: endpoint {
3259                                                 remote-endpoint = <&etm4_out>;
3260                                         };
3261                                 };
3262
3263                                 port@5 {
3264                                         reg = <5>;
3265                                         apss_funnel_in5: endpoint {
3266                                                 remote-endpoint = <&etm5_out>;
3267                                         };
3268                                 };
3269
3270                                 port@6 {
3271                                         reg = <6>;
3272                                         apss_funnel_in6: endpoint {
3273                                                 remote-endpoint = <&etm6_out>;
3274                                         };
3275                                 };
3276
3277                                 port@7 {
3278                                         reg = <7>;
3279                                         apss_funnel_in7: endpoint {
3280                                                 remote-endpoint = <&etm7_out>;
3281                                         };
3282                                 };
3283                         };
3284                 };
3285
3286                 funnel@7810000 {
3287                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3288                         reg = <0 0x07810000 0 0x1000>;
3289
3290                         clocks = <&aoss_qmp>;
3291                         clock-names = "apb_pclk";
3292
3293                         out-ports {
3294                                 port {
3295                                         apss_merge_funnel_out: endpoint {
3296                                                 remote-endpoint = <&funnel2_in2>;
3297                                         };
3298                                 };
3299                         };
3300
3301                         in-ports {
3302                                 port {
3303                                         apss_merge_funnel_in: endpoint {
3304                                                 remote-endpoint = <&apss_funnel_out>;
3305                                         };
3306                                 };
3307                         };
3308                 };
3309
3310                 remoteproc_cdsp: remoteproc@8300000 {
3311                         compatible = "qcom,sm8150-cdsp-pas";
3312                         reg = <0x0 0x08300000 0x0 0x4040>;
3313
3314                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3315                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3316                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3317                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3318                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3319                         interrupt-names = "wdog", "fatal", "ready",
3320                                           "handover", "stop-ack";
3321
3322                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3323                         clock-names = "xo";
3324
3325                         power-domains = <&rpmhpd SM8150_CX>;
3326
3327                         memory-region = <&cdsp_mem>;
3328
3329                         qcom,qmp = <&aoss_qmp>;
3330
3331                         qcom,smem-states = <&cdsp_smp2p_out 0>;
3332                         qcom,smem-state-names = "stop";
3333
3334                         status = "disabled";
3335
3336                         glink-edge {
3337                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3338                                 label = "cdsp";
3339                                 qcom,remote-pid = <5>;
3340                                 mboxes = <&apss_shared 4>;
3341
3342                                 fastrpc {
3343                                         compatible = "qcom,fastrpc";
3344                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3345                                         label = "cdsp";
3346                                         qcom,non-secure-domain;
3347                                         #address-cells = <1>;
3348                                         #size-cells = <0>;
3349
3350                                         compute-cb@1 {
3351                                                 compatible = "qcom,fastrpc-compute-cb";
3352                                                 reg = <1>;
3353                                                 iommus = <&apps_smmu 0x1001 0x0460>;
3354                                         };
3355
3356                                         compute-cb@2 {
3357                                                 compatible = "qcom,fastrpc-compute-cb";
3358                                                 reg = <2>;
3359                                                 iommus = <&apps_smmu 0x1002 0x0460>;
3360                                         };
3361
3362                                         compute-cb@3 {
3363                                                 compatible = "qcom,fastrpc-compute-cb";
3364                                                 reg = <3>;
3365                                                 iommus = <&apps_smmu 0x1003 0x0460>;
3366                                         };
3367
3368                                         compute-cb@4 {
3369                                                 compatible = "qcom,fastrpc-compute-cb";
3370                                                 reg = <4>;
3371                                                 iommus = <&apps_smmu 0x1004 0x0460>;
3372                                         };
3373
3374                                         compute-cb@5 {
3375                                                 compatible = "qcom,fastrpc-compute-cb";
3376                                                 reg = <5>;
3377                                                 iommus = <&apps_smmu 0x1005 0x0460>;
3378                                         };
3379
3380                                         compute-cb@6 {
3381                                                 compatible = "qcom,fastrpc-compute-cb";
3382                                                 reg = <6>;
3383                                                 iommus = <&apps_smmu 0x1006 0x0460>;
3384                                         };
3385
3386                                         compute-cb@7 {
3387                                                 compatible = "qcom,fastrpc-compute-cb";
3388                                                 reg = <7>;
3389                                                 iommus = <&apps_smmu 0x1007 0x0460>;
3390                                         };
3391
3392                                         compute-cb@8 {
3393                                                 compatible = "qcom,fastrpc-compute-cb";
3394                                                 reg = <8>;
3395                                                 iommus = <&apps_smmu 0x1008 0x0460>;
3396                                         };
3397
3398                                         /* note: secure cb9 in downstream */
3399                                 };
3400                         };
3401                 };
3402
3403                 usb_1_hsphy: phy@88e2000 {
3404                         compatible = "qcom,sm8150-usb-hs-phy",
3405                                      "qcom,usb-snps-hs-7nm-phy";
3406                         reg = <0 0x088e2000 0 0x400>;
3407                         status = "disabled";
3408                         #phy-cells = <0>;
3409
3410                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3411                         clock-names = "ref";
3412
3413                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3414                 };
3415
3416                 usb_2_hsphy: phy@88e3000 {
3417                         compatible = "qcom,sm8150-usb-hs-phy",
3418                                      "qcom,usb-snps-hs-7nm-phy";
3419                         reg = <0 0x088e3000 0 0x400>;
3420                         status = "disabled";
3421                         #phy-cells = <0>;
3422
3423                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3424                         clock-names = "ref";
3425
3426                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3427                 };
3428
3429                 usb_1_qmpphy: phy@88e8000 {
3430                         compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3431                         reg = <0 0x088e8000 0 0x3000>;
3432
3433                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3434                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3435                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3436                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3437                         clock-names = "aux",
3438                                       "ref",
3439                                       "com_aux",
3440                                       "usb3_pipe";
3441
3442                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3443                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3444                         reset-names = "phy", "common";
3445
3446                         #clock-cells = <1>;
3447                         #phy-cells = <1>;
3448
3449                         status = "disabled";
3450                 };
3451
3452                 usb_2_qmpphy: phy@88eb000 {
3453                         compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3454                         reg = <0 0x088eb000 0 0x200>;
3455                         status = "disabled";
3456                         #address-cells = <2>;
3457                         #size-cells = <2>;
3458                         ranges;
3459
3460                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3461                                  <&rpmhcc RPMH_CXO_CLK>,
3462                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3463                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3464                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3465
3466                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3467                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3468                         reset-names = "phy", "common";
3469
3470                         usb_2_ssphy: phy@88eb200 {
3471                                 reg = <0 0x088eb200 0 0x200>,
3472                                       <0 0x088eb400 0 0x200>,
3473                                       <0 0x088eb800 0 0x800>,
3474                                       <0 0x088eb600 0 0x200>;
3475                                 #clock-cells = <0>;
3476                                 #phy-cells = <0>;
3477                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3478                                 clock-names = "pipe0";
3479                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3480                         };
3481                 };
3482
3483                 sdhc_2: mmc@8804000 {
3484                         compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3485                         reg = <0 0x08804000 0 0x1000>;
3486
3487                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3488                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3489                         interrupt-names = "hc_irq", "pwr_irq";
3490
3491                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3492                                  <&gcc GCC_SDCC2_APPS_CLK>,
3493                                  <&rpmhcc RPMH_CXO_CLK>;
3494                         clock-names = "iface", "core", "xo";
3495                         iommus = <&apps_smmu 0x6a0 0x0>;
3496                         qcom,dll-config = <0x0007642c>;
3497                         qcom,ddr-config = <0x80040868>;
3498                         power-domains = <&rpmhpd 0>;
3499                         operating-points-v2 = <&sdhc2_opp_table>;
3500
3501                         status = "disabled";
3502
3503                         sdhc2_opp_table: opp-table {
3504                                 compatible = "operating-points-v2";
3505
3506                                 opp-19200000 {
3507                                         opp-hz = /bits/ 64 <19200000>;
3508                                         required-opps = <&rpmhpd_opp_min_svs>;
3509                                 };
3510
3511                                 opp-50000000 {
3512                                         opp-hz = /bits/ 64 <50000000>;
3513                                         required-opps = <&rpmhpd_opp_low_svs>;
3514                                 };
3515
3516                                 opp-100000000 {
3517                                         opp-hz = /bits/ 64 <100000000>;
3518                                         required-opps = <&rpmhpd_opp_svs>;
3519                                 };
3520
3521                                 opp-202000000 {
3522                                         opp-hz = /bits/ 64 <202000000>;
3523                                         required-opps = <&rpmhpd_opp_svs_l1>;
3524                                 };
3525                         };
3526                 };
3527
3528                 dc_noc: interconnect@9160000 {
3529                         compatible = "qcom,sm8150-dc-noc";
3530                         reg = <0 0x09160000 0 0x3200>;
3531                         #interconnect-cells = <2>;
3532                         qcom,bcm-voters = <&apps_bcm_voter>;
3533                 };
3534
3535                 gem_noc: interconnect@9680000 {
3536                         compatible = "qcom,sm8150-gem-noc";
3537                         reg = <0 0x09680000 0 0x3e200>;
3538                         #interconnect-cells = <2>;
3539                         qcom,bcm-voters = <&apps_bcm_voter>;
3540                 };
3541
3542                 usb_1: usb@a6f8800 {
3543                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3544                         reg = <0 0x0a6f8800 0 0x400>;
3545                         status = "disabled";
3546                         #address-cells = <2>;
3547                         #size-cells = <2>;
3548                         ranges;
3549                         dma-ranges;
3550
3551                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3552                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3553                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3554                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3555                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3556                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3557                         clock-names = "cfg_noc",
3558                                       "core",
3559                                       "iface",
3560                                       "sleep",
3561                                       "mock_utmi",
3562                                       "xo";
3563
3564                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3565                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3566                         assigned-clock-rates = <19200000>, <200000000>;
3567
3568                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3569                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3570                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3571                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3572                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3573                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3574
3575                         power-domains = <&gcc USB30_PRIM_GDSC>;
3576
3577                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3578
3579                         interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3580                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3581                         interconnect-names = "usb-ddr", "apps-usb";
3582
3583                         usb_1_dwc3: usb@a600000 {
3584                                 compatible = "snps,dwc3";
3585                                 reg = <0 0x0a600000 0 0xcd00>;
3586                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3587                                 iommus = <&apps_smmu 0x140 0>;
3588                                 snps,dis_u2_susphy_quirk;
3589                                 snps,dis_enblslpm_quirk;
3590                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3591                                 phy-names = "usb2-phy", "usb3-phy";
3592                         };
3593                 };
3594
3595                 usb_2: usb@a8f8800 {
3596                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3597                         reg = <0 0x0a8f8800 0 0x400>;
3598                         status = "disabled";
3599                         #address-cells = <2>;
3600                         #size-cells = <2>;
3601                         ranges;
3602                         dma-ranges;
3603
3604                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3605                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3606                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3607                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3608                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3609                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3610                         clock-names = "cfg_noc",
3611                                       "core",
3612                                       "iface",
3613                                       "sleep",
3614                                       "mock_utmi",
3615                                       "xo";
3616
3617                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3618                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3619                         assigned-clock-rates = <19200000>, <200000000>;
3620
3621                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3622                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3623                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3624                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3625                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3626                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3627
3628                         power-domains = <&gcc USB30_SEC_GDSC>;
3629
3630                         resets = <&gcc GCC_USB30_SEC_BCR>;
3631
3632                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3633                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3634                         interconnect-names = "usb-ddr", "apps-usb";
3635
3636                         usb_2_dwc3: usb@a800000 {
3637                                 compatible = "snps,dwc3";
3638                                 reg = <0 0x0a800000 0 0xcd00>;
3639                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3640                                 iommus = <&apps_smmu 0x160 0>;
3641                                 snps,dis_u2_susphy_quirk;
3642                                 snps,dis_enblslpm_quirk;
3643                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3644                                 phy-names = "usb2-phy", "usb3-phy";
3645                         };
3646                 };
3647
3648                 camnoc_virt: interconnect@ac00000 {
3649                         compatible = "qcom,sm8150-camnoc-virt";
3650                         reg = <0 0x0ac00000 0 0x1000>;
3651                         #interconnect-cells = <2>;
3652                         qcom,bcm-voters = <&apps_bcm_voter>;
3653                 };
3654
3655                 mdss: display-subsystem@ae00000 {
3656                         compatible = "qcom,sm8150-mdss";
3657                         reg = <0 0x0ae00000 0 0x1000>;
3658                         reg-names = "mdss";
3659
3660                         interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3661                                         <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3662                         interconnect-names = "mdp0-mem", "mdp1-mem";
3663
3664                         power-domains = <&dispcc MDSS_GDSC>;
3665
3666                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3667                                  <&gcc GCC_DISP_HF_AXI_CLK>,
3668                                  <&gcc GCC_DISP_SF_AXI_CLK>,
3669                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3670                         clock-names = "iface", "bus", "nrt_bus", "core";
3671
3672                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3673                         interrupt-controller;
3674                         #interrupt-cells = <1>;
3675
3676                         iommus = <&apps_smmu 0x800 0x420>;
3677
3678                         status = "disabled";
3679
3680                         #address-cells = <2>;
3681                         #size-cells = <2>;
3682                         ranges;
3683
3684                         mdss_mdp: display-controller@ae01000 {
3685                                 compatible = "qcom,sm8150-dpu";
3686                                 reg = <0 0x0ae01000 0 0x8f000>,
3687                                       <0 0x0aeb0000 0 0x2008>;
3688                                 reg-names = "mdp", "vbif";
3689
3690                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3691                                          <&gcc GCC_DISP_HF_AXI_CLK>,
3692                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3693                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3694                                 clock-names = "iface", "bus", "core", "vsync";
3695
3696                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3697                                 assigned-clock-rates = <19200000>;
3698
3699                                 operating-points-v2 = <&mdp_opp_table>;
3700                                 power-domains = <&rpmhpd SM8150_MMCX>;
3701
3702                                 interrupt-parent = <&mdss>;
3703                                 interrupts = <0>;
3704
3705                                 ports {
3706                                         #address-cells = <1>;
3707                                         #size-cells = <0>;
3708
3709                                         port@0 {
3710                                                 reg = <0>;
3711                                                 dpu_intf1_out: endpoint {
3712                                                         remote-endpoint = <&mdss_dsi0_in>;
3713                                                 };
3714                                         };
3715
3716                                         port@1 {
3717                                                 reg = <1>;
3718                                                 dpu_intf2_out: endpoint {
3719                                                         remote-endpoint = <&mdss_dsi1_in>;
3720                                                 };
3721                                         };
3722                                 };
3723
3724                                 mdp_opp_table: opp-table {
3725                                         compatible = "operating-points-v2";
3726
3727                                         opp-171428571 {
3728                                                 opp-hz = /bits/ 64 <171428571>;
3729                                                 required-opps = <&rpmhpd_opp_low_svs>;
3730                                         };
3731
3732                                         opp-300000000 {
3733                                                 opp-hz = /bits/ 64 <300000000>;
3734                                                 required-opps = <&rpmhpd_opp_svs>;
3735                                         };
3736
3737                                         opp-345000000 {
3738                                                 opp-hz = /bits/ 64 <345000000>;
3739                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3740                                         };
3741
3742                                         opp-460000000 {
3743                                                 opp-hz = /bits/ 64 <460000000>;
3744                                                 required-opps = <&rpmhpd_opp_nom>;
3745                                         };
3746                                 };
3747                         };
3748
3749                         mdss_dsi0: dsi@ae94000 {
3750                                 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3751                                 reg = <0 0x0ae94000 0 0x400>;
3752                                 reg-names = "dsi_ctrl";
3753
3754                                 interrupt-parent = <&mdss>;
3755                                 interrupts = <4>;
3756
3757                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3758                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3759                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3760                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3761                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3762                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3763                                 clock-names = "byte",
3764                                               "byte_intf",
3765                                               "pixel",
3766                                               "core",
3767                                               "iface",
3768                                               "bus";
3769
3770                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3771                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3772                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3773                                                          <&mdss_dsi0_phy 1>;
3774
3775                                 operating-points-v2 = <&dsi_opp_table>;
3776                                 power-domains = <&rpmhpd SM8150_MMCX>;
3777
3778                                 phys = <&mdss_dsi0_phy>;
3779
3780                                 status = "disabled";
3781
3782                                 #address-cells = <1>;
3783                                 #size-cells = <0>;
3784
3785                                 ports {
3786                                         #address-cells = <1>;
3787                                         #size-cells = <0>;
3788
3789                                         port@0 {
3790                                                 reg = <0>;
3791                                                 mdss_dsi0_in: endpoint {
3792                                                         remote-endpoint = <&dpu_intf1_out>;
3793                                                 };
3794                                         };
3795
3796                                         port@1 {
3797                                                 reg = <1>;
3798                                                 mdss_dsi0_out: endpoint {
3799                                                 };
3800                                         };
3801                                 };
3802
3803                                 dsi_opp_table: opp-table {
3804                                         compatible = "operating-points-v2";
3805
3806                                         opp-187500000 {
3807                                                 opp-hz = /bits/ 64 <187500000>;
3808                                                 required-opps = <&rpmhpd_opp_low_svs>;
3809                                         };
3810
3811                                         opp-300000000 {
3812                                                 opp-hz = /bits/ 64 <300000000>;
3813                                                 required-opps = <&rpmhpd_opp_svs>;
3814                                         };
3815
3816                                         opp-358000000 {
3817                                                 opp-hz = /bits/ 64 <358000000>;
3818                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3819                                         };
3820                                 };
3821                         };
3822
3823                         mdss_dsi0_phy: phy@ae94400 {
3824                                 compatible = "qcom,dsi-phy-7nm-8150";
3825                                 reg = <0 0x0ae94400 0 0x200>,
3826                                       <0 0x0ae94600 0 0x280>,
3827                                       <0 0x0ae94900 0 0x260>;
3828                                 reg-names = "dsi_phy",
3829                                             "dsi_phy_lane",
3830                                             "dsi_pll";
3831
3832                                 #clock-cells = <1>;
3833                                 #phy-cells = <0>;
3834
3835                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3836                                          <&rpmhcc RPMH_CXO_CLK>;
3837                                 clock-names = "iface", "ref";
3838
3839                                 status = "disabled";
3840                         };
3841
3842                         mdss_dsi1: dsi@ae96000 {
3843                                 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3844                                 reg = <0 0x0ae96000 0 0x400>;
3845                                 reg-names = "dsi_ctrl";
3846
3847                                 interrupt-parent = <&mdss>;
3848                                 interrupts = <5>;
3849
3850                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3851                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3852                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3853                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3854                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3855                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3856                                 clock-names = "byte",
3857                                               "byte_intf",
3858                                               "pixel",
3859                                               "core",
3860                                               "iface",
3861                                               "bus";
3862
3863                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3864                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3865                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3866                                                          <&mdss_dsi1_phy 1>;
3867
3868                                 operating-points-v2 = <&dsi_opp_table>;
3869                                 power-domains = <&rpmhpd SM8150_MMCX>;
3870
3871                                 phys = <&mdss_dsi1_phy>;
3872
3873                                 status = "disabled";
3874
3875                                 #address-cells = <1>;
3876                                 #size-cells = <0>;
3877
3878                                 ports {
3879                                         #address-cells = <1>;
3880                                         #size-cells = <0>;
3881
3882                                         port@0 {
3883                                                 reg = <0>;
3884                                                 mdss_dsi1_in: endpoint {
3885                                                         remote-endpoint = <&dpu_intf2_out>;
3886                                                 };
3887                                         };
3888
3889                                         port@1 {
3890                                                 reg = <1>;
3891                                                 mdss_dsi1_out: endpoint {
3892                                                 };
3893                                         };
3894                                 };
3895                         };
3896
3897                         mdss_dsi1_phy: phy@ae96400 {
3898                                 compatible = "qcom,dsi-phy-7nm-8150";
3899                                 reg = <0 0x0ae96400 0 0x200>,
3900                                       <0 0x0ae96600 0 0x280>,
3901                                       <0 0x0ae96900 0 0x260>;
3902                                 reg-names = "dsi_phy",
3903                                             "dsi_phy_lane",
3904                                             "dsi_pll";
3905
3906                                 #clock-cells = <1>;
3907                                 #phy-cells = <0>;
3908
3909                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3910                                          <&rpmhcc RPMH_CXO_CLK>;
3911                                 clock-names = "iface", "ref";
3912
3913                                 status = "disabled";
3914                         };
3915                 };
3916
3917                 dispcc: clock-controller@af00000 {
3918                         compatible = "qcom,sm8150-dispcc";
3919                         reg = <0 0x0af00000 0 0x10000>;
3920                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3921                                  <&mdss_dsi0_phy 0>,
3922                                  <&mdss_dsi0_phy 1>,
3923                                  <&mdss_dsi1_phy 0>,
3924                                  <&mdss_dsi1_phy 1>,
3925                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3926                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3927                         clock-names = "bi_tcxo",
3928                                       "dsi0_phy_pll_out_byteclk",
3929                                       "dsi0_phy_pll_out_dsiclk",
3930                                       "dsi1_phy_pll_out_byteclk",
3931                                       "dsi1_phy_pll_out_dsiclk",
3932                                       "dp_phy_pll_link_clk",
3933                                       "dp_phy_pll_vco_div_clk";
3934                         power-domains = <&rpmhpd SM8150_MMCX>;
3935                         #clock-cells = <1>;
3936                         #reset-cells = <1>;
3937                         #power-domain-cells = <1>;
3938                 };
3939
3940                 pdc: interrupt-controller@b220000 {
3941                         compatible = "qcom,sm8150-pdc", "qcom,pdc";
3942                         reg = <0 0x0b220000 0 0x30000>;
3943                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3944                                           <125 63 1>;
3945                         #interrupt-cells = <2>;
3946                         interrupt-parent = <&intc>;
3947                         interrupt-controller;
3948                 };
3949
3950                 aoss_qmp: power-management@c300000 {
3951                         compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3952                         reg = <0x0 0x0c300000 0x0 0x400>;
3953                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3954                         mboxes = <&apss_shared 0>;
3955
3956                         #clock-cells = <0>;
3957                 };
3958
3959                 sram@c3f0000 {
3960                         compatible = "qcom,rpmh-stats";
3961                         reg = <0 0x0c3f0000 0 0x400>;
3962                 };
3963
3964                 tsens0: thermal-sensor@c263000 {
3965                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3966                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3967                               <0 0x0c222000 0 0x1ff>; /* SROT */
3968                         #qcom,sensors = <16>;
3969                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3970                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3971                         interrupt-names = "uplow", "critical";
3972                         #thermal-sensor-cells = <1>;
3973                 };
3974
3975                 tsens1: thermal-sensor@c265000 {
3976                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3977                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3978                               <0 0x0c223000 0 0x1ff>; /* SROT */
3979                         #qcom,sensors = <8>;
3980                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3981                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3982                         interrupt-names = "uplow", "critical";
3983                         #thermal-sensor-cells = <1>;
3984                 };
3985
3986                 spmi_bus: spmi@c440000 {
3987                         compatible = "qcom,spmi-pmic-arb";
3988                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3989                               <0x0 0x0c600000 0x0 0x2000000>,
3990                               <0x0 0x0e600000 0x0 0x0100000>,
3991                               <0x0 0x0e700000 0x0 0x00a0000>,
3992                               <0x0 0x0c40a000 0x0 0x0026000>;
3993                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3994                         interrupt-names = "periph_irq";
3995                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3996                         qcom,ee = <0>;
3997                         qcom,channel = <0>;
3998                         #address-cells = <2>;
3999                         #size-cells = <0>;
4000                         interrupt-controller;
4001                         #interrupt-cells = <4>;
4002                 };
4003
4004                 apps_smmu: iommu@15000000 {
4005                         compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4006                         reg = <0 0x15000000 0 0x100000>;
4007                         #iommu-cells = <2>;
4008                         #global-interrupts = <1>;
4009                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4010                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4011                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4012                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4013                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4014                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4015                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4016                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4017                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4018                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4019                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4020                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4021                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4022                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4023                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4024                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4025                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4026                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4027                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4028                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4029                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4030                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4031                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4032                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4033                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4034                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4035                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4036                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4037                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4038                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4039                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4040                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4041                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4042                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4043                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4044                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4045                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4046                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4047                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4048                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4049                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4050                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4051                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4052                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4053                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4054                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4055                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4056                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4057                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4058                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4059                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4060                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4061                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4062                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4063                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4064                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4065                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4066                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4067                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4068                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4069                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4070                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4071                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4072                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4073                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4074                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4075                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4076                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4077                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4078                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4079                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4080                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4081                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4082                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4083                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4084                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4085                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4086                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4087                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4088                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4089                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4090                 };
4091
4092                 remoteproc_adsp: remoteproc@17300000 {
4093                         compatible = "qcom,sm8150-adsp-pas";
4094                         reg = <0x0 0x17300000 0x0 0x4040>;
4095
4096                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4097                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4098                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4099                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4100                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4101                         interrupt-names = "wdog", "fatal", "ready",
4102                                           "handover", "stop-ack";
4103
4104                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4105                         clock-names = "xo";
4106
4107                         power-domains = <&rpmhpd SM8150_CX>;
4108
4109                         memory-region = <&adsp_mem>;
4110
4111                         qcom,qmp = <&aoss_qmp>;
4112
4113                         qcom,smem-states = <&adsp_smp2p_out 0>;
4114                         qcom,smem-state-names = "stop";
4115
4116                         status = "disabled";
4117
4118                         glink-edge {
4119                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4120                                 label = "lpass";
4121                                 qcom,remote-pid = <2>;
4122                                 mboxes = <&apss_shared 8>;
4123
4124                                 fastrpc {
4125                                         compatible = "qcom,fastrpc";
4126                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4127                                         label = "adsp";
4128                                         qcom,non-secure-domain;
4129                                         #address-cells = <1>;
4130                                         #size-cells = <0>;
4131
4132                                         compute-cb@3 {
4133                                                 compatible = "qcom,fastrpc-compute-cb";
4134                                                 reg = <3>;
4135                                                 iommus = <&apps_smmu 0x1b23 0x0>;
4136                                         };
4137
4138                                         compute-cb@4 {
4139                                                 compatible = "qcom,fastrpc-compute-cb";
4140                                                 reg = <4>;
4141                                                 iommus = <&apps_smmu 0x1b24 0x0>;
4142                                         };
4143
4144                                         compute-cb@5 {
4145                                                 compatible = "qcom,fastrpc-compute-cb";
4146                                                 reg = <5>;
4147                                                 iommus = <&apps_smmu 0x1b25 0x0>;
4148                                         };
4149                                 };
4150                         };
4151                 };
4152
4153                 intc: interrupt-controller@17a00000 {
4154                         compatible = "arm,gic-v3";
4155                         interrupt-controller;
4156                         #interrupt-cells = <3>;
4157                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4158                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4159                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4160                 };
4161
4162                 apss_shared: mailbox@17c00000 {
4163                         compatible = "qcom,sm8150-apss-shared",
4164                                      "qcom,sdm845-apss-shared";
4165                         reg = <0x0 0x17c00000 0x0 0x1000>;
4166                         #mbox-cells = <1>;
4167                 };
4168
4169                 watchdog@17c10000 {
4170                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4171                         reg = <0 0x17c10000 0 0x1000>;
4172                         clocks = <&sleep_clk>;
4173                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4174                 };
4175
4176                 timer@17c20000 {
4177                         #address-cells = <1>;
4178                         #size-cells = <1>;
4179                         ranges = <0 0 0 0x20000000>;
4180                         compatible = "arm,armv7-timer-mem";
4181                         reg = <0x0 0x17c20000 0x0 0x1000>;
4182                         clock-frequency = <19200000>;
4183
4184                         frame@17c21000 {
4185                                 frame-number = <0>;
4186                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4187                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4188                                 reg = <0x17c21000 0x1000>,
4189                                       <0x17c22000 0x1000>;
4190                         };
4191
4192                         frame@17c23000 {
4193                                 frame-number = <1>;
4194                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4195                                 reg = <0x17c23000 0x1000>;
4196                                 status = "disabled";
4197                         };
4198
4199                         frame@17c25000 {
4200                                 frame-number = <2>;
4201                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4202                                 reg = <0x17c25000 0x1000>;
4203                                 status = "disabled";
4204                         };
4205
4206                         frame@17c27000 {
4207                                 frame-number = <3>;
4208                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4209                                 reg = <0x17c26000 0x1000>;
4210                                 status = "disabled";
4211                         };
4212
4213                         frame@17c29000 {
4214                                 frame-number = <4>;
4215                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4216                                 reg = <0x17c29000 0x1000>;
4217                                 status = "disabled";
4218                         };
4219
4220                         frame@17c2b000 {
4221                                 frame-number = <5>;
4222                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4223                                 reg = <0x17c2b000 0x1000>;
4224                                 status = "disabled";
4225                         };
4226
4227                         frame@17c2d000 {
4228                                 frame-number = <6>;
4229                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4230                                 reg = <0x17c2d000 0x1000>;
4231                                 status = "disabled";
4232                         };
4233                 };
4234
4235                 apps_rsc: rsc@18200000 {
4236                         label = "apps_rsc";
4237                         compatible = "qcom,rpmh-rsc";
4238                         reg = <0x0 0x18200000 0x0 0x10000>,
4239                               <0x0 0x18210000 0x0 0x10000>,
4240                               <0x0 0x18220000 0x0 0x10000>;
4241                         reg-names = "drv-0", "drv-1", "drv-2";
4242                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4243                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4244                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4245                         qcom,tcs-offset = <0xd00>;
4246                         qcom,drv-id = <2>;
4247                         qcom,tcs-config = <ACTIVE_TCS  2>,
4248                                           <SLEEP_TCS   3>,
4249                                           <WAKE_TCS    3>,
4250                                           <CONTROL_TCS 1>;
4251                         power-domains = <&CLUSTER_PD>;
4252
4253                         rpmhcc: clock-controller {
4254                                 compatible = "qcom,sm8150-rpmh-clk";
4255                                 #clock-cells = <1>;
4256                                 clock-names = "xo";
4257                                 clocks = <&xo_board>;
4258                         };
4259
4260                         rpmhpd: power-controller {
4261                                 compatible = "qcom,sm8150-rpmhpd";
4262                                 #power-domain-cells = <1>;
4263                                 operating-points-v2 = <&rpmhpd_opp_table>;
4264
4265                                 rpmhpd_opp_table: opp-table {
4266                                         compatible = "operating-points-v2";
4267
4268                                         rpmhpd_opp_ret: opp1 {
4269                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4270                                         };
4271
4272                                         rpmhpd_opp_min_svs: opp2 {
4273                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4274                                         };
4275
4276                                         rpmhpd_opp_low_svs: opp3 {
4277                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4278                                         };
4279
4280                                         rpmhpd_opp_svs: opp4 {
4281                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4282                                         };
4283
4284                                         rpmhpd_opp_svs_l1: opp5 {
4285                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4286                                         };
4287
4288                                         rpmhpd_opp_svs_l2: opp6 {
4289                                                 opp-level = <224>;
4290                                         };
4291
4292                                         rpmhpd_opp_nom: opp7 {
4293                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4294                                         };
4295
4296                                         rpmhpd_opp_nom_l1: opp8 {
4297                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4298                                         };
4299
4300                                         rpmhpd_opp_nom_l2: opp9 {
4301                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4302                                         };
4303
4304                                         rpmhpd_opp_turbo: opp10 {
4305                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4306                                         };
4307
4308                                         rpmhpd_opp_turbo_l1: opp11 {
4309                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4310                                         };
4311                                 };
4312                         };
4313
4314                         apps_bcm_voter: bcm-voter {
4315                                 compatible = "qcom,bcm-voter";
4316                         };
4317                 };
4318
4319                 osm_l3: interconnect@18321000 {
4320                         compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4321                         reg = <0 0x18321000 0 0x1400>;
4322
4323                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4324                         clock-names = "xo", "alternate";
4325
4326                         #interconnect-cells = <1>;
4327                 };
4328
4329                 cpufreq_hw: cpufreq@18323000 {
4330                         compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4331                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4332                               <0 0x18327800 0 0x1400>;
4333                         reg-names = "freq-domain0", "freq-domain1",
4334                                     "freq-domain2";
4335
4336                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4337                         clock-names = "xo", "alternate";
4338
4339                         #freq-domain-cells = <1>;
4340                         #clock-cells = <1>;
4341                 };
4342
4343                 lmh_cluster1: lmh@18350800 {
4344                         compatible = "qcom,sm8150-lmh";
4345                         reg = <0 0x18350800 0 0x400>;
4346                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4347                         cpus = <&CPU4>;
4348                         qcom,lmh-temp-arm-millicelsius = <60000>;
4349                         qcom,lmh-temp-low-millicelsius = <84500>;
4350                         qcom,lmh-temp-high-millicelsius = <85000>;
4351                         interrupt-controller;
4352                         #interrupt-cells = <1>;
4353                 };
4354
4355                 lmh_cluster0: lmh@18358800 {
4356                         compatible = "qcom,sm8150-lmh";
4357                         reg = <0 0x18358800 0 0x400>;
4358                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4359                         cpus = <&CPU0>;
4360                         qcom,lmh-temp-arm-millicelsius = <60000>;
4361                         qcom,lmh-temp-low-millicelsius = <84500>;
4362                         qcom,lmh-temp-high-millicelsius = <85000>;
4363                         interrupt-controller;
4364                         #interrupt-cells = <1>;
4365                 };
4366
4367                 wifi: wifi@18800000 {
4368                         compatible = "qcom,wcn3990-wifi";
4369                         reg = <0 0x18800000 0 0x800000>;
4370                         reg-names = "membase";
4371                         memory-region = <&wlan_mem>;
4372                         clock-names = "cxo_ref_clk_pin", "qdss";
4373                         clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4374                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4375                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4376                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4377                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4378                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4379                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4380                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4381                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4382                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4383                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4384                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4385                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4386                         iommus = <&apps_smmu 0x0640 0x1>;
4387                         status = "disabled";
4388                 };
4389         };
4390
4391         timer {
4392                 compatible = "arm,armv8-timer";
4393                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4394                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4395                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4396                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4397         };
4398
4399         thermal-zones {
4400                 cpu0-thermal {
4401                         polling-delay-passive = <250>;
4402                         polling-delay = <1000>;
4403
4404                         thermal-sensors = <&tsens0 1>;
4405
4406                         trips {
4407                                 cpu0_alert0: trip-point0 {
4408                                         temperature = <90000>;
4409                                         hysteresis = <2000>;
4410                                         type = "passive";
4411                                 };
4412
4413                                 cpu0_alert1: trip-point1 {
4414                                         temperature = <95000>;
4415                                         hysteresis = <2000>;
4416                                         type = "passive";
4417                                 };
4418
4419                                 cpu0_crit: cpu-crit {
4420                                         temperature = <110000>;
4421                                         hysteresis = <1000>;
4422                                         type = "critical";
4423                                 };
4424                         };
4425
4426                         cooling-maps {
4427                                 map0 {
4428                                         trip = <&cpu0_alert0>;
4429                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4430                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4431                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4432                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4433                                 };
4434                                 map1 {
4435                                         trip = <&cpu0_alert1>;
4436                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4437                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4438                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4439                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4440                                 };
4441                         };
4442                 };
4443
4444                 cpu1-thermal {
4445                         polling-delay-passive = <250>;
4446                         polling-delay = <1000>;
4447
4448                         thermal-sensors = <&tsens0 2>;
4449
4450                         trips {
4451                                 cpu1_alert0: trip-point0 {
4452                                         temperature = <90000>;
4453                                         hysteresis = <2000>;
4454                                         type = "passive";
4455                                 };
4456
4457                                 cpu1_alert1: trip-point1 {
4458                                         temperature = <95000>;
4459                                         hysteresis = <2000>;
4460                                         type = "passive";
4461                                 };
4462
4463                                 cpu1_crit: cpu-crit {
4464                                         temperature = <110000>;
4465                                         hysteresis = <1000>;
4466                                         type = "critical";
4467                                 };
4468                         };
4469
4470                         cooling-maps {
4471                                 map0 {
4472                                         trip = <&cpu1_alert0>;
4473                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4474                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4475                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4476                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4477                                 };
4478                                 map1 {
4479                                         trip = <&cpu1_alert1>;
4480                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4481                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4482                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4483                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4484                                 };
4485                         };
4486                 };
4487
4488                 cpu2-thermal {
4489                         polling-delay-passive = <250>;
4490                         polling-delay = <1000>;
4491
4492                         thermal-sensors = <&tsens0 3>;
4493
4494                         trips {
4495                                 cpu2_alert0: trip-point0 {
4496                                         temperature = <90000>;
4497                                         hysteresis = <2000>;
4498                                         type = "passive";
4499                                 };
4500
4501                                 cpu2_alert1: trip-point1 {
4502                                         temperature = <95000>;
4503                                         hysteresis = <2000>;
4504                                         type = "passive";
4505                                 };
4506
4507                                 cpu2_crit: cpu-crit {
4508                                         temperature = <110000>;
4509                                         hysteresis = <1000>;
4510                                         type = "critical";
4511                                 };
4512                         };
4513
4514                         cooling-maps {
4515                                 map0 {
4516                                         trip = <&cpu2_alert0>;
4517                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4518                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4519                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4520                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4521                                 };
4522                                 map1 {
4523                                         trip = <&cpu2_alert1>;
4524                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4525                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4526                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4527                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4528                                 };
4529                         };
4530                 };
4531
4532                 cpu3-thermal {
4533                         polling-delay-passive = <250>;
4534                         polling-delay = <1000>;
4535
4536                         thermal-sensors = <&tsens0 4>;
4537
4538                         trips {
4539                                 cpu3_alert0: trip-point0 {
4540                                         temperature = <90000>;
4541                                         hysteresis = <2000>;
4542                                         type = "passive";
4543                                 };
4544
4545                                 cpu3_alert1: trip-point1 {
4546                                         temperature = <95000>;
4547                                         hysteresis = <2000>;
4548                                         type = "passive";
4549                                 };
4550
4551                                 cpu3_crit: cpu-crit {
4552                                         temperature = <110000>;
4553                                         hysteresis = <1000>;
4554                                         type = "critical";
4555                                 };
4556                         };
4557
4558                         cooling-maps {
4559                                 map0 {
4560                                         trip = <&cpu3_alert0>;
4561                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4562                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4563                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4564                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4565                                 };
4566                                 map1 {
4567                                         trip = <&cpu3_alert1>;
4568                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4569                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4570                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4571                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4572                                 };
4573                         };
4574                 };
4575
4576                 cpu4-top-thermal {
4577                         polling-delay-passive = <250>;
4578                         polling-delay = <1000>;
4579
4580                         thermal-sensors = <&tsens0 7>;
4581
4582                         trips {
4583                                 cpu4_top_alert0: trip-point0 {
4584                                         temperature = <90000>;
4585                                         hysteresis = <2000>;
4586                                         type = "passive";
4587                                 };
4588
4589                                 cpu4_top_alert1: trip-point1 {
4590                                         temperature = <95000>;
4591                                         hysteresis = <2000>;
4592                                         type = "passive";
4593                                 };
4594
4595                                 cpu4_top_crit: cpu-crit {
4596                                         temperature = <110000>;
4597                                         hysteresis = <1000>;
4598                                         type = "critical";
4599                                 };
4600                         };
4601
4602                         cooling-maps {
4603                                 map0 {
4604                                         trip = <&cpu4_top_alert0>;
4605                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4606                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4607                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4608                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4609                                 };
4610                                 map1 {
4611                                         trip = <&cpu4_top_alert1>;
4612                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4613                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4614                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4615                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4616                                 };
4617                         };
4618                 };
4619
4620                 cpu5-top-thermal {
4621                         polling-delay-passive = <250>;
4622                         polling-delay = <1000>;
4623
4624                         thermal-sensors = <&tsens0 8>;
4625
4626                         trips {
4627                                 cpu5_top_alert0: trip-point0 {
4628                                         temperature = <90000>;
4629                                         hysteresis = <2000>;
4630                                         type = "passive";
4631                                 };
4632
4633                                 cpu5_top_alert1: trip-point1 {
4634                                         temperature = <95000>;
4635                                         hysteresis = <2000>;
4636                                         type = "passive";
4637                                 };
4638
4639                                 cpu5_top_crit: cpu-crit {
4640                                         temperature = <110000>;
4641                                         hysteresis = <1000>;
4642                                         type = "critical";
4643                                 };
4644                         };
4645
4646                         cooling-maps {
4647                                 map0 {
4648                                         trip = <&cpu5_top_alert0>;
4649                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4650                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4651                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4652                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4653                                 };
4654                                 map1 {
4655                                         trip = <&cpu5_top_alert1>;
4656                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4657                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4658                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4659                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4660                                 };
4661                         };
4662                 };
4663
4664                 cpu6-top-thermal {
4665                         polling-delay-passive = <250>;
4666                         polling-delay = <1000>;
4667
4668                         thermal-sensors = <&tsens0 9>;
4669
4670                         trips {
4671                                 cpu6_top_alert0: trip-point0 {
4672                                         temperature = <90000>;
4673                                         hysteresis = <2000>;
4674                                         type = "passive";
4675                                 };
4676
4677                                 cpu6_top_alert1: trip-point1 {
4678                                         temperature = <95000>;
4679                                         hysteresis = <2000>;
4680                                         type = "passive";
4681                                 };
4682
4683                                 cpu6_top_crit: cpu-crit {
4684                                         temperature = <110000>;
4685                                         hysteresis = <1000>;
4686                                         type = "critical";
4687                                 };
4688                         };
4689
4690                         cooling-maps {
4691                                 map0 {
4692                                         trip = <&cpu6_top_alert0>;
4693                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4694                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4695                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4696                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4697                                 };
4698                                 map1 {
4699                                         trip = <&cpu6_top_alert1>;
4700                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4701                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4702                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4703                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4704                                 };
4705                         };
4706                 };
4707
4708                 cpu7-top-thermal {
4709                         polling-delay-passive = <250>;
4710                         polling-delay = <1000>;
4711
4712                         thermal-sensors = <&tsens0 10>;
4713
4714                         trips {
4715                                 cpu7_top_alert0: trip-point0 {
4716                                         temperature = <90000>;
4717                                         hysteresis = <2000>;
4718                                         type = "passive";
4719                                 };
4720
4721                                 cpu7_top_alert1: trip-point1 {
4722                                         temperature = <95000>;
4723                                         hysteresis = <2000>;
4724                                         type = "passive";
4725                                 };
4726
4727                                 cpu7_top_crit: cpu-crit {
4728                                         temperature = <110000>;
4729                                         hysteresis = <1000>;
4730                                         type = "critical";
4731                                 };
4732                         };
4733
4734                         cooling-maps {
4735                                 map0 {
4736                                         trip = <&cpu7_top_alert0>;
4737                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4738                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4739                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4740                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4741                                 };
4742                                 map1 {
4743                                         trip = <&cpu7_top_alert1>;
4744                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4745                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4746                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4747                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4748                                 };
4749                         };
4750                 };
4751
4752                 cpu4-bottom-thermal {
4753                         polling-delay-passive = <250>;
4754                         polling-delay = <1000>;
4755
4756                         thermal-sensors = <&tsens0 11>;
4757
4758                         trips {
4759                                 cpu4_bottom_alert0: trip-point0 {
4760                                         temperature = <90000>;
4761                                         hysteresis = <2000>;
4762                                         type = "passive";
4763                                 };
4764
4765                                 cpu4_bottom_alert1: trip-point1 {
4766                                         temperature = <95000>;
4767                                         hysteresis = <2000>;
4768                                         type = "passive";
4769                                 };
4770
4771                                 cpu4_bottom_crit: cpu-crit {
4772                                         temperature = <110000>;
4773                                         hysteresis = <1000>;
4774                                         type = "critical";
4775                                 };
4776                         };
4777
4778                         cooling-maps {
4779                                 map0 {
4780                                         trip = <&cpu4_bottom_alert0>;
4781                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4782                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4783                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4784                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4785                                 };
4786                                 map1 {
4787                                         trip = <&cpu4_bottom_alert1>;
4788                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4789                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4790                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4791                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4792                                 };
4793                         };
4794                 };
4795
4796                 cpu5-bottom-thermal {
4797                         polling-delay-passive = <250>;
4798                         polling-delay = <1000>;
4799
4800                         thermal-sensors = <&tsens0 12>;
4801
4802                         trips {
4803                                 cpu5_bottom_alert0: trip-point0 {
4804                                         temperature = <90000>;
4805                                         hysteresis = <2000>;
4806                                         type = "passive";
4807                                 };
4808
4809                                 cpu5_bottom_alert1: trip-point1 {
4810                                         temperature = <95000>;
4811                                         hysteresis = <2000>;
4812                                         type = "passive";
4813                                 };
4814
4815                                 cpu5_bottom_crit: cpu-crit {
4816                                         temperature = <110000>;
4817                                         hysteresis = <1000>;
4818                                         type = "critical";
4819                                 };
4820                         };
4821
4822                         cooling-maps {
4823                                 map0 {
4824                                         trip = <&cpu5_bottom_alert0>;
4825                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4826                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4827                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4828                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4829                                 };
4830                                 map1 {
4831                                         trip = <&cpu5_bottom_alert1>;
4832                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4833                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4834                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4835                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4836                                 };
4837                         };
4838                 };
4839
4840                 cpu6-bottom-thermal {
4841                         polling-delay-passive = <250>;
4842                         polling-delay = <1000>;
4843
4844                         thermal-sensors = <&tsens0 13>;
4845
4846                         trips {
4847                                 cpu6_bottom_alert0: trip-point0 {
4848                                         temperature = <90000>;
4849                                         hysteresis = <2000>;
4850                                         type = "passive";
4851                                 };
4852
4853                                 cpu6_bottom_alert1: trip-point1 {
4854                                         temperature = <95000>;
4855                                         hysteresis = <2000>;
4856                                         type = "passive";
4857                                 };
4858
4859                                 cpu6_bottom_crit: cpu-crit {
4860                                         temperature = <110000>;
4861                                         hysteresis = <1000>;
4862                                         type = "critical";
4863                                 };
4864                         };
4865
4866                         cooling-maps {
4867                                 map0 {
4868                                         trip = <&cpu6_bottom_alert0>;
4869                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4870                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4871                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4872                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4873                                 };
4874                                 map1 {
4875                                         trip = <&cpu6_bottom_alert1>;
4876                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4877                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4878                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4879                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4880                                 };
4881                         };
4882                 };
4883
4884                 cpu7-bottom-thermal {
4885                         polling-delay-passive = <250>;
4886                         polling-delay = <1000>;
4887
4888                         thermal-sensors = <&tsens0 14>;
4889
4890                         trips {
4891                                 cpu7_bottom_alert0: trip-point0 {
4892                                         temperature = <90000>;
4893                                         hysteresis = <2000>;
4894                                         type = "passive";
4895                                 };
4896
4897                                 cpu7_bottom_alert1: trip-point1 {
4898                                         temperature = <95000>;
4899                                         hysteresis = <2000>;
4900                                         type = "passive";
4901                                 };
4902
4903                                 cpu7_bottom_crit: cpu-crit {
4904                                         temperature = <110000>;
4905                                         hysteresis = <1000>;
4906                                         type = "critical";
4907                                 };
4908                         };
4909
4910                         cooling-maps {
4911                                 map0 {
4912                                         trip = <&cpu7_bottom_alert0>;
4913                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4914                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4915                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4916                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4917                                 };
4918                                 map1 {
4919                                         trip = <&cpu7_bottom_alert1>;
4920                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4921                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4922                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4923                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4924                                 };
4925                         };
4926                 };
4927
4928                 aoss0-thermal {
4929                         polling-delay-passive = <250>;
4930                         polling-delay = <1000>;
4931
4932                         thermal-sensors = <&tsens0 0>;
4933
4934                         trips {
4935                                 aoss0_alert0: trip-point0 {
4936                                         temperature = <90000>;
4937                                         hysteresis = <2000>;
4938                                         type = "hot";
4939                                 };
4940                         };
4941                 };
4942
4943                 cluster0-thermal {
4944                         polling-delay-passive = <250>;
4945                         polling-delay = <1000>;
4946
4947                         thermal-sensors = <&tsens0 5>;
4948
4949                         trips {
4950                                 cluster0_alert0: trip-point0 {
4951                                         temperature = <90000>;
4952                                         hysteresis = <2000>;
4953                                         type = "hot";
4954                                 };
4955                                 cluster0_crit: cluster0_crit {
4956                                         temperature = <110000>;
4957                                         hysteresis = <2000>;
4958                                         type = "critical";
4959                                 };
4960                         };
4961                 };
4962
4963                 cluster1-thermal {
4964                         polling-delay-passive = <250>;
4965                         polling-delay = <1000>;
4966
4967                         thermal-sensors = <&tsens0 6>;
4968
4969                         trips {
4970                                 cluster1_alert0: trip-point0 {
4971                                         temperature = <90000>;
4972                                         hysteresis = <2000>;
4973                                         type = "hot";
4974                                 };
4975                                 cluster1_crit: cluster1_crit {
4976                                         temperature = <110000>;
4977                                         hysteresis = <2000>;
4978                                         type = "critical";
4979                                 };
4980                         };
4981                 };
4982
4983                 gpu-top-thermal {
4984                         polling-delay-passive = <250>;
4985                         polling-delay = <1000>;
4986
4987                         thermal-sensors = <&tsens0 15>;
4988
4989                         trips {
4990                                 gpu1_alert0: trip-point0 {
4991                                         temperature = <90000>;
4992                                         hysteresis = <2000>;
4993                                         type = "hot";
4994                                 };
4995                         };
4996                 };
4997
4998                 aoss1-thermal {
4999                         polling-delay-passive = <250>;
5000                         polling-delay = <1000>;
5001
5002                         thermal-sensors = <&tsens1 0>;
5003
5004                         trips {
5005                                 aoss1_alert0: trip-point0 {
5006                                         temperature = <90000>;
5007                                         hysteresis = <2000>;
5008                                         type = "hot";
5009                                 };
5010                         };
5011                 };
5012
5013                 wlan-thermal {
5014                         polling-delay-passive = <250>;
5015                         polling-delay = <1000>;
5016
5017                         thermal-sensors = <&tsens1 1>;
5018
5019                         trips {
5020                                 wlan_alert0: trip-point0 {
5021                                         temperature = <90000>;
5022                                         hysteresis = <2000>;
5023                                         type = "hot";
5024                                 };
5025                         };
5026                 };
5027
5028                 video-thermal {
5029                         polling-delay-passive = <250>;
5030                         polling-delay = <1000>;
5031
5032                         thermal-sensors = <&tsens1 2>;
5033
5034                         trips {
5035                                 video_alert0: trip-point0 {
5036                                         temperature = <90000>;
5037                                         hysteresis = <2000>;
5038                                         type = "hot";
5039                                 };
5040                         };
5041                 };
5042
5043                 mem-thermal {
5044                         polling-delay-passive = <250>;
5045                         polling-delay = <1000>;
5046
5047                         thermal-sensors = <&tsens1 3>;
5048
5049                         trips {
5050                                 mem_alert0: trip-point0 {
5051                                         temperature = <90000>;
5052                                         hysteresis = <2000>;
5053                                         type = "hot";
5054                                 };
5055                         };
5056                 };
5057
5058                 q6-hvx-thermal {
5059                         polling-delay-passive = <250>;
5060                         polling-delay = <1000>;
5061
5062                         thermal-sensors = <&tsens1 4>;
5063
5064                         trips {
5065                                 q6_hvx_alert0: trip-point0 {
5066                                         temperature = <90000>;
5067                                         hysteresis = <2000>;
5068                                         type = "hot";
5069                                 };
5070                         };
5071                 };
5072
5073                 camera-thermal {
5074                         polling-delay-passive = <250>;
5075                         polling-delay = <1000>;
5076
5077                         thermal-sensors = <&tsens1 5>;
5078
5079                         trips {
5080                                 camera_alert0: trip-point0 {
5081                                         temperature = <90000>;
5082                                         hysteresis = <2000>;
5083                                         type = "hot";
5084                                 };
5085                         };
5086                 };
5087
5088                 compute-thermal {
5089                         polling-delay-passive = <250>;
5090                         polling-delay = <1000>;
5091
5092                         thermal-sensors = <&tsens1 6>;
5093
5094                         trips {
5095                                 compute_alert0: trip-point0 {
5096                                         temperature = <90000>;
5097                                         hysteresis = <2000>;
5098                                         type = "hot";
5099                                 };
5100                         };
5101                 };
5102
5103                 modem-thermal {
5104                         polling-delay-passive = <250>;
5105                         polling-delay = <1000>;
5106
5107                         thermal-sensors = <&tsens1 7>;
5108
5109                         trips {
5110                                 modem_alert0: trip-point0 {
5111                                         temperature = <90000>;
5112                                         hysteresis = <2000>;
5113                                         type = "hot";
5114                                 };
5115                         };
5116                 };
5117
5118                 npu-thermal {
5119                         polling-delay-passive = <250>;
5120                         polling-delay = <1000>;
5121
5122                         thermal-sensors = <&tsens1 8>;
5123
5124                         trips {
5125                                 npu_alert0: trip-point0 {
5126                                         temperature = <90000>;
5127                                         hysteresis = <2000>;
5128                                         type = "hot";
5129                                 };
5130                         };
5131                 };
5132
5133                 modem-vec-thermal {
5134                         polling-delay-passive = <250>;
5135                         polling-delay = <1000>;
5136
5137                         thermal-sensors = <&tsens1 9>;
5138
5139                         trips {
5140                                 modem_vec_alert0: trip-point0 {
5141                                         temperature = <90000>;
5142                                         hysteresis = <2000>;
5143                                         type = "hot";
5144                                 };
5145                         };
5146                 };
5147
5148                 modem-scl-thermal {
5149                         polling-delay-passive = <250>;
5150                         polling-delay = <1000>;
5151
5152                         thermal-sensors = <&tsens1 10>;
5153
5154                         trips {
5155                                 modem_scl_alert0: trip-point0 {
5156                                         temperature = <90000>;
5157                                         hysteresis = <2000>;
5158                                         type = "hot";
5159                                 };
5160                         };
5161                 };
5162
5163                 gpu-bottom-thermal {
5164                         polling-delay-passive = <250>;
5165                         polling-delay = <1000>;
5166
5167                         thermal-sensors = <&tsens1 11>;
5168
5169                         trips {
5170                                 gpu2_alert0: trip-point0 {
5171                                         temperature = <90000>;
5172                                         hysteresis = <2000>;
5173                                         type = "hot";
5174                                 };
5175                         };
5176                 };
5177         };
5178 };