arch/arm64/boot/dts/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/dma/qcom-gpi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sm8150.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <38400000>;
  31                         clock-output-names = "xo_board";
  32                 };
  33
  34                 sleep_clk: sleep-clk {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <32764>;
  38                         clock-output-names = "sleep_clk";
  39                 };
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 CPU0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "qcom,kryo485";
  49                         reg = <0x0 0x0>;
  50                         enable-method = "psci";
  51                         capacity-dmips-mhz = <488>;
  52                         dynamic-power-coefficient = <232>;
  53                         next-level-cache = <&L2_0>;
  54                         qcom,freq-domain = <&cpufreq_hw 0>;
  55                         operating-points-v2 = <&cpu0_opp_table>;
  56                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
  57                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  58                         power-domains = <&CPU_PD0>;
  59                         power-domain-names = "psci";
  60                         #cooling-cells = <2>;
  61                         L2_0: l2-cache {
  62                                 compatible = "cache";
  63                                 next-level-cache = <&L3_0>;
  64                                 L3_0: l3-cache {
  65                                       compatible = "cache";
  66                                 };
  67                         };
  68                 };
  69
  70                 CPU1: cpu@100 {
  71                         device_type = "cpu";
  72                         compatible = "qcom,kryo485";
  73                         reg = <0x0 0x100>;
  74                         enable-method = "psci";
  75                         capacity-dmips-mhz = <488>;
  76                         dynamic-power-coefficient = <232>;
  77                         next-level-cache = <&L2_100>;
  78                         qcom,freq-domain = <&cpufreq_hw 0>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
  81                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  82                         power-domains = <&CPU_PD1>;
  83                         power-domain-names = "psci";
  84                         #cooling-cells = <2>;
  85                         L2_100: l2-cache {
  86                                 compatible = "cache";
  87                                 next-level-cache = <&L3_0>;
  88                         };
  89
  90                 };
  91
  92                 CPU2: cpu@200 {
  93                         device_type = "cpu";
  94                         compatible = "qcom,kryo485";
  95                         reg = <0x0 0x200>;
  96                         enable-method = "psci";
  97                         capacity-dmips-mhz = <488>;
  98                         dynamic-power-coefficient = <232>;
  99                         next-level-cache = <&L2_200>;
 100                         qcom,freq-domain = <&cpufreq_hw 0>;
 101                         operating-points-v2 = <&cpu0_opp_table>;
 102                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 103                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 104                         power-domains = <&CPU_PD2>;
 105                         power-domain-names = "psci";
 106                         #cooling-cells = <2>;
 107                         L2_200: l2-cache {
 108                                 compatible = "cache";
 109                                 next-level-cache = <&L3_0>;
 110                         };
 111                 };
 112
 113                 CPU3: cpu@300 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo485";
 116                         reg = <0x0 0x300>;
 117                         enable-method = "psci";
 118                         capacity-dmips-mhz = <488>;
 119                         dynamic-power-coefficient = <232>;
 120                         next-level-cache = <&L2_300>;
 121                         qcom,freq-domain = <&cpufreq_hw 0>;
 122                         operating-points-v2 = <&cpu0_opp_table>;
 123                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 124                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 125                         power-domains = <&CPU_PD3>;
 126                         power-domain-names = "psci";
 127                         #cooling-cells = <2>;
 128                         L2_300: l2-cache {
 129                                 compatible = "cache";
 130                                 next-level-cache = <&L3_0>;
 131                         };
 132                 };
 133
 134                 CPU4: cpu@400 {
 135                         device_type = "cpu";
 136                         compatible = "qcom,kryo485";
 137                         reg = <0x0 0x400>;
 138                         enable-method = "psci";
 139                         capacity-dmips-mhz = <1024>;
 140                         dynamic-power-coefficient = <369>;
 141                         next-level-cache = <&L2_400>;
 142                         qcom,freq-domain = <&cpufreq_hw 1>;
 143                         operating-points-v2 = <&cpu4_opp_table>;
 144                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 145                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 146                         power-domains = <&CPU_PD4>;
 147                         power-domain-names = "psci";
 148                         #cooling-cells = <2>;
 149                         L2_400: l2-cache {
 150                                 compatible = "cache";
 151                                 next-level-cache = <&L3_0>;
 152                         };
 153                 };
 154
 155                 CPU5: cpu@500 {
 156                         device_type = "cpu";
 157                         compatible = "qcom,kryo485";
 158                         reg = <0x0 0x500>;
 159                         enable-method = "psci";
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <369>;
 162                         next-level-cache = <&L2_500>;
 163                         qcom,freq-domain = <&cpufreq_hw 1>;
 164                         operating-points-v2 = <&cpu4_opp_table>;
 165                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 166                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 167                         power-domains = <&CPU_PD5>;
 168                         power-domain-names = "psci";
 169                         #cooling-cells = <2>;
 170                         L2_500: l2-cache {
 171                                 compatible = "cache";
 172                                 next-level-cache = <&L3_0>;
 173                         };
 174                 };
 175
 176                 CPU6: cpu@600 {
 177                         device_type = "cpu";
 178                         compatible = "qcom,kryo485";
 179                         reg = <0x0 0x600>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1024>;
 182                         dynamic-power-coefficient = <369>;
 183                         next-level-cache = <&L2_600>;
 184                         qcom,freq-domain = <&cpufreq_hw 1>;
 185                         operating-points-v2 = <&cpu4_opp_table>;
 186                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         power-domains = <&CPU_PD6>;
 189                         power-domain-names = "psci";
 190                         #cooling-cells = <2>;
 191                         L2_600: l2-cache {
 192                                 compatible = "cache";
 193                                 next-level-cache = <&L3_0>;
 194                         };
 195                 };
 196
 197                 CPU7: cpu@700 {
 198                         device_type = "cpu";
 199                         compatible = "qcom,kryo485";
 200                         reg = <0x0 0x700>;
 201                         enable-method = "psci";
 202                         capacity-dmips-mhz = <1024>;
 203                         dynamic-power-coefficient = <421>;
 204                         next-level-cache = <&L2_700>;
 205                         qcom,freq-domain = <&cpufreq_hw 2>;
 206                         operating-points-v2 = <&cpu7_opp_table>;
 207                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 208                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 209                         power-domains = <&CPU_PD7>;
 210                         power-domain-names = "psci";
 211                         #cooling-cells = <2>;
 212                         L2_700: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 cpu-map {
 219                         cluster0 {
 220                                 core0 {
 221                                         cpu = <&CPU0>;
 222                                 };
 223
 224                                 core1 {
 225                                         cpu = <&CPU1>;
 226                                 };
 227
 228                                 core2 {
 229                                         cpu = <&CPU2>;
 230                                 };
 231
 232                                 core3 {
 233                                         cpu = <&CPU3>;
 234                                 };
 235
 236                                 core4 {
 237                                         cpu = <&CPU4>;
 238                                 };
 239
 240                                 core5 {
 241                                         cpu = <&CPU5>;
 242                                 };
 243
 244                                 core6 {
 245                                         cpu = <&CPU6>;
 246                                 };
 247
 248                                 core7 {
 249                                         cpu = <&CPU7>;
 250                                 };
 251                         };
 252                 };
 253
 254                 idle-states {
 255                         entry-method = "psci";
 256
 257                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 258                                 compatible = "arm,idle-state";
 259                                 idle-state-name = "little-rail-power-collapse";
 260                                 arm,psci-suspend-param = <0x40000004>;
 261                                 entry-latency-us = <355>;
 262                                 exit-latency-us = <909>;
 263                                 min-residency-us = <3934>;
 264                                 local-timer-stop;
 265                         };
 266
 267                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 268                                 compatible = "arm,idle-state";
 269                                 idle-state-name = "big-rail-power-collapse";
 270                                 arm,psci-suspend-param = <0x40000004>;
 271                                 entry-latency-us = <241>;
 272                                 exit-latency-us = <1461>;
 273                                 min-residency-us = <4488>;
 274                                 local-timer-stop;
 275                         };
 276                 };
 277
 278                 domain-idle-states {
 279                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 280                                 compatible = "domain-idle-state";
 281                                 idle-state-name = "cluster-power-collapse";
 282                                 arm,psci-suspend-param = <0x4100c244>;
 283                                 entry-latency-us = <3263>;
 284                                 exit-latency-us = <6562>;
 285                                 min-residency-us = <9987>;
 286                                 local-timer-stop;
 287                         };
 288                 };
 289         };
 290
 291         cpu0_opp_table: opp-table-cpu0 {
 292                 compatible = "operating-points-v2";
 293                 opp-shared;
 294
 295                 cpu0_opp1: opp-300000000 {
 296                         opp-hz = /bits/ 64 <300000000>;
 297                         opp-peak-kBps = <800000 9600000>;
 298                 };
 299
 300                 cpu0_opp2: opp-403200000 {
 301                         opp-hz = /bits/ 64 <403200000>;
 302                         opp-peak-kBps = <800000 9600000>;
 303                 };
 304
 305                 cpu0_opp3: opp-499200000 {
 306                         opp-hz = /bits/ 64 <499200000>;
 307                         opp-peak-kBps = <800000 12902400>;
 308                 };
 309
 310                 cpu0_opp4: opp-576000000 {
 311                         opp-hz = /bits/ 64 <576000000>;
 312                         opp-peak-kBps = <800000 12902400>;
 313                 };
 314
 315                 cpu0_opp5: opp-672000000 {
 316                         opp-hz = /bits/ 64 <672000000>;
 317                         opp-peak-kBps = <800000 15974400>;
 318                 };
 319
 320                 cpu0_opp6: opp-768000000 {
 321                         opp-hz = /bits/ 64 <768000000>;
 322                         opp-peak-kBps = <1804000 19660800>;
 323                 };
 324
 325                 cpu0_opp7: opp-844800000 {
 326                         opp-hz = /bits/ 64 <844800000>;
 327                         opp-peak-kBps = <1804000 19660800>;
 328                 };
 329
 330                 cpu0_opp8: opp-940800000 {
 331                         opp-hz = /bits/ 64 <940800000>;
 332                         opp-peak-kBps = <1804000 22732800>;
 333                 };
 334
 335                 cpu0_opp9: opp-1036800000 {
 336                         opp-hz = /bits/ 64 <1036800000>;
 337                         opp-peak-kBps = <1804000 22732800>;
 338                 };
 339
 340                 cpu0_opp10: opp-1113600000 {
 341                         opp-hz = /bits/ 64 <1113600000>;
 342                         opp-peak-kBps = <2188000 25804800>;
 343                 };
 344
 345                 cpu0_opp11: opp-1209600000 {
 346                         opp-hz = /bits/ 64 <1209600000>;
 347                         opp-peak-kBps = <2188000 31948800>;
 348                 };
 349
 350                 cpu0_opp12: opp-1305600000 {
 351                         opp-hz = /bits/ 64 <1305600000>;
 352                         opp-peak-kBps = <3072000 31948800>;
 353                 };
 354
 355                 cpu0_opp13: opp-1382400000 {
 356                         opp-hz = /bits/ 64 <1382400000>;
 357                         opp-peak-kBps = <3072000 31948800>;
 358                 };
 359
 360                 cpu0_opp14: opp-1478400000 {
 361                         opp-hz = /bits/ 64 <1478400000>;
 362                         opp-peak-kBps = <3072000 31948800>;
 363                 };
 364
 365                 cpu0_opp15: opp-1555200000 {
 366                         opp-hz = /bits/ 64 <1555200000>;
 367                         opp-peak-kBps = <3072000 40550400>;
 368                 };
 369
 370                 cpu0_opp16: opp-1632000000 {
 371                         opp-hz = /bits/ 64 <1632000000>;
 372                         opp-peak-kBps = <3072000 40550400>;
 373                 };
 374
 375                 cpu0_opp17: opp-1708800000 {
 376                         opp-hz = /bits/ 64 <1708800000>;
 377                         opp-peak-kBps = <3072000 43008000>;
 378                 };
 379
 380                 cpu0_opp18: opp-1785600000 {
 381                         opp-hz = /bits/ 64 <1785600000>;
 382                         opp-peak-kBps = <3072000 43008000>;
 383                 };
 384         };
 385
 386         cpu4_opp_table: opp-table-cpu4 {
 387                 compatible = "operating-points-v2";
 388                 opp-shared;
 389
 390                 cpu4_opp1: opp-710400000 {
 391                         opp-hz = /bits/ 64 <710400000>;
 392                         opp-peak-kBps = <1804000 15974400>;
 393                 };
 394
 395                 cpu4_opp2: opp-825600000 {
 396                         opp-hz = /bits/ 64 <825600000>;
 397                         opp-peak-kBps = <2188000 19660800>;
 398                 };
 399
 400                 cpu4_opp3: opp-940800000 {
 401                         opp-hz = /bits/ 64 <940800000>;
 402                         opp-peak-kBps = <2188000 22732800>;
 403                 };
 404
 405                 cpu4_opp4: opp-1056000000 {
 406                         opp-hz = /bits/ 64 <1056000000>;
 407                         opp-peak-kBps = <3072000 25804800>;
 408                 };
 409
 410                 cpu4_opp5: opp-1171200000 {
 411                         opp-hz = /bits/ 64 <1171200000>;
 412                         opp-peak-kBps = <3072000 31948800>;
 413                 };
 414
 415                 cpu4_opp6: opp-1286400000 {
 416                         opp-hz = /bits/ 64 <1286400000>;
 417                         opp-peak-kBps = <4068000 31948800>;
 418                 };
 419
 420                 cpu4_opp7: opp-1401600000 {
 421                         opp-hz = /bits/ 64 <1401600000>;
 422                         opp-peak-kBps = <4068000 31948800>;
 423                 };
 424
 425                 cpu4_opp8: opp-1497600000 {
 426                         opp-hz = /bits/ 64 <1497600000>;
 427                         opp-peak-kBps = <4068000 40550400>;
 428                 };
 429
 430                 cpu4_opp9: opp-1612800000 {
 431                         opp-hz = /bits/ 64 <1612800000>;
 432                         opp-peak-kBps = <4068000 40550400>;
 433                 };
 434
 435                 cpu4_opp10: opp-1708800000 {
 436                         opp-hz = /bits/ 64 <1708800000>;
 437                         opp-peak-kBps = <4068000 43008000>;
 438                 };
 439
 440                 cpu4_opp11: opp-1804800000 {
 441                         opp-hz = /bits/ 64 <1804800000>;
 442                         opp-peak-kBps = <6220000 43008000>;
 443                 };
 444
 445                 cpu4_opp12: opp-1920000000 {
 446                         opp-hz = /bits/ 64 <1920000000>;
 447                         opp-peak-kBps = <6220000 49152000>;
 448                 };
 449
 450                 cpu4_opp13: opp-2016000000 {
 451                         opp-hz = /bits/ 64 <2016000000>;
 452                         opp-peak-kBps = <7216000 49152000>;
 453                 };
 454
 455                 cpu4_opp14: opp-2131200000 {
 456                         opp-hz = /bits/ 64 <2131200000>;
 457                         opp-peak-kBps = <8368000 49152000>;
 458                 };
 459
 460                 cpu4_opp15: opp-2227200000 {
 461                         opp-hz = /bits/ 64 <2227200000>;
 462                         opp-peak-kBps = <8368000 51609600>;
 463                 };
 464
 465                 cpu4_opp16: opp-2323200000 {
 466                         opp-hz = /bits/ 64 <2323200000>;
 467                         opp-peak-kBps = <8368000 51609600>;
 468                 };
 469
 470                 cpu4_opp17: opp-2419200000 {
 471                         opp-hz = /bits/ 64 <2419200000>;
 472                         opp-peak-kBps = <8368000 51609600>;
 473                 };
 474         };
 475
 476         cpu7_opp_table: opp-table-cpu7 {
 477                 compatible = "operating-points-v2";
 478                 opp-shared;
 479
 480                 cpu7_opp1: opp-825600000 {
 481                         opp-hz = /bits/ 64 <825600000>;
 482                         opp-peak-kBps = <2188000 19660800>;
 483                 };
 484
 485                 cpu7_opp2: opp-940800000 {
 486                         opp-hz = /bits/ 64 <940800000>;
 487                         opp-peak-kBps = <2188000 22732800>;
 488                 };
 489
 490                 cpu7_opp3: opp-1056000000 {
 491                         opp-hz = /bits/ 64 <1056000000>;
 492                         opp-peak-kBps = <3072000 25804800>;
 493                 };
 494
 495                 cpu7_opp4: opp-1171200000 {
 496                         opp-hz = /bits/ 64 <1171200000>;
 497                         opp-peak-kBps = <3072000 31948800>;
 498                 };
 499
 500                 cpu7_opp5: opp-1286400000 {
 501                         opp-hz = /bits/ 64 <1286400000>;
 502                         opp-peak-kBps = <4068000 31948800>;
 503                 };
 504
 505                 cpu7_opp6: opp-1401600000 {
 506                         opp-hz = /bits/ 64 <1401600000>;
 507                         opp-peak-kBps = <4068000 31948800>;
 508                 };
 509
 510                 cpu7_opp7: opp-1497600000 {
 511                         opp-hz = /bits/ 64 <1497600000>;
 512                         opp-peak-kBps = <4068000 40550400>;
 513                 };
 514
 515                 cpu7_opp8: opp-1612800000 {
 516                         opp-hz = /bits/ 64 <1612800000>;
 517                         opp-peak-kBps = <4068000 40550400>;
 518                 };
 519
 520                 cpu7_opp9: opp-1708800000 {
 521                         opp-hz = /bits/ 64 <1708800000>;
 522                         opp-peak-kBps = <4068000 43008000>;
 523                 };
 524
 525                 cpu7_opp10: opp-1804800000 {
 526                         opp-hz = /bits/ 64 <1804800000>;
 527                         opp-peak-kBps = <6220000 43008000>;
 528                 };
 529
 530                 cpu7_opp11: opp-1920000000 {
 531                         opp-hz = /bits/ 64 <1920000000>;
 532                         opp-peak-kBps = <6220000 49152000>;
 533                 };
 534
 535                 cpu7_opp12: opp-2016000000 {
 536                         opp-hz = /bits/ 64 <2016000000>;
 537                         opp-peak-kBps = <7216000 49152000>;
 538                 };
 539
 540                 cpu7_opp13: opp-2131200000 {
 541                         opp-hz = /bits/ 64 <2131200000>;
 542                         opp-peak-kBps = <8368000 49152000>;
 543                 };
 544
 545                 cpu7_opp14: opp-2227200000 {
 546                         opp-hz = /bits/ 64 <2227200000>;
 547                         opp-peak-kBps = <8368000 51609600>;
 548                 };
 549
 550                 cpu7_opp15: opp-2323200000 {
 551                         opp-hz = /bits/ 64 <2323200000>;
 552                         opp-peak-kBps = <8368000 51609600>;
 553                 };
 554
 555                 cpu7_opp16: opp-2419200000 {
 556                         opp-hz = /bits/ 64 <2419200000>;
 557                         opp-peak-kBps = <8368000 51609600>;
 558                 };
 559
 560                 cpu7_opp17: opp-2534400000 {
 561                         opp-hz = /bits/ 64 <2534400000>;
 562                         opp-peak-kBps = <8368000 51609600>;
 563                 };
 564
 565                 cpu7_opp18: opp-2649600000 {
 566                         opp-hz = /bits/ 64 <2649600000>;
 567                         opp-peak-kBps = <8368000 51609600>;
 568                 };
 569
 570                 cpu7_opp19: opp-2745600000 {
 571                         opp-hz = /bits/ 64 <2745600000>;
 572                         opp-peak-kBps = <8368000 51609600>;
 573                 };
 574
 575                 cpu7_opp20: opp-2841600000 {
 576                         opp-hz = /bits/ 64 <2841600000>;
 577                         opp-peak-kBps = <8368000 51609600>;
 578                 };
 579         };
 580
 581         firmware {
 582                 scm: scm {
 583                         compatible = "qcom,scm-sm8150", "qcom,scm";
 584                         #reset-cells = <1>;
 585                 };
 586         };
 587
 588         memory@80000000 {
 589                 device_type = "memory";
 590                 /* We expect the bootloader to fill in the size */
 591                 reg = <0x0 0x80000000 0x0 0x0>;
 592         };
 593
 594         pmu {
 595                 compatible = "arm,armv8-pmuv3";
 596                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 597         };
 598
 599         psci {
 600                 compatible = "arm,psci-1.0";
 601                 method = "smc";
 602
 603                 CPU_PD0: cpu0 {
 604                         #power-domain-cells = <0>;
 605                         power-domains = <&CLUSTER_PD>;
 606                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 607                 };
 608
 609                 CPU_PD1: cpu1 {
 610                         #power-domain-cells = <0>;
 611                         power-domains = <&CLUSTER_PD>;
 612                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 613                 };
 614
 615                 CPU_PD2: cpu2 {
 616                         #power-domain-cells = <0>;
 617                         power-domains = <&CLUSTER_PD>;
 618                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 619                 };
 620
 621                 CPU_PD3: cpu3 {
 622                         #power-domain-cells = <0>;
 623                         power-domains = <&CLUSTER_PD>;
 624                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 625                 };
 626
 627                 CPU_PD4: cpu4 {
 628                         #power-domain-cells = <0>;
 629                         power-domains = <&CLUSTER_PD>;
 630                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 631                 };
 632
 633                 CPU_PD5: cpu5 {
 634                         #power-domain-cells = <0>;
 635                         power-domains = <&CLUSTER_PD>;
 636                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 637                 };
 638
 639                 CPU_PD6: cpu6 {
 640                         #power-domain-cells = <0>;
 641                         power-domains = <&CLUSTER_PD>;
 642                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 643                 };
 644
 645                 CPU_PD7: cpu7 {
 646                         #power-domain-cells = <0>;
 647                         power-domains = <&CLUSTER_PD>;
 648                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 649                 };
 650
 651                 CLUSTER_PD: cpu-cluster0 {
 652                         #power-domain-cells = <0>;
 653                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 654                 };
 655         };
 656
 657         reserved-memory {
 658                 #address-cells = <2>;
 659                 #size-cells = <2>;
 660                 ranges;
 661
 662                 hyp_mem: memory@85700000 {
 663                         reg = <0x0 0x85700000 0x0 0x600000>;
 664                         no-map;
 665                 };
 666
 667                 xbl_mem: memory@85d00000 {
 668                         reg = <0x0 0x85d00000 0x0 0x140000>;
 669                         no-map;
 670                 };
 671
 672                 aop_mem: memory@85f00000 {
 673                         reg = <0x0 0x85f00000 0x0 0x20000>;
 674                         no-map;
 675                 };
 676
 677                 aop_cmd_db: memory@85f20000 {
 678                         compatible = "qcom,cmd-db";
 679                         reg = <0x0 0x85f20000 0x0 0x20000>;
 680                         no-map;
 681                 };
 682
 683                 smem_mem: memory@86000000 {
 684                         reg = <0x0 0x86000000 0x0 0x200000>;
 685                         no-map;
 686                 };
 687
 688                 tz_mem: memory@86200000 {
 689                         reg = <0x0 0x86200000 0x0 0x3900000>;
 690                         no-map;
 691                 };
 692
 693                 rmtfs_mem: memory@89b00000 {
 694                         compatible = "qcom,rmtfs-mem";
 695                         reg = <0x0 0x89b00000 0x0 0x200000>;
 696                         no-map;
 697
 698                         qcom,client-id = <1>;
 699                         qcom,vmid = <15>;
 700                 };
 701
 702                 camera_mem: memory@8b700000 {
 703                         reg = <0x0 0x8b700000 0x0 0x500000>;
 704                         no-map;
 705                 };
 706
 707                 wlan_mem: memory@8bc00000 {
 708                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 709                         no-map;
 710                 };
 711
 712                 npu_mem: memory@8bd80000 {
 713                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 714                         no-map;
 715                 };
 716
 717                 adsp_mem: memory@8be00000 {
 718                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 719                         no-map;
 720                 };
 721
 722                 mpss_mem: memory@8d800000 {
 723                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 724                         no-map;
 725                 };
 726
 727                 venus_mem: memory@96e00000 {
 728                         reg = <0x0 0x96e00000 0x0 0x500000>;
 729                         no-map;
 730                 };
 731
 732                 slpi_mem: memory@97300000 {
 733                         reg = <0x0 0x97300000 0x0 0x1400000>;
 734                         no-map;
 735                 };
 736
 737                 ipa_fw_mem: memory@98700000 {
 738                         reg = <0x0 0x98700000 0x0 0x10000>;
 739                         no-map;
 740                 };
 741
 742                 ipa_gsi_mem: memory@98710000 {
 743                         reg = <0x0 0x98710000 0x0 0x5000>;
 744                         no-map;
 745                 };
 746
 747                 gpu_mem: memory@98715000 {
 748                         reg = <0x0 0x98715000 0x0 0x2000>;
 749                         no-map;
 750                 };
 751
 752                 spss_mem: memory@98800000 {
 753                         reg = <0x0 0x98800000 0x0 0x100000>;
 754                         no-map;
 755                 };
 756
 757                 cdsp_mem: memory@98900000 {
 758                         reg = <0x0 0x98900000 0x0 0x1400000>;
 759                         no-map;
 760                 };
 761
 762                 qseecom_mem: memory@9e400000 {
 763                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 764                         no-map;
 765                 };
 766         };
 767
 768         smem {
 769                 compatible = "qcom,smem";
 770                 memory-region = <&smem_mem>;
 771                 hwlocks = <&tcsr_mutex 3>;
 772         };
 773
 774         smp2p-cdsp {
 775                 compatible = "qcom,smp2p";
 776                 qcom,smem = <94>, <432>;
 777
 778                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 779
 780                 mboxes = <&apss_shared 6>;
 781
 782                 qcom,local-pid = <0>;
 783                 qcom,remote-pid = <5>;
 784
 785                 cdsp_smp2p_out: master-kernel {
 786                         qcom,entry-name = "master-kernel";
 787                         #qcom,smem-state-cells = <1>;
 788                 };
 789
 790                 cdsp_smp2p_in: slave-kernel {
 791                         qcom,entry-name = "slave-kernel";
 792
 793                         interrupt-controller;
 794                         #interrupt-cells = <2>;
 795                 };
 796         };
 797
 798         smp2p-lpass {
 799                 compatible = "qcom,smp2p";
 800                 qcom,smem = <443>, <429>;
 801
 802                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 803
 804                 mboxes = <&apss_shared 10>;
 805
 806                 qcom,local-pid = <0>;
 807                 qcom,remote-pid = <2>;
 808
 809                 adsp_smp2p_out: master-kernel {
 810                         qcom,entry-name = "master-kernel";
 811                         #qcom,smem-state-cells = <1>;
 812                 };
 813
 814                 adsp_smp2p_in: slave-kernel {
 815                         qcom,entry-name = "slave-kernel";
 816
 817                         interrupt-controller;
 818                         #interrupt-cells = <2>;
 819                 };
 820         };
 821
 822         smp2p-mpss {
 823                 compatible = "qcom,smp2p";
 824                 qcom,smem = <435>, <428>;
 825
 826                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 827
 828                 mboxes = <&apss_shared 14>;
 829
 830                 qcom,local-pid = <0>;
 831                 qcom,remote-pid = <1>;
 832
 833                 modem_smp2p_out: master-kernel {
 834                         qcom,entry-name = "master-kernel";
 835                         #qcom,smem-state-cells = <1>;
 836                 };
 837
 838                 modem_smp2p_in: slave-kernel {
 839                         qcom,entry-name = "slave-kernel";
 840
 841                         interrupt-controller;
 842                         #interrupt-cells = <2>;
 843                 };
 844         };
 845
 846         smp2p-slpi {
 847                 compatible = "qcom,smp2p";
 848                 qcom,smem = <481>, <430>;
 849
 850                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 851
 852                 mboxes = <&apss_shared 26>;
 853
 854                 qcom,local-pid = <0>;
 855                 qcom,remote-pid = <3>;
 856
 857                 slpi_smp2p_out: master-kernel {
 858                         qcom,entry-name = "master-kernel";
 859                         #qcom,smem-state-cells = <1>;
 860                 };
 861
 862                 slpi_smp2p_in: slave-kernel {
 863                         qcom,entry-name = "slave-kernel";
 864
 865                         interrupt-controller;
 866                         #interrupt-cells = <2>;
 867                 };
 868         };
 869
 870         soc: soc@0 {
 871                 #address-cells = <2>;
 872                 #size-cells = <2>;
 873                 ranges = <0 0 0 0 0x10 0>;
 874                 dma-ranges = <0 0 0 0 0x10 0>;
 875                 compatible = "simple-bus";
 876
 877                 gcc: clock-controller@100000 {
 878                         compatible = "qcom,gcc-sm8150";
 879                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 880                         #clock-cells = <1>;
 881                         #reset-cells = <1>;
 882                         #power-domain-cells = <1>;
 883                         clock-names = "bi_tcxo",
 884                                       "sleep_clk";
 885                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 886                                  <&sleep_clk>;
 887                 };
 888
 889                 gpi_dma0: dma-controller@800000 {
 890                         compatible = "qcom,sm8150-gpi-dma";
 891                         reg = <0 0x800000 0 0x60000>;
 892                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 893                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 894                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 895                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 896                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 897                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 898                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 899                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 900                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 902                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 903                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 904                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 905                         dma-channels = <13>;
 906                         dma-channel-mask = <0xfa>;
 907                         iommus = <&apps_smmu 0x00d6 0x0>;
 908                         #dma-cells = <3>;
 909                         status = "disabled";
 910                 };
 911
 912                 ethernet: ethernet@20000 {
 913                         compatible = "qcom,sm8150-ethqos";
 914                         reg = <0x0 0x00020000 0x0 0x10000>,
 915                               <0x0 0x00036000 0x0 0x100>;
 916                         reg-names = "stmmaceth", "rgmii";
 917                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
 918                         clocks = <&gcc GCC_EMAC_AXI_CLK>,
 919                                 <&gcc GCC_EMAC_SLV_AHB_CLK>,
 920                                 <&gcc GCC_EMAC_PTP_CLK>,
 921                                 <&gcc GCC_EMAC_RGMII_CLK>;
 922                         interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
 923                                      <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
 924                         interrupt-names = "macirq", "eth_lpi";
 925
 926                         power-domains = <&gcc EMAC_GDSC>;
 927                         resets = <&gcc GCC_EMAC_BCR>;
 928
 929                         iommus = <&apps_smmu 0x3C0 0x0>;
 930
 931                         snps,tso;
 932                         rx-fifo-depth = <4096>;
 933                         tx-fifo-depth = <4096>;
 934
 935                         status = "disabled";
 936                 };
 937
 938
 939                 qupv3_id_0: geniqup@8c0000 {
 940                         compatible = "qcom,geni-se-qup";
 941                         reg = <0x0 0x008c0000 0x0 0x6000>;
 942                         clock-names = "m-ahb", "s-ahb";
 943                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 944                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 945                         iommus = <&apps_smmu 0xc3 0x0>;
 946                         #address-cells = <2>;
 947                         #size-cells = <2>;
 948                         ranges;
 949                         status = "disabled";
 950
 951                         i2c0: i2c@880000 {
 952                                 compatible = "qcom,geni-i2c";
 953                                 reg = <0 0x00880000 0 0x4000>;
 954                                 clock-names = "se";
 955                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 956                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 957                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 958                                 dma-names = "tx", "rx";
 959                                 pinctrl-names = "default";
 960                                 pinctrl-0 = <&qup_i2c0_default>;
 961                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 962                                 #address-cells = <1>;
 963                                 #size-cells = <0>;
 964                                 status = "disabled";
 965                         };
 966
 967                         spi0: spi@880000 {
 968                                 compatible = "qcom,geni-spi";
 969                                 reg = <0 0x880000 0 0x4000>;
 970                                 reg-names = "se";
 971                                 clock-names = "se";
 972                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 973                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 974                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 975                                 dma-names = "tx", "rx";
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_spi0_default>;
 978                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 979                                 spi-max-frequency = <50000000>;
 980                                 #address-cells = <1>;
 981                                 #size-cells = <0>;
 982                                 status = "disabled";
 983                         };
 984
 985                         i2c1: i2c@884000 {
 986                                 compatible = "qcom,geni-i2c";
 987                                 reg = <0 0x00884000 0 0x4000>;
 988                                 clock-names = "se";
 989                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 990                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 991                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 992                                 dma-names = "tx", "rx";
 993                                 pinctrl-names = "default";
 994                                 pinctrl-0 = <&qup_i2c1_default>;
 995                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 996                                 #address-cells = <1>;
 997                                 #size-cells = <0>;
 998                                 status = "disabled";
 999                         };
1000
1001                         spi1: spi@884000 {
1002                                 compatible = "qcom,geni-spi";
1003                                 reg = <0 0x884000 0 0x4000>;
1004                                 reg-names = "se";
1005                                 clock-names = "se";
1006                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1007                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1008                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1009                                 dma-names = "tx", "rx";
1010                                 pinctrl-names = "default";
1011                                 pinctrl-0 = <&qup_spi1_default>;
1012                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1013                                 spi-max-frequency = <50000000>;
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 status = "disabled";
1017                         };
1018
1019                         i2c2: i2c@888000 {
1020                                 compatible = "qcom,geni-i2c";
1021                                 reg = <0 0x00888000 0 0x4000>;
1022                                 clock-names = "se";
1023                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1024                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1025                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1026                                 dma-names = "tx", "rx";
1027                                 pinctrl-names = "default";
1028                                 pinctrl-0 = <&qup_i2c2_default>;
1029                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1030                                 #address-cells = <1>;
1031                                 #size-cells = <0>;
1032                                 status = "disabled";
1033                         };
1034
1035                         spi2: spi@888000 {
1036                                 compatible = "qcom,geni-spi";
1037                                 reg = <0 0x888000 0 0x4000>;
1038                                 reg-names = "se";
1039                                 clock-names = "se";
1040                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1041                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1042                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1043                                 dma-names = "tx", "rx";
1044                                 pinctrl-names = "default";
1045                                 pinctrl-0 = <&qup_spi2_default>;
1046                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1047                                 spi-max-frequency = <50000000>;
1048                                 #address-cells = <1>;
1049                                 #size-cells = <0>;
1050                                 status = "disabled";
1051                         };
1052
1053                         i2c3: i2c@88c000 {
1054                                 compatible = "qcom,geni-i2c";
1055                                 reg = <0 0x0088c000 0 0x4000>;
1056                                 clock-names = "se";
1057                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1059                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1060                                 dma-names = "tx", "rx";
1061                                 pinctrl-names = "default";
1062                                 pinctrl-0 = <&qup_i2c3_default>;
1063                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1064                                 #address-cells = <1>;
1065                                 #size-cells = <0>;
1066                                 status = "disabled";
1067                         };
1068
1069                         spi3: spi@88c000 {
1070                                 compatible = "qcom,geni-spi";
1071                                 reg = <0 0x88c000 0 0x4000>;
1072                                 reg-names = "se";
1073                                 clock-names = "se";
1074                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1075                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1076                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1077                                 dma-names = "tx", "rx";
1078                                 pinctrl-names = "default";
1079                                 pinctrl-0 = <&qup_spi3_default>;
1080                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1081                                 spi-max-frequency = <50000000>;
1082                                 #address-cells = <1>;
1083                                 #size-cells = <0>;
1084                                 status = "disabled";
1085                         };
1086
1087                         i2c4: i2c@890000 {
1088                                 compatible = "qcom,geni-i2c";
1089                                 reg = <0 0x00890000 0 0x4000>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1093                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1094                                 dma-names = "tx", "rx";
1095                                 pinctrl-names = "default";
1096                                 pinctrl-0 = <&qup_i2c4_default>;
1097                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1098                                 #address-cells = <1>;
1099                                 #size-cells = <0>;
1100                                 status = "disabled";
1101                         };
1102
1103                         spi4: spi@890000 {
1104                                 compatible = "qcom,geni-spi";
1105                                 reg = <0 0x890000 0 0x4000>;
1106                                 reg-names = "se";
1107                                 clock-names = "se";
1108                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1109                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1110                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1111                                 dma-names = "tx", "rx";
1112                                 pinctrl-names = "default";
1113                                 pinctrl-0 = <&qup_spi4_default>;
1114                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115                                 spi-max-frequency = <50000000>;
1116                                 #address-cells = <1>;
1117                                 #size-cells = <0>;
1118                                 status = "disabled";
1119                         };
1120
1121                         i2c5: i2c@894000 {
1122                                 compatible = "qcom,geni-i2c";
1123                                 reg = <0 0x00894000 0 0x4000>;
1124                                 clock-names = "se";
1125                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1126                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1127                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1128                                 dma-names = "tx", "rx";
1129                                 pinctrl-names = "default";
1130                                 pinctrl-0 = <&qup_i2c5_default>;
1131                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1132                                 #address-cells = <1>;
1133                                 #size-cells = <0>;
1134                                 status = "disabled";
1135                         };
1136
1137                         spi5: spi@894000 {
1138                                 compatible = "qcom,geni-spi";
1139                                 reg = <0 0x894000 0 0x4000>;
1140                                 reg-names = "se";
1141                                 clock-names = "se";
1142                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1143                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1144                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1145                                 dma-names = "tx", "rx";
1146                                 pinctrl-names = "default";
1147                                 pinctrl-0 = <&qup_spi5_default>;
1148                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1149                                 spi-max-frequency = <50000000>;
1150                                 #address-cells = <1>;
1151                                 #size-cells = <0>;
1152                                 status = "disabled";
1153                         };
1154
1155                         i2c6: i2c@898000 {
1156                                 compatible = "qcom,geni-i2c";
1157                                 reg = <0 0x00898000 0 0x4000>;
1158                                 clock-names = "se";
1159                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1160                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1161                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1162                                 dma-names = "tx", "rx";
1163                                 pinctrl-names = "default";
1164                                 pinctrl-0 = <&qup_i2c6_default>;
1165                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1166                                 #address-cells = <1>;
1167                                 #size-cells = <0>;
1168                                 status = "disabled";
1169                         };
1170
1171                         spi6: spi@898000 {
1172                                 compatible = "qcom,geni-spi";
1173                                 reg = <0 0x898000 0 0x4000>;
1174                                 reg-names = "se";
1175                                 clock-names = "se";
1176                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1177                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1178                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1179                                 dma-names = "tx", "rx";
1180                                 pinctrl-names = "default";
1181                                 pinctrl-0 = <&qup_spi6_default>;
1182                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1183                                 spi-max-frequency = <50000000>;
1184                                 #address-cells = <1>;
1185                                 #size-cells = <0>;
1186                                 status = "disabled";
1187                         };
1188
1189                         i2c7: i2c@89c000 {
1190                                 compatible = "qcom,geni-i2c";
1191                                 reg = <0 0x0089c000 0 0x4000>;
1192                                 clock-names = "se";
1193                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1194                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1195                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1196                                 dma-names = "tx", "rx";
1197                                 pinctrl-names = "default";
1198                                 pinctrl-0 = <&qup_i2c7_default>;
1199                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1200                                 #address-cells = <1>;
1201                                 #size-cells = <0>;
1202                                 status = "disabled";
1203                         };
1204
1205                         spi7: spi@89c000 {
1206                                 compatible = "qcom,geni-spi";
1207                                 reg = <0 0x89c000 0 0x4000>;
1208                                 reg-names = "se";
1209                                 clock-names = "se";
1210                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1211                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1212                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1213                                 dma-names = "tx", "rx";
1214                                 pinctrl-names = "default";
1215                                 pinctrl-0 = <&qup_spi7_default>;
1216                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1217                                 spi-max-frequency = <50000000>;
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 status = "disabled";
1221                         };
1222                 };
1223
1224                 gpi_dma1: dma-controller@a00000 {
1225                         compatible = "qcom,sm8150-gpi-dma";
1226                         reg = <0 0xa00000 0 0x60000>;
1227                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1228                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1229                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1230                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1231                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1232                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1233                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1234                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1235                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1236                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1237                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1238                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1239                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1240                         dma-channels = <13>;
1241                         dma-channel-mask = <0xfa>;
1242                         iommus = <&apps_smmu 0x0616 0x0>;
1243                         #dma-cells = <3>;
1244                         status = "disabled";
1245                 };
1246
1247                 qupv3_id_1: geniqup@ac0000 {
1248                         compatible = "qcom,geni-se-qup";
1249                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1250                         clock-names = "m-ahb", "s-ahb";
1251                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1252                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1253                         iommus = <&apps_smmu 0x603 0x0>;
1254                         #address-cells = <2>;
1255                         #size-cells = <2>;
1256                         ranges;
1257                         status = "disabled";
1258
1259                         i2c8: i2c@a80000 {
1260                                 compatible = "qcom,geni-i2c";
1261                                 reg = <0 0x00a80000 0 0x4000>;
1262                                 clock-names = "se";
1263                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1264                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1265                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1266                                 dma-names = "tx", "rx";
1267                                 pinctrl-names = "default";
1268                                 pinctrl-0 = <&qup_i2c8_default>;
1269                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1270                                 #address-cells = <1>;
1271                                 #size-cells = <0>;
1272                                 status = "disabled";
1273                         };
1274
1275                         spi8: spi@a80000 {
1276                                 compatible = "qcom,geni-spi";
1277                                 reg = <0 0xa80000 0 0x4000>;
1278                                 reg-names = "se";
1279                                 clock-names = "se";
1280                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1281                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1282                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1283                                 dma-names = "tx", "rx";
1284                                 pinctrl-names = "default";
1285                                 pinctrl-0 = <&qup_spi8_default>;
1286                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1287                                 spi-max-frequency = <50000000>;
1288                                 #address-cells = <1>;
1289                                 #size-cells = <0>;
1290                                 status = "disabled";
1291                         };
1292
1293                         i2c9: i2c@a84000 {
1294                                 compatible = "qcom,geni-i2c";
1295                                 reg = <0 0x00a84000 0 0x4000>;
1296                                 clock-names = "se";
1297                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1298                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1299                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1300                                 dma-names = "tx", "rx";
1301                                 pinctrl-names = "default";
1302                                 pinctrl-0 = <&qup_i2c9_default>;
1303                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1304                                 #address-cells = <1>;
1305                                 #size-cells = <0>;
1306                                 status = "disabled";
1307                         };
1308
1309                         spi9: spi@a84000 {
1310                                 compatible = "qcom,geni-spi";
1311                                 reg = <0 0xa84000 0 0x4000>;
1312                                 reg-names = "se";
1313                                 clock-names = "se";
1314                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1315                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1316                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1317                                 dma-names = "tx", "rx";
1318                                 pinctrl-names = "default";
1319                                 pinctrl-0 = <&qup_spi9_default>;
1320                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1321                                 spi-max-frequency = <50000000>;
1322                                 #address-cells = <1>;
1323                                 #size-cells = <0>;
1324                                 status = "disabled";
1325                         };
1326
1327                         i2c10: i2c@a88000 {
1328                                 compatible = "qcom,geni-i2c";
1329                                 reg = <0 0x00a88000 0 0x4000>;
1330                                 clock-names = "se";
1331                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1332                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1333                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1334                                 dma-names = "tx", "rx";
1335                                 pinctrl-names = "default";
1336                                 pinctrl-0 = <&qup_i2c10_default>;
1337                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1338                                 #address-cells = <1>;
1339                                 #size-cells = <0>;
1340                                 status = "disabled";
1341                         };
1342
1343                         spi10: spi@a88000 {
1344                                 compatible = "qcom,geni-spi";
1345                                 reg = <0 0xa88000 0 0x4000>;
1346                                 reg-names = "se";
1347                                 clock-names = "se";
1348                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1349                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1350                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1351                                 dma-names = "tx", "rx";
1352                                 pinctrl-names = "default";
1353                                 pinctrl-0 = <&qup_spi10_default>;
1354                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1355                                 spi-max-frequency = <50000000>;
1356                                 #address-cells = <1>;
1357                                 #size-cells = <0>;
1358                                 status = "disabled";
1359                         };
1360
1361                         i2c11: i2c@a8c000 {
1362                                 compatible = "qcom,geni-i2c";
1363                                 reg = <0 0x00a8c000 0 0x4000>;
1364                                 clock-names = "se";
1365                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1366                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1367                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1368                                 dma-names = "tx", "rx";
1369                                 pinctrl-names = "default";
1370                                 pinctrl-0 = <&qup_i2c11_default>;
1371                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1372                                 #address-cells = <1>;
1373                                 #size-cells = <0>;
1374                                 status = "disabled";
1375                         };
1376
1377                         spi11: spi@a8c000 {
1378                                 compatible = "qcom,geni-spi";
1379                                 reg = <0 0xa8c000 0 0x4000>;
1380                                 reg-names = "se";
1381                                 clock-names = "se";
1382                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1383                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1384                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1385                                 dma-names = "tx", "rx";
1386                                 pinctrl-names = "default";
1387                                 pinctrl-0 = <&qup_spi11_default>;
1388                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1389                                 spi-max-frequency = <50000000>;
1390                                 #address-cells = <1>;
1391                                 #size-cells = <0>;
1392                                 status = "disabled";
1393                         };
1394
1395                         uart2: serial@a90000 {
1396                                 compatible = "qcom,geni-debug-uart";
1397                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1398                                 clock-names = "se";
1399                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1400                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1401                                 status = "disabled";
1402                         };
1403
1404                         i2c12: i2c@a90000 {
1405                                 compatible = "qcom,geni-i2c";
1406                                 reg = <0 0x00a90000 0 0x4000>;
1407                                 clock-names = "se";
1408                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1409                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1410                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1411                                 dma-names = "tx", "rx";
1412                                 pinctrl-names = "default";
1413                                 pinctrl-0 = <&qup_i2c12_default>;
1414                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1415                                 #address-cells = <1>;
1416                                 #size-cells = <0>;
1417                                 status = "disabled";
1418                         };
1419
1420                         spi12: spi@a90000 {
1421                                 compatible = "qcom,geni-spi";
1422                                 reg = <0 0xa90000 0 0x4000>;
1423                                 reg-names = "se";
1424                                 clock-names = "se";
1425                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1426                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1427                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1428                                 dma-names = "tx", "rx";
1429                                 pinctrl-names = "default";
1430                                 pinctrl-0 = <&qup_spi12_default>;
1431                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1432                                 spi-max-frequency = <50000000>;
1433                                 #address-cells = <1>;
1434                                 #size-cells = <0>;
1435                                 status = "disabled";
1436                         };
1437
1438                         i2c16: i2c@94000 {
1439                                 compatible = "qcom,geni-i2c";
1440                                 reg = <0 0x0094000 0 0x4000>;
1441                                 clock-names = "se";
1442                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1443                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1444                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1445                                 dma-names = "tx", "rx";
1446                                 pinctrl-names = "default";
1447                                 pinctrl-0 = <&qup_i2c16_default>;
1448                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1449                                 #address-cells = <1>;
1450                                 #size-cells = <0>;
1451                                 status = "disabled";
1452                         };
1453
1454                         spi16: spi@a94000 {
1455                                 compatible = "qcom,geni-spi";
1456                                 reg = <0 0xa94000 0 0x4000>;
1457                                 reg-names = "se";
1458                                 clock-names = "se";
1459                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1460                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1461                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1462                                 dma-names = "tx", "rx";
1463                                 pinctrl-names = "default";
1464                                 pinctrl-0 = <&qup_spi16_default>;
1465                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1466                                 spi-max-frequency = <50000000>;
1467                                 #address-cells = <1>;
1468                                 #size-cells = <0>;
1469                                 status = "disabled";
1470                         };
1471                 };
1472
1473                 gpi_dma2: dma-controller@c00000 {
1474                         compatible = "qcom,sm8150-gpi-dma";
1475                         reg = <0 0xc00000 0 0x60000>;
1476                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1477                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1478                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1479                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1480                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1481                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1482                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1483                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1484                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1485                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1486                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1487                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1488                                      <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1489                         dma-channels = <13>;
1490                         dma-channel-mask = <0xfa>;
1491                         iommus = <&apps_smmu 0x07b6 0x0>;
1492                         #dma-cells = <3>;
1493                         status = "disabled";
1494                 };
1495
1496                 qupv3_id_2: geniqup@cc0000 {
1497                         compatible = "qcom,geni-se-qup";
1498                         reg = <0x0 0x00cc0000 0x0 0x6000>;
1499
1500                         clock-names = "m-ahb", "s-ahb";
1501                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1502                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1503                         iommus = <&apps_smmu 0x7a3 0x0>;
1504                         #address-cells = <2>;
1505                         #size-cells = <2>;
1506                         ranges;
1507                         status = "disabled";
1508
1509                         i2c17: i2c@c80000 {
1510                                 compatible = "qcom,geni-i2c";
1511                                 reg = <0 0x00c80000 0 0x4000>;
1512                                 clock-names = "se";
1513                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1514                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1515                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1516                                 dma-names = "tx", "rx";
1517                                 pinctrl-names = "default";
1518                                 pinctrl-0 = <&qup_i2c17_default>;
1519                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1520                                 #address-cells = <1>;
1521                                 #size-cells = <0>;
1522                                 status = "disabled";
1523                         };
1524
1525                         spi17: spi@c80000 {
1526                                 compatible = "qcom,geni-spi";
1527                                 reg = <0 0xc80000 0 0x4000>;
1528                                 reg-names = "se";
1529                                 clock-names = "se";
1530                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1531                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1532                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1533                                 dma-names = "tx", "rx";
1534                                 pinctrl-names = "default";
1535                                 pinctrl-0 = <&qup_spi17_default>;
1536                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1537                                 spi-max-frequency = <50000000>;
1538                                 #address-cells = <1>;
1539                                 #size-cells = <0>;
1540                                 status = "disabled";
1541                         };
1542
1543                         i2c18: i2c@c84000 {
1544                                 compatible = "qcom,geni-i2c";
1545                                 reg = <0 0x00c84000 0 0x4000>;
1546                                 clock-names = "se";
1547                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1548                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1549                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1550                                 dma-names = "tx", "rx";
1551                                 pinctrl-names = "default";
1552                                 pinctrl-0 = <&qup_i2c18_default>;
1553                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1554                                 #address-cells = <1>;
1555                                 #size-cells = <0>;
1556                                 status = "disabled";
1557                         };
1558
1559                         spi18: spi@c84000 {
1560                                 compatible = "qcom,geni-spi";
1561                                 reg = <0 0xc84000 0 0x4000>;
1562                                 reg-names = "se";
1563                                 clock-names = "se";
1564                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1565                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1566                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1567                                 dma-names = "tx", "rx";
1568                                 pinctrl-names = "default";
1569                                 pinctrl-0 = <&qup_spi18_default>;
1570                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1571                                 spi-max-frequency = <50000000>;
1572                                 #address-cells = <1>;
1573                                 #size-cells = <0>;
1574                                 status = "disabled";
1575                         };
1576
1577                         i2c19: i2c@c88000 {
1578                                 compatible = "qcom,geni-i2c";
1579                                 reg = <0 0x00c88000 0 0x4000>;
1580                                 clock-names = "se";
1581                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1582                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1583                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1584                                 dma-names = "tx", "rx";
1585                                 pinctrl-names = "default";
1586                                 pinctrl-0 = <&qup_i2c19_default>;
1587                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1588                                 #address-cells = <1>;
1589                                 #size-cells = <0>;
1590                                 status = "disabled";
1591                         };
1592
1593                         spi19: spi@c88000 {
1594                                 compatible = "qcom,geni-spi";
1595                                 reg = <0 0xc88000 0 0x4000>;
1596                                 reg-names = "se";
1597                                 clock-names = "se";
1598                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1599                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1600                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1601                                 dma-names = "tx", "rx";
1602                                 pinctrl-names = "default";
1603                                 pinctrl-0 = <&qup_spi19_default>;
1604                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1605                                 spi-max-frequency = <50000000>;
1606                                 #address-cells = <1>;
1607                                 #size-cells = <0>;
1608                                 status = "disabled";
1609                         };
1610
1611                         i2c13: i2c@c8c000 {
1612                                 compatible = "qcom,geni-i2c";
1613                                 reg = <0 0x00c8c000 0 0x4000>;
1614                                 clock-names = "se";
1615                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1616                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1617                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1618                                 dma-names = "tx", "rx";
1619                                 pinctrl-names = "default";
1620                                 pinctrl-0 = <&qup_i2c13_default>;
1621                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1622                                 #address-cells = <1>;
1623                                 #size-cells = <0>;
1624                                 status = "disabled";
1625                         };
1626
1627                         spi13: spi@c8c000 {
1628                                 compatible = "qcom,geni-spi";
1629                                 reg = <0 0xc8c000 0 0x4000>;
1630                                 reg-names = "se";
1631                                 clock-names = "se";
1632                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1633                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1634                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1635                                 dma-names = "tx", "rx";
1636                                 pinctrl-names = "default";
1637                                 pinctrl-0 = <&qup_spi13_default>;
1638                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1639                                 spi-max-frequency = <50000000>;
1640                                 #address-cells = <1>;
1641                                 #size-cells = <0>;
1642                                 status = "disabled";
1643                         };
1644
1645                         i2c14: i2c@c90000 {
1646                                 compatible = "qcom,geni-i2c";
1647                                 reg = <0 0x00c90000 0 0x4000>;
1648                                 clock-names = "se";
1649                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1650                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1651                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1652                                 dma-names = "tx", "rx";
1653                                 pinctrl-names = "default";
1654                                 pinctrl-0 = <&qup_i2c14_default>;
1655                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1656                                 #address-cells = <1>;
1657                                 #size-cells = <0>;
1658                                 status = "disabled";
1659                         };
1660
1661                         spi14: spi@c90000 {
1662                                 compatible = "qcom,geni-spi";
1663                                 reg = <0 0xc90000 0 0x4000>;
1664                                 reg-names = "se";
1665                                 clock-names = "se";
1666                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1667                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1668                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1669                                 dma-names = "tx", "rx";
1670                                 pinctrl-names = "default";
1671                                 pinctrl-0 = <&qup_spi14_default>;
1672                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1673                                 spi-max-frequency = <50000000>;
1674                                 #address-cells = <1>;
1675                                 #size-cells = <0>;
1676                                 status = "disabled";
1677                         };
1678
1679                         i2c15: i2c@c94000 {
1680                                 compatible = "qcom,geni-i2c";
1681                                 reg = <0 0x00c94000 0 0x4000>;
1682                                 clock-names = "se";
1683                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1684                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1685                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1686                                 dma-names = "tx", "rx";
1687                                 pinctrl-names = "default";
1688                                 pinctrl-0 = <&qup_i2c15_default>;
1689                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1690                                 #address-cells = <1>;
1691                                 #size-cells = <0>;
1692                                 status = "disabled";
1693                         };
1694
1695                         spi15: spi@c94000 {
1696                                 compatible = "qcom,geni-spi";
1697                                 reg = <0 0xc94000 0 0x4000>;
1698                                 reg-names = "se";
1699                                 clock-names = "se";
1700                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1701                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1702                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1703                                 dma-names = "tx", "rx";
1704                                 pinctrl-names = "default";
1705                                 pinctrl-0 = <&qup_spi15_default>;
1706                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1707                                 spi-max-frequency = <50000000>;
1708                                 #address-cells = <1>;
1709                                 #size-cells = <0>;
1710                                 status = "disabled";
1711                         };
1712                 };
1713
1714                 config_noc: interconnect@1500000 {
1715                         compatible = "qcom,sm8150-config-noc";
1716                         reg = <0 0x01500000 0 0x7400>;
1717                         #interconnect-cells = <1>;
1718                         qcom,bcm-voters = <&apps_bcm_voter>;
1719                 };
1720
1721                 system_noc: interconnect@1620000 {
1722                         compatible = "qcom,sm8150-system-noc";
1723                         reg = <0 0x01620000 0 0x19400>;
1724                         #interconnect-cells = <1>;
1725                         qcom,bcm-voters = <&apps_bcm_voter>;
1726                 };
1727
1728                 mc_virt: interconnect@163a000 {
1729                         compatible = "qcom,sm8150-mc-virt";
1730                         reg = <0 0x0163a000 0 0x1000>;
1731                         #interconnect-cells = <1>;
1732                         qcom,bcm-voters = <&apps_bcm_voter>;
1733                 };
1734
1735                 aggre1_noc: interconnect@16e0000 {
1736                         compatible = "qcom,sm8150-aggre1-noc";
1737                         reg = <0 0x016e0000 0 0xd080>;
1738                         #interconnect-cells = <1>;
1739                         qcom,bcm-voters = <&apps_bcm_voter>;
1740                 };
1741
1742                 aggre2_noc: interconnect@1700000 {
1743                         compatible = "qcom,sm8150-aggre2-noc";
1744                         reg = <0 0x01700000 0 0x20000>;
1745                         #interconnect-cells = <1>;
1746                         qcom,bcm-voters = <&apps_bcm_voter>;
1747                 };
1748
1749                 compute_noc: interconnect@1720000 {
1750                         compatible = "qcom,sm8150-compute-noc";
1751                         reg = <0 0x01720000 0 0x7000>;
1752                         #interconnect-cells = <1>;
1753                         qcom,bcm-voters = <&apps_bcm_voter>;
1754                 };
1755
1756                 mmss_noc: interconnect@1740000 {
1757                         compatible = "qcom,sm8150-mmss-noc";
1758                         reg = <0 0x01740000 0 0x1c100>;
1759                         #interconnect-cells = <1>;
1760                         qcom,bcm-voters = <&apps_bcm_voter>;
1761                 };
1762
1763                 system-cache-controller@9200000 {
1764                         compatible = "qcom,sm8150-llcc";
1765                         reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1766                         reg-names = "llcc_base", "llcc_broadcast_base";
1767                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1768                 };
1769
1770                 pcie0: pci@1c00000 {
1771                         compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1772                         reg = <0 0x01c00000 0 0x3000>,
1773                               <0 0x60000000 0 0xf1d>,
1774                               <0 0x60000f20 0 0xa8>,
1775                               <0 0x60001000 0 0x1000>,
1776                               <0 0x60100000 0 0x100000>;
1777                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1778                         device_type = "pci";
1779                         linux,pci-domain = <0>;
1780                         bus-range = <0x00 0xff>;
1781                         num-lanes = <1>;
1782
1783                         #address-cells = <3>;
1784                         #size-cells = <2>;
1785
1786                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1787                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1788
1789                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1790                         interrupt-names = "msi";
1791                         #interrupt-cells = <1>;
1792                         interrupt-map-mask = <0 0 0 0x7>;
1793                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1794                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1795                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1796                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1797
1798                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1799                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1800                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1801                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1802                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1803                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1804                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1805                         clock-names = "pipe",
1806                                       "aux",
1807                                       "cfg",
1808                                       "bus_master",
1809                                       "bus_slave",
1810                                       "slave_q2a",
1811                                       "tbu";
1812
1813                         iommus = <&apps_smmu 0x1d80 0x3f>;
1814                         iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
1815                                     <0x100 &apps_smmu 0x1d81 0x1>;
1816
1817                         resets = <&gcc GCC_PCIE_0_BCR>;
1818                         reset-names = "pci";
1819
1820                         power-domains = <&gcc PCIE_0_GDSC>;
1821
1822                         phys = <&pcie0_lane>;
1823                         phy-names = "pciephy";
1824
1825                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1826                         wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1827
1828                         pinctrl-names = "default";
1829                         pinctrl-0 = <&pcie0_default_state>;
1830
1831                         status = "disabled";
1832                 };
1833
1834                 pcie0_phy: phy@1c06000 {
1835                         compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1836                         reg = <0 0x01c06000 0 0x1c0>;
1837                         #address-cells = <2>;
1838                         #size-cells = <2>;
1839                         ranges;
1840                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1841                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1842                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1843                                  <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1844                         clock-names = "aux",
1845                                       "cfg_ahb",
1846                                       "ref",
1847                                       "refgen";
1848
1849                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1850                         reset-names = "phy";
1851
1852                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1853                         assigned-clock-rates = <100000000>;
1854
1855                         status = "disabled";
1856
1857                         pcie0_lane: phy@1c06200 {
1858                                 reg = <0 0x1c06200 0 0x170>, /* tx */
1859                                       <0 0x1c06400 0 0x200>, /* rx */
1860                                       <0 0x1c06800 0 0x1f0>, /* pcs */
1861                                       <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
1862                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1863                                 clock-names = "pipe0";
1864
1865                                 #phy-cells = <0>;
1866                                 clock-output-names = "pcie_0_pipe_clk";
1867                         };
1868                 };
1869
1870                 pcie1: pci@1c08000 {
1871                         compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1872                         reg = <0 0x01c08000 0 0x3000>,
1873                               <0 0x40000000 0 0xf1d>,
1874                               <0 0x40000f20 0 0xa8>,
1875                               <0 0x40001000 0 0x1000>,
1876                               <0 0x40100000 0 0x100000>;
1877                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1878                         device_type = "pci";
1879                         linux,pci-domain = <1>;
1880                         bus-range = <0x00 0xff>;
1881                         num-lanes = <2>;
1882
1883                         #address-cells = <3>;
1884                         #size-cells = <2>;
1885
1886                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1887                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1888
1889                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1890                         interrupt-names = "msi";
1891                         #interrupt-cells = <1>;
1892                         interrupt-map-mask = <0 0 0 0x7>;
1893                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1894                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1895                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1896                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1897
1898                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1899                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1900                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1901                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1902                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1903                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1904                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1905                         clock-names = "pipe",
1906                                       "aux",
1907                                       "cfg",
1908                                       "bus_master",
1909                                       "bus_slave",
1910                                       "slave_q2a",
1911                                       "tbu";
1912
1913                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1914                         assigned-clock-rates = <19200000>;
1915
1916                         iommus = <&apps_smmu 0x1e00 0x3f>;
1917                         iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
1918                                     <0x100 &apps_smmu 0x1e01 0x1>;
1919
1920                         resets = <&gcc GCC_PCIE_1_BCR>;
1921                         reset-names = "pci";
1922
1923                         power-domains = <&gcc PCIE_1_GDSC>;
1924
1925                         phys = <&pcie1_lane>;
1926                         phy-names = "pciephy";
1927
1928                         perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1929                         enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1930
1931                         pinctrl-names = "default";
1932                         pinctrl-0 = <&pcie1_default_state>;
1933
1934                         status = "disabled";
1935                 };
1936
1937                 pcie1_phy: phy@1c0e000 {
1938                         compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1939                         reg = <0 0x01c0e000 0 0x1c0>;
1940                         #address-cells = <2>;
1941                         #size-cells = <2>;
1942                         ranges;
1943                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1944                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1945                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1946                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1947                         clock-names = "aux",
1948                                       "cfg_ahb",
1949                                       "ref",
1950                                       "refgen";
1951
1952                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1953                         reset-names = "phy";
1954
1955                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1956                         assigned-clock-rates = <100000000>;
1957
1958                         status = "disabled";
1959
1960                         pcie1_lane: phy@1c0e200 {
1961                                 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
1962                                       <0 0x1c0e400 0 0x200>, /* rx0 */
1963                                       <0 0x1c0ea00 0 0x1f0>, /* pcs */
1964                                       <0 0x1c0e600 0 0x170>, /* tx1 */
1965                                       <0 0x1c0e800 0 0x200>, /* rx1 */
1966                                       <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
1967                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1968                                 clock-names = "pipe0";
1969
1970                                 #phy-cells = <0>;
1971                                 clock-output-names = "pcie_1_pipe_clk";
1972                         };
1973                 };
1974
1975                 ufs_mem_hc: ufshc@1d84000 {
1976                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
1977                                      "jedec,ufs-2.0";
1978                         reg = <0 0x01d84000 0 0x2500>,
1979                               <0 0x01d90000 0 0x8000>;
1980                         reg-names = "std", "ice";
1981                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1982                         phys = <&ufs_mem_phy_lanes>;
1983                         phy-names = "ufsphy";
1984                         lanes-per-direction = <2>;
1985                         #reset-cells = <1>;
1986                         resets = <&gcc GCC_UFS_PHY_BCR>;
1987                         reset-names = "rst";
1988
1989                         iommus = <&apps_smmu 0x300 0>;
1990
1991                         clock-names =
1992                                 "core_clk",
1993                                 "bus_aggr_clk",
1994                                 "iface_clk",
1995                                 "core_clk_unipro",
1996                                 "ref_clk",
1997                                 "tx_lane0_sync_clk",
1998                                 "rx_lane0_sync_clk",
1999                                 "rx_lane1_sync_clk",
2000                                 "ice_core_clk";
2001                         clocks =
2002                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2003                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2004                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2005                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2006                                 <&rpmhcc RPMH_CXO_CLK>,
2007                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2008                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2009                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2010                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2011                         freq-table-hz =
2012                                 <37500000 300000000>,
2013                                 <0 0>,
2014                                 <0 0>,
2015                                 <37500000 300000000>,
2016                                 <0 0>,
2017                                 <0 0>,
2018                                 <0 0>,
2019                                 <0 0>,
2020                                 <0 300000000>;
2021
2022                         status = "disabled";
2023                 };
2024
2025                 ufs_mem_phy: phy@1d87000 {
2026                         compatible = "qcom,sm8150-qmp-ufs-phy";
2027                         reg = <0 0x01d87000 0 0x1c0>;
2028                         #address-cells = <2>;
2029                         #size-cells = <2>;
2030                         ranges;
2031                         clock-names = "ref",
2032                                       "ref_aux";
2033                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2034                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2035
2036                         power-domains = <&gcc UFS_PHY_GDSC>;
2037
2038                         resets = <&ufs_mem_hc 0>;
2039                         reset-names = "ufsphy";
2040                         status = "disabled";
2041
2042                         ufs_mem_phy_lanes: phy@1d87400 {
2043                                 reg = <0 0x01d87400 0 0x16c>,
2044                                       <0 0x01d87600 0 0x200>,
2045                                       <0 0x01d87c00 0 0x200>,
2046                                       <0 0x01d87800 0 0x16c>,
2047                                       <0 0x01d87a00 0 0x200>;
2048                                 #phy-cells = <0>;
2049                         };
2050                 };
2051
2052                 ipa_virt: interconnect@1e00000 {
2053                         compatible = "qcom,sm8150-ipa-virt";
2054                         reg = <0 0x01e00000 0 0x1000>;
2055                         #interconnect-cells = <1>;
2056                         qcom,bcm-voters = <&apps_bcm_voter>;
2057                 };
2058
2059                 tcsr_mutex: hwlock@1f40000 {
2060                         compatible = "qcom,tcsr-mutex";
2061                         reg = <0x0 0x01f40000 0x0 0x20000>;
2062                         #hwlock-cells = <1>;
2063                 };
2064
2065                 tcsr_regs_1: syscon@1f60000 {
2066                         compatible = "qcom,sm8150-tcsr", "syscon";
2067                         reg = <0x0 0x01f60000 0x0 0x20000>;
2068                 };
2069
2070                 remoteproc_slpi: remoteproc@2400000 {
2071                         compatible = "qcom,sm8150-slpi-pas";
2072                         reg = <0x0 0x02400000 0x0 0x4040>;
2073
2074                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2075                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2076                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2077                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2078                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2079                         interrupt-names = "wdog", "fatal", "ready",
2080                                           "handover", "stop-ack";
2081
2082                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2083                         clock-names = "xo";
2084
2085                         power-domains = <&rpmhpd 3>,
2086                                         <&rpmhpd 2>;
2087                         power-domain-names = "lcx", "lmx";
2088
2089                         memory-region = <&slpi_mem>;
2090
2091                         qcom,qmp = <&aoss_qmp>;
2092
2093                         qcom,smem-states = <&slpi_smp2p_out 0>;
2094                         qcom,smem-state-names = "stop";
2095
2096                         status = "disabled";
2097
2098                         glink-edge {
2099                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2100                                 label = "dsps";
2101                                 qcom,remote-pid = <3>;
2102                                 mboxes = <&apss_shared 24>;
2103
2104                                 fastrpc {
2105                                         compatible = "qcom,fastrpc";
2106                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2107                                         label = "sdsp";
2108                                         qcom,non-secure-domain;
2109                                         #address-cells = <1>;
2110                                         #size-cells = <0>;
2111
2112                                         compute-cb@1 {
2113                                                 compatible = "qcom,fastrpc-compute-cb";
2114                                                 reg = <1>;
2115                                                 iommus = <&apps_smmu 0x05a1 0x0>;
2116                                         };
2117
2118                                         compute-cb@2 {
2119                                                 compatible = "qcom,fastrpc-compute-cb";
2120                                                 reg = <2>;
2121                                                 iommus = <&apps_smmu 0x05a2 0x0>;
2122                                         };
2123
2124                                         compute-cb@3 {
2125                                                 compatible = "qcom,fastrpc-compute-cb";
2126                                                 reg = <3>;
2127                                                 iommus = <&apps_smmu 0x05a3 0x0>;
2128                                                 /* note: shared-cb = <4> in downstream */
2129                                         };
2130                                 };
2131                         };
2132                 };
2133
2134                 gpu: gpu@2c00000 {
2135                         /*
2136                          * note: the amd,imageon compatible makes it possible
2137                          * to use the drm/msm driver without the display node,
2138                          * make sure to remove it when display node is added
2139                          */
2140                         compatible = "qcom,adreno-640.1",
2141                                      "qcom,adreno",
2142                                      "amd,imageon";
2143
2144                         reg = <0 0x02c00000 0 0x40000>;
2145                         reg-names = "kgsl_3d0_reg_memory";
2146
2147                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2148
2149                         iommus = <&adreno_smmu 0 0x401>;
2150
2151                         operating-points-v2 = <&gpu_opp_table>;
2152
2153                         qcom,gmu = <&gmu>;
2154
2155                         status = "disabled";
2156
2157                         zap-shader {
2158                                 memory-region = <&gpu_mem>;
2159                         };
2160
2161                         /* note: downstream checks gpu binning for 675 Mhz */
2162                         gpu_opp_table: opp-table {
2163                                 compatible = "operating-points-v2";
2164
2165                                 opp-675000000 {
2166                                         opp-hz = /bits/ 64 <675000000>;
2167                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2168                                 };
2169
2170                                 opp-585000000 {
2171                                         opp-hz = /bits/ 64 <585000000>;
2172                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2173                                 };
2174
2175                                 opp-499200000 {
2176                                         opp-hz = /bits/ 64 <499200000>;
2177                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2178                                 };
2179
2180                                 opp-427000000 {
2181                                         opp-hz = /bits/ 64 <427000000>;
2182                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2183                                 };
2184
2185                                 opp-345000000 {
2186                                         opp-hz = /bits/ 64 <345000000>;
2187                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2188                                 };
2189
2190                                 opp-257000000 {
2191                                         opp-hz = /bits/ 64 <257000000>;
2192                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2193                                 };
2194                         };
2195                 };
2196
2197                 gmu: gmu@2c6a000 {
2198                         compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2199
2200                         reg = <0 0x02c6a000 0 0x30000>,
2201                               <0 0x0b290000 0 0x10000>,
2202                               <0 0x0b490000 0 0x10000>;
2203                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2204
2205                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2206                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2207                         interrupt-names = "hfi", "gmu";
2208
2209                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2210                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2211                                  <&gpucc GPU_CC_CXO_CLK>,
2212                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2213                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2214                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2215
2216                         power-domains = <&gpucc GPU_CX_GDSC>,
2217                                         <&gpucc GPU_GX_GDSC>;
2218                         power-domain-names = "cx", "gx";
2219
2220                         iommus = <&adreno_smmu 5 0x400>;
2221
2222                         operating-points-v2 = <&gmu_opp_table>;
2223
2224                         status = "disabled";
2225
2226                         gmu_opp_table: opp-table {
2227                                 compatible = "operating-points-v2";
2228
2229                                 opp-200000000 {
2230                                         opp-hz = /bits/ 64 <200000000>;
2231                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2232                                 };
2233                         };
2234                 };
2235
2236                 gpucc: clock-controller@2c90000 {
2237                         compatible = "qcom,sm8150-gpucc";
2238                         reg = <0 0x02c90000 0 0x9000>;
2239                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2240                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2241                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2242                         clock-names = "bi_tcxo",
2243                                       "gcc_gpu_gpll0_clk_src",
2244                                       "gcc_gpu_gpll0_div_clk_src";
2245                         #clock-cells = <1>;
2246                         #reset-cells = <1>;
2247                         #power-domain-cells = <1>;
2248                 };
2249
2250                 adreno_smmu: iommu@2ca0000 {
2251                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2252                         reg = <0 0x02ca0000 0 0x10000>;
2253                         #iommu-cells = <2>;
2254                         #global-interrupts = <1>;
2255                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2256                                 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2257                                 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2258                                 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2259                                 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2260                                 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2261                                 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2262                                 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2263                                 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2264                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2265                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2266                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2267                         clock-names = "ahb", "bus", "iface";
2268
2269                         power-domains = <&gpucc GPU_CX_GDSC>;
2270                 };
2271
2272                 tlmm: pinctrl@3100000 {
2273                         compatible = "qcom,sm8150-pinctrl";
2274                         reg = <0x0 0x03100000 0x0 0x300000>,
2275                               <0x0 0x03500000 0x0 0x300000>,
2276                               <0x0 0x03900000 0x0 0x300000>,
2277                               <0x0 0x03D00000 0x0 0x300000>;
2278                         reg-names = "west", "east", "north", "south";
2279                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2280                         gpio-ranges = <&tlmm 0 0 176>;
2281                         gpio-controller;
2282                         #gpio-cells = <2>;
2283                         interrupt-controller;
2284                         #interrupt-cells = <2>;
2285                         wakeup-parent = <&pdc>;
2286
2287                         qup_i2c0_default: qup-i2c0-default {
2288                                 mux {
2289                                         pins = "gpio0", "gpio1";
2290                                         function = "qup0";
2291                                 };
2292
2293                                 config {
2294                                         pins = "gpio0", "gpio1";
2295                                         drive-strength = <0x02>;
2296                                         bias-disable;
2297                                 };
2298                         };
2299
2300                         qup_spi0_default: qup-spi0-default {
2301                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2302                                 function = "qup0";
2303                                 drive-strength = <6>;
2304                                 bias-disable;
2305                         };
2306
2307                         qup_i2c1_default: qup-i2c1-default {
2308                                 mux {
2309                                         pins = "gpio114", "gpio115";
2310                                         function = "qup1";
2311                                 };
2312
2313                                 config {
2314                                         pins = "gpio114", "gpio115";
2315                                         drive-strength = <0x02>;
2316                                         bias-disable;
2317                                 };
2318                         };
2319
2320                         qup_spi1_default: qup-spi1-default {
2321                                 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2322                                 function = "qup1";
2323                                 drive-strength = <6>;
2324                                 bias-disable;
2325                         };
2326
2327                         qup_i2c2_default: qup-i2c2-default {
2328                                 mux {
2329                                         pins = "gpio126", "gpio127";
2330                                         function = "qup2";
2331                                 };
2332
2333                                 config {
2334                                         pins = "gpio126", "gpio127";
2335                                         drive-strength = <0x02>;
2336                                         bias-disable;
2337                                 };
2338                         };
2339
2340                         qup_spi2_default: qup-spi2-default {
2341                                 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2342                                 function = "qup2";
2343                                 drive-strength = <6>;
2344                                 bias-disable;
2345                         };
2346
2347                         qup_i2c3_default: qup-i2c3-default {
2348                                 mux {
2349                                         pins = "gpio144", "gpio145";
2350                                         function = "qup3";
2351                                 };
2352
2353                                 config {
2354                                         pins = "gpio144", "gpio145";
2355                                         drive-strength = <0x02>;
2356                                         bias-disable;
2357                                 };
2358                         };
2359
2360                         qup_spi3_default: qup-spi3-default {
2361                                 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2362                                 function = "qup3";
2363                                 drive-strength = <6>;
2364                                 bias-disable;
2365                         };
2366
2367                         qup_i2c4_default: qup-i2c4-default {
2368                                 mux {
2369                                         pins = "gpio51", "gpio52";
2370                                         function = "qup4";
2371                                 };
2372
2373                                 config {
2374                                         pins = "gpio51", "gpio52";
2375                                         drive-strength = <0x02>;
2376                                         bias-disable;
2377                                 };
2378                         };
2379
2380                         qup_spi4_default: qup-spi4-default {
2381                                 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2382                                 function = "qup4";
2383                                 drive-strength = <6>;
2384                                 bias-disable;
2385                         };
2386
2387                         qup_i2c5_default: qup-i2c5-default {
2388                                 mux {
2389                                         pins = "gpio121", "gpio122";
2390                                         function = "qup5";
2391                                 };
2392
2393                                 config {
2394                                         pins = "gpio121", "gpio122";
2395                                         drive-strength = <0x02>;
2396                                         bias-disable;
2397                                 };
2398                         };
2399
2400                         qup_spi5_default: qup-spi5-default {
2401                                 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2402                                 function = "qup5";
2403                                 drive-strength = <6>;
2404                                 bias-disable;
2405                         };
2406
2407                         qup_i2c6_default: qup-i2c6-default {
2408                                 mux {
2409                                         pins = "gpio6", "gpio7";
2410                                         function = "qup6";
2411                                 };
2412
2413                                 config {
2414                                         pins = "gpio6", "gpio7";
2415                                         drive-strength = <0x02>;
2416                                         bias-disable;
2417                                 };
2418                         };
2419
2420                         qup_spi6_default: qup-spi6_default {
2421                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2422                                 function = "qup6";
2423                                 drive-strength = <6>;
2424                                 bias-disable;
2425                         };
2426
2427                         qup_i2c7_default: qup-i2c7-default {
2428                                 mux {
2429                                         pins = "gpio98", "gpio99";
2430                                         function = "qup7";
2431                                 };
2432
2433                                 config {
2434                                         pins = "gpio98", "gpio99";
2435                                         drive-strength = <0x02>;
2436                                         bias-disable;
2437                                 };
2438                         };
2439
2440                         qup_spi7_default: qup-spi7_default {
2441                                 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2442                                 function = "qup7";
2443                                 drive-strength = <6>;
2444                                 bias-disable;
2445                         };
2446
2447                         qup_i2c8_default: qup-i2c8-default {
2448                                 mux {
2449                                         pins = "gpio88", "gpio89";
2450                                         function = "qup8";
2451                                 };
2452
2453                                 config {
2454                                         pins = "gpio88", "gpio89";
2455                                         drive-strength = <0x02>;
2456                                         bias-disable;
2457                                 };
2458                         };
2459
2460                         qup_spi8_default: qup-spi8-default {
2461                                 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2462                                 function = "qup8";
2463                                 drive-strength = <6>;
2464                                 bias-disable;
2465                         };
2466
2467                         qup_i2c9_default: qup-i2c9-default {
2468                                 mux {
2469                                         pins = "gpio39", "gpio40";
2470                                         function = "qup9";
2471                                 };
2472
2473                                 config {
2474                                         pins = "gpio39", "gpio40";
2475                                         drive-strength = <0x02>;
2476                                         bias-disable;
2477                                 };
2478                         };
2479
2480                         qup_spi9_default: qup-spi9-default {
2481                                 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2482                                 function = "qup9";
2483                                 drive-strength = <6>;
2484                                 bias-disable;
2485                         };
2486
2487                         qup_i2c10_default: qup-i2c10-default {
2488                                 mux {
2489                                         pins = "gpio9", "gpio10";
2490                                         function = "qup10";
2491                                 };
2492
2493                                 config {
2494                                         pins = "gpio9", "gpio10";
2495                                         drive-strength = <0x02>;
2496                                         bias-disable;
2497                                 };
2498                         };
2499
2500                         qup_spi10_default: qup-spi10-default {
2501                                 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2502                                 function = "qup10";
2503                                 drive-strength = <6>;
2504                                 bias-disable;
2505                         };
2506
2507                         qup_i2c11_default: qup-i2c11-default {
2508                                 mux {
2509                                         pins = "gpio94", "gpio95";
2510                                         function = "qup11";
2511                                 };
2512
2513                                 config {
2514                                         pins = "gpio94", "gpio95";
2515                                         drive-strength = <0x02>;
2516                                         bias-disable;
2517                                 };
2518                         };
2519
2520                         qup_spi11_default: qup-spi11-default {
2521                                 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2522                                 function = "qup11";
2523                                 drive-strength = <6>;
2524                                 bias-disable;
2525                         };
2526
2527                         qup_i2c12_default: qup-i2c12-default {
2528                                 mux {
2529                                         pins = "gpio83", "gpio84";
2530                                         function = "qup12";
2531                                 };
2532
2533                                 config {
2534                                         pins = "gpio83", "gpio84";
2535                                         drive-strength = <0x02>;
2536                                         bias-disable;
2537                                 };
2538                         };
2539
2540                         qup_spi12_default: qup-spi12-default {
2541                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2542                                 function = "qup12";
2543                                 drive-strength = <6>;
2544                                 bias-disable;
2545                         };
2546
2547                         qup_i2c13_default: qup-i2c13-default {
2548                                 mux {
2549                                         pins = "gpio43", "gpio44";
2550                                         function = "qup13";
2551                                 };
2552
2553                                 config {
2554                                         pins = "gpio43", "gpio44";
2555                                         drive-strength = <0x02>;
2556                                         bias-disable;
2557                                 };
2558                         };
2559
2560                         qup_spi13_default: qup-spi13-default {
2561                                 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2562                                 function = "qup13";
2563                                 drive-strength = <6>;
2564                                 bias-disable;
2565                         };
2566
2567                         qup_i2c14_default: qup-i2c14-default {
2568                                 mux {
2569                                         pins = "gpio47", "gpio48";
2570                                         function = "qup14";
2571                                 };
2572
2573                                 config {
2574                                         pins = "gpio47", "gpio48";
2575                                         drive-strength = <0x02>;
2576                                         bias-disable;
2577                                 };
2578                         };
2579
2580                         qup_spi14_default: qup-spi14-default {
2581                                 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2582                                 function = "qup14";
2583                                 drive-strength = <6>;
2584                                 bias-disable;
2585                         };
2586
2587                         qup_i2c15_default: qup-i2c15-default {
2588                                 mux {
2589                                         pins = "gpio27", "gpio28";
2590                                         function = "qup15";
2591                                 };
2592
2593                                 config {
2594                                         pins = "gpio27", "gpio28";
2595                                         drive-strength = <0x02>;
2596                                         bias-disable;
2597                                 };
2598                         };
2599
2600                         qup_spi15_default: qup-spi15-default {
2601                                 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2602                                 function = "qup15";
2603                                 drive-strength = <6>;
2604                                 bias-disable;
2605                         };
2606
2607                         qup_i2c16_default: qup-i2c16-default {
2608                                 mux {
2609                                         pins = "gpio86", "gpio85";
2610                                         function = "qup16";
2611                                 };
2612
2613                                 config {
2614                                         pins = "gpio86", "gpio85";
2615                                         drive-strength = <0x02>;
2616                                         bias-disable;
2617                                 };
2618                         };
2619
2620                         qup_spi16_default: qup-spi16-default {
2621                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2622                                 function = "qup16";
2623                                 drive-strength = <6>;
2624                                 bias-disable;
2625                         };
2626
2627                         qup_i2c17_default: qup-i2c17-default {
2628                                 mux {
2629                                         pins = "gpio55", "gpio56";
2630                                         function = "qup17";
2631                                 };
2632
2633                                 config {
2634                                         pins = "gpio55", "gpio56";
2635                                         drive-strength = <0x02>;
2636                                         bias-disable;
2637                                 };
2638                         };
2639
2640                         qup_spi17_default: qup-spi17-default {
2641                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2642                                 function = "qup17";
2643                                 drive-strength = <6>;
2644                                 bias-disable;
2645                         };
2646
2647                         qup_i2c18_default: qup-i2c18-default {
2648                                 mux {
2649                                         pins = "gpio23", "gpio24";
2650                                         function = "qup18";
2651                                 };
2652
2653                                 config {
2654                                         pins = "gpio23", "gpio24";
2655                                         drive-strength = <0x02>;
2656                                         bias-disable;
2657                                 };
2658                         };
2659
2660                         qup_spi18_default: qup-spi18-default {
2661                                 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2662                                 function = "qup18";
2663                                 drive-strength = <6>;
2664                                 bias-disable;
2665                         };
2666
2667                         qup_i2c19_default: qup-i2c19-default {
2668                                 mux {
2669                                         pins = "gpio57", "gpio58";
2670                                         function = "qup19";
2671                                 };
2672
2673                                 config {
2674                                         pins = "gpio57", "gpio58";
2675                                         drive-strength = <0x02>;
2676                                         bias-disable;
2677                                 };
2678                         };
2679
2680                         qup_spi19_default: qup-spi19-default {
2681                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2682                                 function = "qup19";
2683                                 drive-strength = <6>;
2684                                 bias-disable;
2685                         };
2686
2687                         pcie0_default_state: pcie0-default {
2688                                 perst {
2689                                         pins = "gpio35";
2690                                         function = "gpio";
2691                                         drive-strength = <2>;
2692                                         bias-pull-down;
2693                                 };
2694
2695                                 clkreq {
2696                                         pins = "gpio36";
2697                                         function = "pci_e0";
2698                                         drive-strength = <2>;
2699                                         bias-pull-up;
2700                                 };
2701
2702                                 wake {
2703                                         pins = "gpio37";
2704                                         function = "gpio";
2705                                         drive-strength = <2>;
2706                                         bias-pull-up;
2707                                 };
2708                         };
2709
2710                         pcie1_default_state: pcie1-default {
2711                                 perst {
2712                                         pins = "gpio102";
2713                                         function = "gpio";
2714                                         drive-strength = <2>;
2715                                         bias-pull-down;
2716                                 };
2717
2718                                 clkreq {
2719                                         pins = "gpio103";
2720                                         function = "pci_e1";
2721                                         drive-strength = <2>;
2722                                         bias-pull-up;
2723                                 };
2724
2725                                 wake {
2726                                         pins = "gpio104";
2727                                         function = "gpio";
2728                                         drive-strength = <2>;
2729                                         bias-pull-up;
2730                                 };
2731                         };
2732                 };
2733
2734                 remoteproc_mpss: remoteproc@4080000 {
2735                         compatible = "qcom,sm8150-mpss-pas";
2736                         reg = <0x0 0x04080000 0x0 0x4040>;
2737
2738                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2739                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2740                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2741                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2742                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2743                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2744                         interrupt-names = "wdog", "fatal", "ready", "handover",
2745                                           "stop-ack", "shutdown-ack";
2746
2747                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2748                         clock-names = "xo";
2749
2750                         power-domains = <&rpmhpd 7>,
2751                                         <&rpmhpd 0>;
2752                         power-domain-names = "cx", "mss";
2753
2754                         memory-region = <&mpss_mem>;
2755
2756                         qcom,qmp = <&aoss_qmp>;
2757
2758                         qcom,smem-states = <&modem_smp2p_out 0>;
2759                         qcom,smem-state-names = "stop";
2760
2761                         status = "disabled";
2762
2763                         glink-edge {
2764                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2765                                 label = "modem";
2766                                 qcom,remote-pid = <1>;
2767                                 mboxes = <&apss_shared 12>;
2768                         };
2769                 };
2770
2771                 stm@6002000 {
2772                         compatible = "arm,coresight-stm", "arm,primecell";
2773                         reg = <0 0x06002000 0 0x1000>,
2774                               <0 0x16280000 0 0x180000>;
2775                         reg-names = "stm-base", "stm-stimulus-base";
2776
2777                         clocks = <&aoss_qmp>;
2778                         clock-names = "apb_pclk";
2779
2780                         out-ports {
2781                                 port {
2782                                         stm_out: endpoint {
2783                                                 remote-endpoint = <&funnel0_in7>;
2784                                         };
2785                                 };
2786                         };
2787                 };
2788
2789                 funnel@6041000 {
2790                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2791                         reg = <0 0x06041000 0 0x1000>;
2792
2793                         clocks = <&aoss_qmp>;
2794                         clock-names = "apb_pclk";
2795
2796                         out-ports {
2797                                 port {
2798                                         funnel0_out: endpoint {
2799                                                 remote-endpoint = <&merge_funnel_in0>;
2800                                         };
2801                                 };
2802                         };
2803
2804                         in-ports {
2805                                 #address-cells = <1>;
2806                                 #size-cells = <0>;
2807
2808                                 port@7 {
2809                                         reg = <7>;
2810                                         funnel0_in7: endpoint {
2811                                                 remote-endpoint = <&stm_out>;
2812                                         };
2813                                 };
2814                         };
2815                 };
2816
2817                 funnel@6042000 {
2818                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2819                         reg = <0 0x06042000 0 0x1000>;
2820
2821                         clocks = <&aoss_qmp>;
2822                         clock-names = "apb_pclk";
2823
2824                         out-ports {
2825                                 port {
2826                                         funnel1_out: endpoint {
2827                                                 remote-endpoint = <&merge_funnel_in1>;
2828                                         };
2829                                 };
2830                         };
2831
2832                         in-ports {
2833                                 #address-cells = <1>;
2834                                 #size-cells = <0>;
2835
2836                                 port@4 {
2837                                         reg = <4>;
2838                                         funnel1_in4: endpoint {
2839                                                 remote-endpoint = <&swao_replicator_out>;
2840                                         };
2841                                 };
2842                         };
2843                 };
2844
2845                 funnel@6043000 {
2846                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2847                         reg = <0 0x06043000 0 0x1000>;
2848
2849                         clocks = <&aoss_qmp>;
2850                         clock-names = "apb_pclk";
2851
2852                         out-ports {
2853                                 port {
2854                                         funnel2_out: endpoint {
2855                                                 remote-endpoint = <&merge_funnel_in2>;
2856                                         };
2857                                 };
2858                         };
2859
2860                         in-ports {
2861                                 #address-cells = <1>;
2862                                 #size-cells = <0>;
2863
2864                                 port@2 {
2865                                         reg = <2>;
2866                                         funnel2_in2: endpoint {
2867                                                 remote-endpoint = <&apss_merge_funnel_out>;
2868                                         };
2869                                 };
2870                         };
2871                 };
2872
2873                 funnel@6045000 {
2874                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2875                         reg = <0 0x06045000 0 0x1000>;
2876
2877                         clocks = <&aoss_qmp>;
2878                         clock-names = "apb_pclk";
2879
2880                         out-ports {
2881                                 port {
2882                                         merge_funnel_out: endpoint {
2883                                                 remote-endpoint = <&etf_in>;
2884                                         };
2885                                 };
2886                         };
2887
2888                         in-ports {
2889                                 #address-cells = <1>;
2890                                 #size-cells = <0>;
2891
2892                                 port@0 {
2893                                         reg = <0>;
2894                                         merge_funnel_in0: endpoint {
2895                                                 remote-endpoint = <&funnel0_out>;
2896                                         };
2897                                 };
2898
2899                                 port@1 {
2900                                         reg = <1>;
2901                                         merge_funnel_in1: endpoint {
2902                                                 remote-endpoint = <&funnel1_out>;
2903                                         };
2904                                 };
2905
2906                                 port@2 {
2907                                         reg = <2>;
2908                                         merge_funnel_in2: endpoint {
2909                                                 remote-endpoint = <&funnel2_out>;
2910                                         };
2911                                 };
2912                         };
2913                 };
2914
2915                 replicator@6046000 {
2916                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2917                         reg = <0 0x06046000 0 0x1000>;
2918
2919                         clocks = <&aoss_qmp>;
2920                         clock-names = "apb_pclk";
2921
2922                         out-ports {
2923                                 #address-cells = <1>;
2924                                 #size-cells = <0>;
2925
2926                                 port@0 {
2927                                         reg = <0>;
2928                                         replicator_out0: endpoint {
2929                                                 remote-endpoint = <&etr_in>;
2930                                         };
2931                                 };
2932
2933                                 port@1 {
2934                                         reg = <1>;
2935                                         replicator_out1: endpoint {
2936                                                 remote-endpoint = <&replicator1_in>;
2937                                         };
2938                                 };
2939                         };
2940
2941                         in-ports {
2942                                 port {
2943                                         replicator_in0: endpoint {
2944                                                 remote-endpoint = <&etf_out>;
2945                                         };
2946                                 };
2947                         };
2948                 };
2949
2950                 etf@6047000 {
2951                         compatible = "arm,coresight-tmc", "arm,primecell";
2952                         reg = <0 0x06047000 0 0x1000>;
2953
2954                         clocks = <&aoss_qmp>;
2955                         clock-names = "apb_pclk";
2956
2957                         out-ports {
2958                                 port {
2959                                         etf_out: endpoint {
2960                                                 remote-endpoint = <&replicator_in0>;
2961                                         };
2962                                 };
2963                         };
2964
2965                         in-ports {
2966                                 port {
2967                                         etf_in: endpoint {
2968                                                 remote-endpoint = <&merge_funnel_out>;
2969                                         };
2970                                 };
2971                         };
2972                 };
2973
2974                 etr@6048000 {
2975                         compatible = "arm,coresight-tmc", "arm,primecell";
2976                         reg = <0 0x06048000 0 0x1000>;
2977                         iommus = <&apps_smmu 0x05e0 0x0>;
2978
2979                         clocks = <&aoss_qmp>;
2980                         clock-names = "apb_pclk";
2981                         arm,scatter-gather;
2982
2983                         in-ports {
2984                                 port {
2985                                         etr_in: endpoint {
2986                                                 remote-endpoint = <&replicator_out0>;
2987                                         };
2988                                 };
2989                         };
2990                 };
2991
2992                 replicator@604a000 {
2993                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2994                         reg = <0 0x0604a000 0 0x1000>;
2995
2996                         clocks = <&aoss_qmp>;
2997                         clock-names = "apb_pclk";
2998
2999                         out-ports {
3000                                 #address-cells = <1>;
3001                                 #size-cells = <0>;
3002
3003                                 port@1 {
3004                                         reg = <1>;
3005                                         replicator1_out: endpoint {
3006                                                 remote-endpoint = <&swao_funnel_in>;
3007                                         };
3008                                 };
3009                         };
3010
3011                         in-ports {
3012                                 #address-cells = <1>;
3013                                 #size-cells = <0>;
3014
3015                                 port@1 {
3016                                         reg = <1>;
3017                                         replicator1_in: endpoint {
3018                                                 remote-endpoint = <&replicator_out1>;
3019                                         };
3020                                 };
3021                         };
3022                 };
3023
3024                 funnel@6b08000 {
3025                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3026                         reg = <0 0x06b08000 0 0x1000>;
3027
3028                         clocks = <&aoss_qmp>;
3029                         clock-names = "apb_pclk";
3030
3031                         out-ports {
3032                                 port {
3033                                         swao_funnel_out: endpoint {
3034                                                 remote-endpoint = <&swao_etf_in>;
3035                                         };
3036                                 };
3037                         };
3038
3039                         in-ports {
3040                                 #address-cells = <1>;
3041                                 #size-cells = <0>;
3042
3043                                 port@6 {
3044                                         reg = <6>;
3045                                         swao_funnel_in: endpoint {
3046                                                 remote-endpoint = <&replicator1_out>;
3047                                         };
3048                                 };
3049                         };
3050                 };
3051
3052                 etf@6b09000 {
3053                         compatible = "arm,coresight-tmc", "arm,primecell";
3054                         reg = <0 0x06b09000 0 0x1000>;
3055
3056                         clocks = <&aoss_qmp>;
3057                         clock-names = "apb_pclk";
3058
3059                         out-ports {
3060                                 port {
3061                                         swao_etf_out: endpoint {
3062                                                 remote-endpoint = <&swao_replicator_in>;
3063                                         };
3064                                 };
3065                         };
3066
3067                         in-ports {
3068                                 port {
3069                                         swao_etf_in: endpoint {
3070                                                 remote-endpoint = <&swao_funnel_out>;
3071                                         };
3072                                 };
3073                         };
3074                 };
3075
3076                 replicator@6b0a000 {
3077                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3078                         reg = <0 0x06b0a000 0 0x1000>;
3079
3080                         clocks = <&aoss_qmp>;
3081                         clock-names = "apb_pclk";
3082                         qcom,replicator-loses-context;
3083
3084                         out-ports {
3085                                 port {
3086                                         swao_replicator_out: endpoint {
3087                                                 remote-endpoint = <&funnel1_in4>;
3088                                         };
3089                                 };
3090                         };
3091
3092                         in-ports {
3093                                 port {
3094                                         swao_replicator_in: endpoint {
3095                                                 remote-endpoint = <&swao_etf_out>;
3096                                         };
3097                                 };
3098                         };
3099                 };
3100
3101                 etm@7040000 {
3102                         compatible = "arm,coresight-etm4x", "arm,primecell";
3103                         reg = <0 0x07040000 0 0x1000>;
3104
3105                         cpu = <&CPU0>;
3106
3107                         clocks = <&aoss_qmp>;
3108                         clock-names = "apb_pclk";
3109                         arm,coresight-loses-context-with-cpu;
3110                         qcom,skip-power-up;
3111
3112                         out-ports {
3113                                 port {
3114                                         etm0_out: endpoint {
3115                                                 remote-endpoint = <&apss_funnel_in0>;
3116                                         };
3117                                 };
3118                         };
3119                 };
3120
3121                 etm@7140000 {
3122                         compatible = "arm,coresight-etm4x", "arm,primecell";
3123                         reg = <0 0x07140000 0 0x1000>;
3124
3125                         cpu = <&CPU1>;
3126
3127                         clocks = <&aoss_qmp>;
3128                         clock-names = "apb_pclk";
3129                         arm,coresight-loses-context-with-cpu;
3130                         qcom,skip-power-up;
3131
3132                         out-ports {
3133                                 port {
3134                                         etm1_out: endpoint {
3135                                                 remote-endpoint = <&apss_funnel_in1>;
3136                                         };
3137                                 };
3138                         };
3139                 };
3140
3141                 etm@7240000 {
3142                         compatible = "arm,coresight-etm4x", "arm,primecell";
3143                         reg = <0 0x07240000 0 0x1000>;
3144
3145                         cpu = <&CPU2>;
3146
3147                         clocks = <&aoss_qmp>;
3148                         clock-names = "apb_pclk";
3149                         arm,coresight-loses-context-with-cpu;
3150                         qcom,skip-power-up;
3151
3152                         out-ports {
3153                                 port {
3154                                         etm2_out: endpoint {
3155                                                 remote-endpoint = <&apss_funnel_in2>;
3156                                         };
3157                                 };
3158                         };
3159                 };
3160
3161                 etm@7340000 {
3162                         compatible = "arm,coresight-etm4x", "arm,primecell";
3163                         reg = <0 0x07340000 0 0x1000>;
3164
3165                         cpu = <&CPU3>;
3166
3167                         clocks = <&aoss_qmp>;
3168                         clock-names = "apb_pclk";
3169                         arm,coresight-loses-context-with-cpu;
3170                         qcom,skip-power-up;
3171
3172                         out-ports {
3173                                 port {
3174                                         etm3_out: endpoint {
3175                                                 remote-endpoint = <&apss_funnel_in3>;
3176                                         };
3177                                 };
3178                         };
3179                 };
3180
3181                 etm@7440000 {
3182                         compatible = "arm,coresight-etm4x", "arm,primecell";
3183                         reg = <0 0x07440000 0 0x1000>;
3184
3185                         cpu = <&CPU4>;
3186
3187                         clocks = <&aoss_qmp>;
3188                         clock-names = "apb_pclk";
3189                         arm,coresight-loses-context-with-cpu;
3190                         qcom,skip-power-up;
3191
3192                         out-ports {
3193                                 port {
3194                                         etm4_out: endpoint {
3195                                                 remote-endpoint = <&apss_funnel_in4>;
3196                                         };
3197                                 };
3198                         };
3199                 };
3200
3201                 etm@7540000 {
3202                         compatible = "arm,coresight-etm4x", "arm,primecell";
3203                         reg = <0 0x07540000 0 0x1000>;
3204
3205                         cpu = <&CPU5>;
3206
3207                         clocks = <&aoss_qmp>;
3208                         clock-names = "apb_pclk";
3209                         arm,coresight-loses-context-with-cpu;
3210                         qcom,skip-power-up;
3211
3212                         out-ports {
3213                                 port {
3214                                         etm5_out: endpoint {
3215                                                 remote-endpoint = <&apss_funnel_in5>;
3216                                         };
3217                                 };
3218                         };
3219                 };
3220
3221                 etm@7640000 {
3222                         compatible = "arm,coresight-etm4x", "arm,primecell";
3223                         reg = <0 0x07640000 0 0x1000>;
3224
3225                         cpu = <&CPU6>;
3226
3227                         clocks = <&aoss_qmp>;
3228                         clock-names = "apb_pclk";
3229                         arm,coresight-loses-context-with-cpu;
3230                         qcom,skip-power-up;
3231
3232                         out-ports {
3233                                 port {
3234                                         etm6_out: endpoint {
3235                                                 remote-endpoint = <&apss_funnel_in6>;
3236                                         };
3237                                 };
3238                         };
3239                 };
3240
3241                 etm@7740000 {
3242                         compatible = "arm,coresight-etm4x", "arm,primecell";
3243                         reg = <0 0x07740000 0 0x1000>;
3244
3245                         cpu = <&CPU7>;
3246
3247                         clocks = <&aoss_qmp>;
3248                         clock-names = "apb_pclk";
3249                         arm,coresight-loses-context-with-cpu;
3250                         qcom,skip-power-up;
3251
3252                         out-ports {
3253                                 port {
3254                                         etm7_out: endpoint {
3255                                                 remote-endpoint = <&apss_funnel_in7>;
3256                                         };
3257                                 };
3258                         };
3259                 };
3260
3261                 funnel@7800000 { /* APSS Funnel */
3262                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3263                         reg = <0 0x07800000 0 0x1000>;
3264
3265                         clocks = <&aoss_qmp>;
3266                         clock-names = "apb_pclk";
3267
3268                         out-ports {
3269                                 port {
3270                                         apss_funnel_out: endpoint {
3271                                                 remote-endpoint = <&apss_merge_funnel_in>;
3272                                         };
3273                                 };
3274                         };
3275
3276                         in-ports {
3277                                 #address-cells = <1>;
3278                                 #size-cells = <0>;
3279
3280                                 port@0 {
3281                                         reg = <0>;
3282                                         apss_funnel_in0: endpoint {
3283                                                 remote-endpoint = <&etm0_out>;
3284                                         };
3285                                 };
3286
3287                                 port@1 {
3288                                         reg = <1>;
3289                                         apss_funnel_in1: endpoint {
3290                                                 remote-endpoint = <&etm1_out>;
3291                                         };
3292                                 };
3293
3294                                 port@2 {
3295                                         reg = <2>;
3296                                         apss_funnel_in2: endpoint {
3297                                                 remote-endpoint = <&etm2_out>;
3298                                         };
3299                                 };
3300
3301                                 port@3 {
3302                                         reg = <3>;
3303                                         apss_funnel_in3: endpoint {
3304                                                 remote-endpoint = <&etm3_out>;
3305                                         };
3306                                 };
3307
3308                                 port@4 {
3309                                         reg = <4>;
3310                                         apss_funnel_in4: endpoint {
3311                                                 remote-endpoint = <&etm4_out>;
3312                                         };
3313                                 };
3314
3315                                 port@5 {
3316                                         reg = <5>;
3317                                         apss_funnel_in5: endpoint {
3318                                                 remote-endpoint = <&etm5_out>;
3319                                         };
3320                                 };
3321
3322                                 port@6 {
3323                                         reg = <6>;
3324                                         apss_funnel_in6: endpoint {
3325                                                 remote-endpoint = <&etm6_out>;
3326                                         };
3327                                 };
3328
3329                                 port@7 {
3330                                         reg = <7>;
3331                                         apss_funnel_in7: endpoint {
3332                                                 remote-endpoint = <&etm7_out>;
3333                                         };
3334                                 };
3335                         };
3336                 };
3337
3338                 funnel@7810000 {
3339                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3340                         reg = <0 0x07810000 0 0x1000>;
3341
3342                         clocks = <&aoss_qmp>;
3343                         clock-names = "apb_pclk";
3344
3345                         out-ports {
3346                                 port {
3347                                         apss_merge_funnel_out: endpoint {
3348                                                 remote-endpoint = <&funnel2_in2>;
3349                                         };
3350                                 };
3351                         };
3352
3353                         in-ports {
3354                                 port {
3355                                         apss_merge_funnel_in: endpoint {
3356                                                 remote-endpoint = <&apss_funnel_out>;
3357                                         };
3358                                 };
3359                         };
3360                 };
3361
3362                 remoteproc_cdsp: remoteproc@8300000 {
3363                         compatible = "qcom,sm8150-cdsp-pas";
3364                         reg = <0x0 0x08300000 0x0 0x4040>;
3365
3366                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3367                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3368                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3369                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3370                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3371                         interrupt-names = "wdog", "fatal", "ready",
3372                                           "handover", "stop-ack";
3373
3374                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3375                         clock-names = "xo";
3376
3377                         power-domains = <&rpmhpd 7>;
3378
3379                         memory-region = <&cdsp_mem>;
3380
3381                         qcom,qmp = <&aoss_qmp>;
3382
3383                         qcom,smem-states = <&cdsp_smp2p_out 0>;
3384                         qcom,smem-state-names = "stop";
3385
3386                         status = "disabled";
3387
3388                         glink-edge {
3389                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3390                                 label = "cdsp";
3391                                 qcom,remote-pid = <5>;
3392                                 mboxes = <&apss_shared 4>;
3393
3394                                 fastrpc {
3395                                         compatible = "qcom,fastrpc";
3396                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3397                                         label = "cdsp";
3398                                         qcom,non-secure-domain;
3399                                         #address-cells = <1>;
3400                                         #size-cells = <0>;
3401
3402                                         compute-cb@1 {
3403                                                 compatible = "qcom,fastrpc-compute-cb";
3404                                                 reg = <1>;
3405                                                 iommus = <&apps_smmu 0x1001 0x0460>;
3406                                         };
3407
3408                                         compute-cb@2 {
3409                                                 compatible = "qcom,fastrpc-compute-cb";
3410                                                 reg = <2>;
3411                                                 iommus = <&apps_smmu 0x1002 0x0460>;
3412                                         };
3413
3414                                         compute-cb@3 {
3415                                                 compatible = "qcom,fastrpc-compute-cb";
3416                                                 reg = <3>;
3417                                                 iommus = <&apps_smmu 0x1003 0x0460>;
3418                                         };
3419
3420                                         compute-cb@4 {
3421                                                 compatible = "qcom,fastrpc-compute-cb";
3422                                                 reg = <4>;
3423                                                 iommus = <&apps_smmu 0x1004 0x0460>;
3424                                         };
3425
3426                                         compute-cb@5 {
3427                                                 compatible = "qcom,fastrpc-compute-cb";
3428                                                 reg = <5>;
3429                                                 iommus = <&apps_smmu 0x1005 0x0460>;
3430                                         };
3431
3432                                         compute-cb@6 {
3433                                                 compatible = "qcom,fastrpc-compute-cb";
3434                                                 reg = <6>;
3435                                                 iommus = <&apps_smmu 0x1006 0x0460>;
3436                                         };
3437
3438                                         compute-cb@7 {
3439                                                 compatible = "qcom,fastrpc-compute-cb";
3440                                                 reg = <7>;
3441                                                 iommus = <&apps_smmu 0x1007 0x0460>;
3442                                         };
3443
3444                                         compute-cb@8 {
3445                                                 compatible = "qcom,fastrpc-compute-cb";
3446                                                 reg = <8>;
3447                                                 iommus = <&apps_smmu 0x1008 0x0460>;
3448                                         };
3449
3450                                         /* note: secure cb9 in downstream */
3451                                 };
3452                         };
3453                 };
3454
3455                 usb_1_hsphy: phy@88e2000 {
3456                         compatible = "qcom,sm8150-usb-hs-phy",
3457                                      "qcom,usb-snps-hs-7nm-phy";
3458                         reg = <0 0x088e2000 0 0x400>;
3459                         status = "disabled";
3460                         #phy-cells = <0>;
3461
3462                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3463                         clock-names = "ref";
3464
3465                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3466                 };
3467
3468                 usb_2_hsphy: phy@88e3000 {
3469                         compatible = "qcom,sm8150-usb-hs-phy",
3470                                      "qcom,usb-snps-hs-7nm-phy";
3471                         reg = <0 0x088e3000 0 0x400>;
3472                         status = "disabled";
3473                         #phy-cells = <0>;
3474
3475                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3476                         clock-names = "ref";
3477
3478                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3479                 };
3480
3481                 usb_1_qmpphy: phy@88e9000 {
3482                         compatible = "qcom,sm8150-qmp-usb3-phy";
3483                         reg = <0 0x088e9000 0 0x18c>,
3484                               <0 0x088e8000 0 0x10>;
3485                         status = "disabled";
3486                         #address-cells = <2>;
3487                         #size-cells = <2>;
3488                         ranges;
3489
3490                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3491                                  <&rpmhcc RPMH_CXO_CLK>,
3492                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3493                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3494                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3495
3496                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3497                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3498                         reset-names = "phy", "common";
3499
3500                         usb_1_ssphy: phy@88e9200 {
3501                                 reg = <0 0x088e9200 0 0x200>,
3502                                       <0 0x088e9400 0 0x200>,
3503                                       <0 0x088e9c00 0 0x218>,
3504                                       <0 0x088e9600 0 0x200>,
3505                                       <0 0x088e9800 0 0x200>,
3506                                       <0 0x088e9a00 0 0x100>;
3507                                 #clock-cells = <0>;
3508                                 #phy-cells = <0>;
3509                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3510                                 clock-names = "pipe0";
3511                                 clock-output-names = "usb3_phy_pipe_clk_src";
3512                         };
3513                 };
3514
3515                 usb_2_qmpphy: phy@88eb000 {
3516                         compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3517                         reg = <0 0x088eb000 0 0x200>;
3518                         status = "disabled";
3519                         #address-cells = <2>;
3520                         #size-cells = <2>;
3521                         ranges;
3522
3523                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3524                                  <&rpmhcc RPMH_CXO_CLK>,
3525                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3526                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3527                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3528
3529                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3530                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3531                         reset-names = "phy", "common";
3532
3533                         usb_2_ssphy: phy@88eb200 {
3534                                 reg = <0 0x088eb200 0 0x200>,
3535                                       <0 0x088eb400 0 0x200>,
3536                                       <0 0x088eb800 0 0x800>,
3537                                       <0 0x088eb600 0 0x200>;
3538                                 #clock-cells = <0>;
3539                                 #phy-cells = <0>;
3540                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3541                                 clock-names = "pipe0";
3542                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3543                         };
3544                 };
3545
3546                 sdhc_2: mmc@8804000 {
3547                         compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3548                         reg = <0 0x08804000 0 0x1000>;
3549
3550                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3551                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3552                         interrupt-names = "hc_irq", "pwr_irq";
3553
3554                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3555                                  <&gcc GCC_SDCC2_APPS_CLK>,
3556                                  <&rpmhcc RPMH_CXO_CLK>;
3557                         clock-names = "iface", "core", "xo";
3558                         iommus = <&apps_smmu 0x6a0 0x0>;
3559                         qcom,dll-config = <0x0007642c>;
3560                         qcom,ddr-config = <0x80040868>;
3561                         power-domains = <&rpmhpd 0>;
3562                         operating-points-v2 = <&sdhc2_opp_table>;
3563
3564                         status = "disabled";
3565
3566                         sdhc2_opp_table: opp-table {
3567                                 compatible = "operating-points-v2";
3568
3569                                 opp-19200000 {
3570                                         opp-hz = /bits/ 64 <19200000>;
3571                                         required-opps = <&rpmhpd_opp_min_svs>;
3572                                 };
3573
3574                                 opp-50000000 {
3575                                         opp-hz = /bits/ 64 <50000000>;
3576                                         required-opps = <&rpmhpd_opp_low_svs>;
3577                                 };
3578
3579                                 opp-100000000 {
3580                                         opp-hz = /bits/ 64 <100000000>;
3581                                         required-opps = <&rpmhpd_opp_svs>;
3582                                 };
3583
3584                                 opp-202000000 {
3585                                         opp-hz = /bits/ 64 <202000000>;
3586                                         required-opps = <&rpmhpd_opp_svs_l1>;
3587                                 };
3588                         };
3589                 };
3590
3591                 dc_noc: interconnect@9160000 {
3592                         compatible = "qcom,sm8150-dc-noc";
3593                         reg = <0 0x09160000 0 0x3200>;
3594                         #interconnect-cells = <1>;
3595                         qcom,bcm-voters = <&apps_bcm_voter>;
3596                 };
3597
3598                 gem_noc: interconnect@9680000 {
3599                         compatible = "qcom,sm8150-gem-noc";
3600                         reg = <0 0x09680000 0 0x3e200>;
3601                         #interconnect-cells = <1>;
3602                         qcom,bcm-voters = <&apps_bcm_voter>;
3603                 };
3604
3605                 usb_1: usb@a6f8800 {
3606                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3607                         reg = <0 0x0a6f8800 0 0x400>;
3608                         status = "disabled";
3609                         #address-cells = <2>;
3610                         #size-cells = <2>;
3611                         ranges;
3612                         dma-ranges;
3613
3614                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3615                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3616                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3617                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3618                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3619                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3620                         clock-names = "cfg_noc",
3621                                       "core",
3622                                       "iface",
3623                                       "sleep",
3624                                       "mock_utmi",
3625                                       "xo";
3626
3627                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3628                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3629                         assigned-clock-rates = <19200000>, <200000000>;
3630
3631                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3632                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3633                                               <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3634                                               <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3635                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3636                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3637
3638                         power-domains = <&gcc USB30_PRIM_GDSC>;
3639
3640                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3641
3642                         usb_1_dwc3: usb@a600000 {
3643                                 compatible = "snps,dwc3";
3644                                 reg = <0 0x0a600000 0 0xcd00>;
3645                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3646                                 iommus = <&apps_smmu 0x140 0>;
3647                                 snps,dis_u2_susphy_quirk;
3648                                 snps,dis_enblslpm_quirk;
3649                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3650                                 phy-names = "usb2-phy", "usb3-phy";
3651                         };
3652                 };
3653
3654                 usb_2: usb@a8f8800 {
3655                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3656                         reg = <0 0x0a8f8800 0 0x400>;
3657                         status = "disabled";
3658                         #address-cells = <2>;
3659                         #size-cells = <2>;
3660                         ranges;
3661                         dma-ranges;
3662
3663                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3664                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3665                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3666                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3667                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3668                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3669                         clock-names = "cfg_noc",
3670                                       "core",
3671                                       "iface",
3672                                       "sleep",
3673                                       "mock_utmi",
3674                                       "xo";
3675
3676                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3677                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3678                         assigned-clock-rates = <19200000>, <200000000>;
3679
3680                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3681                                               <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
3682                                               <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3683                                               <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
3684                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3685                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3686
3687                         power-domains = <&gcc USB30_SEC_GDSC>;
3688
3689                         resets = <&gcc GCC_USB30_SEC_BCR>;
3690
3691                         usb_2_dwc3: usb@a800000 {
3692                                 compatible = "snps,dwc3";
3693                                 reg = <0 0x0a800000 0 0xcd00>;
3694                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3695                                 iommus = <&apps_smmu 0x160 0>;
3696                                 snps,dis_u2_susphy_quirk;
3697                                 snps,dis_enblslpm_quirk;
3698                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3699                                 phy-names = "usb2-phy", "usb3-phy";
3700                         };
3701                 };
3702
3703                 camnoc_virt: interconnect@ac00000 {
3704                         compatible = "qcom,sm8150-camnoc-virt";
3705                         reg = <0 0x0ac00000 0 0x1000>;
3706                         #interconnect-cells = <1>;
3707                         qcom,bcm-voters = <&apps_bcm_voter>;
3708                 };
3709
3710                 pdc: interrupt-controller@b220000 {
3711                         compatible = "qcom,sm8150-pdc", "qcom,pdc";
3712                         reg = <0 0x0b220000 0 0x30000>;
3713                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3714                                           <125 63 1>;
3715                         #interrupt-cells = <2>;
3716                         interrupt-parent = <&intc>;
3717                         interrupt-controller;
3718                 };
3719
3720                 aoss_qmp: power-controller@c300000 {
3721                         compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3722                         reg = <0x0 0x0c300000 0x0 0x400>;
3723                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3724                         mboxes = <&apss_shared 0>;
3725
3726                         #clock-cells = <0>;
3727                 };
3728
3729                 sram@c3f0000 {
3730                         compatible = "qcom,rpmh-stats";
3731                         reg = <0 0x0c3f0000 0 0x400>;
3732                 };
3733
3734                 tsens0: thermal-sensor@c263000 {
3735                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3736                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3737                               <0 0x0c222000 0 0x1ff>; /* SROT */
3738                         #qcom,sensors = <16>;
3739                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3740                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3741                         interrupt-names = "uplow", "critical";
3742                         #thermal-sensor-cells = <1>;
3743                 };
3744
3745                 tsens1: thermal-sensor@c265000 {
3746                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3747                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3748                               <0 0x0c223000 0 0x1ff>; /* SROT */
3749                         #qcom,sensors = <8>;
3750                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3751                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3752                         interrupt-names = "uplow", "critical";
3753                         #thermal-sensor-cells = <1>;
3754                 };
3755
3756                 spmi_bus: spmi@c440000 {
3757                         compatible = "qcom,spmi-pmic-arb";
3758                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3759                               <0x0 0x0c600000 0x0 0x2000000>,
3760                               <0x0 0x0e600000 0x0 0x0100000>,
3761                               <0x0 0x0e700000 0x0 0x00a0000>,
3762                               <0x0 0x0c40a000 0x0 0x0026000>;
3763                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3764                         interrupt-names = "periph_irq";
3765                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3766                         qcom,ee = <0>;
3767                         qcom,channel = <0>;
3768                         #address-cells = <2>;
3769                         #size-cells = <0>;
3770                         interrupt-controller;
3771                         #interrupt-cells = <4>;
3772                         cell-index = <0>;
3773                 };
3774
3775                 apps_smmu: iommu@15000000 {
3776                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
3777                         reg = <0 0x15000000 0 0x100000>;
3778                         #iommu-cells = <2>;
3779                         #global-interrupts = <1>;
3780                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3781                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3782                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3783                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3784                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3785                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3786                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3787                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3788                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3789                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3790                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3791                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3792                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3793                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3794                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3795                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3796                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3797                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3798                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3799                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3800                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3801                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3802                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3803                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3804                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3805                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3806                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3807                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3808                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3809                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3810                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3811                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3812                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3813                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3814                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3815                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3816                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3817                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3818                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3819                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3820                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3821                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3822                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3823                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3824                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3825                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3826                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3827                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3828                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3829                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3830                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3831                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3832                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3833                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3834                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3835                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3836                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3837                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3838                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3839                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3840                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3841                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3842                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3843                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3844                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3845                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3846                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3847                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3848                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3849                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3850                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3851                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3852                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3853                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3854                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3855                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3856                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3857                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3858                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3859                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3860                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
3861                 };
3862
3863                 remoteproc_adsp: remoteproc@17300000 {
3864                         compatible = "qcom,sm8150-adsp-pas";
3865                         reg = <0x0 0x17300000 0x0 0x4040>;
3866
3867                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3868                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3869                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3870                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3871                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3872                         interrupt-names = "wdog", "fatal", "ready",
3873                                           "handover", "stop-ack";
3874
3875                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3876                         clock-names = "xo";
3877
3878                         power-domains = <&rpmhpd 7>;
3879
3880                         memory-region = <&adsp_mem>;
3881
3882                         qcom,qmp = <&aoss_qmp>;
3883
3884                         qcom,smem-states = <&adsp_smp2p_out 0>;
3885                         qcom,smem-state-names = "stop";
3886
3887                         status = "disabled";
3888
3889                         glink-edge {
3890                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3891                                 label = "lpass";
3892                                 qcom,remote-pid = <2>;
3893                                 mboxes = <&apss_shared 8>;
3894
3895                                 fastrpc {
3896                                         compatible = "qcom,fastrpc";
3897                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3898                                         label = "adsp";
3899                                         qcom,non-secure-domain;
3900                                         #address-cells = <1>;
3901                                         #size-cells = <0>;
3902
3903                                         compute-cb@3 {
3904                                                 compatible = "qcom,fastrpc-compute-cb";
3905                                                 reg = <3>;
3906                                                 iommus = <&apps_smmu 0x1b23 0x0>;
3907                                         };
3908
3909                                         compute-cb@4 {
3910                                                 compatible = "qcom,fastrpc-compute-cb";
3911                                                 reg = <4>;
3912                                                 iommus = <&apps_smmu 0x1b24 0x0>;
3913                                         };
3914
3915                                         compute-cb@5 {
3916                                                 compatible = "qcom,fastrpc-compute-cb";
3917                                                 reg = <5>;
3918                                                 iommus = <&apps_smmu 0x1b25 0x0>;
3919                                         };
3920                                 };
3921                         };
3922                 };
3923
3924                 intc: interrupt-controller@17a00000 {
3925                         compatible = "arm,gic-v3";
3926                         interrupt-controller;
3927                         #interrupt-cells = <3>;
3928                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3929                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3930                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3931                 };
3932
3933                 apss_shared: mailbox@17c00000 {
3934                         compatible = "qcom,sm8150-apss-shared";
3935                         reg = <0x0 0x17c00000 0x0 0x1000>;
3936                         #mbox-cells = <1>;
3937                 };
3938
3939                 watchdog@17c10000 {
3940                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
3941                         reg = <0 0x17c10000 0 0x1000>;
3942                         clocks = <&sleep_clk>;
3943                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3944                 };
3945
3946                 timer@17c20000 {
3947                         #address-cells = <1>;
3948                         #size-cells = <1>;
3949                         ranges = <0 0 0 0x20000000>;
3950                         compatible = "arm,armv7-timer-mem";
3951                         reg = <0x0 0x17c20000 0x0 0x1000>;
3952                         clock-frequency = <19200000>;
3953
3954                         frame@17c21000{
3955                                 frame-number = <0>;
3956                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3957                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3958                                 reg = <0x17c21000 0x1000>,
3959                                       <0x17c22000 0x1000>;
3960                         };
3961
3962                         frame@17c23000 {
3963                                 frame-number = <1>;
3964                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3965                                 reg = <0x17c23000 0x1000>;
3966                                 status = "disabled";
3967                         };
3968
3969                         frame@17c25000 {
3970                                 frame-number = <2>;
3971                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3972                                 reg = <0x17c25000 0x1000>;
3973                                 status = "disabled";
3974                         };
3975
3976                         frame@17c27000 {
3977                                 frame-number = <3>;
3978                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3979                                 reg = <0x17c26000 0x1000>;
3980                                 status = "disabled";
3981                         };
3982
3983                         frame@17c29000 {
3984                                 frame-number = <4>;
3985                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3986                                 reg = <0x17c29000 0x1000>;
3987                                 status = "disabled";
3988                         };
3989
3990                         frame@17c2b000 {
3991                                 frame-number = <5>;
3992                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3993                                 reg = <0x17c2b000 0x1000>;
3994                                 status = "disabled";
3995                         };
3996
3997                         frame@17c2d000 {
3998                                 frame-number = <6>;
3999                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4000                                 reg = <0x17c2d000 0x1000>;
4001                                 status = "disabled";
4002                         };
4003                 };
4004
4005                 apps_rsc: rsc@18200000 {
4006                         label = "apps_rsc";
4007                         compatible = "qcom,rpmh-rsc";
4008                         reg = <0x0 0x18200000 0x0 0x10000>,
4009                               <0x0 0x18210000 0x0 0x10000>,
4010                               <0x0 0x18220000 0x0 0x10000>;
4011                         reg-names = "drv-0", "drv-1", "drv-2";
4012                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4013                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4014                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4015                         qcom,tcs-offset = <0xd00>;
4016                         qcom,drv-id = <2>;
4017                         qcom,tcs-config = <ACTIVE_TCS  2>,
4018                                           <SLEEP_TCS   3>,
4019                                           <WAKE_TCS    3>,
4020                                           <CONTROL_TCS 1>;
4021
4022                         rpmhcc: clock-controller {
4023                                 compatible = "qcom,sm8150-rpmh-clk";
4024                                 #clock-cells = <1>;
4025                                 clock-names = "xo";
4026                                 clocks = <&xo_board>;
4027                         };
4028
4029                         rpmhpd: power-controller {
4030                                 compatible = "qcom,sm8150-rpmhpd";
4031                                 #power-domain-cells = <1>;
4032                                 operating-points-v2 = <&rpmhpd_opp_table>;
4033
4034                                 rpmhpd_opp_table: opp-table {
4035                                         compatible = "operating-points-v2";
4036
4037                                         rpmhpd_opp_ret: opp1 {
4038                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4039                                         };
4040
4041                                         rpmhpd_opp_min_svs: opp2 {
4042                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4043                                         };
4044
4045                                         rpmhpd_opp_low_svs: opp3 {
4046                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4047                                         };
4048
4049                                         rpmhpd_opp_svs: opp4 {
4050                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4051                                         };
4052
4053                                         rpmhpd_opp_svs_l1: opp5 {
4054                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4055                                         };
4056
4057                                         rpmhpd_opp_svs_l2: opp6 {
4058                                                 opp-level = <224>;
4059                                         };
4060
4061                                         rpmhpd_opp_nom: opp7 {
4062                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4063                                         };
4064
4065                                         rpmhpd_opp_nom_l1: opp8 {
4066                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4067                                         };
4068
4069                                         rpmhpd_opp_nom_l2: opp9 {
4070                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4071                                         };
4072
4073                                         rpmhpd_opp_turbo: opp10 {
4074                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4075                                         };
4076
4077                                         rpmhpd_opp_turbo_l1: opp11 {
4078                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4079                                         };
4080                                 };
4081                         };
4082
4083                         apps_bcm_voter: bcm-voter {
4084                                 compatible = "qcom,bcm-voter";
4085                         };
4086                 };
4087
4088                 osm_l3: interconnect@18321000 {
4089                         compatible = "qcom,sm8150-osm-l3";
4090                         reg = <0 0x18321000 0 0x1400>;
4091
4092                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4093                         clock-names = "xo", "alternate";
4094
4095                         #interconnect-cells = <1>;
4096                 };
4097
4098                 cpufreq_hw: cpufreq@18323000 {
4099                         compatible = "qcom,cpufreq-hw";
4100                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4101                               <0 0x18327800 0 0x1400>;
4102                         reg-names = "freq-domain0", "freq-domain1",
4103                                     "freq-domain2";
4104
4105                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4106                         clock-names = "xo", "alternate";
4107
4108                         #freq-domain-cells = <1>;
4109                 };
4110
4111                 lmh_cluster1: lmh@18350800 {
4112                         compatible = "qcom,sm8150-lmh";
4113                         reg = <0 0x18350800 0 0x400>;
4114                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4115                         cpus = <&CPU4>;
4116                         qcom,lmh-temp-arm-millicelsius = <60000>;
4117                         qcom,lmh-temp-low-millicelsius = <84500>;
4118                         qcom,lmh-temp-high-millicelsius = <85000>;
4119                         interrupt-controller;
4120                         #interrupt-cells = <1>;
4121                 };
4122
4123                 lmh_cluster0: lmh@18358800 {
4124                         compatible = "qcom,sm8150-lmh";
4125                         reg = <0 0x18358800 0 0x400>;
4126                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4127                         cpus = <&CPU0>;
4128                         qcom,lmh-temp-arm-millicelsius = <60000>;
4129                         qcom,lmh-temp-low-millicelsius = <84500>;
4130                         qcom,lmh-temp-high-millicelsius = <85000>;
4131                         interrupt-controller;
4132                         #interrupt-cells = <1>;
4133                 };
4134
4135                 wifi: wifi@18800000 {
4136                         compatible = "qcom,wcn3990-wifi";
4137                         reg = <0 0x18800000 0 0x800000>;
4138                         reg-names = "membase";
4139                         memory-region = <&wlan_mem>;
4140                         clock-names = "cxo_ref_clk_pin", "qdss";
4141                         clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4142                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4143                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4144                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4145                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4146                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4147                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4148                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4149                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4150                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4151                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4152                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4153                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4154                         iommus = <&apps_smmu 0x0640 0x1>;
4155                         status = "disabled";
4156                 };
4157         };
4158
4159         timer {
4160                 compatible = "arm,armv8-timer";
4161                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4162                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4163                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4164                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4165         };
4166
4167         thermal-zones {
4168                 cpu0-thermal {
4169                         polling-delay-passive = <250>;
4170                         polling-delay = <1000>;
4171
4172                         thermal-sensors = <&tsens0 1>;
4173
4174                         trips {
4175                                 cpu0_alert0: trip-point0 {
4176                                         temperature = <90000>;
4177                                         hysteresis = <2000>;
4178                                         type = "passive";
4179                                 };
4180
4181                                 cpu0_alert1: trip-point1 {
4182                                         temperature = <95000>;
4183                                         hysteresis = <2000>;
4184                                         type = "passive";
4185                                 };
4186
4187                                 cpu0_crit: cpu_crit {
4188                                         temperature = <110000>;
4189                                         hysteresis = <1000>;
4190                                         type = "critical";
4191                                 };
4192                         };
4193
4194                         cooling-maps {
4195                                 map0 {
4196                                         trip = <&cpu0_alert0>;
4197                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4198                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4199                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4200                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4201                                 };
4202                                 map1 {
4203                                         trip = <&cpu0_alert1>;
4204                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4205                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4206                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4207                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4208                                 };
4209                         };
4210                 };
4211
4212                 cpu1-thermal {
4213                         polling-delay-passive = <250>;
4214                         polling-delay = <1000>;
4215
4216                         thermal-sensors = <&tsens0 2>;
4217
4218                         trips {
4219                                 cpu1_alert0: trip-point0 {
4220                                         temperature = <90000>;
4221                                         hysteresis = <2000>;
4222                                         type = "passive";
4223                                 };
4224
4225                                 cpu1_alert1: trip-point1 {
4226                                         temperature = <95000>;
4227                                         hysteresis = <2000>;
4228                                         type = "passive";
4229                                 };
4230
4231                                 cpu1_crit: cpu_crit {
4232                                         temperature = <110000>;
4233                                         hysteresis = <1000>;
4234                                         type = "critical";
4235                                 };
4236                         };
4237
4238                         cooling-maps {
4239                                 map0 {
4240                                         trip = <&cpu1_alert0>;
4241                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4242                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4243                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4244                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4245                                 };
4246                                 map1 {
4247                                         trip = <&cpu1_alert1>;
4248                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4249                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4250                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4251                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4252                                 };
4253                         };
4254                 };
4255
4256                 cpu2-thermal {
4257                         polling-delay-passive = <250>;
4258                         polling-delay = <1000>;
4259
4260                         thermal-sensors = <&tsens0 3>;
4261
4262                         trips {
4263                                 cpu2_alert0: trip-point0 {
4264                                         temperature = <90000>;
4265                                         hysteresis = <2000>;
4266                                         type = "passive";
4267                                 };
4268
4269                                 cpu2_alert1: trip-point1 {
4270                                         temperature = <95000>;
4271                                         hysteresis = <2000>;
4272                                         type = "passive";
4273                                 };
4274
4275                                 cpu2_crit: cpu_crit {
4276                                         temperature = <110000>;
4277                                         hysteresis = <1000>;
4278                                         type = "critical";
4279                                 };
4280                         };
4281
4282                         cooling-maps {
4283                                 map0 {
4284                                         trip = <&cpu2_alert0>;
4285                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4286                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4287                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4288                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4289                                 };
4290                                 map1 {
4291                                         trip = <&cpu2_alert1>;
4292                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4293                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4294                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4295                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4296                                 };
4297                         };
4298                 };
4299
4300                 cpu3-thermal {
4301                         polling-delay-passive = <250>;
4302                         polling-delay = <1000>;
4303
4304                         thermal-sensors = <&tsens0 4>;
4305
4306                         trips {
4307                                 cpu3_alert0: trip-point0 {
4308                                         temperature = <90000>;
4309                                         hysteresis = <2000>;
4310                                         type = "passive";
4311                                 };
4312
4313                                 cpu3_alert1: trip-point1 {
4314                                         temperature = <95000>;
4315                                         hysteresis = <2000>;
4316                                         type = "passive";
4317                                 };
4318
4319                                 cpu3_crit: cpu_crit {
4320                                         temperature = <110000>;
4321                                         hysteresis = <1000>;
4322                                         type = "critical";
4323                                 };
4324                         };
4325
4326                         cooling-maps {
4327                                 map0 {
4328                                         trip = <&cpu3_alert0>;
4329                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4330                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4331                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4332                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4333                                 };
4334                                 map1 {
4335                                         trip = <&cpu3_alert1>;
4336                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4337                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4338                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4339                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4340                                 };
4341                         };
4342                 };
4343
4344                 cpu4-top-thermal {
4345                         polling-delay-passive = <250>;
4346                         polling-delay = <1000>;
4347
4348                         thermal-sensors = <&tsens0 7>;
4349
4350                         trips {
4351                                 cpu4_top_alert0: trip-point0 {
4352                                         temperature = <90000>;
4353                                         hysteresis = <2000>;
4354                                         type = "passive";
4355                                 };
4356
4357                                 cpu4_top_alert1: trip-point1 {
4358                                         temperature = <95000>;
4359                                         hysteresis = <2000>;
4360                                         type = "passive";
4361                                 };
4362
4363                                 cpu4_top_crit: cpu_crit {
4364                                         temperature = <110000>;
4365                                         hysteresis = <1000>;
4366                                         type = "critical";
4367                                 };
4368                         };
4369
4370                         cooling-maps {
4371                                 map0 {
4372                                         trip = <&cpu4_top_alert0>;
4373                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4374                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4375                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4376                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4377                                 };
4378                                 map1 {
4379                                         trip = <&cpu4_top_alert1>;
4380                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4381                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4382                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4383                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4384                                 };
4385                         };
4386                 };
4387
4388                 cpu5-top-thermal {
4389                         polling-delay-passive = <250>;
4390                         polling-delay = <1000>;
4391
4392                         thermal-sensors = <&tsens0 8>;
4393
4394                         trips {
4395                                 cpu5_top_alert0: trip-point0 {
4396                                         temperature = <90000>;
4397                                         hysteresis = <2000>;
4398                                         type = "passive";
4399                                 };
4400
4401                                 cpu5_top_alert1: trip-point1 {
4402                                         temperature = <95000>;
4403                                         hysteresis = <2000>;
4404                                         type = "passive";
4405                                 };
4406
4407                                 cpu5_top_crit: cpu_crit {
4408                                         temperature = <110000>;
4409                                         hysteresis = <1000>;
4410                                         type = "critical";
4411                                 };
4412                         };
4413
4414                         cooling-maps {
4415                                 map0 {
4416                                         trip = <&cpu5_top_alert0>;
4417                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4418                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4419                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4420                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4421                                 };
4422                                 map1 {
4423                                         trip = <&cpu5_top_alert1>;
4424                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4425                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4426                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4427                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4428                                 };
4429                         };
4430                 };
4431
4432                 cpu6-top-thermal {
4433                         polling-delay-passive = <250>;
4434                         polling-delay = <1000>;
4435
4436                         thermal-sensors = <&tsens0 9>;
4437
4438                         trips {
4439                                 cpu6_top_alert0: trip-point0 {
4440                                         temperature = <90000>;
4441                                         hysteresis = <2000>;
4442                                         type = "passive";
4443                                 };
4444
4445                                 cpu6_top_alert1: trip-point1 {
4446                                         temperature = <95000>;
4447                                         hysteresis = <2000>;
4448                                         type = "passive";
4449                                 };
4450
4451                                 cpu6_top_crit: cpu_crit {
4452                                         temperature = <110000>;
4453                                         hysteresis = <1000>;
4454                                         type = "critical";
4455                                 };
4456                         };
4457
4458                         cooling-maps {
4459                                 map0 {
4460                                         trip = <&cpu6_top_alert0>;
4461                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4462                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4463                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4464                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4465                                 };
4466                                 map1 {
4467                                         trip = <&cpu6_top_alert1>;
4468                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4469                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4470                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4471                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4472                                 };
4473                         };
4474                 };
4475
4476                 cpu7-top-thermal {
4477                         polling-delay-passive = <250>;
4478                         polling-delay = <1000>;
4479
4480                         thermal-sensors = <&tsens0 10>;
4481
4482                         trips {
4483                                 cpu7_top_alert0: trip-point0 {
4484                                         temperature = <90000>;
4485                                         hysteresis = <2000>;
4486                                         type = "passive";
4487                                 };
4488
4489                                 cpu7_top_alert1: trip-point1 {
4490                                         temperature = <95000>;
4491                                         hysteresis = <2000>;
4492                                         type = "passive";
4493                                 };
4494
4495                                 cpu7_top_crit: cpu_crit {
4496                                         temperature = <110000>;
4497                                         hysteresis = <1000>;
4498                                         type = "critical";
4499                                 };
4500                         };
4501
4502                         cooling-maps {
4503                                 map0 {
4504                                         trip = <&cpu7_top_alert0>;
4505                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4506                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4507                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4508                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4509                                 };
4510                                 map1 {
4511                                         trip = <&cpu7_top_alert1>;
4512                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4513                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4514                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4515                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4516                                 };
4517                         };
4518                 };
4519
4520                 cpu4-bottom-thermal {
4521                         polling-delay-passive = <250>;
4522                         polling-delay = <1000>;
4523
4524                         thermal-sensors = <&tsens0 11>;
4525
4526                         trips {
4527                                 cpu4_bottom_alert0: trip-point0 {
4528                                         temperature = <90000>;
4529                                         hysteresis = <2000>;
4530                                         type = "passive";
4531                                 };
4532
4533                                 cpu4_bottom_alert1: trip-point1 {
4534                                         temperature = <95000>;
4535                                         hysteresis = <2000>;
4536                                         type = "passive";
4537                                 };
4538
4539                                 cpu4_bottom_crit: cpu_crit {
4540                                         temperature = <110000>;
4541                                         hysteresis = <1000>;
4542                                         type = "critical";
4543                                 };
4544                         };
4545
4546                         cooling-maps {
4547                                 map0 {
4548                                         trip = <&cpu4_bottom_alert0>;
4549                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4550                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4551                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4552                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4553                                 };
4554                                 map1 {
4555                                         trip = <&cpu4_bottom_alert1>;
4556                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4557                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4558                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4559                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4560                                 };
4561                         };
4562                 };
4563
4564                 cpu5-bottom-thermal {
4565                         polling-delay-passive = <250>;
4566                         polling-delay = <1000>;
4567
4568                         thermal-sensors = <&tsens0 12>;
4569
4570                         trips {
4571                                 cpu5_bottom_alert0: trip-point0 {
4572                                         temperature = <90000>;
4573                                         hysteresis = <2000>;
4574                                         type = "passive";
4575                                 };
4576
4577                                 cpu5_bottom_alert1: trip-point1 {
4578                                         temperature = <95000>;
4579                                         hysteresis = <2000>;
4580                                         type = "passive";
4581                                 };
4582
4583                                 cpu5_bottom_crit: cpu_crit {
4584                                         temperature = <110000>;
4585                                         hysteresis = <1000>;
4586                                         type = "critical";
4587                                 };
4588                         };
4589
4590                         cooling-maps {
4591                                 map0 {
4592                                         trip = <&cpu5_bottom_alert0>;
4593                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4594                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4595                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4596                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4597                                 };
4598                                 map1 {
4599                                         trip = <&cpu5_bottom_alert1>;
4600                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4601                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4602                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4603                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4604                                 };
4605                         };
4606                 };
4607
4608                 cpu6-bottom-thermal {
4609                         polling-delay-passive = <250>;
4610                         polling-delay = <1000>;
4611
4612                         thermal-sensors = <&tsens0 13>;
4613
4614                         trips {
4615                                 cpu6_bottom_alert0: trip-point0 {
4616                                         temperature = <90000>;
4617                                         hysteresis = <2000>;
4618                                         type = "passive";
4619                                 };
4620
4621                                 cpu6_bottom_alert1: trip-point1 {
4622                                         temperature = <95000>;
4623                                         hysteresis = <2000>;
4624                                         type = "passive";
4625                                 };
4626
4627                                 cpu6_bottom_crit: cpu_crit {
4628                                         temperature = <110000>;
4629                                         hysteresis = <1000>;
4630                                         type = "critical";
4631                                 };
4632                         };
4633
4634                         cooling-maps {
4635                                 map0 {
4636                                         trip = <&cpu6_bottom_alert0>;
4637                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641                                 };
4642                                 map1 {
4643                                         trip = <&cpu6_bottom_alert1>;
4644                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648                                 };
4649                         };
4650                 };
4651
4652                 cpu7-bottom-thermal {
4653                         polling-delay-passive = <250>;
4654                         polling-delay = <1000>;
4655
4656                         thermal-sensors = <&tsens0 14>;
4657
4658                         trips {
4659                                 cpu7_bottom_alert0: trip-point0 {
4660                                         temperature = <90000>;
4661                                         hysteresis = <2000>;
4662                                         type = "passive";
4663                                 };
4664
4665                                 cpu7_bottom_alert1: trip-point1 {
4666                                         temperature = <95000>;
4667                                         hysteresis = <2000>;
4668                                         type = "passive";
4669                                 };
4670
4671                                 cpu7_bottom_crit: cpu_crit {
4672                                         temperature = <110000>;
4673                                         hysteresis = <1000>;
4674                                         type = "critical";
4675                                 };
4676                         };
4677
4678                         cooling-maps {
4679                                 map0 {
4680                                         trip = <&cpu7_bottom_alert0>;
4681                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4684                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4685                                 };
4686                                 map1 {
4687                                         trip = <&cpu7_bottom_alert1>;
4688                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4691                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4692                                 };
4693                         };
4694                 };
4695
4696                 aoss0-thermal {
4697                         polling-delay-passive = <250>;
4698                         polling-delay = <1000>;
4699
4700                         thermal-sensors = <&tsens0 0>;
4701
4702                         trips {
4703                                 aoss0_alert0: trip-point0 {
4704                                         temperature = <90000>;
4705                                         hysteresis = <2000>;
4706                                         type = "hot";
4707                                 };
4708                         };
4709                 };
4710
4711                 cluster0-thermal {
4712                         polling-delay-passive = <250>;
4713                         polling-delay = <1000>;
4714
4715                         thermal-sensors = <&tsens0 5>;
4716
4717                         trips {
4718                                 cluster0_alert0: trip-point0 {
4719                                         temperature = <90000>;
4720                                         hysteresis = <2000>;
4721                                         type = "hot";
4722                                 };
4723                                 cluster0_crit: cluster0_crit {
4724                                         temperature = <110000>;
4725                                         hysteresis = <2000>;
4726                                         type = "critical";
4727                                 };
4728                         };
4729                 };
4730
4731                 cluster1-thermal {
4732                         polling-delay-passive = <250>;
4733                         polling-delay = <1000>;
4734
4735                         thermal-sensors = <&tsens0 6>;
4736
4737                         trips {
4738                                 cluster1_alert0: trip-point0 {
4739                                         temperature = <90000>;
4740                                         hysteresis = <2000>;
4741                                         type = "hot";
4742                                 };
4743                                 cluster1_crit: cluster1_crit {
4744                                         temperature = <110000>;
4745                                         hysteresis = <2000>;
4746                                         type = "critical";
4747                                 };
4748                         };
4749                 };
4750
4751                 gpu-top-thermal {
4752                         polling-delay-passive = <250>;
4753                         polling-delay = <1000>;
4754
4755                         thermal-sensors = <&tsens0 15>;
4756
4757                         trips {
4758                                 gpu1_alert0: trip-point0 {
4759                                         temperature = <90000>;
4760                                         hysteresis = <2000>;
4761                                         type = "hot";
4762                                 };
4763                         };
4764                 };
4765
4766                 aoss1-thermal {
4767                         polling-delay-passive = <250>;
4768                         polling-delay = <1000>;
4769
4770                         thermal-sensors = <&tsens1 0>;
4771
4772                         trips {
4773                                 aoss1_alert0: trip-point0 {
4774                                         temperature = <90000>;
4775                                         hysteresis = <2000>;
4776                                         type = "hot";
4777                                 };
4778                         };
4779                 };
4780
4781                 wlan-thermal {
4782                         polling-delay-passive = <250>;
4783                         polling-delay = <1000>;
4784
4785                         thermal-sensors = <&tsens1 1>;
4786
4787                         trips {
4788                                 wlan_alert0: trip-point0 {
4789                                         temperature = <90000>;
4790                                         hysteresis = <2000>;
4791                                         type = "hot";
4792                                 };
4793                         };
4794                 };
4795
4796                 video-thermal {
4797                         polling-delay-passive = <250>;
4798                         polling-delay = <1000>;
4799
4800                         thermal-sensors = <&tsens1 2>;
4801
4802                         trips {
4803                                 video_alert0: trip-point0 {
4804                                         temperature = <90000>;
4805                                         hysteresis = <2000>;
4806                                         type = "hot";
4807                                 };
4808                         };
4809                 };
4810
4811                 mem-thermal {
4812                         polling-delay-passive = <250>;
4813                         polling-delay = <1000>;
4814
4815                         thermal-sensors = <&tsens1 3>;
4816
4817                         trips {
4818                                 mem_alert0: trip-point0 {
4819                                         temperature = <90000>;
4820                                         hysteresis = <2000>;
4821                                         type = "hot";
4822                                 };
4823                         };
4824                 };
4825
4826                 q6-hvx-thermal {
4827                         polling-delay-passive = <250>;
4828                         polling-delay = <1000>;
4829
4830                         thermal-sensors = <&tsens1 4>;
4831
4832                         trips {
4833                                 q6_hvx_alert0: trip-point0 {
4834                                         temperature = <90000>;
4835                                         hysteresis = <2000>;
4836                                         type = "hot";
4837                                 };
4838                         };
4839                 };
4840
4841                 camera-thermal {
4842                         polling-delay-passive = <250>;
4843                         polling-delay = <1000>;
4844
4845                         thermal-sensors = <&tsens1 5>;
4846
4847                         trips {
4848                                 camera_alert0: trip-point0 {
4849                                         temperature = <90000>;
4850                                         hysteresis = <2000>;
4851                                         type = "hot";
4852                                 };
4853                         };
4854                 };
4855
4856                 compute-thermal {
4857                         polling-delay-passive = <250>;
4858                         polling-delay = <1000>;
4859
4860                         thermal-sensors = <&tsens1 6>;
4861
4862                         trips {
4863                                 compute_alert0: trip-point0 {
4864                                         temperature = <90000>;
4865                                         hysteresis = <2000>;
4866                                         type = "hot";
4867                                 };
4868                         };
4869                 };
4870
4871                 modem-thermal {
4872                         polling-delay-passive = <250>;
4873                         polling-delay = <1000>;
4874
4875                         thermal-sensors = <&tsens1 7>;
4876
4877                         trips {
4878                                 modem_alert0: trip-point0 {
4879                                         temperature = <90000>;
4880                                         hysteresis = <2000>;
4881                                         type = "hot";
4882                                 };
4883                         };
4884                 };
4885
4886                 npu-thermal {
4887                         polling-delay-passive = <250>;
4888                         polling-delay = <1000>;
4889
4890                         thermal-sensors = <&tsens1 8>;
4891
4892                         trips {
4893                                 npu_alert0: trip-point0 {
4894                                         temperature = <90000>;
4895                                         hysteresis = <2000>;
4896                                         type = "hot";
4897                                 };
4898                         };
4899                 };
4900
4901                 modem-vec-thermal {
4902                         polling-delay-passive = <250>;
4903                         polling-delay = <1000>;
4904
4905                         thermal-sensors = <&tsens1 9>;
4906
4907                         trips {
4908                                 modem_vec_alert0: trip-point0 {
4909                                         temperature = <90000>;
4910                                         hysteresis = <2000>;
4911                                         type = "hot";
4912                                 };
4913                         };
4914                 };
4915
4916                 modem-scl-thermal {
4917                         polling-delay-passive = <250>;
4918                         polling-delay = <1000>;
4919
4920                         thermal-sensors = <&tsens1 10>;
4921
4922                         trips {
4923                                 modem_scl_alert0: trip-point0 {
4924                                         temperature = <90000>;
4925                                         hysteresis = <2000>;
4926                                         type = "hot";
4927                                 };
4928                         };
4929                 };
4930
4931                 gpu-bottom-thermal {
4932                         polling-delay-passive = <250>;
4933                         polling-delay = <1000>;
4934
4935                         thermal-sensors = <&tsens1 11>;
4936
4937                         trips {
4938                                 gpu2_alert0: trip-point0 {
4939                                         temperature = <90000>;
4940                                         hysteresis = <2000>;
4941                                         type = "hot";
4942                                 };
4943                         };
4944                 };
4945         };
4946 };