1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org>
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
15 interrupt-parent = <&intc>;
23 compatible = "fixed-clock";
25 clock-frequency = <19200000>;
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
31 clock-frequency = <32000>;
32 clock-output-names = "sleep_clk";
42 compatible = "qcom,kryo260";
44 enable-method = "psci";
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
56 compatible = "qcom,kryo260";
58 enable-method = "psci";
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
65 compatible = "qcom,kryo260";
67 enable-method = "psci";
68 capacity-dmips-mhz = <1024>;
69 next-level-cache = <&L2_0>;
74 compatible = "qcom,kryo260";
76 enable-method = "psci";
77 capacity-dmips-mhz = <1024>;
78 next-level-cache = <&L2_0>;
83 compatible = "qcom,kryo260";
85 enable-method = "psci";
86 capacity-dmips-mhz = <1638>;
87 next-level-cache = <&L2_1>;
97 compatible = "qcom,kryo260";
99 enable-method = "psci";
100 capacity-dmips-mhz = <1638>;
101 next-level-cache = <&L2_1>;
106 compatible = "qcom,kryo260";
108 enable-method = "psci";
109 capacity-dmips-mhz = <1638>;
110 next-level-cache = <&L2_1>;
115 compatible = "qcom,kryo260";
117 enable-method = "psci";
118 capacity-dmips-mhz = <1638>;
119 next-level-cache = <&L2_1>;
163 compatible = "qcom,scm-sm6125", "qcom,scm";
169 /* We expect the bootloader to fill in the size */
170 reg = <0x0 0x40000000 0x0 0x0>;
171 device_type = "memory";
175 compatible = "arm,armv8-pmuv3";
176 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
180 compatible = "arm,psci-1.0";
185 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
188 compatible = "qcom,glink-rpm";
190 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
191 qcom,rpm-msg-ram = <&rpm_msg_ram>;
192 mboxes = <&apcs_glb 0>;
194 rpm_requests: rpm-requests {
195 compatible = "qcom,rpm-sm6125";
196 qcom,glink-channels = "rpm_requests";
198 rpmcc: clock-controller {
199 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
201 clocks = <&xo_board>;
205 rpmpd: power-controller {
206 compatible = "qcom,sm6125-rpmpd";
207 #power-domain-cells = <1>;
208 operating-points-v2 = <&rpmpd_opp_table>;
210 rpmpd_opp_table: opp-table {
211 compatible = "operating-points-v2";
213 rpmpd_opp_ret: opp1 {
214 opp-level = <RPM_SMD_LEVEL_RETENTION>;
217 rpmpd_opp_ret_plus: opp2 {
218 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
221 rpmpd_opp_min_svs: opp3 {
222 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
225 rpmpd_opp_low_svs: opp4 {
226 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
229 rpmpd_opp_svs: opp5 {
230 opp-level = <RPM_SMD_LEVEL_SVS>;
233 rpmpd_opp_svs_plus: opp6 {
234 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
237 rpmpd_opp_nom: opp7 {
238 opp-level = <RPM_SMD_LEVEL_NOM>;
241 rpmpd_opp_nom_plus: opp8 {
242 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
245 rpmpd_opp_turbo: opp9 {
246 opp-level = <RPM_SMD_LEVEL_TURBO>;
249 rpmpd_opp_turbo_no_cpr: opp10 {
250 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
258 reserved_memory: reserved-memory {
259 #address-cells = <2>;
263 hyp_mem: memory@45700000 {
264 reg = <0x0 0x45700000 0x0 0x600000>;
268 xbl_aop_mem: memory@45e00000 {
269 reg = <0x0 0x45e00000 0x0 0x140000>;
273 sec_apps_mem: memory@45fff000 {
274 reg = <0x0 0x45fff000 0x0 0x1000>;
278 smem_mem: memory@46000000 {
279 reg = <0x0 0x46000000 0x0 0x200000>;
283 reserved_mem1: memory@46200000 {
284 reg = <0x0 0x46200000 0x0 0x2d00000>;
288 camera_mem: memory@4ab00000 {
289 reg = <0x0 0x4ab00000 0x0 0x500000>;
293 modem_mem: memory@4b000000 {
294 reg = <0x0 0x4b000000 0x0 0x7e00000>;
298 venus_mem: memory@52e00000 {
299 reg = <0x0 0x52e00000 0x0 0x500000>;
303 wlan_msa_mem: memory@53300000 {
304 reg = <0x0 0x53300000 0x0 0x200000>;
308 cdsp_mem: memory@53500000 {
309 reg = <0x0 0x53500000 0x0 0x1e00000>;
313 adsp_pil_mem: memory@55300000 {
314 reg = <0x0 0x55300000 0x0 0x1e00000>;
318 ipa_fw_mem: memory@57100000 {
319 reg = <0x0 0x57100000 0x0 0x10000>;
323 ipa_gsi_mem: memory@57110000 {
324 reg = <0x0 0x57110000 0x0 0x5000>;
328 gpu_mem: memory@57115000 {
329 reg = <0x0 0x57115000 0x0 0x2000>;
333 cont_splash_mem: memory@5c000000 {
334 reg = <0x0 0x5c000000 0x0 0x00f00000>;
338 dfps_data_mem: memory@5cf00000 {
339 reg = <0x0 0x5cf00000 0x0 0x0100000>;
343 cdsp_sec_mem: memory@5f800000 {
344 reg = <0x0 0x5f800000 0x0 0x1e00000>;
348 qseecom_mem: memory@5e400000 {
349 reg = <0x0 0x5e400000 0x0 0x1400000>;
353 sdsp_mem: memory@f3000000 {
354 reg = <0x0 0xf3000000 0x0 0x400000>;
358 adsp_mem: memory@f3400000 {
359 reg = <0x0 0xf3400000 0x0 0x800000>;
363 qseecom_ta_mem: memory@13fc00000 {
364 reg = <0x1 0x3fc00000 0x0 0x400000>;
370 compatible = "qcom,smem";
371 memory-region = <&smem_mem>;
372 hwlocks = <&tcsr_mutex 3>;
376 #address-cells = <1>;
378 ranges = <0x00 0x00 0x00 0xffffffff>;
379 compatible = "simple-bus";
381 tcsr_mutex: hwlock@340000 {
382 compatible = "qcom,tcsr-mutex";
383 reg = <0x00340000 0x20000>;
387 tlmm: pinctrl@500000 {
388 compatible = "qcom,sm6125-tlmm";
389 reg = <0x00500000 0x400000>,
390 <0x00900000 0x400000>,
391 <0x00d00000 0x400000>;
392 reg-names = "west", "south", "east";
393 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
395 gpio-ranges = <&tlmm 0 0 134>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
400 sdc2_off_state: sdc2-off-state {
403 drive-strength = <2>;
409 drive-strength = <2>;
415 drive-strength = <2>;
420 sdc2_on_state: sdc2-on-state {
423 drive-strength = <16>;
429 drive-strength = <10>;
435 drive-strength = <10>;
440 qup_i2c0_default: qup-i2c0-default-state {
441 pins = "gpio0", "gpio1";
443 drive-strength = <2>;
447 qup_i2c0_sleep: qup-i2c0-sleep-state {
448 pins = "gpio0", "gpio1";
450 drive-strength = <2>;
454 qup_i2c1_default: qup-i2c1-default-state {
455 pins = "gpio4", "gpio5";
457 drive-strength = <2>;
461 qup_i2c1_sleep: qup-i2c1-sleep-state {
462 pins = "gpio4", "gpio5";
464 drive-strength = <2>;
468 qup_i2c2_default: qup-i2c2-default-state {
469 pins = "gpio6", "gpio7";
471 drive-strength = <2>;
475 qup_i2c2_sleep: qup-i2c2-sleep-state {
476 pins = "gpio6", "gpio7";
478 drive-strength = <2>;
482 qup_i2c3_default: qup-i2c3-default-state {
483 pins = "gpio14", "gpio15";
485 drive-strength = <2>;
489 qup_i2c3_sleep: qup-i2c3-sleep-state {
490 pins = "gpio14", "gpio15";
492 drive-strength = <2>;
496 qup_i2c4_default: qup-i2c4-default-state {
497 pins = "gpio16", "gpio17";
499 drive-strength = <2>;
503 qup_i2c4_sleep: qup-i2c4-sleep-state {
504 pins = "gpio16", "gpio17";
506 drive-strength = <2>;
510 qup_i2c5_default: qup-i2c5-default-state {
511 pins = "gpio22", "gpio23";
513 drive-strength = <2>;
517 qup_i2c5_sleep: qup-i2c5-sleep-state {
518 pins = "gpio22", "gpio23";
520 drive-strength = <2>;
524 qup_i2c6_default: qup-i2c6-default-state {
525 pins = "gpio30", "gpio31";
527 drive-strength = <2>;
531 qup_i2c6_sleep: qup-i2c6-sleep-state {
532 pins = "gpio30", "gpio31";
534 drive-strength = <2>;
538 qup_i2c7_default: qup-i2c7-default-state {
539 pins = "gpio28", "gpio29";
541 drive-strength = <2>;
545 qup_i2c7_sleep: qup-i2c7-sleep-state {
546 pins = "gpio28", "gpio29";
548 drive-strength = <2>;
552 qup_i2c8_default: qup-i2c8-default-state {
553 pins = "gpio18", "gpio19";
555 drive-strength = <2>;
559 qup_i2c8_sleep: qup-i2c8-sleep-state {
560 pins = "gpio18", "gpio19";
562 drive-strength = <2>;
566 qup_i2c9_default: qup-i2c9-default-state {
567 pins = "gpio10", "gpio11";
569 drive-strength = <2>;
573 qup_i2c9_sleep: qup-i2c9-sleep-state {
574 pins = "gpio10", "gpio11";
576 drive-strength = <2>;
580 qup_spi0_default: qup-spi0-default-state {
581 pins = "gpio0", "gpio1", "gpio2", "gpio3";
583 drive-strength = <6>;
587 qup_spi0_sleep: qup-spi0-sleep-state {
588 pins = "gpio0", "gpio1", "gpio2", "gpio3";
590 drive-strength = <6>;
594 qup_spi2_default: qup-spi2-default-state {
595 pins = "gpio6", "gpio7", "gpio8", "gpio9";
597 drive-strength = <6>;
601 qup_spi2_sleep: qup-spi2-sleep-state {
602 pins = "gpio6", "gpio7", "gpio8", "gpio9";
604 drive-strength = <6>;
608 qup_spi5_default: qup-spi5-default-state {
609 pins = "gpio22", "gpio23", "gpio24", "gpio25";
611 drive-strength = <6>;
615 qup_spi5_sleep: qup-spi5-sleep-state {
616 pins = "gpio22", "gpio23", "gpio24", "gpio25";
618 drive-strength = <6>;
622 qup_spi6_default: qup-spi6-default-state {
623 pins = "gpio30", "gpio31", "gpio32", "gpio33";
625 drive-strength = <6>;
629 qup_spi6_sleep: qup-spi6-sleep-state {
630 pins = "gpio30", "gpio31", "gpio32", "gpio33";
632 drive-strength = <6>;
636 qup_spi8_default: qup-spi8-default-state {
637 pins = "gpio18", "gpio19", "gpio20", "gpio21";
639 drive-strength = <6>;
643 qup_spi8_sleep: qup-spi8-sleep-state {
644 pins = "gpio18", "gpio19", "gpio20", "gpio21";
646 drive-strength = <6>;
650 qup_spi9_default: qup-spi9-default-state {
651 pins = "gpio10", "gpio11", "gpio12", "gpio13";
653 drive-strength = <6>;
657 qup_spi9_sleep: qup-spi9-sleep-state {
658 pins = "gpio10", "gpio11", "gpio12", "gpio13";
660 drive-strength = <6>;
665 gcc: clock-controller@1400000 {
666 compatible = "qcom,gcc-sm6125";
667 reg = <0x01400000 0x1f0000>;
670 #power-domain-cells = <1>;
671 clock-names = "bi_tcxo", "sleep_clk";
672 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
675 hsusb_phy1: phy@1613000 {
676 compatible = "qcom,msm8996-qusb2-phy";
677 reg = <0x01613000 0x180>;
680 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
681 <&rpmcc RPM_SMD_XO_CLK_SRC>;
682 clock-names = "cfg_ahb", "ref";
684 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
688 spmi_bus: spmi@1c40000 {
689 compatible = "qcom,spmi-pmic-arb";
690 reg = <0x01c40000 0x1100>,
691 <0x01e00000 0x2000000>,
692 <0x03e00000 0x100000>,
693 <0x03f00000 0xa0000>,
694 <0x01c0a000 0x26000>;
695 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
696 interrupt-names = "periph_irq";
697 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
700 #address-cells = <2>;
702 interrupt-controller;
703 #interrupt-cells = <4>;
706 rpm_msg_ram: sram@45f0000 {
707 compatible = "qcom,rpm-msg-ram";
708 reg = <0x045f0000 0x7000>;
711 sdhc_1: mmc@4744000 {
712 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
713 reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
714 reg-names = "hc", "cqhci";
716 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
718 interrupt-names = "hc_irq", "pwr_irq";
720 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
721 <&gcc GCC_SDCC1_APPS_CLK>,
722 <&rpmcc RPM_SMD_XO_CLK_SRC>;
723 clock-names = "iface", "core", "xo";
724 iommus = <&apps_smmu 0x160 0x0>;
726 power-domains = <&rpmpd SM6125_VDDCX>;
728 qcom,dll-config = <0x000f642c>;
729 qcom,ddr-config = <0x80040873>;
738 sdhc_2: mmc@4784000 {
739 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
740 reg = <0x04784000 0x1000>;
743 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "hc_irq", "pwr_irq";
747 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
748 <&gcc GCC_SDCC2_APPS_CLK>,
749 <&rpmcc RPM_SMD_XO_CLK_SRC>;
750 clock-names = "iface", "core", "xo";
751 iommus = <&apps_smmu 0x180 0x0>;
753 pinctrl-0 = <&sdc2_on_state>;
754 pinctrl-1 = <&sdc2_off_state>;
755 pinctrl-names = "default", "sleep";
757 power-domains = <&rpmpd SM6125_VDDCX>;
759 qcom,dll-config = <0x0007642c>;
760 qcom,ddr-config = <0x80040873>;
766 ufs_mem_hc: ufs@4804000 {
767 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
768 reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
769 reg-names = "std", "ice";
770 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
773 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
774 <&gcc GCC_UFS_PHY_AHB_CLK>,
775 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
776 <&rpmcc RPM_SMD_XO_CLK_SRC>,
777 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
778 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
779 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
780 clock-names = "core_clk",
788 freq-table-hz = <50000000 240000000>,
791 <37500000 150000000>,
795 <75000000 300000000>;
797 resets = <&gcc GCC_UFS_PHY_BCR>;
801 phys = <&ufs_mem_phy>;
802 phy-names = "ufsphy";
804 lanes-per-direction = <1>;
806 iommus = <&apps_smmu 0x200 0x0>;
811 ufs_mem_phy: phy@4807000 {
812 compatible = "qcom,sm6125-qmp-ufs-phy";
813 reg = <0x04807000 0xdb8>;
815 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
816 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
820 resets = <&ufs_mem_hc 0>;
821 reset-names = "ufsphy";
823 power-domains = <&gcc UFS_PHY_GDSC>;
830 gpi_dma0: dma-controller@4a00000 {
831 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
832 reg = <0x04a00000 0x60000>;
833 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
839 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
842 dma-channel-mask = <0x1f>;
843 iommus = <&apps_smmu 0x136 0x0>;
848 qupv3_id_0: geniqup@4ac0000 {
849 compatible = "qcom,geni-se-qup";
850 reg = <0x04ac0000 0x2000>;
851 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
852 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
853 clock-names = "m-ahb", "s-ahb";
854 iommus = <&apps_smmu 0x123 0x0>;
855 #address-cells = <1>;
861 compatible = "qcom,geni-i2c";
862 reg = <0x04a80000 0x4000>;
863 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
865 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
866 pinctrl-0 = <&qup_i2c0_default>;
867 pinctrl-1 = <&qup_i2c0_sleep>;
868 pinctrl-names = "default", "sleep";
869 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
870 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
871 dma-names = "tx", "rx";
872 #address-cells = <1>;
878 compatible = "qcom,geni-spi";
879 reg = <0x04a80000 0x4000>;
880 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
882 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
883 pinctrl-0 = <&qup_spi0_default>;
884 pinctrl-1 = <&qup_spi0_sleep>;
885 pinctrl-names = "default", "sleep";
886 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
887 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
888 dma-names = "tx", "rx";
889 #address-cells = <1>;
895 compatible = "qcom,geni-i2c";
896 reg = <0x04a84000 0x4000>;
897 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
899 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
900 pinctrl-0 = <&qup_i2c1_default>;
901 pinctrl-1 = <&qup_i2c1_sleep>;
902 pinctrl-names = "default", "sleep";
903 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
904 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
905 dma-names = "tx", "rx";
906 #address-cells = <1>;
912 compatible = "qcom,geni-i2c";
913 reg = <0x04a88000 0x4000>;
914 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
916 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
917 pinctrl-0 = <&qup_i2c2_default>;
918 pinctrl-1 = <&qup_i2c2_sleep>;
919 pinctrl-names = "default", "sleep";
920 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
921 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
922 dma-names = "tx", "rx";
923 #address-cells = <1>;
929 compatible = "qcom,geni-spi";
930 reg = <0x04a88000 0x4000>;
931 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
933 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
934 pinctrl-0 = <&qup_spi2_default>;
935 pinctrl-1 = <&qup_spi2_sleep>;
936 pinctrl-names = "default", "sleep";
937 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
938 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
939 dma-names = "tx", "rx";
940 #address-cells = <1>;
946 compatible = "qcom,geni-i2c";
947 reg = <0x04a8c000 0x4000>;
948 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
950 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
951 pinctrl-0 = <&qup_i2c3_default>;
952 pinctrl-1 = <&qup_i2c3_sleep>;
953 pinctrl-names = "default", "sleep";
954 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
955 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
956 dma-names = "tx", "rx";
957 #address-cells = <1>;
963 compatible = "qcom,geni-i2c";
964 reg = <0x04a90000 0x4000>;
965 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
967 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
968 pinctrl-0 = <&qup_i2c4_default>;
969 pinctrl-1 = <&qup_i2c4_sleep>;
970 pinctrl-names = "default", "sleep";
971 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
972 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
973 dma-names = "tx", "rx";
974 #address-cells = <1>;
980 gpi_dma1: dma-controller@4c00000 {
981 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
982 reg = <0x04c00000 0x60000>;
983 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
992 dma-channel-mask = <0x0f>;
993 iommus = <&apps_smmu 0x156 0x0>;
998 qupv3_id_1: geniqup@4cc0000 {
999 compatible = "qcom,geni-se-qup";
1000 reg = <0x04cc0000 0x2000>;
1001 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1002 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1003 clock-names = "m-ahb", "s-ahb";
1004 iommus = <&apps_smmu 0x143 0x0>;
1005 #address-cells = <1>;
1008 status = "disabled";
1011 compatible = "qcom,geni-i2c";
1012 reg = <0x04c80000 0x4000>;
1013 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1015 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
1016 pinctrl-0 = <&qup_i2c5_default>;
1017 pinctrl-1 = <&qup_i2c5_sleep>;
1018 pinctrl-names = "default", "sleep";
1019 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1020 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1021 dma-names = "tx", "rx";
1022 #address-cells = <1>;
1024 status = "disabled";
1028 compatible = "qcom,geni-spi";
1029 reg = <0x04c80000 0x4000>;
1030 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1032 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
1033 pinctrl-0 = <&qup_spi5_default>;
1034 pinctrl-1 = <&qup_spi5_sleep>;
1035 pinctrl-names = "default", "sleep";
1036 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1037 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1038 dma-names = "tx", "rx";
1039 #address-cells = <1>;
1041 status = "disabled";
1045 compatible = "qcom,geni-i2c";
1046 reg = <0x04c84000 0x4000>;
1047 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1049 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1050 pinctrl-0 = <&qup_i2c6_default>;
1051 pinctrl-1 = <&qup_i2c6_sleep>;
1052 pinctrl-names = "default", "sleep";
1053 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1054 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1055 dma-names = "tx", "rx";
1056 #address-cells = <1>;
1058 status = "disabled";
1062 compatible = "qcom,geni-spi";
1063 reg = <0x04c84000 0x4000>;
1064 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1066 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
1067 pinctrl-0 = <&qup_spi6_default>;
1068 pinctrl-1 = <&qup_spi6_sleep>;
1069 pinctrl-names = "default", "sleep";
1070 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1071 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1072 dma-names = "tx", "rx";
1073 #address-cells = <1>;
1075 status = "disabled";
1079 compatible = "qcom,geni-i2c";
1080 reg = <0x04c88000 0x4000>;
1081 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1083 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
1084 pinctrl-0 = <&qup_i2c7_default>;
1085 pinctrl-1 = <&qup_i2c7_sleep>;
1086 pinctrl-names = "default", "sleep";
1087 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1088 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1092 status = "disabled";
1096 compatible = "qcom,geni-i2c";
1097 reg = <0x04c8c000 0x4000>;
1098 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1100 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
1101 pinctrl-0 = <&qup_i2c8_default>;
1102 pinctrl-1 = <&qup_i2c8_sleep>;
1103 pinctrl-names = "default", "sleep";
1104 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1105 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1106 dma-names = "tx", "rx";
1107 #address-cells = <1>;
1109 status = "disabled";
1113 compatible = "qcom,geni-spi";
1114 reg = <0x04c8c000 0x4000>;
1115 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1117 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
1118 pinctrl-0 = <&qup_spi8_default>;
1119 pinctrl-1 = <&qup_spi8_sleep>;
1120 pinctrl-names = "default", "sleep";
1121 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1122 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1123 dma-names = "tx", "rx";
1124 #address-cells = <1>;
1126 status = "disabled";
1130 compatible = "qcom,geni-i2c";
1131 reg = <0x04c90000 0x4000>;
1132 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1134 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
1135 pinctrl-0 = <&qup_i2c9_default>;
1136 pinctrl-1 = <&qup_i2c9_sleep>;
1137 pinctrl-names = "default", "sleep";
1138 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1139 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1140 dma-names = "tx", "rx";
1141 #address-cells = <1>;
1143 status = "disabled";
1147 compatible = "qcom,geni-spi";
1148 reg = <0x04c90000 0x4000>;
1149 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1151 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
1152 pinctrl-0 = <&qup_spi9_default>;
1153 pinctrl-1 = <&qup_spi9_sleep>;
1154 pinctrl-names = "default", "sleep";
1155 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1156 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1157 dma-names = "tx", "rx";
1158 #address-cells = <1>;
1160 status = "disabled";
1165 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
1166 reg = <0x04ef8800 0x400>;
1167 #address-cells = <1>;
1171 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1172 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1173 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1174 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1175 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1176 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1177 clock-names = "cfg_noc",
1184 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1185 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1186 assigned-clock-rates = <19200000>, <66666667>;
1188 power-domains = <&gcc USB30_PRIM_GDSC>;
1189 qcom,select-utmi-as-pipe-clk;
1190 status = "disabled";
1192 usb3_dwc3: usb@4e00000 {
1193 compatible = "snps,dwc3";
1194 reg = <0x04e00000 0xcd00>;
1195 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1196 iommus = <&apps_smmu 0x100 0x0>;
1197 phys = <&hsusb_phy1>;
1198 phy-names = "usb2-phy";
1199 snps,dis_u2_susphy_quirk;
1200 snps,dis_enblslpm_quirk;
1201 maximum-speed = "high-speed";
1202 dr_mode = "peripheral";
1207 compatible = "qcom,rpm-stats";
1208 reg = <0x04690000 0x10000>;
1211 mdss: display-subsystem@5e00000 {
1212 compatible = "qcom,sm6125-mdss";
1213 reg = <0x05e00000 0x1000>;
1216 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1217 interrupt-controller;
1218 #interrupt-cells = <1>;
1220 clocks = <&gcc GCC_DISP_AHB_CLK>,
1221 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1222 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1223 clock-names = "iface",
1227 power-domains = <&dispcc MDSS_GDSC>;
1229 iommus = <&apps_smmu 0x400 0x0>;
1231 #address-cells = <1>;
1235 status = "disabled";
1237 mdss_mdp: display-controller@5e01000 {
1238 compatible = "qcom,sm6125-dpu";
1239 reg = <0x05e01000 0x83208>,
1240 <0x05eb0000 0x2008>;
1241 reg-names = "mdp", "vbif";
1243 interrupt-parent = <&mdss>;
1246 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1247 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1248 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1249 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1250 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1251 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
1252 <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
1253 clock-names = "bus",
1260 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1261 assigned-clock-rates = <19200000>;
1263 operating-points-v2 = <&mdp_opp_table>;
1264 power-domains = <&rpmpd SM6125_VDDCX>;
1267 #address-cells = <1>;
1272 dpu_intf1_out: endpoint {
1273 remote-endpoint = <&mdss_dsi0_in>;
1278 mdp_opp_table: opp-table {
1279 compatible = "operating-points-v2";
1282 opp-hz = /bits/ 64 <192000000>;
1283 required-opps = <&rpmpd_opp_low_svs>;
1287 opp-hz = /bits/ 64 <256000000>;
1288 required-opps = <&rpmpd_opp_svs>;
1292 opp-hz = /bits/ 64 <307200000>;
1293 required-opps = <&rpmpd_opp_svs_plus>;
1297 opp-hz = /bits/ 64 <384000000>;
1298 required-opps = <&rpmpd_opp_nom>;
1302 opp-hz = /bits/ 64 <400000000>;
1303 required-opps = <&rpmpd_opp_turbo>;
1308 mdss_dsi0: dsi@5e94000 {
1309 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1310 reg = <0x05e94000 0x400>;
1311 reg-names = "dsi_ctrl";
1313 interrupt-parent = <&mdss>;
1316 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1317 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1318 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1319 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1320 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1321 <&gcc GCC_DISP_HF_AXI_CLK>;
1322 clock-names = "byte",
1328 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1329 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1330 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1332 operating-points-v2 = <&dsi_opp_table>;
1333 power-domains = <&rpmpd SM6125_VDDCX>;
1335 phys = <&mdss_dsi0_phy>;
1338 #address-cells = <1>;
1341 status = "disabled";
1344 #address-cells = <1>;
1349 mdss_dsi0_in: endpoint {
1350 remote-endpoint = <&dpu_intf1_out>;
1356 mdss_dsi0_out: endpoint {
1361 dsi_opp_table: opp-table {
1362 compatible = "operating-points-v2";
1365 opp-hz = /bits/ 64 <164000000>;
1366 required-opps = <&rpmpd_opp_low_svs>;
1370 opp-hz = /bits/ 64 <187500000>;
1371 required-opps = <&rpmpd_opp_svs>;
1376 mdss_dsi0_phy: phy@5e94400 {
1377 compatible = "qcom,sm6125-dsi-phy-14nm";
1378 reg = <0x05e94400 0x100>,
1381 reg-names = "dsi_phy",
1388 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1389 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1390 clock-names = "iface",
1393 required-opps = <&rpmpd_opp_nom>;
1394 power-domains = <&rpmpd SM6125_VDDMX>;
1396 status = "disabled";
1400 dispcc: clock-controller@5f00000 {
1401 compatible = "qcom,sm6125-dispcc";
1402 reg = <0x05f00000 0x20000>;
1404 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1410 <&gcc GCC_DISP_AHB_CLK>,
1411 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
1412 clock-names = "bi_tcxo",
1413 "dsi0_phy_pll_out_byteclk",
1414 "dsi0_phy_pll_out_dsiclk",
1415 "dsi1_phy_pll_out_dsiclk",
1416 "dp_phy_pll_link_clk",
1417 "dp_phy_pll_vco_div_clk",
1419 "gcc_disp_gpll0_div_clk_src";
1421 required-opps = <&rpmpd_opp_ret>;
1422 power-domains = <&rpmpd SM6125_VDDCX>;
1425 #power-domain-cells = <1>;
1428 apps_smmu: iommu@c600000 {
1429 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1430 reg = <0x0c600000 0x80000>;
1431 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1437 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
1497 #global-interrupts = <1>;
1501 apcs_glb: mailbox@f111000 {
1502 compatible = "qcom,sm6125-apcs-hmss-global",
1503 "qcom,msm8994-apcs-kpss-global";
1504 reg = <0x0f111000 0x1000>;
1510 compatible = "arm,armv7-timer-mem";
1511 #address-cells = <1>;
1514 reg = <0x0f120000 0x1000>;
1515 clock-frequency = <19200000>;
1519 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1521 reg = <0x0f121000 0x1000>,
1522 <0x0f122000 0x1000>;
1527 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1528 reg = <0x0f123000 0x1000>;
1529 status = "disabled";
1534 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1535 reg = <0x0f124000 0x1000>;
1536 status = "disabled";
1541 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1542 reg = <0x0f125000 0x1000>;
1543 status = "disabled";
1548 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1549 reg = <0x0f126000 0x1000>;
1550 status = "disabled";
1555 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1556 reg = <0x0f127000 0x1000>;
1557 status = "disabled";
1562 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1563 reg = <0x0f128000 0x1000>;
1564 status = "disabled";
1568 intc: interrupt-controller@f200000 {
1569 compatible = "arm,gic-v3";
1570 reg = <0x0f200000 0x20000>,
1571 <0x0f300000 0x100000>;
1572 #interrupt-cells = <3>;
1573 interrupt-controller;
1574 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1579 compatible = "arm,armv8-timer";
1580 interrupts = <GIC_PPI 1 0xf08
1584 clock-frequency = <19200000>;