1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
26 compatible = "fixed-clock";
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
42 compatible = "qcom,kryo260";
44 clocks = <&cpufreq_hw 0>;
45 capacity-dmips-mhz = <1024>;
46 dynamic-power-coefficient = <100>;
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 power-domains = <&CPU_PD0>;
51 power-domain-names = "psci";
61 compatible = "qcom,kryo260";
63 clocks = <&cpufreq_hw 0>;
64 capacity-dmips-mhz = <1024>;
65 dynamic-power-coefficient = <100>;
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 power-domains = <&CPU_PD1>;
70 power-domain-names = "psci";
75 compatible = "qcom,kryo260";
77 clocks = <&cpufreq_hw 0>;
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 enable-method = "psci";
81 next-level-cache = <&L2_0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 power-domains = <&CPU_PD2>;
84 power-domain-names = "psci";
89 compatible = "qcom,kryo260";
91 clocks = <&cpufreq_hw 0>;
92 capacity-dmips-mhz = <1024>;
93 dynamic-power-coefficient = <100>;
94 enable-method = "psci";
95 next-level-cache = <&L2_0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 power-domains = <&CPU_PD3>;
98 power-domain-names = "psci";
103 compatible = "qcom,kryo260";
105 clocks = <&cpufreq_hw 1>;
106 enable-method = "psci";
107 capacity-dmips-mhz = <1638>;
108 dynamic-power-coefficient = <282>;
109 next-level-cache = <&L2_1>;
110 qcom,freq-domain = <&cpufreq_hw 1>;
111 power-domains = <&CPU_PD4>;
112 power-domain-names = "psci";
114 compatible = "cache";
122 compatible = "qcom,kryo260";
124 clocks = <&cpufreq_hw 1>;
125 capacity-dmips-mhz = <1638>;
126 dynamic-power-coefficient = <282>;
127 enable-method = "psci";
128 next-level-cache = <&L2_1>;
129 qcom,freq-domain = <&cpufreq_hw 1>;
130 power-domains = <&CPU_PD5>;
131 power-domain-names = "psci";
136 compatible = "qcom,kryo260";
138 clocks = <&cpufreq_hw 1>;
139 capacity-dmips-mhz = <1638>;
140 dynamic-power-coefficient = <282>;
141 enable-method = "psci";
142 next-level-cache = <&L2_1>;
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 power-domains = <&CPU_PD6>;
145 power-domain-names = "psci";
150 compatible = "qcom,kryo260";
152 clocks = <&cpufreq_hw 1>;
153 capacity-dmips-mhz = <1638>;
154 dynamic-power-coefficient = <282>;
155 enable-method = "psci";
156 next-level-cache = <&L2_1>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 power-domains = <&CPU_PD7>;
159 power-domain-names = "psci";
201 entry-method = "psci";
203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
204 compatible = "arm,idle-state";
205 idle-state-name = "silver-rail-power-collapse";
206 arm,psci-suspend-param = <0x40000003>;
207 entry-latency-us = <290>;
208 exit-latency-us = <376>;
209 min-residency-us = <1182>;
213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
214 compatible = "arm,idle-state";
215 idle-state-name = "gold-rail-power-collapse";
216 arm,psci-suspend-param = <0x40000003>;
217 entry-latency-us = <297>;
218 exit-latency-us = <324>;
219 min-residency-us = <1110>;
225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
227 compatible = "domain-idle-state";
228 arm,psci-suspend-param = <0x40000022>;
229 entry-latency-us = <360>;
230 exit-latency-us = <421>;
231 min-residency-us = <782>;
234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
236 compatible = "domain-idle-state";
237 arm,psci-suspend-param = <0x41000044>;
238 entry-latency-us = <800>;
239 exit-latency-us = <2118>;
240 min-residency-us = <7376>;
243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
245 compatible = "domain-idle-state";
246 arm,psci-suspend-param = <0x40000042>;
247 entry-latency-us = <314>;
248 exit-latency-us = <345>;
249 min-residency-us = <660>;
252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
254 compatible = "domain-idle-state";
255 arm,psci-suspend-param = <0x41000044>;
256 entry-latency-us = <640>;
257 exit-latency-us = <1654>;
258 min-residency-us = <8094>;
265 compatible = "qcom,scm-sm6115", "qcom,scm";
271 device_type = "memory";
272 /* We expect the bootloader to fill in the size */
273 reg = <0 0x80000000 0 0>;
277 compatible = "arm,armv8-pmuv3";
278 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
282 compatible = "arm,psci-1.0";
285 CPU_PD0: power-domain-cpu0 {
286 #power-domain-cells = <0>;
287 power-domains = <&CLUSTER_0_PD>;
288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
291 CPU_PD1: power-domain-cpu1 {
292 #power-domain-cells = <0>;
293 power-domains = <&CLUSTER_0_PD>;
294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
297 CPU_PD2: power-domain-cpu2 {
298 #power-domain-cells = <0>;
299 power-domains = <&CLUSTER_0_PD>;
300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
303 CPU_PD3: power-domain-cpu3 {
304 #power-domain-cells = <0>;
305 power-domains = <&CLUSTER_0_PD>;
306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
309 CPU_PD4: power-domain-cpu4 {
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_1_PD>;
312 domain-idle-states = <&BIG_CPU_SLEEP_0>;
315 CPU_PD5: power-domain-cpu5 {
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_1_PD>;
318 domain-idle-states = <&BIG_CPU_SLEEP_0>;
321 CPU_PD6: power-domain-cpu6 {
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_1_PD>;
324 domain-idle-states = <&BIG_CPU_SLEEP_0>;
327 CPU_PD7: power-domain-cpu7 {
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_1_PD>;
330 domain-idle-states = <&BIG_CPU_SLEEP_0>;
333 CLUSTER_0_PD: power-domain-cpu-cluster0 {
334 #power-domain-cells = <0>;
335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
338 CLUSTER_1_PD: power-domain-cpu-cluster1 {
339 #power-domain-cells = <0>;
340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
345 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
348 compatible = "qcom,glink-rpm";
350 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
352 mboxes = <&apcs_glb 0>;
354 rpm_requests: rpm-requests {
355 compatible = "qcom,rpm-sm6115";
356 qcom,glink-channels = "rpm_requests";
358 rpmcc: clock-controller {
359 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
360 clocks = <&xo_board>;
365 rpmpd: power-controller {
366 compatible = "qcom,sm6115-rpmpd";
367 #power-domain-cells = <1>;
368 operating-points-v2 = <&rpmpd_opp_table>;
370 rpmpd_opp_table: opp-table {
371 compatible = "operating-points-v2";
373 rpmpd_opp_min_svs: opp1 {
374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
377 rpmpd_opp_low_svs: opp2 {
378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
381 rpmpd_opp_svs: opp3 {
382 opp-level = <RPM_SMD_LEVEL_SVS>;
385 rpmpd_opp_svs_plus: opp4 {
386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
389 rpmpd_opp_nom: opp5 {
390 opp-level = <RPM_SMD_LEVEL_NOM>;
393 rpmpd_opp_nom_plus: opp6 {
394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
397 rpmpd_opp_turbo: opp7 {
398 opp-level = <RPM_SMD_LEVEL_TURBO>;
401 rpmpd_opp_turbo_plus: opp8 {
402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
410 reserved_memory: reserved-memory {
411 #address-cells = <2>;
415 hyp_mem: memory@45700000 {
416 reg = <0x0 0x45700000 0x0 0x600000>;
420 xbl_aop_mem: memory@45e00000 {
421 reg = <0x0 0x45e00000 0x0 0x140000>;
425 sec_apps_mem: memory@45fff000 {
426 reg = <0x0 0x45fff000 0x0 0x1000>;
430 smem_mem: memory@46000000 {
431 compatible = "qcom,smem";
432 reg = <0x0 0x46000000 0x0 0x200000>;
435 hwlocks = <&tcsr_mutex 3>;
436 qcom,rpm-msg-ram = <&rpm_msg_ram>;
439 cdsp_sec_mem: memory@46200000 {
440 reg = <0x0 0x46200000 0x0 0x1e00000>;
444 pil_modem_mem: memory@4ab00000 {
445 reg = <0x0 0x4ab00000 0x0 0x6900000>;
449 pil_video_mem: memory@51400000 {
450 reg = <0x0 0x51400000 0x0 0x500000>;
454 wlan_msa_mem: memory@51900000 {
455 reg = <0x0 0x51900000 0x0 0x100000>;
459 pil_cdsp_mem: memory@51a00000 {
460 reg = <0x0 0x51a00000 0x0 0x1e00000>;
464 pil_adsp_mem: memory@53800000 {
465 reg = <0x0 0x53800000 0x0 0x2800000>;
469 pil_ipa_fw_mem: memory@56100000 {
470 reg = <0x0 0x56100000 0x0 0x10000>;
474 pil_ipa_gsi_mem: memory@56110000 {
475 reg = <0x0 0x56110000 0x0 0x5000>;
479 pil_gpu_mem: memory@56115000 {
480 reg = <0x0 0x56115000 0x0 0x2000>;
484 cont_splash_memory: memory@5c000000 {
485 reg = <0x0 0x5c000000 0x0 0x00f00000>;
489 dfps_data_memory: memory@5cf00000 {
490 reg = <0x0 0x5cf00000 0x0 0x0100000>;
494 removed_mem: memory@60000000 {
495 reg = <0x0 0x60000000 0x0 0x3900000>;
499 rmtfs_mem: memory@89b01000 {
500 compatible = "qcom,rmtfs-mem";
501 reg = <0x0 0x89b01000 0x0 0x200000>;
504 qcom,client-id = <1>;
505 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
510 compatible = "qcom,smp2p";
511 qcom,smem = <443>, <429>;
513 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
515 mboxes = <&apcs_glb 10>;
517 qcom,local-pid = <0>;
518 qcom,remote-pid = <2>;
520 adsp_smp2p_out: master-kernel {
521 qcom,entry-name = "master-kernel";
522 #qcom,smem-state-cells = <1>;
525 adsp_smp2p_in: slave-kernel {
526 qcom,entry-name = "slave-kernel";
528 interrupt-controller;
529 #interrupt-cells = <2>;
534 compatible = "qcom,smp2p";
535 qcom,smem = <94>, <432>;
537 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
539 mboxes = <&apcs_glb 30>;
541 qcom,local-pid = <0>;
542 qcom,remote-pid = <5>;
544 cdsp_smp2p_out: master-kernel {
545 qcom,entry-name = "master-kernel";
546 #qcom,smem-state-cells = <1>;
549 cdsp_smp2p_in: slave-kernel {
550 qcom,entry-name = "slave-kernel";
552 interrupt-controller;
553 #interrupt-cells = <2>;
558 compatible = "qcom,smp2p";
559 qcom,smem = <435>, <428>;
561 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
563 mboxes = <&apcs_glb 14>;
565 qcom,local-pid = <0>;
566 qcom,remote-pid = <1>;
568 modem_smp2p_out: master-kernel {
569 qcom,entry-name = "master-kernel";
570 #qcom,smem-state-cells = <1>;
573 modem_smp2p_in: slave-kernel {
574 qcom,entry-name = "slave-kernel";
576 interrupt-controller;
577 #interrupt-cells = <2>;
582 compatible = "simple-bus";
583 #address-cells = <2>;
585 ranges = <0 0 0 0 0x10 0>;
586 dma-ranges = <0 0 0 0 0x10 0>;
588 tcsr_mutex: hwlock@340000 {
589 compatible = "qcom,tcsr-mutex";
590 reg = <0x0 0x00340000 0x0 0x20000>;
594 tlmm: pinctrl@500000 {
595 compatible = "qcom,sm6115-tlmm";
596 reg = <0x0 0x00500000 0x0 0x400000>,
597 <0x0 0x00900000 0x0 0x400000>,
598 <0x0 0x00d00000 0x0 0x400000>;
599 reg-names = "west", "south", "east";
600 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
602 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
604 interrupt-controller;
605 #interrupt-cells = <2>;
607 qup_i2c0_default: qup-i2c0-default-state {
608 pins = "gpio0", "gpio1";
610 drive-strength = <2>;
614 qup_i2c1_default: qup-i2c1-default-state {
615 pins = "gpio4", "gpio5";
617 drive-strength = <2>;
621 qup_i2c2_default: qup-i2c2-default-state {
622 pins = "gpio6", "gpio7";
624 drive-strength = <2>;
628 qup_i2c3_default: qup-i2c3-default-state {
629 pins = "gpio8", "gpio9";
631 drive-strength = <2>;
635 qup_i2c4_default: qup-i2c4-default-state {
636 pins = "gpio12", "gpio13";
638 drive-strength = <2>;
642 qup_i2c5_default: qup-i2c5-default-state {
643 pins = "gpio14", "gpio15";
645 drive-strength = <2>;
649 qup_spi0_default: qup-spi0-default-state {
650 pins = "gpio0", "gpio1","gpio2", "gpio3";
652 drive-strength = <2>;
656 qup_spi1_default: qup-spi1-default-state {
657 pins = "gpio4", "gpio5", "gpio69", "gpio70";
659 drive-strength = <2>;
663 qup_spi2_default: qup-spi2-default-state {
664 pins = "gpio6", "gpio7", "gpio71", "gpio80";
666 drive-strength = <2>;
670 qup_spi3_default: qup-spi3-default-state {
671 pins = "gpio8", "gpio9", "gpio10", "gpio11";
673 drive-strength = <2>;
677 qup_spi4_default: qup-spi4-default-state {
678 pins = "gpio12", "gpio13", "gpio96", "gpio97";
680 drive-strength = <2>;
684 qup_spi5_default: qup-spi5-default-state {
685 pins = "gpio14", "gpio15", "gpio16", "gpio17";
687 drive-strength = <2>;
691 sdc1_state_on: sdc1-on-state {
695 drive-strength = <16>;
701 drive-strength = <10>;
707 drive-strength = <10>;
716 sdc1_state_off: sdc1-off-state {
720 drive-strength = <2>;
726 drive-strength = <2>;
732 drive-strength = <2>;
741 sdc2_state_on: sdc2-on-state {
745 drive-strength = <16>;
751 drive-strength = <10>;
757 drive-strength = <10>;
761 sdc2_state_off: sdc2-off-state {
765 drive-strength = <2>;
771 drive-strength = <2>;
777 drive-strength = <2>;
782 gcc: clock-controller@1400000 {
783 compatible = "qcom,gcc-sm6115";
784 reg = <0x0 0x01400000 0x0 0x1f0000>;
785 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
786 clock-names = "bi_tcxo", "sleep_clk";
789 #power-domain-cells = <1>;
792 usb_hsphy: phy@1613000 {
793 compatible = "qcom,sm6115-qusb2-phy";
794 reg = <0x0 0x01613000 0x0 0x180>;
797 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
798 clock-names = "cfg_ahb", "ref";
800 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
801 nvmem-cells = <&qusb2_hstx_trim>;
806 cryptobam: dma-controller@1b04000 {
807 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
808 reg = <0x0 0x01b04000 0x0 0x24000>;
809 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
811 clock-names = "bam_clk";
814 qcom,controlled-remotely;
815 iommus = <&apps_smmu 0x92 0>,
816 <&apps_smmu 0x94 0x11>,
817 <&apps_smmu 0x96 0x11>,
818 <&apps_smmu 0x98 0x1>,
822 crypto: crypto@1b3a000 {
823 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
824 reg = <0x0 0x01b3a000 0x0 0x6000>;
825 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
826 clock-names = "core";
828 dmas = <&cryptobam 6>, <&cryptobam 7>;
829 dma-names = "rx", "tx";
830 iommus = <&apps_smmu 0x92 0>,
831 <&apps_smmu 0x94 0x11>,
832 <&apps_smmu 0x96 0x11>,
833 <&apps_smmu 0x98 0x1>,
837 usb_qmpphy: phy@1615000 {
838 compatible = "qcom,sm6115-qmp-usb3-phy";
839 reg = <0x0 0x01615000 0x0 0x1000>;
841 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
842 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
843 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
844 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
845 clock-names = "cfg_ahb",
850 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
851 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
852 reset-names = "phy", "phy_phy";
855 clock-output-names = "usb3_phy_pipe_clk_src";
863 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
864 reg = <0x0 0x01b40000 0x0 0x7000>;
865 #address-cells = <1>;
868 qusb2_hstx_trim: hstx-trim@25b {
873 gpu_speed_bin: gpu-speed-bin@6006 {
880 compatible = "qcom,prng-ee";
881 reg = <0x0 0x01b53000 0x0 0x1000>;
882 clocks = <&gcc GCC_PRNG_AHB_CLK>;
883 clock-names = "core";
886 spmi_bus: spmi@1c40000 {
887 compatible = "qcom,spmi-pmic-arb";
888 reg = <0x0 0x01c40000 0x0 0x1100>,
889 <0x0 0x01e00000 0x0 0x2000000>,
890 <0x0 0x03e00000 0x0 0x100000>,
891 <0x0 0x03f00000 0x0 0xa0000>,
892 <0x0 0x01c0a000 0x0 0x26000>;
893 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
894 interrupt-names = "periph_irq";
895 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
898 #address-cells = <2>;
900 interrupt-controller;
901 #interrupt-cells = <4>;
904 tsens0: thermal-sensor@4411000 {
905 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
906 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
907 <0x0 0x04410000 0x0 0x8>; /* SROT */
908 #qcom,sensors = <16>;
909 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
911 interrupt-names = "uplow", "critical";
912 #thermal-sensor-cells = <1>;
915 rpm_msg_ram: sram@45f0000 {
916 compatible = "qcom,rpm-msg-ram";
917 reg = <0x0 0x045f0000 0x0 0x7000>;
921 compatible = "qcom,rpm-stats";
922 reg = <0x0 0x04690000 0x0 0x10000>;
925 sdhc_1: mmc@4744000 {
926 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
927 reg = <0x0 0x04744000 0x0 0x1000>,
928 <0x0 0x04745000 0x0 0x1000>,
929 <0x0 0x04748000 0x0 0x8000>;
930 reg-names = "hc", "cqhci", "ice";
932 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
934 interrupt-names = "hc_irq", "pwr_irq";
936 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
937 <&gcc GCC_SDCC1_APPS_CLK>,
938 <&rpmcc RPM_SMD_XO_CLK_SRC>,
939 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
940 clock-names = "iface", "core", "xo", "ice";
946 sdhc_2: mmc@4784000 {
947 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
948 reg = <0x0 0x04784000 0x0 0x1000>;
951 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
953 interrupt-names = "hc_irq", "pwr_irq";
955 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
956 <&gcc GCC_SDCC2_APPS_CLK>,
957 <&rpmcc RPM_SMD_XO_CLK_SRC>;
958 clock-names = "iface", "core", "xo";
960 power-domains = <&rpmpd SM6115_VDDCX>;
961 operating-points-v2 = <&sdhc2_opp_table>;
962 iommus = <&apps_smmu 0x00a0 0x0>;
963 resets = <&gcc GCC_SDCC2_BCR>;
966 qcom,dll-config = <0x0007642c>;
967 qcom,ddr-config = <0x80040868>;
970 sdhc2_opp_table: opp-table {
971 compatible = "operating-points-v2";
974 opp-hz = /bits/ 64 <100000000>;
975 required-opps = <&rpmpd_opp_low_svs>;
979 opp-hz = /bits/ 64 <202000000>;
980 required-opps = <&rpmpd_opp_nom>;
985 ufs_mem_hc: ufs@4804000 {
986 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
987 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
988 reg-names = "std", "ice";
989 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
990 phys = <&ufs_mem_phy_lanes>;
991 phy-names = "ufsphy";
992 lanes-per-direction = <1>;
994 resets = <&gcc GCC_UFS_PHY_BCR>;
997 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
998 iommus = <&apps_smmu 0x100 0>;
1000 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1001 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
1002 <&gcc GCC_UFS_PHY_AHB_CLK>,
1003 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1004 <&rpmcc RPM_SMD_XO_CLK_SRC>,
1005 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1006 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1007 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1008 clock-names = "core_clk",
1013 "tx_lane0_sync_clk",
1014 "rx_lane0_sync_clk",
1017 freq-table-hz = <50000000 200000000>,
1020 <37500000 150000000>,
1024 <75000000 300000000>;
1026 status = "disabled";
1029 ufs_mem_phy: phy@4807000 {
1030 compatible = "qcom,sm6115-qmp-ufs-phy";
1031 reg = <0x0 0x04807000 0x0 0x1c4>;
1032 #address-cells = <2>;
1036 clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1037 clock-names = "ref", "ref_aux";
1039 resets = <&ufs_mem_hc 0>;
1040 reset-names = "ufsphy";
1041 status = "disabled";
1043 ufs_mem_phy_lanes: phy@4807400 {
1044 reg = <0x0 0x04807400 0x0 0x098>,
1045 <0x0 0x04807600 0x0 0x130>,
1046 <0x0 0x04807c00 0x0 0x16c>;
1051 gpi_dma0: dma-controller@4a00000 {
1052 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1053 reg = <0x0 0x04a00000 0x0 0x60000>;
1054 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1063 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1064 dma-channels = <10>;
1065 dma-channel-mask = <0xf>;
1066 iommus = <&apps_smmu 0xf6 0x0>;
1068 status = "disabled";
1071 qupv3_id_0: geniqup@4ac0000 {
1072 compatible = "qcom,geni-se-qup";
1073 reg = <0x0 0x04ac0000 0x0 0x2000>;
1074 clock-names = "m-ahb", "s-ahb";
1075 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1076 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1077 #address-cells = <2>;
1079 iommus = <&apps_smmu 0xe3 0x0>;
1081 status = "disabled";
1084 compatible = "qcom,geni-i2c";
1085 reg = <0x0 0x04a80000 0x0 0x4000>;
1087 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_i2c0_default>;
1090 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1091 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1092 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1093 dma-names = "tx", "rx";
1094 #address-cells = <1>;
1096 status = "disabled";
1100 compatible = "qcom,geni-spi";
1101 reg = <0x0 0x04a80000 0x0 0x4000>;
1103 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&qup_spi0_default>;
1106 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1107 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1108 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1109 dma-names = "tx", "rx";
1110 #address-cells = <1>;
1112 status = "disabled";
1116 compatible = "qcom,geni-i2c";
1117 reg = <0x0 0x04a84000 0x0 0x4000>;
1119 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&qup_i2c1_default>;
1122 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1123 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1124 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1125 dma-names = "tx", "rx";
1126 #address-cells = <1>;
1128 status = "disabled";
1132 compatible = "qcom,geni-spi";
1133 reg = <0x0 0x04a84000 0x0 0x4000>;
1135 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&qup_spi1_default>;
1138 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1139 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1140 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1141 dma-names = "tx", "rx";
1142 #address-cells = <1>;
1144 status = "disabled";
1148 compatible = "qcom,geni-i2c";
1149 reg = <0x0 0x04a88000 0x0 0x4000>;
1151 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&qup_i2c2_default>;
1154 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1155 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1156 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1157 dma-names = "tx", "rx";
1158 #address-cells = <1>;
1160 status = "disabled";
1164 compatible = "qcom,geni-spi";
1165 reg = <0x0 0x04a88000 0x0 0x4000>;
1167 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_spi2_default>;
1170 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1171 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1172 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1173 dma-names = "tx", "rx";
1174 #address-cells = <1>;
1176 status = "disabled";
1180 compatible = "qcom,geni-i2c";
1181 reg = <0x0 0x04a8c000 0x0 0x4000>;
1183 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1184 pinctrl-names = "default";
1185 pinctrl-0 = <&qup_i2c3_default>;
1186 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1187 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1188 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1189 dma-names = "tx", "rx";
1190 #address-cells = <1>;
1192 status = "disabled";
1196 compatible = "qcom,geni-spi";
1197 reg = <0x0 0x04a8c000 0x0 0x4000>;
1199 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&qup_spi3_default>;
1202 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1203 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1204 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1205 dma-names = "tx", "rx";
1206 #address-cells = <1>;
1208 status = "disabled";
1212 compatible = "qcom,geni-i2c";
1213 reg = <0x0 0x04a90000 0x0 0x4000>;
1215 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_i2c4_default>;
1218 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1219 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1220 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1221 dma-names = "tx", "rx";
1222 #address-cells = <1>;
1224 status = "disabled";
1228 compatible = "qcom,geni-spi";
1229 reg = <0x0 0x04a90000 0x0 0x4000>;
1231 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_spi4_default>;
1234 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1235 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1236 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1237 dma-names = "tx", "rx";
1238 #address-cells = <1>;
1240 status = "disabled";
1243 uart4: serial@4a90000 {
1244 compatible = "qcom,geni-debug-uart";
1245 reg = <0x0 0x04a90000 0x0 0x4000>;
1247 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1248 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1249 status = "disabled";
1253 compatible = "qcom,geni-i2c";
1254 reg = <0x0 0x04a94000 0x0 0x4000>;
1256 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&qup_i2c5_default>;
1259 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1260 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1261 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1262 dma-names = "tx", "rx";
1263 #address-cells = <1>;
1265 status = "disabled";
1269 compatible = "qcom,geni-spi";
1270 reg = <0x0 0x04a94000 0x0 0x4000>;
1272 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1273 pinctrl-names = "default";
1274 pinctrl-0 = <&qup_spi5_default>;
1275 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1276 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1277 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1278 dma-names = "tx", "rx";
1279 #address-cells = <1>;
1281 status = "disabled";
1286 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1287 reg = <0x0 0x04ef8800 0x0 0x400>;
1288 #address-cells = <2>;
1292 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1293 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1294 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1295 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1296 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1297 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1298 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1300 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1301 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1302 assigned-clock-rates = <19200000>, <66666667>;
1304 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1306 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1308 resets = <&gcc GCC_USB30_PRIM_BCR>;
1309 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1310 qcom,select-utmi-as-pipe-clk;
1311 status = "disabled";
1313 usb_dwc3: usb@4e00000 {
1314 compatible = "snps,dwc3";
1315 reg = <0x0 0x04e00000 0x0 0xcd00>;
1316 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1317 phys = <&usb_hsphy>, <&usb_qmpphy>;
1318 phy-names = "usb2-phy", "usb3-phy";
1319 iommus = <&apps_smmu 0x120 0x0>;
1320 snps,dis_u2_susphy_quirk;
1321 snps,dis_enblslpm_quirk;
1322 snps,has-lpm-erratum;
1323 snps,hird-threshold = /bits/ 8 <0x10>;
1324 snps,usb3_lpm_capable;
1329 compatible = "qcom,adreno-610.0", "qcom,adreno";
1330 reg = <0x0 0x05900000 0x0 0x40000>;
1331 reg-names = "kgsl_3d0_reg_memory";
1333 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1334 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
1335 <&gpucc GPU_CC_AHB_CLK>,
1336 <&gcc GCC_BIMC_GPU_AXI_CLK>,
1337 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1338 <&gpucc GPU_CC_CX_GMU_CLK>,
1339 <&gpucc GPU_CC_CXO_CLK>;
1340 clock-names = "core",
1347 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1349 iommus = <&adreno_smmu 0 1>;
1350 operating-points-v2 = <&gpu_opp_table>;
1351 power-domains = <&rpmpd SM6115_VDDCX>;
1352 qcom,gmu = <&gmu_wrapper>;
1354 nvmem-cells = <&gpu_speed_bin>;
1355 nvmem-cell-names = "speed_bin";
1357 status = "disabled";
1360 memory-region = <&pil_gpu_mem>;
1363 gpu_opp_table: opp-table {
1364 compatible = "operating-points-v2";
1367 opp-hz = /bits/ 64 <320000000>;
1368 required-opps = <&rpmpd_opp_low_svs>;
1369 opp-supported-hw = <0x1f>;
1373 opp-hz = /bits/ 64 <465000000>;
1374 required-opps = <&rpmpd_opp_svs>;
1375 opp-supported-hw = <0x1f>;
1379 opp-hz = /bits/ 64 <600000000>;
1380 required-opps = <&rpmpd_opp_svs_plus>;
1381 opp-supported-hw = <0x1f>;
1385 opp-hz = /bits/ 64 <745000000>;
1386 required-opps = <&rpmpd_opp_nom>;
1387 opp-supported-hw = <0xf>;
1391 opp-hz = /bits/ 64 <820000000>;
1392 required-opps = <&rpmpd_opp_nom_plus>;
1393 opp-supported-hw = <0x7>;
1397 opp-hz = /bits/ 64 <900000000>;
1398 required-opps = <&rpmpd_opp_turbo>;
1399 opp-supported-hw = <0x7>;
1402 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
1404 opp-hz = /bits/ 64 <950000000>;
1405 required-opps = <&rpmpd_opp_turbo_plus>;
1406 opp-supported-hw = <0x4>;
1410 opp-hz = /bits/ 64 <980000000>;
1411 required-opps = <&rpmpd_opp_turbo_plus>;
1412 opp-supported-hw = <0x3>;
1417 gmu_wrapper: gmu@596a000 {
1418 compatible = "qcom,adreno-gmu-wrapper";
1419 reg = <0x0 0x0596a000 0x0 0x30000>;
1421 power-domains = <&gpucc GPU_CX_GDSC>,
1422 <&gpucc GPU_GX_GDSC>;
1423 power-domain-names = "cx", "gx";
1426 gpucc: clock-controller@5990000 {
1427 compatible = "qcom,sm6115-gpucc";
1428 reg = <0x0 0x05990000 0x0 0x9000>;
1429 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1430 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1431 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1434 #power-domain-cells = <1>;
1437 adreno_smmu: iommu@59a0000 {
1438 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1439 "qcom,smmu-500", "arm,mmu-500";
1440 reg = <0x0 0x059a0000 0x0 0x10000>;
1441 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1451 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1452 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1453 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1454 clock-names = "mem",
1457 power-domains = <&gpucc GPU_CX_GDSC>;
1459 #global-interrupts = <1>;
1463 mdss: display-subsystem@5e00000 {
1464 compatible = "qcom,sm6115-mdss";
1465 reg = <0x0 0x05e00000 0x0 0x1000>;
1468 power-domains = <&dispcc MDSS_GDSC>;
1470 clocks = <&gcc GCC_DISP_AHB_CLK>,
1471 <&gcc GCC_DISP_HF_AXI_CLK>,
1472 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1474 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1475 interrupt-controller;
1476 #interrupt-cells = <1>;
1478 iommus = <&apps_smmu 0x420 0x2>,
1479 <&apps_smmu 0x421 0x0>;
1481 #address-cells = <2>;
1485 status = "disabled";
1487 mdp: display-controller@5e01000 {
1488 compatible = "qcom,sm6115-dpu";
1489 reg = <0x0 0x05e01000 0x0 0x8f000>,
1490 <0x0 0x05eb0000 0x0 0x2008>;
1491 reg-names = "mdp", "vbif";
1493 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1494 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1495 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1496 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1497 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1498 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1499 clock-names = "bus",
1506 operating-points-v2 = <&mdp_opp_table>;
1507 power-domains = <&rpmpd SM6115_VDDCX>;
1509 interrupt-parent = <&mdss>;
1513 #address-cells = <1>;
1518 dpu_intf1_out: endpoint {
1519 remote-endpoint = <&mdss_dsi0_in>;
1524 mdp_opp_table: opp-table {
1525 compatible = "operating-points-v2";
1528 opp-hz = /bits/ 64 <19200000>;
1529 required-opps = <&rpmpd_opp_min_svs>;
1533 opp-hz = /bits/ 64 <192000000>;
1534 required-opps = <&rpmpd_opp_low_svs>;
1538 opp-hz = /bits/ 64 <256000000>;
1539 required-opps = <&rpmpd_opp_svs>;
1543 opp-hz = /bits/ 64 <307200000>;
1544 required-opps = <&rpmpd_opp_svs_plus>;
1548 opp-hz = /bits/ 64 <384000000>;
1549 required-opps = <&rpmpd_opp_nom>;
1554 mdss_dsi0: dsi@5e94000 {
1555 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1556 reg = <0x0 0x05e94000 0x0 0x400>;
1557 reg-names = "dsi_ctrl";
1559 interrupt-parent = <&mdss>;
1562 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1563 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1564 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1565 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1566 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1567 <&gcc GCC_DISP_HF_AXI_CLK>;
1568 clock-names = "byte",
1575 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1576 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1577 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1579 operating-points-v2 = <&dsi_opp_table>;
1580 power-domains = <&rpmpd SM6115_VDDCX>;
1581 phys = <&mdss_dsi0_phy>;
1583 #address-cells = <1>;
1586 status = "disabled";
1589 #address-cells = <1>;
1594 mdss_dsi0_in: endpoint {
1595 remote-endpoint = <&dpu_intf1_out>;
1601 mdss_dsi0_out: endpoint {
1606 dsi_opp_table: opp-table {
1607 compatible = "operating-points-v2";
1610 opp-hz = /bits/ 64 <19200000>;
1611 required-opps = <&rpmpd_opp_min_svs>;
1615 opp-hz = /bits/ 64 <164000000>;
1616 required-opps = <&rpmpd_opp_low_svs>;
1620 opp-hz = /bits/ 64 <187500000>;
1621 required-opps = <&rpmpd_opp_svs>;
1626 mdss_dsi0_phy: phy@5e94400 {
1627 compatible = "qcom,dsi-phy-14nm-2290";
1628 reg = <0x0 0x05e94400 0x0 0x100>,
1629 <0x0 0x05e94500 0x0 0x300>,
1630 <0x0 0x05e94800 0x0 0x188>;
1631 reg-names = "dsi_phy",
1638 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1639 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1640 clock-names = "iface", "ref";
1642 status = "disabled";
1646 dispcc: clock-controller@5f00000 {
1647 compatible = "qcom,sm6115-dispcc";
1648 reg = <0x0 0x05f00000 0 0x20000>;
1649 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1653 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
1656 #power-domain-cells = <1>;
1659 remoteproc_mpss: remoteproc@6080000 {
1660 compatible = "qcom,sm6115-mpss-pas";
1661 reg = <0x0 0x06080000 0x0 0x100>;
1663 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1664 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1665 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1666 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1667 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1668 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1669 interrupt-names = "wdog", "fatal", "ready", "handover",
1670 "stop-ack", "shutdown-ack";
1672 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1675 power-domains = <&rpmpd SM6115_VDDCX>;
1677 memory-region = <&pil_modem_mem>;
1679 qcom,smem-states = <&modem_smp2p_out 0>;
1680 qcom,smem-state-names = "stop";
1682 status = "disabled";
1685 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1687 qcom,remote-pid = <1>;
1688 mboxes = <&apcs_glb 12>;
1693 compatible = "arm,coresight-stm", "arm,primecell";
1694 reg = <0x0 0x08002000 0x0 0x1000>,
1695 <0x0 0x0e280000 0x0 0x180000>;
1696 reg-names = "stm-base", "stm-stimulus-base";
1698 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1699 clock-names = "apb_pclk";
1701 status = "disabled";
1706 remote-endpoint = <&funnel_in0_in>;
1713 compatible = "arm,coresight-cti", "arm,primecell";
1714 reg = <0x0 0x08010000 0x0 0x1000>;
1716 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1717 clock-names = "apb_pclk";
1719 status = "disabled";
1723 compatible = "arm,coresight-cti", "arm,primecell";
1724 reg = <0x0 0x08011000 0x0 0x1000>;
1726 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1727 clock-names = "apb_pclk";
1729 status = "disabled";
1733 compatible = "arm,coresight-cti", "arm,primecell";
1734 reg = <0x0 0x08012000 0x0 0x1000>;
1736 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1737 clock-names = "apb_pclk";
1739 status = "disabled";
1743 compatible = "arm,coresight-cti", "arm,primecell";
1744 reg = <0x0 0x08013000 0x0 0x1000>;
1746 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1747 clock-names = "apb_pclk";
1749 status = "disabled";
1753 compatible = "arm,coresight-cti", "arm,primecell";
1754 reg = <0x0 0x08014000 0x0 0x1000>;
1756 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1757 clock-names = "apb_pclk";
1759 status = "disabled";
1763 compatible = "arm,coresight-cti", "arm,primecell";
1764 reg = <0x0 0x08015000 0x0 0x1000>;
1766 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1767 clock-names = "apb_pclk";
1769 status = "disabled";
1773 compatible = "arm,coresight-cti", "arm,primecell";
1774 reg = <0x0 0x08016000 0x0 0x1000>;
1776 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1777 clock-names = "apb_pclk";
1779 status = "disabled";
1783 compatible = "arm,coresight-cti", "arm,primecell";
1784 reg = <0x0 0x08017000 0x0 0x1000>;
1786 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1787 clock-names = "apb_pclk";
1789 status = "disabled";
1793 compatible = "arm,coresight-cti", "arm,primecell";
1794 reg = <0x0 0x08018000 0x0 0x1000>;
1796 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1797 clock-names = "apb_pclk";
1799 status = "disabled";
1803 compatible = "arm,coresight-cti", "arm,primecell";
1804 reg = <0x0 0x08019000 0x0 0x1000>;
1806 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1807 clock-names = "apb_pclk";
1809 status = "disabled";
1812 cti10: cti@801a000 {
1813 compatible = "arm,coresight-cti", "arm,primecell";
1814 reg = <0x0 0x0801a000 0x0 0x1000>;
1816 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1817 clock-names = "apb_pclk";
1819 status = "disabled";
1822 cti11: cti@801b000 {
1823 compatible = "arm,coresight-cti", "arm,primecell";
1824 reg = <0x0 0x0801b000 0x0 0x1000>;
1826 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1827 clock-names = "apb_pclk";
1829 status = "disabled";
1832 cti12: cti@801c000 {
1833 compatible = "arm,coresight-cti", "arm,primecell";
1834 reg = <0x0 0x0801c000 0x0 0x1000>;
1836 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1837 clock-names = "apb_pclk";
1839 status = "disabled";
1842 cti13: cti@801d000 {
1843 compatible = "arm,coresight-cti", "arm,primecell";
1844 reg = <0x0 0x0801d000 0x0 0x1000>;
1846 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1847 clock-names = "apb_pclk";
1849 status = "disabled";
1852 cti14: cti@801e000 {
1853 compatible = "arm,coresight-cti", "arm,primecell";
1854 reg = <0x0 0x0801e000 0x0 0x1000>;
1856 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1857 clock-names = "apb_pclk";
1859 status = "disabled";
1862 cti15: cti@801f000 {
1863 compatible = "arm,coresight-cti", "arm,primecell";
1864 reg = <0x0 0x0801f000 0x0 0x1000>;
1866 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1867 clock-names = "apb_pclk";
1869 status = "disabled";
1872 replicator@8046000 {
1873 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1874 reg = <0x0 0x08046000 0x0 0x1000>;
1876 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1877 clock-names = "apb_pclk";
1879 status = "disabled";
1883 replicator_out: endpoint {
1884 remote-endpoint = <&etr_in>;
1891 replicator_in: endpoint {
1892 remote-endpoint = <&etf_out>;
1899 compatible = "arm,coresight-tmc", "arm,primecell";
1900 reg = <0x0 0x08047000 0x0 0x1000>;
1902 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1903 clock-names = "apb_pclk";
1905 status = "disabled";
1910 remote-endpoint = <&merge_funnel_out>;
1918 remote-endpoint = <&replicator_in>;
1925 compatible = "arm,coresight-tmc", "arm,primecell";
1926 reg = <0x0 0x08048000 0x0 0x1000>;
1928 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1929 clock-names = "apb_pclk";
1931 status = "disabled";
1936 remote-endpoint = <&replicator_out>;
1943 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1944 reg = <0x0 0x08041000 0x0 0x1000>;
1946 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1947 clock-names = "apb_pclk";
1949 status = "disabled";
1953 funnel_in0_out: endpoint {
1954 remote-endpoint = <&merge_funnel_in0>;
1961 funnel_in0_in: endpoint {
1962 remote-endpoint = <&stm_out>;
1969 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1970 reg = <0x0 0x08042000 0x0 0x1000>;
1972 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1973 clock-names = "apb_pclk";
1975 status = "disabled";
1979 funnel_in1_out: endpoint {
1980 remote-endpoint = <&merge_funnel_in1>;
1987 funnel_in1_in: endpoint {
1988 remote-endpoint = <&funnel_apss1_out>;
1995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1996 reg = <0x0 0x08045000 0x0 0x1000>;
1998 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
1999 clock-names = "apb_pclk";
2001 status = "disabled";
2005 merge_funnel_out: endpoint {
2006 remote-endpoint = <&etf_in>;
2012 #address-cells = <1>;
2017 merge_funnel_in0: endpoint {
2018 remote-endpoint = <&funnel_in0_out>;
2024 merge_funnel_in1: endpoint {
2025 remote-endpoint = <&funnel_in1_out>;
2032 compatible = "arm,coresight-etm4x", "arm,primecell";
2033 reg = <0x0 0x09040000 0x0 0x1000>;
2035 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2036 clock-names = "apb_pclk";
2037 arm,coresight-loses-context-with-cpu;
2041 status = "disabled";
2045 etm0_out: endpoint {
2046 remote-endpoint = <&funnel_apss0_in0>;
2053 compatible = "arm,coresight-etm4x", "arm,primecell";
2054 reg = <0x0 0x09140000 0x0 0x1000>;
2056 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2057 clock-names = "apb_pclk";
2058 arm,coresight-loses-context-with-cpu;
2062 status = "disabled";
2066 etm1_out: endpoint {
2067 remote-endpoint = <&funnel_apss0_in1>;
2074 compatible = "arm,coresight-etm4x", "arm,primecell";
2075 reg = <0x0 0x09240000 0x0 0x1000>;
2077 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2078 clock-names = "apb_pclk";
2079 arm,coresight-loses-context-with-cpu;
2083 status = "disabled";
2087 etm2_out: endpoint {
2088 remote-endpoint = <&funnel_apss0_in2>;
2095 compatible = "arm,coresight-etm4x", "arm,primecell";
2096 reg = <0x0 0x09340000 0x0 0x1000>;
2098 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2099 clock-names = "apb_pclk";
2100 arm,coresight-loses-context-with-cpu;
2104 status = "disabled";
2108 etm3_out: endpoint {
2109 remote-endpoint = <&funnel_apss0_in3>;
2116 compatible = "arm,coresight-etm4x", "arm,primecell";
2117 reg = <0x0 0x09440000 0x0 0x1000>;
2119 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2120 clock-names = "apb_pclk";
2121 arm,coresight-loses-context-with-cpu;
2125 status = "disabled";
2129 etm4_out: endpoint {
2130 remote-endpoint = <&funnel_apss0_in4>;
2137 compatible = "arm,coresight-etm4x", "arm,primecell";
2138 reg = <0x0 0x09540000 0x0 0x1000>;
2140 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2141 clock-names = "apb_pclk";
2142 arm,coresight-loses-context-with-cpu;
2146 status = "disabled";
2150 etm5_out: endpoint {
2151 remote-endpoint = <&funnel_apss0_in5>;
2158 compatible = "arm,coresight-etm4x", "arm,primecell";
2159 reg = <0x0 0x09640000 0x0 0x1000>;
2161 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2162 clock-names = "apb_pclk";
2163 arm,coresight-loses-context-with-cpu;
2167 status = "disabled";
2171 etm6_out: endpoint {
2172 remote-endpoint = <&funnel_apss0_in6>;
2179 compatible = "arm,coresight-etm4x", "arm,primecell";
2180 reg = <0x0 0x09740000 0x0 0x1000>;
2182 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2183 clock-names = "apb_pclk";
2184 arm,coresight-loses-context-with-cpu;
2188 status = "disabled";
2192 etm7_out: endpoint {
2193 remote-endpoint = <&funnel_apss0_in7>;
2200 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2201 reg = <0x0 0x09800000 0x0 0x1000>;
2203 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2204 clock-names = "apb_pclk";
2206 status = "disabled";
2210 funnel_apss0_out: endpoint {
2211 remote-endpoint = <&funnel_apss1_in>;
2217 #address-cells = <1>;
2222 funnel_apss0_in0: endpoint {
2223 remote-endpoint = <&etm0_out>;
2229 funnel_apss0_in1: endpoint {
2230 remote-endpoint = <&etm1_out>;
2236 funnel_apss0_in2: endpoint {
2237 remote-endpoint = <&etm2_out>;
2243 funnel_apss0_in3: endpoint {
2244 remote-endpoint = <&etm3_out>;
2250 funnel_apss0_in4: endpoint {
2251 remote-endpoint = <&etm4_out>;
2257 funnel_apss0_in5: endpoint {
2258 remote-endpoint = <&etm5_out>;
2264 funnel_apss0_in6: endpoint {
2265 remote-endpoint = <&etm6_out>;
2271 funnel_apss0_in7: endpoint {
2272 remote-endpoint = <&etm7_out>;
2279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2280 reg = <0x0 0x09810000 0x0 0x1000>;
2282 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2283 clock-names = "apb_pclk";
2285 status = "disabled";
2289 funnel_apss1_out: endpoint {
2290 remote-endpoint = <&funnel_in1_in>;
2297 funnel_apss1_in: endpoint {
2298 remote-endpoint = <&funnel_apss0_out>;
2304 remoteproc_adsp: remoteproc@ab00000 {
2305 compatible = "qcom,sm6115-adsp-pas";
2306 reg = <0x0 0x0ab00000 0x0 0x100>;
2308 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2309 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2310 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2311 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2312 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2313 interrupt-names = "wdog", "fatal", "ready",
2314 "handover", "stop-ack";
2316 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2319 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2320 <&rpmpd SM6115_VDD_LPI_MX>;
2322 memory-region = <&pil_adsp_mem>;
2324 qcom,smem-states = <&adsp_smp2p_out 0>;
2325 qcom,smem-state-names = "stop";
2327 status = "disabled";
2330 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2332 qcom,remote-pid = <2>;
2333 mboxes = <&apcs_glb 8>;
2336 compatible = "qcom,fastrpc";
2337 qcom,glink-channels = "fastrpcglink-apps-dsp";
2339 qcom,non-secure-domain;
2340 #address-cells = <1>;
2344 compatible = "qcom,fastrpc-compute-cb";
2346 iommus = <&apps_smmu 0x01c3 0x0>;
2350 compatible = "qcom,fastrpc-compute-cb";
2352 iommus = <&apps_smmu 0x01c4 0x0>;
2356 compatible = "qcom,fastrpc-compute-cb";
2358 iommus = <&apps_smmu 0x01c5 0x0>;
2362 compatible = "qcom,fastrpc-compute-cb";
2364 iommus = <&apps_smmu 0x01c6 0x0>;
2368 compatible = "qcom,fastrpc-compute-cb";
2370 iommus = <&apps_smmu 0x01c7 0x0>;
2376 remoteproc_cdsp: remoteproc@b300000 {
2377 compatible = "qcom,sm6115-cdsp-pas";
2378 reg = <0x0 0x0b300000 0x0 0x100000>;
2380 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2381 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2382 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2383 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2384 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2385 interrupt-names = "wdog", "fatal", "ready",
2386 "handover", "stop-ack";
2388 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2391 power-domains = <&rpmpd SM6115_VDDCX>;
2393 memory-region = <&pil_cdsp_mem>;
2395 qcom,smem-states = <&cdsp_smp2p_out 0>;
2396 qcom,smem-state-names = "stop";
2398 status = "disabled";
2401 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2403 qcom,remote-pid = <5>;
2404 mboxes = <&apcs_glb 28>;
2407 compatible = "qcom,fastrpc";
2408 qcom,glink-channels = "fastrpcglink-apps-dsp";
2410 qcom,non-secure-domain;
2411 #address-cells = <1>;
2415 compatible = "qcom,fastrpc-compute-cb";
2417 iommus = <&apps_smmu 0x0c01 0x0>;
2421 compatible = "qcom,fastrpc-compute-cb";
2423 iommus = <&apps_smmu 0x0c02 0x0>;
2427 compatible = "qcom,fastrpc-compute-cb";
2429 iommus = <&apps_smmu 0x0c03 0x0>;
2433 compatible = "qcom,fastrpc-compute-cb";
2435 iommus = <&apps_smmu 0x0c04 0x0>;
2439 compatible = "qcom,fastrpc-compute-cb";
2441 iommus = <&apps_smmu 0x0c05 0x0>;
2445 compatible = "qcom,fastrpc-compute-cb";
2447 iommus = <&apps_smmu 0x0c06 0x0>;
2450 /* note: secure cb9 in downstream */
2455 apps_smmu: iommu@c600000 {
2456 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2457 reg = <0x0 0x0c600000 0x0 0x80000>;
2459 #global-interrupts = <1>;
2461 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
2462 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
2463 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
2464 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
2465 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
2466 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
2467 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
2468 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
2469 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2470 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2471 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2472 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2473 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2474 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2475 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2476 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2477 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2478 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2479 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2480 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2481 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2482 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2483 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2484 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2485 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2486 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2487 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2488 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2489 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2490 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2491 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2492 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2493 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
2494 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
2495 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
2496 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
2497 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2498 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2499 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2500 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2501 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2502 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2503 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2504 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2505 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2506 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2507 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2508 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2509 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2510 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2511 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
2512 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
2513 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2514 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2515 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2516 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2517 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2518 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2519 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2520 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2521 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2522 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2523 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2524 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2525 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2528 wifi: wifi@c800000 {
2529 compatible = "qcom,wcn3990-wifi";
2530 reg = <0x0 0x0c800000 0x0 0x800000>;
2531 reg-names = "membase";
2532 memory-region = <&wlan_msa_mem>;
2533 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
2534 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
2535 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
2536 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
2537 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
2538 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
2539 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
2540 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
2541 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
2542 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
2543 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
2544 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2545 iommus = <&apps_smmu 0x1a0 0x1>;
2546 qcom,msa-fixed-perm;
2547 status = "disabled";
2551 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2552 reg = <0x0 0x0f017000 0x0 0x1000>;
2553 clocks = <&sleep_clk>;
2554 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2557 apcs_glb: mailbox@f111000 {
2558 compatible = "qcom,sm6115-apcs-hmss-global",
2559 "qcom,msm8994-apcs-kpss-global";
2560 reg = <0x0 0x0f111000 0x0 0x1000>;
2566 compatible = "arm,armv7-timer-mem";
2567 reg = <0x0 0x0f120000 0x0 0x1000>;
2568 #address-cells = <2>;
2571 clock-frequency = <19200000>;
2574 reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
2576 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2577 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2581 reg = <0x0 0x0f123000 0x0 0x1000>;
2583 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2584 status = "disabled";
2588 reg = <0x0 0x0f124000 0x0 0x1000>;
2590 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2591 status = "disabled";
2595 reg = <0x0 0x0f125000 0x0 0x1000>;
2597 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2598 status = "disabled";
2602 reg = <0x0 0x0f126000 0x0 0x1000>;
2604 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2605 status = "disabled";
2609 reg = <0x0 0x0f127000 0x0 0x1000>;
2611 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2612 status = "disabled";
2616 reg = <0x0 0x0f128000 0x0 0x1000>;
2618 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2619 status = "disabled";
2623 intc: interrupt-controller@f200000 {
2624 compatible = "arm,gic-v3";
2625 reg = <0x0 0x0f200000 0x0 0x10000>,
2626 <0x0 0x0f300000 0x0 0x100000>;
2627 #interrupt-cells = <3>;
2628 interrupt-controller;
2629 interrupt-parent = <&intc>;
2630 #redistributor-regions = <1>;
2631 redistributor-stride = <0x0 0x20000>;
2632 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2635 cpufreq_hw: cpufreq@f521000 {
2636 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2637 reg = <0x0 0x0f521000 0x0 0x1000>,
2638 <0x0 0x0f523000 0x0 0x1000>;
2640 reg-names = "freq-domain0", "freq-domain1";
2641 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2642 clock-names = "xo", "alternate";
2644 #freq-domain-cells = <1>;
2651 polling-delay-passive = <0>;
2652 polling-delay = <0>;
2653 thermal-sensors = <&tsens0 0>;
2657 temperature = <115000>;
2658 hysteresis = <5000>;
2663 temperature = <125000>;
2664 hysteresis = <1000>;
2671 polling-delay-passive = <0>;
2672 polling-delay = <0>;
2673 thermal-sensors = <&tsens0 1>;
2677 temperature = <115000>;
2678 hysteresis = <5000>;
2683 temperature = <125000>;
2684 hysteresis = <1000>;
2691 polling-delay-passive = <0>;
2692 polling-delay = <0>;
2693 thermal-sensors = <&tsens0 2>;
2697 temperature = <115000>;
2698 hysteresis = <5000>;
2703 temperature = <125000>;
2704 hysteresis = <1000>;
2711 polling-delay-passive = <0>;
2712 polling-delay = <0>;
2713 thermal-sensors = <&tsens0 3>;
2717 temperature = <115000>;
2718 hysteresis = <5000>;
2723 temperature = <125000>;
2724 hysteresis = <1000>;
2731 polling-delay-passive = <0>;
2732 polling-delay = <0>;
2733 thermal-sensors = <&tsens0 4>;
2737 temperature = <115000>;
2738 hysteresis = <5000>;
2743 temperature = <125000>;
2744 hysteresis = <1000>;
2751 polling-delay-passive = <0>;
2752 polling-delay = <0>;
2753 thermal-sensors = <&tsens0 5>;
2757 temperature = <115000>;
2758 hysteresis = <5000>;
2763 temperature = <125000>;
2764 hysteresis = <1000>;
2771 polling-delay-passive = <0>;
2772 polling-delay = <0>;
2773 thermal-sensors = <&tsens0 6>;
2776 cpu4_alert0: trip-point0 {
2777 temperature = <90000>;
2778 hysteresis = <2000>;
2782 cpu4_alert1: trip-point1 {
2783 temperature = <95000>;
2784 hysteresis = <2000>;
2788 cpu4_crit: cpu_crit {
2789 temperature = <110000>;
2790 hysteresis = <1000>;
2797 polling-delay-passive = <0>;
2798 polling-delay = <0>;
2799 thermal-sensors = <&tsens0 7>;
2802 cpu5_alert0: trip-point0 {
2803 temperature = <90000>;
2804 hysteresis = <2000>;
2808 cpu5_alert1: trip-point1 {
2809 temperature = <95000>;
2810 hysteresis = <2000>;
2814 cpu5_crit: cpu_crit {
2815 temperature = <110000>;
2816 hysteresis = <1000>;
2823 polling-delay-passive = <0>;
2824 polling-delay = <0>;
2825 thermal-sensors = <&tsens0 8>;
2828 cpu6_alert0: trip-point0 {
2829 temperature = <90000>;
2830 hysteresis = <2000>;
2834 cpu6_alert1: trip-point1 {
2835 temperature = <95000>;
2836 hysteresis = <2000>;
2840 cpu6_crit: cpu_crit {
2841 temperature = <110000>;
2842 hysteresis = <1000>;
2849 polling-delay-passive = <0>;
2850 polling-delay = <0>;
2851 thermal-sensors = <&tsens0 9>;
2854 cpu7_alert0: trip-point0 {
2855 temperature = <90000>;
2856 hysteresis = <2000>;
2860 cpu7_alert1: trip-point1 {
2861 temperature = <95000>;
2862 hysteresis = <2000>;
2866 cpu7_crit: cpu_crit {
2867 temperature = <110000>;
2868 hysteresis = <1000>;
2875 polling-delay-passive = <0>;
2876 polling-delay = <0>;
2877 thermal-sensors = <&tsens0 10>;
2880 cpu45_alert0: trip-point0 {
2881 temperature = <90000>;
2882 hysteresis = <2000>;
2886 cpu45_alert1: trip-point1 {
2887 temperature = <95000>;
2888 hysteresis = <2000>;
2892 cpu45_crit: cpu_crit {
2893 temperature = <110000>;
2894 hysteresis = <1000>;
2901 polling-delay-passive = <0>;
2902 polling-delay = <0>;
2903 thermal-sensors = <&tsens0 11>;
2906 cpu67_alert0: trip-point0 {
2907 temperature = <90000>;
2908 hysteresis = <2000>;
2912 cpu67_alert1: trip-point1 {
2913 temperature = <95000>;
2914 hysteresis = <2000>;
2918 cpu67_crit: cpu_crit {
2919 temperature = <110000>;
2920 hysteresis = <1000>;
2927 polling-delay-passive = <0>;
2928 polling-delay = <0>;
2929 thermal-sensors = <&tsens0 12>;
2932 cpu0123_alert0: trip-point0 {
2933 temperature = <90000>;
2934 hysteresis = <2000>;
2938 cpu0123_alert1: trip-point1 {
2939 temperature = <95000>;
2940 hysteresis = <2000>;
2944 cpu0123_crit: cpu_crit {
2945 temperature = <110000>;
2946 hysteresis = <1000>;
2953 polling-delay-passive = <0>;
2954 polling-delay = <0>;
2955 thermal-sensors = <&tsens0 13>;
2959 temperature = <115000>;
2960 hysteresis = <5000>;
2965 temperature = <125000>;
2966 hysteresis = <1000>;
2973 polling-delay-passive = <0>;
2974 polling-delay = <0>;
2975 thermal-sensors = <&tsens0 14>;
2979 temperature = <115000>;
2980 hysteresis = <5000>;
2985 temperature = <125000>;
2986 hysteresis = <1000>;
2993 polling-delay-passive = <0>;
2994 polling-delay = <0>;
2995 thermal-sensors = <&tsens0 15>;
2999 temperature = <115000>;
3000 hysteresis = <5000>;
3005 temperature = <125000>;
3006 hysteresis = <1000>;
3014 compatible = "arm,armv8-timer";
3015 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3016 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3017 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3018 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;