1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <76800000>;
24 sleep_clk: sleep-clk {
25 compatible = "fixed-clock";
26 clock-frequency = <32000>;
37 compatible = "arm,cortex-a55";
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
41 power-domains = <&CPU_PD0>;
42 power-domain-names = "psci";
49 next-level-cache = <&L3_0>;
61 compatible = "arm,cortex-a55";
63 enable-method = "psci";
64 next-level-cache = <&L2_100>;
65 power-domains = <&CPU_PD0>;
66 power-domain-names = "psci";
73 next-level-cache = <&L3_0>;
79 compatible = "arm,cortex-a55";
81 enable-method = "psci";
82 next-level-cache = <&L2_200>;
83 power-domains = <&CPU_PD0>;
84 power-domain-names = "psci";
91 next-level-cache = <&L3_0>;
97 compatible = "arm,cortex-a55";
99 enable-method = "psci";
100 next-level-cache = <&L2_300>;
101 power-domains = <&CPU_PD0>;
102 power-domain-names = "psci";
103 #cooling-cells = <2>;
106 compatible = "cache";
109 next-level-cache = <&L3_0>;
115 compatible = "arm,cortex-a55";
117 enable-method = "psci";
118 next-level-cache = <&L2_400>;
119 power-domains = <&CPU_PD0>;
120 power-domain-names = "psci";
121 #cooling-cells = <2>;
124 compatible = "cache";
127 next-level-cache = <&L3_0>;
133 compatible = "arm,cortex-a55";
135 enable-method = "psci";
136 next-level-cache = <&L2_500>;
137 power-domains = <&CPU_PD0>;
138 power-domain-names = "psci";
139 #cooling-cells = <2>;
142 compatible = "cache";
145 next-level-cache = <&L3_0>;
151 compatible = "arm,cortex-a78";
153 enable-method = "psci";
154 next-level-cache = <&L2_600>;
155 power-domains = <&CPU_PD0>;
156 power-domain-names = "psci";
157 #cooling-cells = <2>;
160 compatible = "cache";
163 next-level-cache = <&L3_0>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 next-level-cache = <&L2_700>;
173 power-domains = <&CPU_PD0>;
174 power-domain-names = "psci";
175 #cooling-cells = <2>;
178 compatible = "cache";
181 next-level-cache = <&L3_0>;
222 entry-method = "psci";
224 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
225 compatible = "arm,idle-state";
226 arm,psci-suspend-param = <0x40000004>;
227 entry-latency-us = <800>;
228 exit-latency-us = <750>;
229 min-residency-us = <4090>;
233 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
234 compatible = "arm,idle-state";
235 arm,psci-suspend-param = <0x40000004>;
236 entry-latency-us = <600>;
237 exit-latency-us = <1550>;
238 min-residency-us = <4791>;
244 CLUSTER_SLEEP_0: cluster-sleep-0 {
245 compatible = "domain-idle-state";
246 arm,psci-suspend-param = <0x41000044>;
247 entry-latency-us = <1050>;
248 exit-latency-us = <2500>;
249 min-residency-us = <5309>;
252 CLUSTER_SLEEP_1: cluster-sleep-1 {
253 compatible = "domain-idle-state";
254 arm,psci-suspend-param = <0x41003344>;
255 entry-latency-us = <1561>;
256 exit-latency-us = <2801>;
257 min-residency-us = <8550>;
263 device_type = "memory";
264 /* We expect the bootloader to fill in the size */
265 reg = <0x0 0xa0000000 0x0 0x0>;
269 compatible = "arm,armv8-pmuv3";
270 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
274 compatible = "arm,psci-1.0";
277 CPU_PD0: power-domain-cpu0 {
278 #power-domain-cells = <0>;
279 power-domains = <&CLUSTER_PD>;
280 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
283 CPU_PD1: power-domain-cpu1 {
284 #power-domain-cells = <0>;
285 power-domains = <&CLUSTER_PD>;
286 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
289 CPU_PD2: power-domain-cpu2 {
290 #power-domain-cells = <0>;
291 power-domains = <&CLUSTER_PD>;
292 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
295 CPU_PD3: power-domain-cpu3 {
296 #power-domain-cells = <0>;
297 power-domains = <&CLUSTER_PD>;
298 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
301 CPU_PD4: power-domain-cpu4 {
302 #power-domain-cells = <0>;
303 power-domains = <&CLUSTER_PD>;
304 domain-idle-states = <&BIG_CPU_SLEEP_0>;
307 CPU_PD5: power-domain-cpu5 {
308 #power-domain-cells = <0>;
309 power-domains = <&CLUSTER_PD>;
310 domain-idle-states = <&BIG_CPU_SLEEP_0>;
313 CPU_PD6: power-domain-cpu6 {
314 #power-domain-cells = <0>;
315 power-domains = <&CLUSTER_PD>;
316 domain-idle-states = <&BIG_CPU_SLEEP_0>;
319 CPU_PD7: power-domain-cpu7 {
320 #power-domain-cells = <0>;
321 power-domains = <&CLUSTER_PD>;
322 domain-idle-states = <&BIG_CPU_SLEEP_0>;
325 CLUSTER_PD: power-domain-cpu-cluster0 {
326 #power-domain-cells = <0>;
327 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
332 #address-cells = <2>;
334 ranges = <0 0 0 0 0x10 0>;
335 dma-ranges = <0 0 0 0 0x10 0>;
336 compatible = "simple-bus";
338 tcsr_mutex: hwlock@1f40000 {
339 compatible = "qcom,tcsr-mutex";
340 reg = <0x0 0x01f40000 0x0 0x40000>;
344 pdc: interrupt-controller@b220000 {
345 compatible = "qcom,sm4450-pdc", "qcom,pdc";
346 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
347 qcom,pdc-ranges = <0 480 94>, <94 494 31>,
349 #interrupt-cells = <2>;
350 interrupt-parent = <&intc>;
351 interrupt-controller;
354 intc: interrupt-controller@17200000 {
355 compatible = "arm,gic-v3";
356 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
357 <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
358 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
359 #interrupt-cells = <3>;
360 interrupt-controller;
361 #redistributor-regions = <1>;
362 redistributor-stride = <0x0 0x20000>;
366 compatible = "arm,armv7-timer-mem";
367 reg = <0x0 0x17420000 0x0 0x1000>;
368 ranges = <0 0 0 0x20000000>;
369 #address-cells = <1>;
373 reg = <0x17421000 0x1000>,
376 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
381 reg = <0x17423000 0x1000>;
383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
388 reg = <0x17425000 0x1000>;
390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
395 reg = <0x17427000 0x1000>;
397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
402 reg = <0x17429000 0x1000>;
404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
409 reg = <0x1742b000 0x1000>;
411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
416 reg = <0x1742d000 0x1000>;
418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
425 compatible = "arm,armv8-timer";
426 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
427 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
428 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
429 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;