1 // SPDX-License-Identifier: BSD-3-Clause
3 * SDX75 SoC device tree source
5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19 interrupt-parent = <&intc>;
25 compatible = "fixed-clock";
26 clock-frequency = <76800000>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
43 compatible = "arm,cortex-a55";
45 clocks = <&cpufreq_hw 0>;
46 enable-method = "psci";
47 power-domains = <&CPU_PD0>;
48 power-domain-names = "psci";
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 capacity-dmips-mhz = <1024>;
51 dynamic-power-coefficient = <100>;
52 next-level-cache = <&L2_0>;
58 next-level-cache = <&L3_0>;
69 compatible = "arm,cortex-a55";
71 clocks = <&cpufreq_hw 0>;
72 enable-method = "psci";
73 power-domains = <&CPU_PD1>;
74 power-domain-names = "psci";
75 qcom,freq-domain = <&cpufreq_hw 0>;
76 capacity-dmips-mhz = <1024>;
77 dynamic-power-coefficient = <100>;
78 next-level-cache = <&L2_100>;
84 next-level-cache = <&L3_0>;
90 compatible = "arm,cortex-a55";
92 clocks = <&cpufreq_hw 0>;
93 enable-method = "psci";
94 power-domains = <&CPU_PD2>;
95 power-domain-names = "psci";
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 capacity-dmips-mhz = <1024>;
98 dynamic-power-coefficient = <100>;
99 next-level-cache = <&L2_200>;
102 compatible = "cache";
105 next-level-cache = <&L3_0>;
111 compatible = "arm,cortex-a55";
113 clocks = <&cpufreq_hw 0>;
114 enable-method = "psci";
115 power-domains = <&CPU_PD3>;
116 power-domain-names = "psci";
117 qcom,freq-domain = <&cpufreq_hw 0>;
118 capacity-dmips-mhz = <1024>;
119 dynamic-power-coefficient = <100>;
120 next-level-cache = <&L2_300>;
123 compatible = "cache";
126 next-level-cache = <&L3_0>;
151 entry-method = "psci";
153 CPU_OFF: cpu-sleep-0 {
154 compatible = "arm,idle-state";
155 entry-latency-us = <235>;
156 exit-latency-us = <428>;
157 min-residency-us = <1774>;
158 arm,psci-suspend-param = <0x40000003>;
162 CPU_RAIL_OFF: cpu-rail-sleep-1 {
163 compatible = "arm,idle-state";
164 entry-latency-us = <800>;
165 exit-latency-us = <750>;
166 min-residency-us = <4090>;
167 arm,psci-suspend-param = <0x40000004>;
174 CLUSTER_SLEEP_0: cluster-sleep-0 {
175 compatible = "domain-idle-state";
176 arm,psci-suspend-param = <0x41000044>;
177 entry-latency-us = <1050>;
178 exit-latency-us = <2500>;
179 min-residency-us = <5309>;
182 CLUSTER_SLEEP_1: cluster-sleep-1 {
183 compatible = "domain-idle-state";
184 arm,psci-suspend-param = <0x41001344>;
185 entry-latency-us = <2761>;
186 exit-latency-us = <3964>;
187 min-residency-us = <8467>;
190 CLUSTER_SLEEP_2: cluster-sleep-2 {
191 compatible = "domain-idle-state";
192 arm,psci-suspend-param = <0x4100b344>;
193 entry-latency-us = <2793>;
194 exit-latency-us = <4023>;
195 min-residency-us = <9826>;
202 compatible = "qcom,scm-sdx75", "qcom,scm";
207 device_type = "memory";
208 reg = <0x0 0x80000000 0x0 0x0>;
212 compatible = "arm,armv8-pmuv3";
213 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 compatible = "arm,psci-1.0";
220 CPU_PD0: power-domain-cpu0 {
221 #power-domain-cells = <0>;
222 power-domains = <&CLUSTER_PD>;
223 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
226 CPU_PD1: power-domain-cpu1 {
227 #power-domain-cells = <0>;
228 power-domains = <&CLUSTER_PD>;
229 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
232 CPU_PD2: power-domain-cpu2 {
233 #power-domain-cells = <0>;
234 power-domains = <&CLUSTER_PD>;
235 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
238 CPU_PD3: power-domain-cpu3 {
239 #power-domain-cells = <0>;
240 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
244 CLUSTER_PD: power-domain-cpu-cluster0 {
245 #power-domain-cells = <0>;
246 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
251 #address-cells = <2>;
255 gunyah_hyp_mem: gunyah-hyp@80000000 {
256 reg = <0x0 0x80000000 0x0 0x800000>;
260 hyp_elf_package_mem: hyp-elf-package@80800000 {
261 reg = <0x0 0x80800000 0x0 0x200000>;
265 access_control_db_mem: access-control-db@81380000 {
266 reg = <0x0 0x81380000 0x0 0x80000>;
270 qteetz_mem: qteetz@814e0000 {
271 reg = <0x0 0x814e0000 0x0 0x2a0000>;
275 trusted_apps_mem: trusted-apps@81780000 {
276 reg = <0x0 0x81780000 0x0 0xa00000>;
280 xbl_ramdump_mem: xbl-ramdump@87a00000 {
281 reg = <0x0 0x87a00000 0x0 0x1c0000>;
285 cpucp_fw_mem: cpucp-fw@87c00000 {
286 reg = <0x0 0x87c00000 0x0 0x100000>;
290 xbl_dtlog_mem: xbl-dtlog@87d00000 {
291 reg = <0x0 0x87d00000 0x0 0x40000>;
295 xbl_sc_mem: xbl-sc@87d40000 {
296 reg = <0x0 0x87d40000 0x0 0x40000>;
300 modem_efs_shared_mem: modem-efs-shared@87d80000 {
301 reg = <0x0 0x87d80000 0x0 0x10000>;
305 aop_image_mem: aop-image@87e00000 {
306 reg = <0x0 0x87e00000 0x0 0x20000>;
310 smem_mem: smem@87e20000 {
311 reg = <0x0 0x87e20000 0x0 0xc0000>;
315 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
316 compatible = "qcom,cmd-db";
317 reg = <0x0 0x87ee0000 0x0 0x20000>;
321 aop_config_mem: aop-config@87f00000 {
322 reg = <0x0 0x87f00000 0x0 0x20000>;
326 ipa_fw_mem: ipa-fw@87f20000 {
327 reg = <0x0 0x87f20000 0x0 0x10000>;
331 secdata_mem: secdata@87f30000 {
332 reg = <0x0 0x87f30000 0x0 0x1000>;
336 tme_crashdump_mem: tme-crashdump@87f31000 {
337 reg = <0x0 0x87f31000 0x0 0x40000>;
341 tme_log_mem: tme-log@87f71000 {
342 reg = <0x0 0x87f71000 0x0 0x4000>;
346 uefi_log_mem: uefi-log@87f75000 {
347 reg = <0x0 0x87f75000 0x0 0x10000>;
351 qdss_mem: qdss@88800000 {
352 reg = <0x0 0x88800000 0x0 0x300000>;
356 audio_heap_mem: audio-heap@88b00000 {
357 compatible = "shared-dma-pool";
358 reg = <0x0 0x88b00000 0x0 0x400000>;
362 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
363 reg = <0x0 0x88f00000 0x0 0x5080000>;
367 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
368 reg = <0x0 0x8df80000 0x0 0x80000>;
372 mpssadsp_mem: mpssadsp@8e000000 {
373 reg = <0x0 0x8e000000 0x0 0xf400000>;
377 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
378 reg = <0x0 0xbdb00000 0x0 0x2000000>;
382 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
383 reg = <0x0 0xbfb00000 0x0 0x100000>;
387 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
388 reg = <0x0 0xbfc00000 0x0 0x400000>;
394 compatible = "qcom,smem";
395 memory-region = <&smem_mem>;
396 hwlocks = <&tcsr_mutex 3>;
400 compatible = "simple-bus";
401 #address-cells = <2>;
403 ranges = <0 0 0 0 0x10 0>;
404 dma-ranges = <0 0 0 0 0x10 0>;
406 gcc: clock-controller@80000 {
407 compatible = "qcom,sdx75-gcc";
408 reg = <0x0 0x0080000 0x0 0x1f7400>;
409 clocks = <&rpmhcc RPMH_CXO_CLK>,
426 #power-domain-cells = <1>;
429 qupv3_id_0: geniqup@9c0000 {
430 compatible = "qcom,geni-se-qup";
431 reg = <0x0 0x009c0000 0x0 0x2000>;
432 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
433 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
434 clock-names = "m-ahb",
436 iommus = <&apps_smmu 0xe3 0x0>;
437 #address-cells = <2>;
442 uart1: serial@984000 {
443 compatible = "qcom,geni-debug-uart";
444 reg = <0x0 0x00984000 0x0 0x4000>;
445 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
447 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
448 pinctrl-0 = <&qupv3_se1_2uart_active>;
449 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
450 pinctrl-names = "default",
456 tcsr_mutex: hwlock@1f40000 {
457 compatible = "qcom,tcsr-mutex";
458 reg = <0x0 0x01f40000 0x0 0x40000>;
462 pdc: interrupt-controller@b220000 {
463 compatible = "qcom,sdx75-pdc", "qcom,pdc";
464 reg = <0x0 0xb220000 0x0 0x30000>,
465 <0x0 0x174000f0 0x0 0x64>;
466 qcom,pdc-ranges = <0 147 52>,
469 #interrupt-cells = <2>;
470 interrupt-parent = <&intc>;
471 interrupt-controller;
474 spmi_bus: spmi@c400000 {
475 compatible = "qcom,spmi-pmic-arb";
476 reg = <0x0 0x0c400000 0x0 0x3000>,
477 <0x0 0x0c500000 0x0 0x400000>,
478 <0x0 0x0c440000 0x0 0x80000>,
479 <0x0 0x0c4c0000 0x0 0x10000>,
480 <0x0 0x0c42d000 0x0 0x4000>;
486 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-names = "periph_irq";
491 #address-cells = <2>;
493 interrupt-controller;
494 #interrupt-cells = <4>;
497 tlmm: pinctrl@f000000 {
498 compatible = "qcom,sdx75-tlmm";
499 reg = <0x0 0x0f000000 0x0 0x400000>;
500 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
503 gpio-ranges = <&tlmm 0 0 133>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 wakeup-parent = <&pdc>;
508 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
511 function = "qup_se1_l2_mira";
512 drive-strength = <2>;
518 function = "qup_se1_l3_mira";
519 drive-strength = <2>;
524 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
525 pins = "gpio12", "gpio13";
527 drive-strength = <2>;
532 apps_smmu: iommu@15000000 {
533 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
534 reg = <0x0 0x15000000 0x0 0x40000>;
536 #global-interrupts = <2>;
538 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
573 intc: interrupt-controller@17200000 {
574 compatible = "arm,gic-v3";
575 #interrupt-cells = <3>;
576 interrupt-controller;
577 #redistributor-regions = <1>;
578 redistributor-stride = <0x0 0x20000>;
579 reg = <0x0 0x17200000 0x0 0x10000>,
580 <0x0 0x17260000 0x0 0x80000>;
581 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
585 compatible = "arm,armv7-timer-mem";
586 reg = <0x0 0x17420000 0x0 0x1000>;
587 #address-cells = <1>;
589 ranges = <0 0 0 0x20000000>;
592 reg = <0x17421000 0x1000>,
595 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
600 reg = <0x17423000 0x1000>;
602 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
607 reg = <0x17425000 0x1000>;
609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
614 reg = <0x17427000 0x1000>;
616 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
621 reg = <0x17429000 0x1000>;
623 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
628 reg = <0x1742b000 0x1000>;
630 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
635 reg = <0x1742d000 0x1000>;
637 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
642 apps_rsc: rsc@17a00000 {
644 compatible = "qcom,rpmh-rsc";
645 reg = <0x0 0x17a00000 0x0 0x10000>,
646 <0x0 0x17a10000 0x0 0x10000>,
647 <0x0 0x17a20000 0x0 0x10000>;
648 reg-names = "drv-0", "drv-1", "drv-2";
649 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
653 power-domains = <&CLUSTER_PD>;
654 qcom,tcs-offset = <0xd00>;
656 qcom,tcs-config = <ACTIVE_TCS 3>,
661 apps_bcm_voter: bcm-voter {
662 compatible = "qcom,bcm-voter";
665 rpmhcc: clock-controller {
666 compatible = "qcom,sdx75-rpmh-clk";
667 clocks = <&xo_board>;
672 rpmhpd: power-controller {
673 compatible = "qcom,sdx75-rpmhpd";
674 #power-domain-cells = <1>;
675 operating-points-v2 = <&rpmhpd_opp_table>;
677 rpmhpd_opp_table: opp-table {
678 compatible = "operating-points-v2";
680 rpmhpd_opp_ret: opp-16 {
681 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
684 rpmhpd_opp_min_svs: opp-48 {
685 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
688 rpmhpd_opp_low_svs: opp-64 {
689 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
692 rpmhpd_opp_svs: opp-128 {
693 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
696 rpmhpd_opp_svs_l1: opp-192 {
697 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
700 rpmhpd_opp_nom: opp-256 {
701 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
704 rpmhpd_opp_nom_l1: opp-320 {
705 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
708 rpmhpd_opp_nom_l2: opp-336 {
709 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
712 rpmhpd_opp_turbo: opp-384 {
713 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
716 rpmhpd_opp_turbo_l1: opp-416 {
717 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
723 cpufreq_hw: cpufreq@17d91000 {
724 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
725 reg = <0x0 0x17d91000 0x0 0x1000>;
726 reg-names = "freq-domain0";
727 clocks = <&rpmhcc RPMH_CXO_CLK>,
731 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
732 interrupt-names = "dcvsh-irq-0";
733 #freq-domain-cells = <1>;
739 compatible = "arm,armv8-timer";
740 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
741 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
742 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
743 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;