1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022, Xilin Wu <strongtz@yeah.net>
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 #include <dt-bindings/sound/qcom,q6afe.h>
15 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm850.dtsi"
17 #include "sdm845-wcd9340.dtsi"
18 #include "pm8998.dtsi"
21 * Update following upstream (sdm845.dtsi) reserved
22 * memory mappings for firmware loading to succeed
24 /delete-node/ &qseecom_mem;
25 /delete-node/ &wlan_msa_mem;
26 /delete-node/ &slpi_mem;
27 /delete-node/ &ipa_fw_mem;
28 /delete-node/ &ipa_gsi_mem;
29 /delete-node/ &gpu_mem;
30 /delete-node/ &mpss_region;
31 /delete-node/ &adsp_mem;
32 /delete-node/ &cdsp_mem;
33 /delete-node/ &venus_mem;
34 /delete-node/ &mba_region;
35 /delete-node/ &spss_mem;
38 model = "Samsung Galaxy Book2";
39 compatible = "samsung,w737", "qcom,sdm845";
40 chassis-type = "convertible";
47 /* Firmware initialized the display at 1280p instead of 1440p */
48 framebuffer0: framebuffer@80400000 {
49 compatible = "simple-framebuffer";
50 reg = <0 0x80400000 0 (1920 * 1280 * 4)>;
53 stride = <(1920 * 4)>;
62 /* Reserved memory changes */
64 /* Bootloader display framebuffer region */
65 cont_splash_mem: memory@80400000 {
66 reg = <0x0 0x80400000 0x0 0x960000>;
70 qseecom_mem: memory@8b500000 {
71 reg = <0 0x8b500000 0 0xa00000>;
75 wlan_msa_mem: memory@8c400000 {
76 reg = <0 0x8c400000 0 0x100000>;
80 slpi_mem: memory@8c500000 {
81 reg = <0 0x8c500000 0 0x1200000>;
85 ipa_fw_mem: memory@8d700000 {
86 reg = <0 0x8d700000 0 0x100000>;
90 gpu_mem: memory@8d800000 {
91 reg = <0 0x8d800000 0 0x5000>;
95 mpss_region: memory@8e000000 {
96 reg = <0 0x8e000000 0 0x8000000>;
100 adsp_mem: memory@96000000 {
101 reg = <0 0x96000000 0 0x2000000>;
105 cdsp_mem: memory@98000000 {
106 reg = <0 0x98000000 0 0x800000>;
110 venus_mem: memory@98800000 {
111 reg = <0 0x98800000 0 0x500000>;
115 mba_region: memory@98d00000 {
116 reg = <0 0x98d00000 0 0x200000>;
120 spss_mem: memory@98f00000 {
121 reg = <0 0x98f00000 0 0x100000>;
128 firmware-name = "/*(DEBLOBBED)*/";
134 compatible = "qcom,pm8998-rpmh-regulators";
137 vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
138 vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
140 vreg_s2a_1p125: smps2 {
143 vreg_s3a_1p35: smps3 {
144 regulator-min-microvolt = <1352000>;
145 regulator-max-microvolt = <1352000>;
146 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
149 vreg_s4a_1p8: smps4 {
150 regulator-min-microvolt = <1800000>;
151 regulator-max-microvolt = <1800000>;
152 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
155 vreg_s5a_2p04: smps5 {
156 regulator-min-microvolt = <2040000>;
157 regulator-max-microvolt = <2040000>;
158 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
161 vreg_s7a_1p025: smps7 {
182 vreg_l1a_0p875: ldo1 {
183 regulator-min-microvolt = <880000>;
184 regulator-max-microvolt = <880000>;
185 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
190 regulator-min-microvolt = <1200000>;
191 regulator-max-microvolt = <1200000>;
192 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
203 regulator-min-microvolt = <800000>;
204 regulator-max-microvolt = <800000>;
205 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
210 regulator-min-microvolt = <1800000>;
211 regulator-max-microvolt = <1800000>;
212 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
216 regulator-min-microvolt = <1800000>;
217 regulator-max-microvolt = <1800000>;
218 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
227 vreg_l10a_1p8: ldo10 {
230 vreg_l11a_1p0: ldo11 {
240 vreg_l12a_1p8: ldo12 {
241 regulator-min-microvolt = <1800000>;
242 regulator-max-microvolt = <1800000>;
243 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
247 vreg_l13a_2p95: ldo13 {
250 vreg_l14a_1p88: ldo14 {
251 regulator-min-microvolt = <1880000>;
252 regulator-max-microvolt = <1880000>;
253 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
257 vreg_l15a_1p8: ldo15 {
260 vreg_l16a_2p7: ldo16 {
263 vreg_l17a_1p3: ldo17 {
264 regulator-min-microvolt = <1304000>;
265 regulator-max-microvolt = <1304000>;
266 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
269 vreg_l18a_1p8: ldo18 {
272 vreg_l19a_3p0: ldo19 {
273 regulator-min-microvolt = <3100000>;
274 regulator-max-microvolt = <3108000>;
275 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
278 vreg_l20a_2p95: ldo20 {
279 regulator-min-microvolt = <2960000>;
280 regulator-max-microvolt = <2960000>;
281 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
284 vreg_l21a_2p95: ldo21 {
287 vreg_l22a_2p85: ldo22 {
290 vreg_l23a_3p3: ldo23 {
291 regulator-min-microvolt = <3300000>;
292 regulator-max-microvolt = <3312000>;
293 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
297 vreg_l24a_3p075: ldo24 {
298 regulator-min-microvolt = <3075000>;
299 regulator-max-microvolt = <3083000>;
300 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
303 vreg_l25a_3p3: ldo25 {
304 regulator-min-microvolt = <3104000>;
305 regulator-max-microvolt = <3112000>;
306 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
322 vreg_l26a_1p2: ldo26 {
323 regulator-min-microvolt = <1200000>;
324 regulator-max-microvolt = <1208000>;
325 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
328 vreg_l28a_3p0: ldo28 {
331 vreg_lvs1a_1p8: lvs1 {
334 vreg_lvs2a_1p8: lvs2 {
340 firmware-name = "/*(DEBLOBBED)*/";
345 protected-clocks = <GCC_QSPI_CORE_CLK>,
346 <GCC_QSPI_CORE_CLK_SRC>,
347 <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
348 <GCC_LPASS_Q6_AXI_CLK>,
349 <GCC_LPASS_SWAY_CLK>;
354 clock-frequency = <400000>;
356 /* SN65DSI86 @ 0x2c */
357 /* The panel requires dual DSI, which is not supported by the bridge driver */
362 clock-frequency = <400000>;
364 /* HID-I2C Touchscreen @ 0x20 */
369 clock-frequency = <400000>;
372 compatible = "wacom,w9013", "hid-over-i2c";
374 pinctrl-names = "default";
375 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
377 post-power-on-delay-ms = <120>;
379 interrupt-parent = <&tlmm>;
380 interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
382 hid-descr-addr = <0x1>;
387 qcom,gsi-loader = "self";
388 memory-region = <&ipa_fw_mem>;
389 firmware-name = "/*(DEBLOBBED)*/";
393 /* No idea why it causes an SError when enabled */
400 firmware-name = "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/";
404 drive-strength = <2>;
409 drive-strength = <2>;
414 drive-strength = <2>;
441 compatible = "qcom,sdm845-sndcard";
442 model = "Samsung-W737";
446 "AMIC2", "MIC BIAS2",
447 "SpkrLeft IN", "SPK1 OUT",
448 "SpkrRight IN", "SPK2 OUT",
449 "MM_DL1", "MultiMedia1 Playback",
450 "MM_DL3", "MultiMedia3 Playback",
451 "MultiMedia2 Capture", "MM_UL2";
454 link-name = "MultiMedia1";
456 sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
461 link-name = "MultiMedia2";
463 sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
468 link-name = "MultiMedia3";
470 sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
475 link-name = "SLIM Playback";
477 sound-dai = <&q6afedai SLIMBUS_0_RX>;
481 sound-dai = <&q6routing>;
485 sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
490 link-name = "SLIM Capture";
492 sound-dai = <&q6afedai SLIMBUS_0_TX>;
496 sound-dai = <&q6routing>;
500 sound-dai = <&wcd9340 1>;
505 link-name = "SLIM WCD Playback";
507 sound-dai = <&q6afedai SLIMBUS_1_RX>;
511 sound-dai = <&q6routing>;
515 sound-dai = <&wcd9340 2>;
521 gpio-reserved-ranges = <0 6>, <85 4>;
523 pen_irq_l: pen-irq-l-state {
529 pen_pdct_l: pen-pdct-l-state {
533 drive-strength = <2>;
537 pen_rst_l: pen-rst-l-state {
541 drive-strength = <2>;
544 * The pen driver doesn't currently support
545 * driving this reset line. By specifying
546 * output-high here we're relying on the fact
547 * that this pin has a default pulldown at boot
548 * (which makes sure the pen was in reset if it
549 * was powered) and then we set it high here to
550 * take it out of reset. Better would be if the
551 * pen driver could control this and we could
552 * remove "output-high" here.
559 pinctrl-names = "default";
560 pinctrl-0 = <&qup_uart6_4pin>;
564 compatible = "qcom,wcn3990-bt";
566 vddio-supply = <&vreg_s4a_1p8>;
567 vddxo-supply = <&vreg_l7a_1p8>;
568 vddrf-supply = <&vreg_l17a_1p3>;
569 vddch0-supply = <&vreg_l25a_3p3>;
570 vddch1-supply = <&vreg_l23a_3p3>;
571 max-speed = <3200000>;
578 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
580 vcc-supply = <&vreg_l20a_2p95>;
581 vcc-max-microamp = <600000>;
587 vdda-phy-supply = <&vdda_ufs1_core>;
588 vdda-pll-supply = <&vdda_ufs1_1p2>;
602 vdd-supply = <&vdda_usb1_ss_core>;
603 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
604 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
606 qcom,imp-res-offset-value = <8>;
607 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
608 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
609 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
615 vdda-phy-supply = <&vdda_usb1_ss_1p2>;
616 vdda-pll-supply = <&vdda_usb1_ss_core>;
630 vdd-supply = <&vdda_usb2_ss_core>;
631 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
632 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
634 qcom,imp-res-offset-value = <8>;
635 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
641 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
642 vdda-pll-supply = <&vdda_usb2_ss_core>;
647 firmware-name = "/*(DEBLOBBED)*/";
651 reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
652 vdd-buck-supply = <&vreg_s4a_1p8>;
653 vdd-buck-sido-supply = <&vreg_s4a_1p8>;
654 vdd-tx-supply = <&vreg_s4a_1p8>;
655 vdd-rx-supply = <&vreg_s4a_1p8>;
656 vdd-io-supply = <&vreg_s4a_1p8>;
657 qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
658 qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
659 qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
662 left_spkr: speaker@0,3 {
663 compatible = "sdw10217211000";
665 powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_LOW>;
666 #thermal-sensor-cells = <0>;
667 sound-name-prefix = "SpkrLeft";
668 #sound-dai-cells = <0>;
671 right_spkr: speaker@0,4 {
672 compatible = "sdw10217211000";
673 powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_LOW>;
675 #thermal-sensor-cells = <0>;
676 sound-name-prefix = "SpkrRight";
677 #sound-dai-cells = <0>;
685 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
686 vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
687 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
688 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
689 vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
691 qcom,snoc-host-cap-8bit-quirk;