1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sdm845.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/phy/phy-qcom-qmp.h>
22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
23 #include <dt-bindings/power/qcom-rpmpd.h>
24 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
25 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
26 #include <dt-bindings/soc/qcom,apr.h>
27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
28 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
29 #include <dt-bindings/thermal/thermal.h>
32 interrupt-parent = <&intc>;
76 compatible = "fixed-clock";
78 clock-frequency = <38400000>;
79 clock-output-names = "xo_board";
82 sleep_clk: sleep-clk {
83 compatible = "fixed-clock";
85 clock-frequency = <32764>;
95 compatible = "qcom,kryo385";
97 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci";
99 capacity-dmips-mhz = <611>;
100 dynamic-power-coefficient = <154>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 operating-points-v2 = <&cpu0_opp_table>;
103 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
105 power-domains = <&CPU_PD0>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 next-level-cache = <&L2_0>;
110 compatible = "cache";
113 next-level-cache = <&L3_0>;
115 compatible = "cache";
124 compatible = "qcom,kryo385";
126 clocks = <&cpufreq_hw 0>;
127 enable-method = "psci";
128 capacity-dmips-mhz = <611>;
129 dynamic-power-coefficient = <154>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
132 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
134 power-domains = <&CPU_PD1>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
137 next-level-cache = <&L2_100>;
139 compatible = "cache";
142 next-level-cache = <&L3_0>;
148 compatible = "qcom,kryo385";
150 clocks = <&cpufreq_hw 0>;
151 enable-method = "psci";
152 capacity-dmips-mhz = <611>;
153 dynamic-power-coefficient = <154>;
154 qcom,freq-domain = <&cpufreq_hw 0>;
155 operating-points-v2 = <&cpu0_opp_table>;
156 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
157 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
158 power-domains = <&CPU_PD2>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
161 next-level-cache = <&L2_200>;
163 compatible = "cache";
166 next-level-cache = <&L3_0>;
172 compatible = "qcom,kryo385";
174 clocks = <&cpufreq_hw 0>;
175 enable-method = "psci";
176 capacity-dmips-mhz = <611>;
177 dynamic-power-coefficient = <154>;
178 qcom,freq-domain = <&cpufreq_hw 0>;
179 operating-points-v2 = <&cpu0_opp_table>;
180 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
182 #cooling-cells = <2>;
183 power-domains = <&CPU_PD3>;
184 power-domain-names = "psci";
185 next-level-cache = <&L2_300>;
187 compatible = "cache";
190 next-level-cache = <&L3_0>;
196 compatible = "qcom,kryo385";
198 clocks = <&cpufreq_hw 1>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 dynamic-power-coefficient = <442>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
206 power-domains = <&CPU_PD4>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 next-level-cache = <&L2_400>;
211 compatible = "cache";
214 next-level-cache = <&L3_0>;
220 compatible = "qcom,kryo385";
222 clocks = <&cpufreq_hw 1>;
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 dynamic-power-coefficient = <442>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
230 power-domains = <&CPU_PD5>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 next-level-cache = <&L2_500>;
235 compatible = "cache";
238 next-level-cache = <&L3_0>;
244 compatible = "qcom,kryo385";
246 clocks = <&cpufreq_hw 1>;
247 enable-method = "psci";
248 capacity-dmips-mhz = <1024>;
249 dynamic-power-coefficient = <442>;
250 qcom,freq-domain = <&cpufreq_hw 1>;
251 operating-points-v2 = <&cpu4_opp_table>;
252 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
254 power-domains = <&CPU_PD6>;
255 power-domain-names = "psci";
256 #cooling-cells = <2>;
257 next-level-cache = <&L2_600>;
259 compatible = "cache";
262 next-level-cache = <&L3_0>;
268 compatible = "qcom,kryo385";
270 clocks = <&cpufreq_hw 1>;
271 enable-method = "psci";
272 capacity-dmips-mhz = <1024>;
273 dynamic-power-coefficient = <442>;
274 qcom,freq-domain = <&cpufreq_hw 1>;
275 operating-points-v2 = <&cpu4_opp_table>;
276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
277 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
278 power-domains = <&CPU_PD7>;
279 power-domain-names = "psci";
280 #cooling-cells = <2>;
281 next-level-cache = <&L2_700>;
283 compatible = "cache";
286 next-level-cache = <&L3_0>;
326 cpu_idle_states: idle-states {
327 entry-method = "psci";
329 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
330 compatible = "arm,idle-state";
331 idle-state-name = "little-rail-power-collapse";
332 arm,psci-suspend-param = <0x40000004>;
333 entry-latency-us = <350>;
334 exit-latency-us = <461>;
335 min-residency-us = <1890>;
339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
340 compatible = "arm,idle-state";
341 idle-state-name = "big-rail-power-collapse";
342 arm,psci-suspend-param = <0x40000004>;
343 entry-latency-us = <264>;
344 exit-latency-us = <621>;
345 min-residency-us = <952>;
351 CLUSTER_SLEEP_0: cluster-sleep-0 {
352 compatible = "domain-idle-state";
353 arm,psci-suspend-param = <0x4100c244>;
354 entry-latency-us = <3263>;
355 exit-latency-us = <6562>;
356 min-residency-us = <9987>;
363 compatible = "qcom,scm-sdm845", "qcom,scm";
368 device_type = "memory";
369 /* We expect the bootloader to fill in the size */
370 reg = <0 0x80000000 0 0>;
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points-v2";
377 cpu0_opp1: opp-300000000 {
378 opp-hz = /bits/ 64 <300000000>;
379 opp-peak-kBps = <800000 4800000>;
382 cpu0_opp2: opp-403200000 {
383 opp-hz = /bits/ 64 <403200000>;
384 opp-peak-kBps = <800000 4800000>;
387 cpu0_opp3: opp-480000000 {
388 opp-hz = /bits/ 64 <480000000>;
389 opp-peak-kBps = <800000 6451200>;
392 cpu0_opp4: opp-576000000 {
393 opp-hz = /bits/ 64 <576000000>;
394 opp-peak-kBps = <800000 6451200>;
397 cpu0_opp5: opp-652800000 {
398 opp-hz = /bits/ 64 <652800000>;
399 opp-peak-kBps = <800000 7680000>;
402 cpu0_opp6: opp-748800000 {
403 opp-hz = /bits/ 64 <748800000>;
404 opp-peak-kBps = <1804000 9216000>;
407 cpu0_opp7: opp-825600000 {
408 opp-hz = /bits/ 64 <825600000>;
409 opp-peak-kBps = <1804000 9216000>;
412 cpu0_opp8: opp-902400000 {
413 opp-hz = /bits/ 64 <902400000>;
414 opp-peak-kBps = <1804000 10444800>;
417 cpu0_opp9: opp-979200000 {
418 opp-hz = /bits/ 64 <979200000>;
419 opp-peak-kBps = <1804000 11980800>;
422 cpu0_opp10: opp-1056000000 {
423 opp-hz = /bits/ 64 <1056000000>;
424 opp-peak-kBps = <1804000 11980800>;
427 cpu0_opp11: opp-1132800000 {
428 opp-hz = /bits/ 64 <1132800000>;
429 opp-peak-kBps = <2188000 13516800>;
432 cpu0_opp12: opp-1228800000 {
433 opp-hz = /bits/ 64 <1228800000>;
434 opp-peak-kBps = <2188000 15052800>;
437 cpu0_opp13: opp-1324800000 {
438 opp-hz = /bits/ 64 <1324800000>;
439 opp-peak-kBps = <2188000 16588800>;
442 cpu0_opp14: opp-1420800000 {
443 opp-hz = /bits/ 64 <1420800000>;
444 opp-peak-kBps = <3072000 18124800>;
447 cpu0_opp15: opp-1516800000 {
448 opp-hz = /bits/ 64 <1516800000>;
449 opp-peak-kBps = <3072000 19353600>;
452 cpu0_opp16: opp-1612800000 {
453 opp-hz = /bits/ 64 <1612800000>;
454 opp-peak-kBps = <4068000 19353600>;
457 cpu0_opp17: opp-1689600000 {
458 opp-hz = /bits/ 64 <1689600000>;
459 opp-peak-kBps = <4068000 20889600>;
462 cpu0_opp18: opp-1766400000 {
463 opp-hz = /bits/ 64 <1766400000>;
464 opp-peak-kBps = <4068000 22425600>;
468 cpu4_opp_table: opp-table-cpu4 {
469 compatible = "operating-points-v2";
472 cpu4_opp1: opp-300000000 {
473 opp-hz = /bits/ 64 <300000000>;
474 opp-peak-kBps = <800000 4800000>;
477 cpu4_opp2: opp-403200000 {
478 opp-hz = /bits/ 64 <403200000>;
479 opp-peak-kBps = <800000 4800000>;
482 cpu4_opp3: opp-480000000 {
483 opp-hz = /bits/ 64 <480000000>;
484 opp-peak-kBps = <1804000 4800000>;
487 cpu4_opp4: opp-576000000 {
488 opp-hz = /bits/ 64 <576000000>;
489 opp-peak-kBps = <1804000 4800000>;
492 cpu4_opp5: opp-652800000 {
493 opp-hz = /bits/ 64 <652800000>;
494 opp-peak-kBps = <1804000 4800000>;
497 cpu4_opp6: opp-748800000 {
498 opp-hz = /bits/ 64 <748800000>;
499 opp-peak-kBps = <1804000 4800000>;
502 cpu4_opp7: opp-825600000 {
503 opp-hz = /bits/ 64 <825600000>;
504 opp-peak-kBps = <2188000 9216000>;
507 cpu4_opp8: opp-902400000 {
508 opp-hz = /bits/ 64 <902400000>;
509 opp-peak-kBps = <2188000 9216000>;
512 cpu4_opp9: opp-979200000 {
513 opp-hz = /bits/ 64 <979200000>;
514 opp-peak-kBps = <2188000 9216000>;
517 cpu4_opp10: opp-1056000000 {
518 opp-hz = /bits/ 64 <1056000000>;
519 opp-peak-kBps = <3072000 9216000>;
522 cpu4_opp11: opp-1132800000 {
523 opp-hz = /bits/ 64 <1132800000>;
524 opp-peak-kBps = <3072000 11980800>;
527 cpu4_opp12: opp-1209600000 {
528 opp-hz = /bits/ 64 <1209600000>;
529 opp-peak-kBps = <4068000 11980800>;
532 cpu4_opp13: opp-1286400000 {
533 opp-hz = /bits/ 64 <1286400000>;
534 opp-peak-kBps = <4068000 11980800>;
537 cpu4_opp14: opp-1363200000 {
538 opp-hz = /bits/ 64 <1363200000>;
539 opp-peak-kBps = <4068000 15052800>;
542 cpu4_opp15: opp-1459200000 {
543 opp-hz = /bits/ 64 <1459200000>;
544 opp-peak-kBps = <4068000 15052800>;
547 cpu4_opp16: opp-1536000000 {
548 opp-hz = /bits/ 64 <1536000000>;
549 opp-peak-kBps = <5412000 15052800>;
552 cpu4_opp17: opp-1612800000 {
553 opp-hz = /bits/ 64 <1612800000>;
554 opp-peak-kBps = <5412000 15052800>;
557 cpu4_opp18: opp-1689600000 {
558 opp-hz = /bits/ 64 <1689600000>;
559 opp-peak-kBps = <5412000 19353600>;
562 cpu4_opp19: opp-1766400000 {
563 opp-hz = /bits/ 64 <1766400000>;
564 opp-peak-kBps = <6220000 19353600>;
567 cpu4_opp20: opp-1843200000 {
568 opp-hz = /bits/ 64 <1843200000>;
569 opp-peak-kBps = <6220000 19353600>;
572 cpu4_opp21: opp-1920000000 {
573 opp-hz = /bits/ 64 <1920000000>;
574 opp-peak-kBps = <7216000 19353600>;
577 cpu4_opp22: opp-1996800000 {
578 opp-hz = /bits/ 64 <1996800000>;
579 opp-peak-kBps = <7216000 20889600>;
582 cpu4_opp23: opp-2092800000 {
583 opp-hz = /bits/ 64 <2092800000>;
584 opp-peak-kBps = <7216000 20889600>;
587 cpu4_opp24: opp-2169600000 {
588 opp-hz = /bits/ 64 <2169600000>;
589 opp-peak-kBps = <7216000 20889600>;
592 cpu4_opp25: opp-2246400000 {
593 opp-hz = /bits/ 64 <2246400000>;
594 opp-peak-kBps = <7216000 20889600>;
597 cpu4_opp26: opp-2323200000 {
598 opp-hz = /bits/ 64 <2323200000>;
599 opp-peak-kBps = <7216000 20889600>;
602 cpu4_opp27: opp-2400000000 {
603 opp-hz = /bits/ 64 <2400000000>;
604 opp-peak-kBps = <7216000 22425600>;
607 cpu4_opp28: opp-2476800000 {
608 opp-hz = /bits/ 64 <2476800000>;
609 opp-peak-kBps = <7216000 22425600>;
612 cpu4_opp29: opp-2553600000 {
613 opp-hz = /bits/ 64 <2553600000>;
614 opp-peak-kBps = <7216000 22425600>;
617 cpu4_opp30: opp-2649600000 {
618 opp-hz = /bits/ 64 <2649600000>;
619 opp-peak-kBps = <7216000 22425600>;
622 cpu4_opp31: opp-2745600000 {
623 opp-hz = /bits/ 64 <2745600000>;
624 opp-peak-kBps = <7216000 25497600>;
627 cpu4_opp32: opp-2803200000 {
628 opp-hz = /bits/ 64 <2803200000>;
629 opp-peak-kBps = <7216000 25497600>;
633 dsi_opp_table: opp-table-dsi {
634 compatible = "operating-points-v2";
637 opp-hz = /bits/ 64 <19200000>;
638 required-opps = <&rpmhpd_opp_min_svs>;
642 opp-hz = /bits/ 64 <180000000>;
643 required-opps = <&rpmhpd_opp_low_svs>;
647 opp-hz = /bits/ 64 <275000000>;
648 required-opps = <&rpmhpd_opp_svs>;
652 opp-hz = /bits/ 64 <328580000>;
653 required-opps = <&rpmhpd_opp_svs_l1>;
657 opp-hz = /bits/ 64 <358000000>;
658 required-opps = <&rpmhpd_opp_nom>;
662 qspi_opp_table: opp-table-qspi {
663 compatible = "operating-points-v2";
666 opp-hz = /bits/ 64 <19200000>;
667 required-opps = <&rpmhpd_opp_min_svs>;
671 opp-hz = /bits/ 64 <100000000>;
672 required-opps = <&rpmhpd_opp_low_svs>;
676 opp-hz = /bits/ 64 <150000000>;
677 required-opps = <&rpmhpd_opp_svs>;
681 opp-hz = /bits/ 64 <300000000>;
682 required-opps = <&rpmhpd_opp_nom>;
686 qup_opp_table: opp-table-qup {
687 compatible = "operating-points-v2";
690 opp-hz = /bits/ 64 <50000000>;
691 required-opps = <&rpmhpd_opp_min_svs>;
695 opp-hz = /bits/ 64 <75000000>;
696 required-opps = <&rpmhpd_opp_low_svs>;
700 opp-hz = /bits/ 64 <100000000>;
701 required-opps = <&rpmhpd_opp_svs>;
705 opp-hz = /bits/ 64 <128000000>;
706 required-opps = <&rpmhpd_opp_nom>;
711 compatible = "arm,armv8-pmuv3";
712 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
716 compatible = "arm,psci-1.0";
719 CPU_PD0: power-domain-cpu0 {
720 #power-domain-cells = <0>;
721 power-domains = <&CLUSTER_PD>;
722 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
725 CPU_PD1: power-domain-cpu1 {
726 #power-domain-cells = <0>;
727 power-domains = <&CLUSTER_PD>;
728 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
731 CPU_PD2: power-domain-cpu2 {
732 #power-domain-cells = <0>;
733 power-domains = <&CLUSTER_PD>;
734 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
737 CPU_PD3: power-domain-cpu3 {
738 #power-domain-cells = <0>;
739 power-domains = <&CLUSTER_PD>;
740 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
743 CPU_PD4: power-domain-cpu4 {
744 #power-domain-cells = <0>;
745 power-domains = <&CLUSTER_PD>;
746 domain-idle-states = <&BIG_CPU_SLEEP_0>;
749 CPU_PD5: power-domain-cpu5 {
750 #power-domain-cells = <0>;
751 power-domains = <&CLUSTER_PD>;
752 domain-idle-states = <&BIG_CPU_SLEEP_0>;
755 CPU_PD6: power-domain-cpu6 {
756 #power-domain-cells = <0>;
757 power-domains = <&CLUSTER_PD>;
758 domain-idle-states = <&BIG_CPU_SLEEP_0>;
761 CPU_PD7: power-domain-cpu7 {
762 #power-domain-cells = <0>;
763 power-domains = <&CLUSTER_PD>;
764 domain-idle-states = <&BIG_CPU_SLEEP_0>;
767 CLUSTER_PD: power-domain-cluster {
768 #power-domain-cells = <0>;
769 domain-idle-states = <&CLUSTER_SLEEP_0>;
774 #address-cells = <2>;
778 hyp_mem: hyp-mem@85700000 {
779 reg = <0 0x85700000 0 0x600000>;
783 xbl_mem: xbl-mem@85e00000 {
784 reg = <0 0x85e00000 0 0x100000>;
788 aop_mem: aop-mem@85fc0000 {
789 reg = <0 0x85fc0000 0 0x20000>;
793 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
794 compatible = "qcom,cmd-db";
795 reg = <0x0 0x85fe0000 0 0x20000>;
800 compatible = "qcom,smem";
801 reg = <0x0 0x86000000 0 0x200000>;
803 hwlocks = <&tcsr_mutex 3>;
806 tz_mem: tz@86200000 {
807 reg = <0 0x86200000 0 0x2d00000>;
811 rmtfs_mem: rmtfs@88f00000 {
812 compatible = "qcom,rmtfs-mem";
813 reg = <0 0x88f00000 0 0x200000>;
816 qcom,client-id = <1>;
817 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
820 qseecom_mem: qseecom@8ab00000 {
821 reg = <0 0x8ab00000 0 0x1400000>;
825 camera_mem: camera-mem@8bf00000 {
826 reg = <0 0x8bf00000 0 0x500000>;
830 ipa_fw_mem: ipa-fw@8c400000 {
831 reg = <0 0x8c400000 0 0x10000>;
835 ipa_gsi_mem: ipa-gsi@8c410000 {
836 reg = <0 0x8c410000 0 0x5000>;
840 gpu_mem: gpu@8c415000 {
841 reg = <0 0x8c415000 0 0x2000>;
845 adsp_mem: adsp@8c500000 {
846 reg = <0 0x8c500000 0 0x1a00000>;
850 wlan_msa_mem: wlan-msa@8df00000 {
851 reg = <0 0x8df00000 0 0x100000>;
855 mpss_region: mpss@8e000000 {
856 reg = <0 0x8e000000 0 0x7800000>;
860 venus_mem: venus@95800000 {
861 reg = <0 0x95800000 0 0x500000>;
865 cdsp_mem: cdsp@95d00000 {
866 reg = <0 0x95d00000 0 0x800000>;
870 mba_region: mba@96500000 {
871 reg = <0 0x96500000 0 0x200000>;
875 slpi_mem: slpi@96700000 {
876 reg = <0 0x96700000 0 0x1400000>;
880 spss_mem: spss@97b00000 {
881 reg = <0 0x97b00000 0 0x100000>;
885 mdata_mem: mpss-metadata {
886 alloc-ranges = <0 0xa0000000 0 0x20000000>;
891 fastrpc_mem: fastrpc {
892 compatible = "shared-dma-pool";
893 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
894 alignment = <0x0 0x400000>;
895 size = <0x0 0x1000000>;
900 adsp_pas: remoteproc-adsp {
901 compatible = "qcom,sdm845-adsp-pas";
903 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
904 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
908 interrupt-names = "wdog", "fatal", "ready",
909 "handover", "stop-ack";
911 clocks = <&rpmhcc RPMH_CXO_CLK>;
914 memory-region = <&adsp_mem>;
916 qcom,qmp = <&aoss_qmp>;
918 qcom,smem-states = <&adsp_smp2p_out 0>;
919 qcom,smem-state-names = "stop";
924 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 qcom,remote-pid = <2>;
927 mboxes = <&apss_shared 8>;
930 compatible = "qcom,apr-v2";
931 qcom,glink-channels = "apr_audio_svc";
932 qcom,domain = <APR_DOMAIN_ADSP>;
933 #address-cells = <1>;
935 qcom,intents = <512 20>;
938 reg = <APR_SVC_ADSP_CORE>;
939 compatible = "qcom,q6core";
940 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
944 compatible = "qcom,q6afe";
946 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 compatible = "qcom,q6afe-dais";
949 #address-cells = <1>;
951 #sound-dai-cells = <1>;
956 compatible = "qcom,q6asm";
958 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 compatible = "qcom,q6asm-dais";
961 #address-cells = <1>;
963 #sound-dai-cells = <1>;
964 iommus = <&apps_smmu 0x1821 0x0>;
969 compatible = "qcom,q6adm";
971 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 compatible = "qcom,q6adm-routing";
974 #sound-dai-cells = <0>;
980 compatible = "qcom,fastrpc";
981 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 qcom,non-secure-domain;
984 #address-cells = <1>;
988 compatible = "qcom,fastrpc-compute-cb";
990 iommus = <&apps_smmu 0x1823 0x0>;
994 compatible = "qcom,fastrpc-compute-cb";
996 iommus = <&apps_smmu 0x1824 0x0>;
1002 cdsp_pas: remoteproc-cdsp {
1003 compatible = "qcom,sdm845-cdsp-pas";
1005 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1006 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1010 interrupt-names = "wdog", "fatal", "ready",
1011 "handover", "stop-ack";
1013 clocks = <&rpmhcc RPMH_CXO_CLK>;
1016 memory-region = <&cdsp_mem>;
1018 qcom,qmp = <&aoss_qmp>;
1020 qcom,smem-states = <&cdsp_smp2p_out 0>;
1021 qcom,smem-state-names = "stop";
1023 status = "disabled";
1026 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 qcom,remote-pid = <5>;
1029 mboxes = <&apss_shared 4>;
1031 compatible = "qcom,fastrpc";
1032 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 qcom,non-secure-domain;
1035 #address-cells = <1>;
1039 compatible = "qcom,fastrpc-compute-cb";
1041 iommus = <&apps_smmu 0x1401 0x30>;
1045 compatible = "qcom,fastrpc-compute-cb";
1047 iommus = <&apps_smmu 0x1402 0x30>;
1051 compatible = "qcom,fastrpc-compute-cb";
1053 iommus = <&apps_smmu 0x1403 0x30>;
1057 compatible = "qcom,fastrpc-compute-cb";
1059 iommus = <&apps_smmu 0x1404 0x30>;
1063 compatible = "qcom,fastrpc-compute-cb";
1065 iommus = <&apps_smmu 0x1405 0x30>;
1069 compatible = "qcom,fastrpc-compute-cb";
1071 iommus = <&apps_smmu 0x1406 0x30>;
1075 compatible = "qcom,fastrpc-compute-cb";
1077 iommus = <&apps_smmu 0x1407 0x30>;
1081 compatible = "qcom,fastrpc-compute-cb";
1083 iommus = <&apps_smmu 0x1408 0x30>;
1090 compatible = "qcom,smp2p";
1091 qcom,smem = <94>, <432>;
1093 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 mboxes = <&apss_shared 6>;
1097 qcom,local-pid = <0>;
1098 qcom,remote-pid = <5>;
1100 cdsp_smp2p_out: master-kernel {
1101 qcom,entry-name = "master-kernel";
1102 #qcom,smem-state-cells = <1>;
1105 cdsp_smp2p_in: slave-kernel {
1106 qcom,entry-name = "slave-kernel";
1108 interrupt-controller;
1109 #interrupt-cells = <2>;
1114 compatible = "qcom,smp2p";
1115 qcom,smem = <443>, <429>;
1117 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 mboxes = <&apss_shared 10>;
1121 qcom,local-pid = <0>;
1122 qcom,remote-pid = <2>;
1124 adsp_smp2p_out: master-kernel {
1125 qcom,entry-name = "master-kernel";
1126 #qcom,smem-state-cells = <1>;
1129 adsp_smp2p_in: slave-kernel {
1130 qcom,entry-name = "slave-kernel";
1132 interrupt-controller;
1133 #interrupt-cells = <2>;
1138 compatible = "qcom,smp2p";
1139 qcom,smem = <435>, <428>;
1140 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1141 mboxes = <&apss_shared 14>;
1142 qcom,local-pid = <0>;
1143 qcom,remote-pid = <1>;
1145 modem_smp2p_out: master-kernel {
1146 qcom,entry-name = "master-kernel";
1147 #qcom,smem-state-cells = <1>;
1150 modem_smp2p_in: slave-kernel {
1151 qcom,entry-name = "slave-kernel";
1152 interrupt-controller;
1153 #interrupt-cells = <2>;
1156 ipa_smp2p_out: ipa-ap-to-modem {
1157 qcom,entry-name = "ipa";
1158 #qcom,smem-state-cells = <1>;
1161 ipa_smp2p_in: ipa-modem-to-ap {
1162 qcom,entry-name = "ipa";
1163 interrupt-controller;
1164 #interrupt-cells = <2>;
1169 compatible = "qcom,smp2p";
1170 qcom,smem = <481>, <430>;
1171 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1172 mboxes = <&apss_shared 26>;
1173 qcom,local-pid = <0>;
1174 qcom,remote-pid = <3>;
1176 slpi_smp2p_out: master-kernel {
1177 qcom,entry-name = "master-kernel";
1178 #qcom,smem-state-cells = <1>;
1181 slpi_smp2p_in: slave-kernel {
1182 qcom,entry-name = "slave-kernel";
1183 interrupt-controller;
1184 #interrupt-cells = <2>;
1189 #address-cells = <2>;
1191 ranges = <0 0 0 0 0x10 0>;
1192 dma-ranges = <0 0 0 0 0x10 0>;
1193 compatible = "simple-bus";
1195 gcc: clock-controller@100000 {
1196 compatible = "qcom,gcc-sdm845";
1197 reg = <0 0x00100000 0 0x1f0000>;
1198 clocks = <&rpmhcc RPMH_CXO_CLK>,
1199 <&rpmhcc RPMH_CXO_CLK_A>,
1203 clock-names = "bi_tcxo",
1210 #power-domain-cells = <1>;
1211 power-domains = <&rpmhpd SDM845_CX>;
1215 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1216 reg = <0 0x00784000 0 0x8ff>;
1217 #address-cells = <1>;
1220 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1225 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1232 compatible = "qcom,prng-ee";
1233 reg = <0 0x00793000 0 0x1000>;
1234 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1235 clock-names = "core";
1238 gpi_dma0: dma-controller@800000 {
1240 compatible = "qcom,sdm845-gpi-dma";
1241 reg = <0 0x00800000 0 0x60000>;
1242 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1255 dma-channels = <13>;
1256 dma-channel-mask = <0xfa>;
1257 iommus = <&apps_smmu 0x0016 0x0>;
1258 status = "disabled";
1261 qupv3_id_0: geniqup@8c0000 {
1262 compatible = "qcom,geni-se-qup";
1263 reg = <0 0x008c0000 0 0x6000>;
1264 clock-names = "m-ahb", "s-ahb";
1265 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1266 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1267 iommus = <&apps_smmu 0x3 0x0>;
1268 #address-cells = <2>;
1271 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1272 interconnect-names = "qup-core";
1273 status = "disabled";
1276 compatible = "qcom,geni-i2c";
1277 reg = <0 0x00880000 0 0x4000>;
1279 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_i2c0_default>;
1282 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1283 #address-cells = <1>;
1285 power-domains = <&rpmhpd SDM845_CX>;
1286 operating-points-v2 = <&qup_opp_table>;
1287 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1288 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1289 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1290 interconnect-names = "qup-core", "qup-config", "qup-memory";
1291 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1292 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1293 dma-names = "tx", "rx";
1294 status = "disabled";
1298 compatible = "qcom,geni-spi";
1299 reg = <0 0x00880000 0 0x4000>;
1301 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_spi0_default>;
1304 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1305 #address-cells = <1>;
1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1309 interconnect-names = "qup-core", "qup-config";
1310 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1311 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1312 dma-names = "tx", "rx";
1313 status = "disabled";
1316 uart0: serial@880000 {
1317 compatible = "qcom,geni-uart";
1318 reg = <0 0x00880000 0 0x4000>;
1320 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&qup_uart0_default>;
1323 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1324 power-domains = <&rpmhpd SDM845_CX>;
1325 operating-points-v2 = <&qup_opp_table>;
1326 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1327 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1328 interconnect-names = "qup-core", "qup-config";
1329 status = "disabled";
1333 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00884000 0 0x4000>;
1336 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1337 pinctrl-names = "default";
1338 pinctrl-0 = <&qup_i2c1_default>;
1339 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1340 #address-cells = <1>;
1342 power-domains = <&rpmhpd SDM845_CX>;
1343 operating-points-v2 = <&qup_opp_table>;
1344 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1345 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1346 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1347 interconnect-names = "qup-core", "qup-config", "qup-memory";
1348 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1349 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1350 dma-names = "tx", "rx";
1351 status = "disabled";
1355 compatible = "qcom,geni-spi";
1356 reg = <0 0x00884000 0 0x4000>;
1358 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_spi1_default>;
1361 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1362 #address-cells = <1>;
1364 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1365 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1366 interconnect-names = "qup-core", "qup-config";
1367 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1368 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1369 dma-names = "tx", "rx";
1370 status = "disabled";
1373 uart1: serial@884000 {
1374 compatible = "qcom,geni-uart";
1375 reg = <0 0x00884000 0 0x4000>;
1377 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&qup_uart1_default>;
1380 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1381 power-domains = <&rpmhpd SDM845_CX>;
1382 operating-points-v2 = <&qup_opp_table>;
1383 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1384 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1385 interconnect-names = "qup-core", "qup-config";
1386 status = "disabled";
1390 compatible = "qcom,geni-i2c";
1391 reg = <0 0x00888000 0 0x4000>;
1393 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1394 pinctrl-names = "default";
1395 pinctrl-0 = <&qup_i2c2_default>;
1396 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1397 #address-cells = <1>;
1399 power-domains = <&rpmhpd SDM845_CX>;
1400 operating-points-v2 = <&qup_opp_table>;
1401 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1402 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1403 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1404 interconnect-names = "qup-core", "qup-config", "qup-memory";
1405 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1406 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1407 dma-names = "tx", "rx";
1408 status = "disabled";
1412 compatible = "qcom,geni-spi";
1413 reg = <0 0x00888000 0 0x4000>;
1415 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1416 pinctrl-names = "default";
1417 pinctrl-0 = <&qup_spi2_default>;
1418 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1419 #address-cells = <1>;
1421 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1422 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1423 interconnect-names = "qup-core", "qup-config";
1424 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1425 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1426 dma-names = "tx", "rx";
1427 status = "disabled";
1430 uart2: serial@888000 {
1431 compatible = "qcom,geni-uart";
1432 reg = <0 0x00888000 0 0x4000>;
1434 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1435 pinctrl-names = "default";
1436 pinctrl-0 = <&qup_uart2_default>;
1437 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1438 power-domains = <&rpmhpd SDM845_CX>;
1439 operating-points-v2 = <&qup_opp_table>;
1440 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1441 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1442 interconnect-names = "qup-core", "qup-config";
1443 status = "disabled";
1447 compatible = "qcom,geni-i2c";
1448 reg = <0 0x0088c000 0 0x4000>;
1450 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&qup_i2c3_default>;
1453 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1454 #address-cells = <1>;
1456 power-domains = <&rpmhpd SDM845_CX>;
1457 operating-points-v2 = <&qup_opp_table>;
1458 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1459 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1460 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1461 interconnect-names = "qup-core", "qup-config", "qup-memory";
1462 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1463 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1464 dma-names = "tx", "rx";
1465 status = "disabled";
1469 compatible = "qcom,geni-spi";
1470 reg = <0 0x0088c000 0 0x4000>;
1472 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1473 pinctrl-names = "default";
1474 pinctrl-0 = <&qup_spi3_default>;
1475 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1476 #address-cells = <1>;
1478 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1479 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1480 interconnect-names = "qup-core", "qup-config";
1481 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1482 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1483 dma-names = "tx", "rx";
1484 status = "disabled";
1487 uart3: serial@88c000 {
1488 compatible = "qcom,geni-uart";
1489 reg = <0 0x0088c000 0 0x4000>;
1491 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&qup_uart3_default>;
1494 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1495 power-domains = <&rpmhpd SDM845_CX>;
1496 operating-points-v2 = <&qup_opp_table>;
1497 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1498 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1499 interconnect-names = "qup-core", "qup-config";
1500 status = "disabled";
1504 compatible = "qcom,geni-i2c";
1505 reg = <0 0x00890000 0 0x4000>;
1507 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&qup_i2c4_default>;
1510 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1511 #address-cells = <1>;
1513 power-domains = <&rpmhpd SDM845_CX>;
1514 operating-points-v2 = <&qup_opp_table>;
1515 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1516 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1517 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1518 interconnect-names = "qup-core", "qup-config", "qup-memory";
1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1520 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1521 dma-names = "tx", "rx";
1522 status = "disabled";
1526 compatible = "qcom,geni-spi";
1527 reg = <0 0x00890000 0 0x4000>;
1529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1530 pinctrl-names = "default";
1531 pinctrl-0 = <&qup_spi4_default>;
1532 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1533 #address-cells = <1>;
1535 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1536 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1537 interconnect-names = "qup-core", "qup-config";
1538 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1539 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1540 dma-names = "tx", "rx";
1541 status = "disabled";
1544 uart4: serial@890000 {
1545 compatible = "qcom,geni-uart";
1546 reg = <0 0x00890000 0 0x4000>;
1548 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1549 pinctrl-names = "default";
1550 pinctrl-0 = <&qup_uart4_default>;
1551 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1552 power-domains = <&rpmhpd SDM845_CX>;
1553 operating-points-v2 = <&qup_opp_table>;
1554 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1555 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1556 interconnect-names = "qup-core", "qup-config";
1557 status = "disabled";
1561 compatible = "qcom,geni-i2c";
1562 reg = <0 0x00894000 0 0x4000>;
1564 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&qup_i2c5_default>;
1567 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1568 #address-cells = <1>;
1570 power-domains = <&rpmhpd SDM845_CX>;
1571 operating-points-v2 = <&qup_opp_table>;
1572 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1574 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1575 interconnect-names = "qup-core", "qup-config", "qup-memory";
1576 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1577 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1578 dma-names = "tx", "rx";
1579 status = "disabled";
1583 compatible = "qcom,geni-spi";
1584 reg = <0 0x00894000 0 0x4000>;
1586 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1587 pinctrl-names = "default";
1588 pinctrl-0 = <&qup_spi5_default>;
1589 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1590 #address-cells = <1>;
1592 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1593 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1594 interconnect-names = "qup-core", "qup-config";
1595 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1596 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1597 dma-names = "tx", "rx";
1598 status = "disabled";
1601 uart5: serial@894000 {
1602 compatible = "qcom,geni-uart";
1603 reg = <0 0x00894000 0 0x4000>;
1605 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1606 pinctrl-names = "default";
1607 pinctrl-0 = <&qup_uart5_default>;
1608 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1609 power-domains = <&rpmhpd SDM845_CX>;
1610 operating-points-v2 = <&qup_opp_table>;
1611 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1612 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1613 interconnect-names = "qup-core", "qup-config";
1614 status = "disabled";
1618 compatible = "qcom,geni-i2c";
1619 reg = <0 0x00898000 0 0x4000>;
1621 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1622 pinctrl-names = "default";
1623 pinctrl-0 = <&qup_i2c6_default>;
1624 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1625 #address-cells = <1>;
1627 power-domains = <&rpmhpd SDM845_CX>;
1628 operating-points-v2 = <&qup_opp_table>;
1629 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1630 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1631 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1632 interconnect-names = "qup-core", "qup-config", "qup-memory";
1633 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1634 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1635 dma-names = "tx", "rx";
1636 status = "disabled";
1640 compatible = "qcom,geni-spi";
1641 reg = <0 0x00898000 0 0x4000>;
1643 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1644 pinctrl-names = "default";
1645 pinctrl-0 = <&qup_spi6_default>;
1646 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1647 #address-cells = <1>;
1649 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1650 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1651 interconnect-names = "qup-core", "qup-config";
1652 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1653 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1654 dma-names = "tx", "rx";
1655 status = "disabled";
1658 uart6: serial@898000 {
1659 compatible = "qcom,geni-uart";
1660 reg = <0 0x00898000 0 0x4000>;
1662 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1663 pinctrl-names = "default";
1664 pinctrl-0 = <&qup_uart6_default>;
1665 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1666 power-domains = <&rpmhpd SDM845_CX>;
1667 operating-points-v2 = <&qup_opp_table>;
1668 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1669 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1670 interconnect-names = "qup-core", "qup-config";
1671 status = "disabled";
1675 compatible = "qcom,geni-i2c";
1676 reg = <0 0x0089c000 0 0x4000>;
1678 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1679 pinctrl-names = "default";
1680 pinctrl-0 = <&qup_i2c7_default>;
1681 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1682 #address-cells = <1>;
1684 power-domains = <&rpmhpd SDM845_CX>;
1685 operating-points-v2 = <&qup_opp_table>;
1686 status = "disabled";
1690 compatible = "qcom,geni-spi";
1691 reg = <0 0x0089c000 0 0x4000>;
1693 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1694 pinctrl-names = "default";
1695 pinctrl-0 = <&qup_spi7_default>;
1696 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1697 #address-cells = <1>;
1699 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1700 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1701 interconnect-names = "qup-core", "qup-config";
1702 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1703 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1704 dma-names = "tx", "rx";
1705 status = "disabled";
1708 uart7: serial@89c000 {
1709 compatible = "qcom,geni-uart";
1710 reg = <0 0x0089c000 0 0x4000>;
1712 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1713 pinctrl-names = "default";
1714 pinctrl-0 = <&qup_uart7_default>;
1715 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1716 power-domains = <&rpmhpd SDM845_CX>;
1717 operating-points-v2 = <&qup_opp_table>;
1718 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1719 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1720 interconnect-names = "qup-core", "qup-config";
1721 status = "disabled";
1725 gpi_dma1: dma-controller@a00000 {
1727 compatible = "qcom,sdm845-gpi-dma";
1728 reg = <0 0x00a00000 0 0x60000>;
1729 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1742 dma-channels = <13>;
1743 dma-channel-mask = <0xfa>;
1744 iommus = <&apps_smmu 0x06d6 0x0>;
1745 status = "disabled";
1748 qupv3_id_1: geniqup@ac0000 {
1749 compatible = "qcom,geni-se-qup";
1750 reg = <0 0x00ac0000 0 0x6000>;
1751 clock-names = "m-ahb", "s-ahb";
1752 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1753 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1754 iommus = <&apps_smmu 0x6c3 0x0>;
1755 #address-cells = <2>;
1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1759 interconnect-names = "qup-core";
1760 status = "disabled";
1763 compatible = "qcom,geni-i2c";
1764 reg = <0 0x00a80000 0 0x4000>;
1766 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1767 pinctrl-names = "default";
1768 pinctrl-0 = <&qup_i2c8_default>;
1769 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1770 #address-cells = <1>;
1772 power-domains = <&rpmhpd SDM845_CX>;
1773 operating-points-v2 = <&qup_opp_table>;
1774 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1775 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1776 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1777 interconnect-names = "qup-core", "qup-config", "qup-memory";
1778 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1779 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1780 dma-names = "tx", "rx";
1781 status = "disabled";
1785 compatible = "qcom,geni-spi";
1786 reg = <0 0x00a80000 0 0x4000>;
1788 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1789 pinctrl-names = "default";
1790 pinctrl-0 = <&qup_spi8_default>;
1791 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1792 #address-cells = <1>;
1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1796 interconnect-names = "qup-core", "qup-config";
1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1798 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1799 dma-names = "tx", "rx";
1800 status = "disabled";
1803 uart8: serial@a80000 {
1804 compatible = "qcom,geni-uart";
1805 reg = <0 0x00a80000 0 0x4000>;
1807 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_uart8_default>;
1810 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1811 power-domains = <&rpmhpd SDM845_CX>;
1812 operating-points-v2 = <&qup_opp_table>;
1813 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1814 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1815 interconnect-names = "qup-core", "qup-config";
1816 status = "disabled";
1820 compatible = "qcom,geni-i2c";
1821 reg = <0 0x00a84000 0 0x4000>;
1823 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1824 pinctrl-names = "default";
1825 pinctrl-0 = <&qup_i2c9_default>;
1826 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1827 #address-cells = <1>;
1829 power-domains = <&rpmhpd SDM845_CX>;
1830 operating-points-v2 = <&qup_opp_table>;
1831 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1832 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1833 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1834 interconnect-names = "qup-core", "qup-config", "qup-memory";
1835 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1836 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1837 dma-names = "tx", "rx";
1838 status = "disabled";
1842 compatible = "qcom,geni-spi";
1843 reg = <0 0x00a84000 0 0x4000>;
1845 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1846 pinctrl-names = "default";
1847 pinctrl-0 = <&qup_spi9_default>;
1848 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1849 #address-cells = <1>;
1851 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1852 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1853 interconnect-names = "qup-core", "qup-config";
1854 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1855 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1856 dma-names = "tx", "rx";
1857 status = "disabled";
1860 uart9: serial@a84000 {
1861 compatible = "qcom,geni-debug-uart";
1862 reg = <0 0x00a84000 0 0x4000>;
1864 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1865 pinctrl-names = "default";
1866 pinctrl-0 = <&qup_uart9_default>;
1867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1868 power-domains = <&rpmhpd SDM845_CX>;
1869 operating-points-v2 = <&qup_opp_table>;
1870 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1871 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1872 interconnect-names = "qup-core", "qup-config";
1873 status = "disabled";
1877 compatible = "qcom,geni-i2c";
1878 reg = <0 0x00a88000 0 0x4000>;
1880 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1881 pinctrl-names = "default";
1882 pinctrl-0 = <&qup_i2c10_default>;
1883 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1884 #address-cells = <1>;
1886 power-domains = <&rpmhpd SDM845_CX>;
1887 operating-points-v2 = <&qup_opp_table>;
1888 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1889 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1890 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1891 interconnect-names = "qup-core", "qup-config", "qup-memory";
1892 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1893 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1894 dma-names = "tx", "rx";
1895 status = "disabled";
1899 compatible = "qcom,geni-spi";
1900 reg = <0 0x00a88000 0 0x4000>;
1902 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1903 pinctrl-names = "default";
1904 pinctrl-0 = <&qup_spi10_default>;
1905 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1906 #address-cells = <1>;
1908 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1909 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1910 interconnect-names = "qup-core", "qup-config";
1911 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1912 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1913 dma-names = "tx", "rx";
1914 status = "disabled";
1917 uart10: serial@a88000 {
1918 compatible = "qcom,geni-uart";
1919 reg = <0 0x00a88000 0 0x4000>;
1921 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1922 pinctrl-names = "default";
1923 pinctrl-0 = <&qup_uart10_default>;
1924 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1925 power-domains = <&rpmhpd SDM845_CX>;
1926 operating-points-v2 = <&qup_opp_table>;
1927 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1928 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1929 interconnect-names = "qup-core", "qup-config";
1930 status = "disabled";
1934 compatible = "qcom,geni-i2c";
1935 reg = <0 0x00a8c000 0 0x4000>;
1937 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1938 pinctrl-names = "default";
1939 pinctrl-0 = <&qup_i2c11_default>;
1940 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1941 #address-cells = <1>;
1943 power-domains = <&rpmhpd SDM845_CX>;
1944 operating-points-v2 = <&qup_opp_table>;
1945 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1946 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1947 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1948 interconnect-names = "qup-core", "qup-config", "qup-memory";
1949 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1950 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1951 dma-names = "tx", "rx";
1952 status = "disabled";
1956 compatible = "qcom,geni-spi";
1957 reg = <0 0x00a8c000 0 0x4000>;
1959 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1960 pinctrl-names = "default";
1961 pinctrl-0 = <&qup_spi11_default>;
1962 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1963 #address-cells = <1>;
1965 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1966 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1967 interconnect-names = "qup-core", "qup-config";
1968 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1969 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1970 dma-names = "tx", "rx";
1971 status = "disabled";
1974 uart11: serial@a8c000 {
1975 compatible = "qcom,geni-uart";
1976 reg = <0 0x00a8c000 0 0x4000>;
1978 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1979 pinctrl-names = "default";
1980 pinctrl-0 = <&qup_uart11_default>;
1981 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1982 power-domains = <&rpmhpd SDM845_CX>;
1983 operating-points-v2 = <&qup_opp_table>;
1984 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1985 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1986 interconnect-names = "qup-core", "qup-config";
1987 status = "disabled";
1991 compatible = "qcom,geni-i2c";
1992 reg = <0 0x00a90000 0 0x4000>;
1994 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1995 pinctrl-names = "default";
1996 pinctrl-0 = <&qup_i2c12_default>;
1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1998 #address-cells = <1>;
2000 power-domains = <&rpmhpd SDM845_CX>;
2001 operating-points-v2 = <&qup_opp_table>;
2002 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2003 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2004 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2005 interconnect-names = "qup-core", "qup-config", "qup-memory";
2006 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2007 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2008 dma-names = "tx", "rx";
2009 status = "disabled";
2013 compatible = "qcom,geni-spi";
2014 reg = <0 0x00a90000 0 0x4000>;
2016 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2017 pinctrl-names = "default";
2018 pinctrl-0 = <&qup_spi12_default>;
2019 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2020 #address-cells = <1>;
2022 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2023 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2024 interconnect-names = "qup-core", "qup-config";
2025 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2026 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2027 dma-names = "tx", "rx";
2028 status = "disabled";
2031 uart12: serial@a90000 {
2032 compatible = "qcom,geni-uart";
2033 reg = <0 0x00a90000 0 0x4000>;
2035 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2036 pinctrl-names = "default";
2037 pinctrl-0 = <&qup_uart12_default>;
2038 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2039 power-domains = <&rpmhpd SDM845_CX>;
2040 operating-points-v2 = <&qup_opp_table>;
2041 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2042 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2043 interconnect-names = "qup-core", "qup-config";
2044 status = "disabled";
2048 compatible = "qcom,geni-i2c";
2049 reg = <0 0x00a94000 0 0x4000>;
2051 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2052 pinctrl-names = "default";
2053 pinctrl-0 = <&qup_i2c13_default>;
2054 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2055 #address-cells = <1>;
2057 power-domains = <&rpmhpd SDM845_CX>;
2058 operating-points-v2 = <&qup_opp_table>;
2059 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2060 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2061 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2062 interconnect-names = "qup-core", "qup-config", "qup-memory";
2063 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2064 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2065 dma-names = "tx", "rx";
2066 status = "disabled";
2070 compatible = "qcom,geni-spi";
2071 reg = <0 0x00a94000 0 0x4000>;
2073 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2074 pinctrl-names = "default";
2075 pinctrl-0 = <&qup_spi13_default>;
2076 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2077 #address-cells = <1>;
2079 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2080 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2081 interconnect-names = "qup-core", "qup-config";
2082 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2083 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2084 dma-names = "tx", "rx";
2085 status = "disabled";
2088 uart13: serial@a94000 {
2089 compatible = "qcom,geni-uart";
2090 reg = <0 0x00a94000 0 0x4000>;
2092 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2093 pinctrl-names = "default";
2094 pinctrl-0 = <&qup_uart13_default>;
2095 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2096 power-domains = <&rpmhpd SDM845_CX>;
2097 operating-points-v2 = <&qup_opp_table>;
2098 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2100 interconnect-names = "qup-core", "qup-config";
2101 status = "disabled";
2105 compatible = "qcom,geni-i2c";
2106 reg = <0 0x00a98000 0 0x4000>;
2108 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2109 pinctrl-names = "default";
2110 pinctrl-0 = <&qup_i2c14_default>;
2111 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2112 #address-cells = <1>;
2114 power-domains = <&rpmhpd SDM845_CX>;
2115 operating-points-v2 = <&qup_opp_table>;
2116 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2117 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2118 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2119 interconnect-names = "qup-core", "qup-config", "qup-memory";
2120 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2121 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2122 dma-names = "tx", "rx";
2123 status = "disabled";
2127 compatible = "qcom,geni-spi";
2128 reg = <0 0x00a98000 0 0x4000>;
2130 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2131 pinctrl-names = "default";
2132 pinctrl-0 = <&qup_spi14_default>;
2133 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2134 #address-cells = <1>;
2136 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2137 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2138 interconnect-names = "qup-core", "qup-config";
2139 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2140 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2141 dma-names = "tx", "rx";
2142 status = "disabled";
2145 uart14: serial@a98000 {
2146 compatible = "qcom,geni-uart";
2147 reg = <0 0x00a98000 0 0x4000>;
2149 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2150 pinctrl-names = "default";
2151 pinctrl-0 = <&qup_uart14_default>;
2152 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2153 power-domains = <&rpmhpd SDM845_CX>;
2154 operating-points-v2 = <&qup_opp_table>;
2155 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2156 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2157 interconnect-names = "qup-core", "qup-config";
2158 status = "disabled";
2162 compatible = "qcom,geni-i2c";
2163 reg = <0 0x00a9c000 0 0x4000>;
2165 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2166 pinctrl-names = "default";
2167 pinctrl-0 = <&qup_i2c15_default>;
2168 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2169 #address-cells = <1>;
2171 power-domains = <&rpmhpd SDM845_CX>;
2172 operating-points-v2 = <&qup_opp_table>;
2173 status = "disabled";
2174 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2175 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2176 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2177 interconnect-names = "qup-core", "qup-config", "qup-memory";
2178 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2179 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2180 dma-names = "tx", "rx";
2184 compatible = "qcom,geni-spi";
2185 reg = <0 0x00a9c000 0 0x4000>;
2187 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2188 pinctrl-names = "default";
2189 pinctrl-0 = <&qup_spi15_default>;
2190 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2191 #address-cells = <1>;
2193 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2194 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2195 interconnect-names = "qup-core", "qup-config";
2196 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2197 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2198 dma-names = "tx", "rx";
2199 status = "disabled";
2202 uart15: serial@a9c000 {
2203 compatible = "qcom,geni-uart";
2204 reg = <0 0x00a9c000 0 0x4000>;
2206 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2207 pinctrl-names = "default";
2208 pinctrl-0 = <&qup_uart15_default>;
2209 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2210 power-domains = <&rpmhpd SDM845_CX>;
2211 operating-points-v2 = <&qup_opp_table>;
2212 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2213 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2214 interconnect-names = "qup-core", "qup-config";
2215 status = "disabled";
2219 llcc: system-cache-controller@1100000 {
2220 compatible = "qcom,sdm845-llcc";
2221 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2222 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2223 <0 0x01300000 0 0x50000>;
2224 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2225 "llcc3_base", "llcc_broadcast_base";
2226 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2230 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2231 reg = <0x0 0x010a2000 0x0 0x1000>,
2232 <0x0 0x010ae000 0x0 0x2000>;
2236 compatible = "qcom,sdm845-llcc-bwmon";
2237 reg = <0 0x0114a000 0 0x1000>;
2238 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2239 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2241 operating-points-v2 = <&llcc_bwmon_opp_table>;
2243 llcc_bwmon_opp_table: opp-table {
2244 compatible = "operating-points-v2";
2247 * The interconnect path bandwidth taken from
2248 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2249 * interconnect. This also matches the
2250 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2251 * bus width: 4 bytes) from msm-4.9 downstream
2255 opp-peak-kBps = <800000>;
2258 opp-peak-kBps = <1804000>;
2261 opp-peak-kBps = <3072000>;
2264 opp-peak-kBps = <5412000>;
2267 opp-peak-kBps = <7216000>;
2273 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2274 reg = <0 0x01436400 0 0x600>;
2275 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2276 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 cpu_bwmon_opp_table: opp-table {
2281 compatible = "operating-points-v2";
2284 * The interconnect path bandwidth taken from
2285 * cpu4_opp_table bandwidth for OSM L3
2286 * interconnect. This also matches the OSM L3
2287 * from bandwidth table of qcom,cpu4-l3lat-mon
2288 * (qcom,core-dev-table, bus width: 16 bytes)
2289 * from msm-4.9 downstream kernel.
2292 opp-peak-kBps = <4800000>;
2295 opp-peak-kBps = <9216000>;
2298 opp-peak-kBps = <15052800>;
2301 opp-peak-kBps = <20889600>;
2304 opp-peak-kBps = <25497600>;
2309 pcie0: pci@1c00000 {
2310 compatible = "qcom,pcie-sdm845";
2311 reg = <0 0x01c00000 0 0x2000>,
2312 <0 0x60000000 0 0xf1d>,
2313 <0 0x60000f20 0 0xa8>,
2314 <0 0x60100000 0 0x100000>,
2315 <0 0x01c07000 0 0x1000>;
2316 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2317 device_type = "pci";
2318 linux,pci-domain = <0>;
2319 bus-range = <0x00 0xff>;
2322 #address-cells = <3>;
2325 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2326 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2328 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2329 interrupt-names = "msi";
2330 #interrupt-cells = <1>;
2331 interrupt-map-mask = <0 0 0 0x7>;
2332 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2333 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2334 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2335 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2338 <&gcc GCC_PCIE_0_AUX_CLK>,
2339 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2340 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2341 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2342 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2343 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2344 clock-names = "pipe",
2352 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2353 <0x100 &apps_smmu 0x1c11 0x1>,
2354 <0x200 &apps_smmu 0x1c12 0x1>,
2355 <0x300 &apps_smmu 0x1c13 0x1>,
2356 <0x400 &apps_smmu 0x1c14 0x1>,
2357 <0x500 &apps_smmu 0x1c15 0x1>,
2358 <0x600 &apps_smmu 0x1c16 0x1>,
2359 <0x700 &apps_smmu 0x1c17 0x1>,
2360 <0x800 &apps_smmu 0x1c18 0x1>,
2361 <0x900 &apps_smmu 0x1c19 0x1>,
2362 <0xa00 &apps_smmu 0x1c1a 0x1>,
2363 <0xb00 &apps_smmu 0x1c1b 0x1>,
2364 <0xc00 &apps_smmu 0x1c1c 0x1>,
2365 <0xd00 &apps_smmu 0x1c1d 0x1>,
2366 <0xe00 &apps_smmu 0x1c1e 0x1>,
2367 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 resets = <&gcc GCC_PCIE_0_BCR>;
2370 reset-names = "pci";
2372 power-domains = <&gcc PCIE_0_GDSC>;
2374 phys = <&pcie0_phy>;
2375 phy-names = "pciephy";
2377 status = "disabled";
2380 pcie0_phy: phy@1c06000 {
2381 compatible = "qcom,sdm845-qmp-pcie-phy";
2382 reg = <0 0x01c06000 0 0x1000>;
2383 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2384 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2385 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2386 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2387 <&gcc GCC_PCIE_0_PIPE_CLK>;
2388 clock-names = "aux",
2394 clock-output-names = "pcie_0_pipe_clk";
2399 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2400 reset-names = "phy";
2402 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2403 assigned-clock-rates = <100000000>;
2405 status = "disabled";
2408 pcie1: pci@1c08000 {
2409 compatible = "qcom,pcie-sdm845";
2410 reg = <0 0x01c08000 0 0x2000>,
2411 <0 0x40000000 0 0xf1d>,
2412 <0 0x40000f20 0 0xa8>,
2413 <0 0x40100000 0 0x100000>,
2414 <0 0x01c0c000 0 0x1000>;
2415 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2416 device_type = "pci";
2417 linux,pci-domain = <1>;
2418 bus-range = <0x00 0xff>;
2421 #address-cells = <3>;
2424 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2425 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2427 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2428 interrupt-names = "msi";
2429 #interrupt-cells = <1>;
2430 interrupt-map-mask = <0 0 0 0x7>;
2431 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2432 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2433 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2434 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2436 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2437 <&gcc GCC_PCIE_1_AUX_CLK>,
2438 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2439 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2440 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2441 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2442 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2443 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2444 clock-names = "pipe",
2453 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2454 assigned-clock-rates = <19200000>;
2456 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2457 <0x100 &apps_smmu 0x1c01 0x1>,
2458 <0x200 &apps_smmu 0x1c02 0x1>,
2459 <0x300 &apps_smmu 0x1c03 0x1>,
2460 <0x400 &apps_smmu 0x1c04 0x1>,
2461 <0x500 &apps_smmu 0x1c05 0x1>,
2462 <0x600 &apps_smmu 0x1c06 0x1>,
2463 <0x700 &apps_smmu 0x1c07 0x1>,
2464 <0x800 &apps_smmu 0x1c08 0x1>,
2465 <0x900 &apps_smmu 0x1c09 0x1>,
2466 <0xa00 &apps_smmu 0x1c0a 0x1>,
2467 <0xb00 &apps_smmu 0x1c0b 0x1>,
2468 <0xc00 &apps_smmu 0x1c0c 0x1>,
2469 <0xd00 &apps_smmu 0x1c0d 0x1>,
2470 <0xe00 &apps_smmu 0x1c0e 0x1>,
2471 <0xf00 &apps_smmu 0x1c0f 0x1>;
2473 resets = <&gcc GCC_PCIE_1_BCR>;
2474 reset-names = "pci";
2476 power-domains = <&gcc PCIE_1_GDSC>;
2478 phys = <&pcie1_phy>;
2479 phy-names = "pciephy";
2481 status = "disabled";
2484 pcie1_phy: phy@1c0a000 {
2485 compatible = "qcom,sdm845-qhp-pcie-phy";
2486 reg = <0 0x01c0a000 0 0x2000>;
2487 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2488 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2489 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2490 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2491 <&gcc GCC_PCIE_1_PIPE_CLK>;
2492 clock-names = "aux",
2498 clock-output-names = "pcie_1_pipe_clk";
2503 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2504 reset-names = "phy";
2506 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2507 assigned-clock-rates = <100000000>;
2509 status = "disabled";
2512 mem_noc: interconnect@1380000 {
2513 compatible = "qcom,sdm845-mem-noc";
2514 reg = <0 0x01380000 0 0x27200>;
2515 #interconnect-cells = <2>;
2516 qcom,bcm-voters = <&apps_bcm_voter>;
2519 dc_noc: interconnect@14e0000 {
2520 compatible = "qcom,sdm845-dc-noc";
2521 reg = <0 0x014e0000 0 0x400>;
2522 #interconnect-cells = <2>;
2523 qcom,bcm-voters = <&apps_bcm_voter>;
2526 config_noc: interconnect@1500000 {
2527 compatible = "qcom,sdm845-config-noc";
2528 reg = <0 0x01500000 0 0x5080>;
2529 #interconnect-cells = <2>;
2530 qcom,bcm-voters = <&apps_bcm_voter>;
2533 system_noc: interconnect@1620000 {
2534 compatible = "qcom,sdm845-system-noc";
2535 reg = <0 0x01620000 0 0x18080>;
2536 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&apps_bcm_voter>;
2540 aggre1_noc: interconnect@16e0000 {
2541 compatible = "qcom,sdm845-aggre1-noc";
2542 reg = <0 0x016e0000 0 0x15080>;
2543 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&apps_bcm_voter>;
2547 aggre2_noc: interconnect@1700000 {
2548 compatible = "qcom,sdm845-aggre2-noc";
2549 reg = <0 0x01700000 0 0x1f300>;
2550 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&apps_bcm_voter>;
2554 mmss_noc: interconnect@1740000 {
2555 compatible = "qcom,sdm845-mmss-noc";
2556 reg = <0 0x01740000 0 0x1c100>;
2557 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&apps_bcm_voter>;
2561 ufs_mem_hc: ufshc@1d84000 {
2562 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2564 reg = <0 0x01d84000 0 0x2500>,
2565 <0 0x01d90000 0 0x8000>;
2566 reg-names = "std", "ice";
2567 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2568 phys = <&ufs_mem_phy_lanes>;
2569 phy-names = "ufsphy";
2570 lanes-per-direction = <2>;
2571 power-domains = <&gcc UFS_PHY_GDSC>;
2573 resets = <&gcc GCC_UFS_PHY_BCR>;
2574 reset-names = "rst";
2576 iommus = <&apps_smmu 0x100 0xf>;
2584 "tx_lane0_sync_clk",
2585 "rx_lane0_sync_clk",
2586 "rx_lane1_sync_clk",
2589 <&gcc GCC_UFS_PHY_AXI_CLK>,
2590 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2591 <&gcc GCC_UFS_PHY_AHB_CLK>,
2592 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2593 <&rpmhcc RPMH_CXO_CLK>,
2594 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2595 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2596 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2597 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2599 <50000000 200000000>,
2602 <37500000 150000000>,
2607 <75000000 300000000>;
2609 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2610 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2611 interconnect-names = "ufs-ddr", "cpu-ufs";
2613 status = "disabled";
2616 ufs_mem_phy: phy@1d87000 {
2617 compatible = "qcom,sdm845-qmp-ufs-phy";
2618 reg = <0 0x01d87000 0 0x18c>;
2619 #address-cells = <2>;
2622 clock-names = "ref",
2624 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2625 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2627 resets = <&ufs_mem_hc 0>;
2628 reset-names = "ufsphy";
2629 status = "disabled";
2631 ufs_mem_phy_lanes: phy@1d87400 {
2632 reg = <0 0x01d87400 0 0x108>,
2633 <0 0x01d87600 0 0x1e0>,
2634 <0 0x01d87c00 0 0x1dc>,
2635 <0 0x01d87800 0 0x108>,
2636 <0 0x01d87a00 0 0x1e0>;
2641 cryptobam: dma-controller@1dc4000 {
2642 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2643 reg = <0 0x01dc4000 0 0x24000>;
2644 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2645 clocks = <&rpmhcc RPMH_CE_CLK>;
2646 clock-names = "bam_clk";
2649 qcom,controlled-remotely;
2650 iommus = <&apps_smmu 0x704 0x1>,
2651 <&apps_smmu 0x706 0x1>,
2652 <&apps_smmu 0x714 0x1>,
2653 <&apps_smmu 0x716 0x1>;
2656 crypto: crypto@1dfa000 {
2657 compatible = "qcom,crypto-v5.4";
2658 reg = <0 0x01dfa000 0 0x6000>;
2659 clocks = <&gcc GCC_CE1_AHB_CLK>,
2660 <&gcc GCC_CE1_AXI_CLK>,
2661 <&rpmhcc RPMH_CE_CLK>;
2662 clock-names = "iface", "bus", "core";
2663 dmas = <&cryptobam 6>, <&cryptobam 7>;
2664 dma-names = "rx", "tx";
2665 iommus = <&apps_smmu 0x704 0x1>,
2666 <&apps_smmu 0x706 0x1>,
2667 <&apps_smmu 0x714 0x1>,
2668 <&apps_smmu 0x716 0x1>;
2672 compatible = "qcom,sdm845-ipa";
2674 iommus = <&apps_smmu 0x720 0x0>,
2675 <&apps_smmu 0x722 0x0>;
2676 reg = <0 0x01e40000 0 0x7000>,
2677 <0 0x01e47000 0 0x2000>,
2678 <0 0x01e04000 0 0x2c000>;
2679 reg-names = "ipa-reg",
2683 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2684 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2685 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2686 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2687 interrupt-names = "ipa",
2692 clocks = <&rpmhcc RPMH_IPA_CLK>;
2693 clock-names = "core";
2695 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2696 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2697 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2698 interconnect-names = "memory",
2702 qcom,smem-states = <&ipa_smp2p_out 0>,
2704 qcom,smem-state-names = "ipa-clock-enabled-valid",
2705 "ipa-clock-enabled";
2707 status = "disabled";
2710 tcsr_mutex: hwlock@1f40000 {
2711 compatible = "qcom,tcsr-mutex";
2712 reg = <0 0x01f40000 0 0x20000>;
2713 #hwlock-cells = <1>;
2716 tcsr_regs_1: syscon@1f60000 {
2717 compatible = "qcom,sdm845-tcsr", "syscon";
2718 reg = <0 0x01f60000 0 0x20000>;
2721 tlmm: pinctrl@3400000 {
2722 compatible = "qcom,sdm845-pinctrl";
2723 reg = <0 0x03400000 0 0xc00000>;
2724 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2727 interrupt-controller;
2728 #interrupt-cells = <2>;
2729 gpio-ranges = <&tlmm 0 0 151>;
2730 wakeup-parent = <&pdc_intc>;
2732 cci0_default: cci0-default-state {
2734 pins = "gpio17", "gpio18";
2735 function = "cci_i2c";
2738 drive-strength = <2>; /* 2 mA */
2741 cci0_sleep: cci0-sleep-state {
2743 pins = "gpio17", "gpio18";
2744 function = "cci_i2c";
2746 drive-strength = <2>; /* 2 mA */
2750 cci1_default: cci1-default-state {
2752 pins = "gpio19", "gpio20";
2753 function = "cci_i2c";
2756 drive-strength = <2>; /* 2 mA */
2759 cci1_sleep: cci1-sleep-state {
2761 pins = "gpio19", "gpio20";
2762 function = "cci_i2c";
2764 drive-strength = <2>; /* 2 mA */
2768 qspi_clk: qspi-clk-state {
2770 function = "qspi_clk";
2773 qspi_cs0: qspi-cs0-state {
2775 function = "qspi_cs";
2778 qspi_cs1: qspi-cs1-state {
2780 function = "qspi_cs";
2783 qspi_data0: qspi-data0-state {
2785 function = "qspi_data";
2788 qspi_data1: qspi-data1-state {
2790 function = "qspi_data";
2793 qspi_data23: qspi-data23-state {
2794 pins = "gpio93", "gpio94";
2795 function = "qspi_data";
2798 qup_i2c0_default: qup-i2c0-default-state {
2799 pins = "gpio0", "gpio1";
2803 qup_i2c1_default: qup-i2c1-default-state {
2804 pins = "gpio17", "gpio18";
2808 qup_i2c2_default: qup-i2c2-default-state {
2809 pins = "gpio27", "gpio28";
2813 qup_i2c3_default: qup-i2c3-default-state {
2814 pins = "gpio41", "gpio42";
2818 qup_i2c4_default: qup-i2c4-default-state {
2819 pins = "gpio89", "gpio90";
2823 qup_i2c5_default: qup-i2c5-default-state {
2824 pins = "gpio85", "gpio86";
2828 qup_i2c6_default: qup-i2c6-default-state {
2829 pins = "gpio45", "gpio46";
2833 qup_i2c7_default: qup-i2c7-default-state {
2834 pins = "gpio93", "gpio94";
2838 qup_i2c8_default: qup-i2c8-default-state {
2839 pins = "gpio65", "gpio66";
2843 qup_i2c9_default: qup-i2c9-default-state {
2844 pins = "gpio6", "gpio7";
2848 qup_i2c10_default: qup-i2c10-default-state {
2849 pins = "gpio55", "gpio56";
2853 qup_i2c11_default: qup-i2c11-default-state {
2854 pins = "gpio31", "gpio32";
2858 qup_i2c12_default: qup-i2c12-default-state {
2859 pins = "gpio49", "gpio50";
2863 qup_i2c13_default: qup-i2c13-default-state {
2864 pins = "gpio105", "gpio106";
2868 qup_i2c14_default: qup-i2c14-default-state {
2869 pins = "gpio33", "gpio34";
2873 qup_i2c15_default: qup-i2c15-default-state {
2874 pins = "gpio81", "gpio82";
2878 qup_spi0_default: qup-spi0-default-state {
2879 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2883 qup_spi1_default: qup-spi1-default-state {
2884 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2888 qup_spi2_default: qup-spi2-default-state {
2889 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2893 qup_spi3_default: qup-spi3-default-state {
2894 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2898 qup_spi4_default: qup-spi4-default-state {
2899 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2903 qup_spi5_default: qup-spi5-default-state {
2904 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2908 qup_spi6_default: qup-spi6-default-state {
2909 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2913 qup_spi7_default: qup-spi7-default-state {
2914 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2918 qup_spi8_default: qup-spi8-default-state {
2919 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2923 qup_spi9_default: qup-spi9-default-state {
2924 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2928 qup_spi10_default: qup-spi10-default-state {
2929 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2933 qup_spi11_default: qup-spi11-default-state {
2934 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2938 qup_spi12_default: qup-spi12-default-state {
2939 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2943 qup_spi13_default: qup-spi13-default-state {
2944 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2948 qup_spi14_default: qup-spi14-default-state {
2949 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2953 qup_spi15_default: qup-spi15-default-state {
2954 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2958 qup_uart0_default: qup-uart0-default-state {
2959 qup_uart0_tx: tx-pins {
2964 qup_uart0_rx: rx-pins {
2970 qup_uart1_default: qup-uart1-default-state {
2971 qup_uart1_tx: tx-pins {
2976 qup_uart1_rx: rx-pins {
2982 qup_uart2_default: qup-uart2-default-state {
2983 qup_uart2_tx: tx-pins {
2988 qup_uart2_rx: rx-pins {
2994 qup_uart3_default: qup-uart3-default-state {
2995 qup_uart3_tx: tx-pins {
3000 qup_uart3_rx: rx-pins {
3006 qup_uart3_4pin: qup-uart3-4pin-state {
3007 qup_uart3_4pin_cts: cts-pins {
3012 qup_uart3_4pin_rts_tx: rts-tx-pins {
3013 pins = "gpio42", "gpio43";
3017 qup_uart3_4pin_rx: rx-pins {
3023 qup_uart4_default: qup-uart4-default-state {
3024 qup_uart4_tx: tx-pins {
3029 qup_uart4_rx: rx-pins {
3035 qup_uart5_default: qup-uart5-default-state {
3036 qup_uart5_tx: tx-pins {
3041 qup_uart5_rx: rx-pins {
3047 qup_uart6_default: qup-uart6-default-state {
3048 qup_uart6_tx: tx-pins {
3053 qup_uart6_rx: rx-pins {
3059 qup_uart6_4pin: qup-uart6-4pin-state {
3060 qup_uart6_4pin_cts: cts-pins {
3066 qup_uart6_4pin_rts_tx: rts-tx-pins {
3067 pins = "gpio46", "gpio47";
3069 drive-strength = <2>;
3073 qup_uart6_4pin_rx: rx-pins {
3080 qup_uart7_default: qup-uart7-default-state {
3081 qup_uart7_tx: tx-pins {
3086 qup_uart7_rx: rx-pins {
3092 qup_uart8_default: qup-uart8-default-state {
3093 qup_uart8_tx: tx-pins {
3098 qup_uart8_rx: rx-pins {
3104 qup_uart9_default: qup-uart9-default-state {
3105 qup_uart9_tx: tx-pins {
3110 qup_uart9_rx: rx-pins {
3116 qup_uart10_default: qup-uart10-default-state {
3117 qup_uart10_tx: tx-pins {
3122 qup_uart10_rx: rx-pins {
3128 qup_uart11_default: qup-uart11-default-state {
3129 qup_uart11_tx: tx-pins {
3134 qup_uart11_rx: rx-pins {
3140 qup_uart12_default: qup-uart12-default-state {
3141 qup_uart12_tx: tx-pins {
3146 qup_uart12_rx: rx-pins {
3152 qup_uart13_default: qup-uart13-default-state {
3153 qup_uart13_tx: tx-pins {
3158 qup_uart13_rx: rx-pins {
3164 qup_uart14_default: qup-uart14-default-state {
3165 qup_uart14_tx: tx-pins {
3170 qup_uart14_rx: rx-pins {
3176 qup_uart15_default: qup-uart15-default-state {
3177 qup_uart15_tx: tx-pins {
3182 qup_uart15_rx: rx-pins {
3188 quat_mi2s_sleep: quat-mi2s-sleep-state {
3189 pins = "gpio58", "gpio59";
3191 drive-strength = <2>;
3195 quat_mi2s_active: quat-mi2s-active-state {
3196 pins = "gpio58", "gpio59";
3197 function = "qua_mi2s";
3198 drive-strength = <8>;
3203 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3206 drive-strength = <2>;
3210 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3212 function = "qua_mi2s";
3213 drive-strength = <8>;
3217 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3220 drive-strength = <2>;
3224 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3226 function = "qua_mi2s";
3227 drive-strength = <8>;
3231 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3234 drive-strength = <2>;
3238 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3240 function = "qua_mi2s";
3241 drive-strength = <8>;
3245 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3248 drive-strength = <2>;
3252 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3254 function = "qua_mi2s";
3255 drive-strength = <8>;
3260 mss_pil: remoteproc@4080000 {
3261 compatible = "qcom,sdm845-mss-pil";
3262 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3263 reg-names = "qdsp6", "rmb";
3265 interrupts-extended =
3266 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3267 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3268 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3269 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3270 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3271 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3272 interrupt-names = "wdog", "fatal", "ready",
3273 "handover", "stop-ack",
3276 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3277 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3278 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3279 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3280 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3281 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3282 <&gcc GCC_PRNG_AHB_CLK>,
3283 <&rpmhcc RPMH_CXO_CLK>;
3284 clock-names = "iface", "bus", "mem", "gpll0_mss",
3285 "snoc_axi", "mnoc_axi", "prng", "xo";
3287 qcom,qmp = <&aoss_qmp>;
3289 qcom,smem-states = <&modem_smp2p_out 0>;
3290 qcom,smem-state-names = "stop";
3292 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3293 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3294 reset-names = "mss_restart", "pdc_reset";
3296 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3298 power-domains = <&rpmhpd SDM845_CX>,
3299 <&rpmhpd SDM845_MX>,
3300 <&rpmhpd SDM845_MSS>;
3301 power-domain-names = "cx", "mx", "mss";
3303 status = "disabled";
3306 memory-region = <&mba_region>;
3310 memory-region = <&mpss_region>;
3314 memory-region = <&mdata_mem>;
3318 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3320 qcom,remote-pid = <1>;
3321 mboxes = <&apss_shared 12>;
3325 gpucc: clock-controller@5090000 {
3326 compatible = "qcom,sdm845-gpucc";
3327 reg = <0 0x05090000 0 0x9000>;
3330 #power-domain-cells = <1>;
3331 clocks = <&rpmhcc RPMH_CXO_CLK>,
3332 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3333 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3334 clock-names = "bi_tcxo",
3335 "gcc_gpu_gpll0_clk_src",
3336 "gcc_gpu_gpll0_div_clk_src";
3339 slpi_pas: remoteproc@5c00000 {
3340 compatible = "qcom,sdm845-slpi-pas";
3341 reg = <0 0x5c00000 0 0x4000>;
3343 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3344 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3345 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3346 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3347 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3348 interrupt-names = "wdog", "fatal", "ready",
3349 "handover", "stop-ack";
3351 clocks = <&rpmhcc RPMH_CXO_CLK>;
3354 qcom,qmp = <&aoss_qmp>;
3356 power-domains = <&rpmhpd SDM845_CX>,
3357 <&rpmhpd SDM845_MX>;
3358 power-domain-names = "lcx", "lmx";
3360 memory-region = <&slpi_mem>;
3362 qcom,smem-states = <&slpi_smp2p_out 0>;
3363 qcom,smem-state-names = "stop";
3365 status = "disabled";
3368 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3370 qcom,remote-pid = <3>;
3371 mboxes = <&apss_shared 24>;
3374 compatible = "qcom,fastrpc";
3375 qcom,glink-channels = "fastrpcglink-apps-dsp";
3377 qcom,non-secure-domain;
3378 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3379 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3380 memory-region = <&fastrpc_mem>;
3381 #address-cells = <1>;
3385 compatible = "qcom,fastrpc-compute-cb";
3393 compatible = "arm,coresight-stm", "arm,primecell";
3394 reg = <0 0x06002000 0 0x1000>,
3395 <0 0x16280000 0 0x180000>;
3396 reg-names = "stm-base", "stm-stimulus-base";
3398 clocks = <&aoss_qmp>;
3399 clock-names = "apb_pclk";
3412 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3413 reg = <0 0x06041000 0 0x1000>;
3415 clocks = <&aoss_qmp>;
3416 clock-names = "apb_pclk";
3420 funnel0_out: endpoint {
3422 <&merge_funnel_in0>;
3428 #address-cells = <1>;
3433 funnel0_in7: endpoint {
3434 remote-endpoint = <&stm_out>;
3441 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3442 reg = <0 0x06043000 0 0x1000>;
3444 clocks = <&aoss_qmp>;
3445 clock-names = "apb_pclk";
3449 funnel2_out: endpoint {
3451 <&merge_funnel_in2>;
3457 #address-cells = <1>;
3462 funnel2_in5: endpoint {
3464 <&apss_merge_funnel_out>;
3471 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3472 reg = <0 0x06045000 0 0x1000>;
3474 clocks = <&aoss_qmp>;
3475 clock-names = "apb_pclk";
3479 merge_funnel_out: endpoint {
3480 remote-endpoint = <&etf_in>;
3486 #address-cells = <1>;
3491 merge_funnel_in0: endpoint {
3499 merge_funnel_in2: endpoint {
3507 replicator@6046000 {
3508 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3509 reg = <0 0x06046000 0 0x1000>;
3511 clocks = <&aoss_qmp>;
3512 clock-names = "apb_pclk";
3516 replicator_out: endpoint {
3517 remote-endpoint = <&etr_in>;
3524 replicator_in: endpoint {
3525 remote-endpoint = <&etf_out>;
3532 compatible = "arm,coresight-tmc", "arm,primecell";
3533 reg = <0 0x06047000 0 0x1000>;
3535 clocks = <&aoss_qmp>;
3536 clock-names = "apb_pclk";
3548 #address-cells = <1>;
3555 <&merge_funnel_out>;
3562 compatible = "arm,coresight-tmc", "arm,primecell";
3563 reg = <0 0x06048000 0 0x1000>;
3565 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pclk";
3580 compatible = "arm,coresight-etm4x", "arm,primecell";
3581 reg = <0 0x07040000 0 0x1000>;
3585 clocks = <&aoss_qmp>;
3586 clock-names = "apb_pclk";
3587 arm,coresight-loses-context-with-cpu;
3591 etm0_out: endpoint {
3600 compatible = "arm,coresight-etm4x", "arm,primecell";
3601 reg = <0 0x07140000 0 0x1000>;
3605 clocks = <&aoss_qmp>;
3606 clock-names = "apb_pclk";
3607 arm,coresight-loses-context-with-cpu;
3611 etm1_out: endpoint {
3620 compatible = "arm,coresight-etm4x", "arm,primecell";
3621 reg = <0 0x07240000 0 0x1000>;
3625 clocks = <&aoss_qmp>;
3626 clock-names = "apb_pclk";
3627 arm,coresight-loses-context-with-cpu;
3631 etm2_out: endpoint {
3640 compatible = "arm,coresight-etm4x", "arm,primecell";
3641 reg = <0 0x07340000 0 0x1000>;
3645 clocks = <&aoss_qmp>;
3646 clock-names = "apb_pclk";
3647 arm,coresight-loses-context-with-cpu;
3651 etm3_out: endpoint {
3660 compatible = "arm,coresight-etm4x", "arm,primecell";
3661 reg = <0 0x07440000 0 0x1000>;
3665 clocks = <&aoss_qmp>;
3666 clock-names = "apb_pclk";
3667 arm,coresight-loses-context-with-cpu;
3671 etm4_out: endpoint {
3680 compatible = "arm,coresight-etm4x", "arm,primecell";
3681 reg = <0 0x07540000 0 0x1000>;
3685 clocks = <&aoss_qmp>;
3686 clock-names = "apb_pclk";
3687 arm,coresight-loses-context-with-cpu;
3691 etm5_out: endpoint {
3700 compatible = "arm,coresight-etm4x", "arm,primecell";
3701 reg = <0 0x07640000 0 0x1000>;
3705 clocks = <&aoss_qmp>;
3706 clock-names = "apb_pclk";
3707 arm,coresight-loses-context-with-cpu;
3711 etm6_out: endpoint {
3720 compatible = "arm,coresight-etm4x", "arm,primecell";
3721 reg = <0 0x07740000 0 0x1000>;
3725 clocks = <&aoss_qmp>;
3726 clock-names = "apb_pclk";
3727 arm,coresight-loses-context-with-cpu;
3731 etm7_out: endpoint {
3739 funnel@7800000 { /* APSS Funnel */
3740 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3741 reg = <0 0x07800000 0 0x1000>;
3743 clocks = <&aoss_qmp>;
3744 clock-names = "apb_pclk";
3748 apss_funnel_out: endpoint {
3750 <&apss_merge_funnel_in>;
3756 #address-cells = <1>;
3761 apss_funnel_in0: endpoint {
3769 apss_funnel_in1: endpoint {
3777 apss_funnel_in2: endpoint {
3785 apss_funnel_in3: endpoint {
3793 apss_funnel_in4: endpoint {
3801 apss_funnel_in5: endpoint {
3809 apss_funnel_in6: endpoint {
3817 apss_funnel_in7: endpoint {
3826 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3827 reg = <0 0x07810000 0 0x1000>;
3829 clocks = <&aoss_qmp>;
3830 clock-names = "apb_pclk";
3834 apss_merge_funnel_out: endpoint {
3843 apss_merge_funnel_in: endpoint {
3851 sdhc_2: mmc@8804000 {
3852 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3853 reg = <0 0x08804000 0 0x1000>;
3855 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3856 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3857 interrupt-names = "hc_irq", "pwr_irq";
3859 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3860 <&gcc GCC_SDCC2_APPS_CLK>,
3861 <&rpmhcc RPMH_CXO_CLK>;
3862 clock-names = "iface", "core", "xo";
3863 iommus = <&apps_smmu 0xa0 0xf>;
3864 power-domains = <&rpmhpd SDM845_CX>;
3865 operating-points-v2 = <&sdhc2_opp_table>;
3867 status = "disabled";
3869 sdhc2_opp_table: opp-table {
3870 compatible = "operating-points-v2";
3873 opp-hz = /bits/ 64 <9600000>;
3874 required-opps = <&rpmhpd_opp_min_svs>;
3878 opp-hz = /bits/ 64 <19200000>;
3879 required-opps = <&rpmhpd_opp_low_svs>;
3883 opp-hz = /bits/ 64 <100000000>;
3884 required-opps = <&rpmhpd_opp_svs>;
3888 opp-hz = /bits/ 64 <201500000>;
3889 required-opps = <&rpmhpd_opp_svs_l1>;
3895 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3896 reg = <0 0x088df000 0 0x600>;
3897 iommus = <&apps_smmu 0x160 0x0>;
3898 #address-cells = <1>;
3900 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3901 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3902 <&gcc GCC_QSPI_CORE_CLK>;
3903 clock-names = "iface", "core";
3904 power-domains = <&rpmhpd SDM845_CX>;
3905 operating-points-v2 = <&qspi_opp_table>;
3906 status = "disabled";
3909 slim: slim-ngd@171c0000 {
3910 compatible = "qcom,slim-ngd-v2.1.0";
3911 reg = <0 0x171c0000 0 0x2c000>;
3912 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3914 dmas = <&slimbam 3>, <&slimbam 4>;
3915 dma-names = "rx", "tx";
3917 iommus = <&apps_smmu 0x1806 0x0>;
3918 #address-cells = <1>;
3920 status = "disabled";
3923 lmh_cluster1: lmh@17d70800 {
3924 compatible = "qcom,sdm845-lmh";
3925 reg = <0 0x17d70800 0 0x400>;
3926 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3928 qcom,lmh-temp-arm-millicelsius = <65000>;
3929 qcom,lmh-temp-low-millicelsius = <94500>;
3930 qcom,lmh-temp-high-millicelsius = <95000>;
3931 interrupt-controller;
3932 #interrupt-cells = <1>;
3935 lmh_cluster0: lmh@17d78800 {
3936 compatible = "qcom,sdm845-lmh";
3937 reg = <0 0x17d78800 0 0x400>;
3938 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3940 qcom,lmh-temp-arm-millicelsius = <65000>;
3941 qcom,lmh-temp-low-millicelsius = <94500>;
3942 qcom,lmh-temp-high-millicelsius = <95000>;
3943 interrupt-controller;
3944 #interrupt-cells = <1>;
3947 usb_1_hsphy: phy@88e2000 {
3948 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3949 reg = <0 0x088e2000 0 0x400>;
3950 status = "disabled";
3953 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3954 <&rpmhcc RPMH_CXO_CLK>;
3955 clock-names = "cfg_ahb", "ref";
3957 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3959 nvmem-cells = <&qusb2p_hstx_trim>;
3962 usb_2_hsphy: phy@88e3000 {
3963 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3964 reg = <0 0x088e3000 0 0x400>;
3965 status = "disabled";
3968 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3969 <&rpmhcc RPMH_CXO_CLK>;
3970 clock-names = "cfg_ahb", "ref";
3972 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3974 nvmem-cells = <&qusb2s_hstx_trim>;
3977 usb_1_qmpphy: phy@88e8000 {
3978 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
3979 reg = <0 0x088e8000 0 0x3000>;
3980 status = "disabled";
3982 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3983 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3984 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3985 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
3986 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3987 clock-names = "aux",
3993 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3994 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
3995 reset-names = "phy", "common";
4001 usb_2_qmpphy: phy@88eb000 {
4002 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4003 reg = <0 0x088eb000 0 0x18c>;
4004 status = "disabled";
4005 #address-cells = <2>;
4009 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4010 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4011 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4012 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4013 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4015 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4016 <&gcc GCC_USB3_PHY_SEC_BCR>;
4017 reset-names = "phy", "common";
4019 usb_2_ssphy: phy@88eb200 {
4020 reg = <0 0x088eb200 0 0x128>,
4021 <0 0x088eb400 0 0x1fc>,
4022 <0 0x088eb800 0 0x218>,
4023 <0 0x088eb600 0 0x70>;
4026 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4027 clock-names = "pipe0";
4028 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4032 usb_1: usb@a6f8800 {
4033 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4034 reg = <0 0x0a6f8800 0 0x400>;
4035 status = "disabled";
4036 #address-cells = <2>;
4041 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4042 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4043 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4044 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4045 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4046 clock-names = "cfg_noc",
4052 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4053 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4054 assigned-clock-rates = <19200000>, <150000000>;
4056 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4057 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4058 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4059 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4060 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4061 "dm_hs_phy_irq", "dp_hs_phy_irq";
4063 power-domains = <&gcc USB30_PRIM_GDSC>;
4065 resets = <&gcc GCC_USB30_PRIM_BCR>;
4067 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4068 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4069 interconnect-names = "usb-ddr", "apps-usb";
4071 usb_1_dwc3: usb@a600000 {
4072 compatible = "snps,dwc3";
4073 reg = <0 0x0a600000 0 0xcd00>;
4074 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4075 iommus = <&apps_smmu 0x740 0>;
4076 snps,dis_u2_susphy_quirk;
4077 snps,dis_enblslpm_quirk;
4078 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4079 phy-names = "usb2-phy", "usb3-phy";
4083 usb_2: usb@a8f8800 {
4084 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4085 reg = <0 0x0a8f8800 0 0x400>;
4086 status = "disabled";
4087 #address-cells = <2>;
4092 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4093 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4094 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4095 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4096 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4097 clock-names = "cfg_noc",
4103 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4104 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4105 assigned-clock-rates = <19200000>, <150000000>;
4107 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4108 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4109 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4110 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4111 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4112 "dm_hs_phy_irq", "dp_hs_phy_irq";
4114 power-domains = <&gcc USB30_SEC_GDSC>;
4116 resets = <&gcc GCC_USB30_SEC_BCR>;
4118 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4119 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4120 interconnect-names = "usb-ddr", "apps-usb";
4122 usb_2_dwc3: usb@a800000 {
4123 compatible = "snps,dwc3";
4124 reg = <0 0x0a800000 0 0xcd00>;
4125 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4126 iommus = <&apps_smmu 0x760 0>;
4127 snps,dis_u2_susphy_quirk;
4128 snps,dis_enblslpm_quirk;
4129 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4130 phy-names = "usb2-phy", "usb3-phy";
4134 venus: video-codec@aa00000 {
4135 compatible = "qcom,sdm845-venus-v2";
4136 reg = <0 0x0aa00000 0 0xff000>;
4137 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4138 power-domains = <&videocc VENUS_GDSC>,
4139 <&videocc VCODEC0_GDSC>,
4140 <&videocc VCODEC1_GDSC>,
4141 <&rpmhpd SDM845_CX>;
4142 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4143 operating-points-v2 = <&venus_opp_table>;
4144 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4145 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4146 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4147 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4148 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4149 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4150 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4151 clock-names = "core", "iface", "bus",
4152 "vcodec0_core", "vcodec0_bus",
4153 "vcodec1_core", "vcodec1_bus";
4154 iommus = <&apps_smmu 0x10a0 0x8>,
4155 <&apps_smmu 0x10b0 0x0>;
4156 memory-region = <&venus_mem>;
4157 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4158 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4159 interconnect-names = "video-mem", "cpu-cfg";
4161 status = "disabled";
4164 compatible = "venus-decoder";
4168 compatible = "venus-encoder";
4171 venus_opp_table: opp-table {
4172 compatible = "operating-points-v2";
4175 opp-hz = /bits/ 64 <100000000>;
4176 required-opps = <&rpmhpd_opp_min_svs>;
4180 opp-hz = /bits/ 64 <200000000>;
4181 required-opps = <&rpmhpd_opp_low_svs>;
4185 opp-hz = /bits/ 64 <320000000>;
4186 required-opps = <&rpmhpd_opp_svs>;
4190 opp-hz = /bits/ 64 <380000000>;
4191 required-opps = <&rpmhpd_opp_svs_l1>;
4195 opp-hz = /bits/ 64 <444000000>;
4196 required-opps = <&rpmhpd_opp_nom>;
4200 opp-hz = /bits/ 64 <533000097>;
4201 required-opps = <&rpmhpd_opp_turbo>;
4206 videocc: clock-controller@ab00000 {
4207 compatible = "qcom,sdm845-videocc";
4208 reg = <0 0x0ab00000 0 0x10000>;
4209 clocks = <&rpmhcc RPMH_CXO_CLK>;
4210 clock-names = "bi_tcxo";
4212 #power-domain-cells = <1>;
4216 camss: camss@acb3000 {
4217 compatible = "qcom,sdm845-camss";
4219 reg = <0 0x0acb3000 0 0x1000>,
4220 <0 0x0acba000 0 0x1000>,
4221 <0 0x0acc8000 0 0x1000>,
4222 <0 0x0ac65000 0 0x1000>,
4223 <0 0x0ac66000 0 0x1000>,
4224 <0 0x0ac67000 0 0x1000>,
4225 <0 0x0ac68000 0 0x1000>,
4226 <0 0x0acaf000 0 0x4000>,
4227 <0 0x0acb6000 0 0x4000>,
4228 <0 0x0acc4000 0 0x4000>;
4229 reg-names = "csid0",
4240 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4250 interrupt-names = "csid0",
4261 power-domains = <&clock_camcc IFE_0_GDSC>,
4262 <&clock_camcc IFE_1_GDSC>,
4263 <&clock_camcc TITAN_TOP_GDSC>;
4265 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4266 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4267 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4268 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4269 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4270 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4271 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4272 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4273 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4274 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4275 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4276 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4277 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4278 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4279 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4280 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4281 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4282 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4283 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4284 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4285 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4286 <&gcc GCC_CAMERA_AHB_CLK>,
4287 <&gcc GCC_CAMERA_AXI_CLK>,
4288 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4289 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4290 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4291 <&clock_camcc CAM_CC_IFE_0_CLK>,
4292 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4293 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4294 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4295 <&clock_camcc CAM_CC_IFE_1_CLK>,
4296 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4297 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4298 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4299 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4300 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4301 clock-names = "camnoc_axi",
4312 "csiphy0_timer_src",
4315 "csiphy1_timer_src",
4318 "csiphy2_timer_src",
4321 "csiphy3_timer_src",
4338 iommus = <&apps_smmu 0x0808 0x0>,
4339 <&apps_smmu 0x0810 0x8>,
4340 <&apps_smmu 0x0c08 0x0>,
4341 <&apps_smmu 0x0c10 0x8>;
4343 status = "disabled";
4346 #address-cells = <1>;
4368 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4369 #address-cells = <1>;
4372 reg = <0 0x0ac4a000 0 0x4000>;
4373 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4374 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4376 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4377 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4378 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4379 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4380 <&clock_camcc CAM_CC_CCI_CLK>,
4381 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4382 clock-names = "camnoc_axi",
4389 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4390 <&clock_camcc CAM_CC_CCI_CLK>;
4391 assigned-clock-rates = <80000000>, <37500000>;
4393 pinctrl-names = "default", "sleep";
4394 pinctrl-0 = <&cci0_default &cci1_default>;
4395 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4397 status = "disabled";
4399 cci_i2c0: i2c-bus@0 {
4401 clock-frequency = <1000000>;
4402 #address-cells = <1>;
4406 cci_i2c1: i2c-bus@1 {
4408 clock-frequency = <1000000>;
4409 #address-cells = <1>;
4414 clock_camcc: clock-controller@ad00000 {
4415 compatible = "qcom,sdm845-camcc";
4416 reg = <0 0x0ad00000 0 0x10000>;
4419 #power-domain-cells = <1>;
4420 clocks = <&rpmhcc RPMH_CXO_CLK>;
4421 clock-names = "bi_tcxo";
4424 mdss: display-subsystem@ae00000 {
4425 compatible = "qcom,sdm845-mdss";
4426 reg = <0 0x0ae00000 0 0x1000>;
4429 power-domains = <&dispcc MDSS_GDSC>;
4431 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4432 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4433 clock-names = "iface", "core";
4435 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4436 interrupt-controller;
4437 #interrupt-cells = <1>;
4439 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4440 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4441 interconnect-names = "mdp0-mem", "mdp1-mem";
4443 iommus = <&apps_smmu 0x880 0x8>,
4444 <&apps_smmu 0xc80 0x8>;
4446 status = "disabled";
4448 #address-cells = <2>;
4452 mdss_mdp: display-controller@ae01000 {
4453 compatible = "qcom,sdm845-dpu";
4454 reg = <0 0x0ae01000 0 0x8f000>,
4455 <0 0x0aeb0000 0 0x2008>;
4456 reg-names = "mdp", "vbif";
4458 clocks = <&gcc GCC_DISP_AXI_CLK>,
4459 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4460 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4461 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4462 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4463 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4465 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4466 assigned-clock-rates = <19200000>;
4467 operating-points-v2 = <&mdp_opp_table>;
4468 power-domains = <&rpmhpd SDM845_CX>;
4470 interrupt-parent = <&mdss>;
4474 #address-cells = <1>;
4479 dpu_intf0_out: endpoint {
4480 remote-endpoint = <&dp_in>;
4486 dpu_intf1_out: endpoint {
4487 remote-endpoint = <&mdss_dsi0_in>;
4493 dpu_intf2_out: endpoint {
4494 remote-endpoint = <&mdss_dsi1_in>;
4499 mdp_opp_table: opp-table {
4500 compatible = "operating-points-v2";
4503 opp-hz = /bits/ 64 <19200000>;
4504 required-opps = <&rpmhpd_opp_min_svs>;
4508 opp-hz = /bits/ 64 <171428571>;
4509 required-opps = <&rpmhpd_opp_low_svs>;
4513 opp-hz = /bits/ 64 <344000000>;
4514 required-opps = <&rpmhpd_opp_svs_l1>;
4518 opp-hz = /bits/ 64 <430000000>;
4519 required-opps = <&rpmhpd_opp_nom>;
4524 mdss_dp: displayport-controller@ae90000 {
4525 status = "disabled";
4526 compatible = "qcom,sdm845-dp";
4528 reg = <0 0x0ae90000 0 0x200>,
4529 <0 0x0ae90200 0 0x200>,
4530 <0 0x0ae90400 0 0x600>,
4531 <0 0x0ae90a00 0 0x600>,
4532 <0 0x0ae91000 0 0x600>;
4534 interrupt-parent = <&mdss>;
4537 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4538 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4539 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4540 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4541 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4542 clock-names = "core_iface", "core_aux", "ctrl_link",
4543 "ctrl_link_iface", "stream_pixel";
4544 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4545 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4546 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4547 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4548 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4551 operating-points-v2 = <&dp_opp_table>;
4552 power-domains = <&rpmhpd SDM845_CX>;
4555 #address-cells = <1>;
4560 remote-endpoint = <&dpu_intf0_out>;
4566 dp_out: endpoint { };
4570 dp_opp_table: opp-table {
4571 compatible = "operating-points-v2";
4574 opp-hz = /bits/ 64 <162000000>;
4575 required-opps = <&rpmhpd_opp_low_svs>;
4579 opp-hz = /bits/ 64 <270000000>;
4580 required-opps = <&rpmhpd_opp_svs>;
4584 opp-hz = /bits/ 64 <540000000>;
4585 required-opps = <&rpmhpd_opp_svs_l1>;
4589 opp-hz = /bits/ 64 <810000000>;
4590 required-opps = <&rpmhpd_opp_nom>;
4595 mdss_dsi0: dsi@ae94000 {
4596 compatible = "qcom,sdm845-dsi-ctrl",
4597 "qcom,mdss-dsi-ctrl";
4598 reg = <0 0x0ae94000 0 0x400>;
4599 reg-names = "dsi_ctrl";
4601 interrupt-parent = <&mdss>;
4604 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4605 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4606 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4607 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4608 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4609 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4610 clock-names = "byte",
4616 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4617 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4619 operating-points-v2 = <&dsi_opp_table>;
4620 power-domains = <&rpmhpd SDM845_CX>;
4622 phys = <&mdss_dsi0_phy>;
4624 status = "disabled";
4626 #address-cells = <1>;
4630 #address-cells = <1>;
4635 mdss_dsi0_in: endpoint {
4636 remote-endpoint = <&dpu_intf1_out>;
4642 mdss_dsi0_out: endpoint {
4648 mdss_dsi0_phy: phy@ae94400 {
4649 compatible = "qcom,dsi-phy-10nm";
4650 reg = <0 0x0ae94400 0 0x200>,
4651 <0 0x0ae94600 0 0x280>,
4652 <0 0x0ae94a00 0 0x1e0>;
4653 reg-names = "dsi_phy",
4660 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4661 <&rpmhcc RPMH_CXO_CLK>;
4662 clock-names = "iface", "ref";
4664 status = "disabled";
4667 mdss_dsi1: dsi@ae96000 {
4668 compatible = "qcom,sdm845-dsi-ctrl",
4669 "qcom,mdss-dsi-ctrl";
4670 reg = <0 0x0ae96000 0 0x400>;
4671 reg-names = "dsi_ctrl";
4673 interrupt-parent = <&mdss>;
4676 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4677 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4678 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4679 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4680 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4681 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4682 clock-names = "byte",
4688 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4689 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4691 operating-points-v2 = <&dsi_opp_table>;
4692 power-domains = <&rpmhpd SDM845_CX>;
4694 phys = <&mdss_dsi1_phy>;
4696 status = "disabled";
4698 #address-cells = <1>;
4702 #address-cells = <1>;
4707 mdss_dsi1_in: endpoint {
4708 remote-endpoint = <&dpu_intf2_out>;
4714 mdss_dsi1_out: endpoint {
4720 mdss_dsi1_phy: phy@ae96400 {
4721 compatible = "qcom,dsi-phy-10nm";
4722 reg = <0 0x0ae96400 0 0x200>,
4723 <0 0x0ae96600 0 0x280>,
4724 <0 0x0ae96a00 0 0x10e>;
4725 reg-names = "dsi_phy",
4732 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4733 <&rpmhcc RPMH_CXO_CLK>;
4734 clock-names = "iface", "ref";
4736 status = "disabled";
4741 compatible = "qcom,adreno-630.2", "qcom,adreno";
4743 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4744 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4747 * Look ma, no clocks! The GPU clocks and power are
4748 * controlled entirely by the GMU
4751 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4753 iommus = <&adreno_smmu 0>;
4755 operating-points-v2 = <&gpu_opp_table>;
4759 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4760 interconnect-names = "gfx-mem";
4762 status = "disabled";
4764 gpu_opp_table: opp-table {
4765 compatible = "operating-points-v2";
4768 opp-hz = /bits/ 64 <710000000>;
4769 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4770 opp-peak-kBps = <7216000>;
4774 opp-hz = /bits/ 64 <675000000>;
4775 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4776 opp-peak-kBps = <7216000>;
4780 opp-hz = /bits/ 64 <596000000>;
4781 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4782 opp-peak-kBps = <6220000>;
4786 opp-hz = /bits/ 64 <520000000>;
4787 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4788 opp-peak-kBps = <6220000>;
4792 opp-hz = /bits/ 64 <414000000>;
4793 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4794 opp-peak-kBps = <4068000>;
4798 opp-hz = /bits/ 64 <342000000>;
4799 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4800 opp-peak-kBps = <2724000>;
4804 opp-hz = /bits/ 64 <257000000>;
4805 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4806 opp-peak-kBps = <1648000>;
4811 adreno_smmu: iommu@5040000 {
4812 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4813 reg = <0 0x05040000 0 0x10000>;
4815 #global-interrupts = <2>;
4816 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4817 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4818 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4819 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4820 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4821 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4822 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4823 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4824 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4825 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4826 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4827 <&gcc GCC_GPU_CFG_AHB_CLK>;
4828 clock-names = "bus", "iface";
4830 power-domains = <&gpucc GPU_CX_GDSC>;
4834 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4836 reg = <0 0x0506a000 0 0x30000>,
4837 <0 0x0b280000 0 0x10000>,
4838 <0 0x0b480000 0 0x10000>;
4839 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4841 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4842 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4843 interrupt-names = "hfi", "gmu";
4845 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4846 <&gpucc GPU_CC_CXO_CLK>,
4847 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4848 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4849 clock-names = "gmu", "cxo", "axi", "memnoc";
4851 power-domains = <&gpucc GPU_CX_GDSC>,
4852 <&gpucc GPU_GX_GDSC>;
4853 power-domain-names = "cx", "gx";
4855 iommus = <&adreno_smmu 5>;
4857 operating-points-v2 = <&gmu_opp_table>;
4859 status = "disabled";
4861 gmu_opp_table: opp-table {
4862 compatible = "operating-points-v2";
4865 opp-hz = /bits/ 64 <400000000>;
4866 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4870 opp-hz = /bits/ 64 <200000000>;
4871 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4876 dispcc: clock-controller@af00000 {
4877 compatible = "qcom,sdm845-dispcc";
4878 reg = <0 0x0af00000 0 0x10000>;
4879 clocks = <&rpmhcc RPMH_CXO_CLK>,
4880 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4881 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4886 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4887 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4888 clock-names = "bi_tcxo",
4889 "gcc_disp_gpll0_clk_src",
4890 "gcc_disp_gpll0_div_clk_src",
4891 "dsi0_phy_pll_out_byteclk",
4892 "dsi0_phy_pll_out_dsiclk",
4893 "dsi1_phy_pll_out_byteclk",
4894 "dsi1_phy_pll_out_dsiclk",
4895 "dp_link_clk_divsel_ten",
4896 "dp_vco_divided_clk_src_mux";
4899 #power-domain-cells = <1>;
4902 pdc_intc: interrupt-controller@b220000 {
4903 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4904 reg = <0 0x0b220000 0 0x30000>;
4905 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4906 #interrupt-cells = <2>;
4907 interrupt-parent = <&intc>;
4908 interrupt-controller;
4911 pdc_reset: reset-controller@b2e0000 {
4912 compatible = "qcom,sdm845-pdc-global";
4913 reg = <0 0x0b2e0000 0 0x20000>;
4917 tsens0: thermal-sensor@c263000 {
4918 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4919 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4920 <0 0x0c222000 0 0x1ff>; /* SROT */
4921 #qcom,sensors = <13>;
4922 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4923 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4924 interrupt-names = "uplow", "critical";
4925 #thermal-sensor-cells = <1>;
4928 tsens1: thermal-sensor@c265000 {
4929 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4930 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4931 <0 0x0c223000 0 0x1ff>; /* SROT */
4932 #qcom,sensors = <8>;
4933 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "uplow", "critical";
4936 #thermal-sensor-cells = <1>;
4939 aoss_reset: reset-controller@c2a0000 {
4940 compatible = "qcom,sdm845-aoss-cc";
4941 reg = <0 0x0c2a0000 0 0x31000>;
4945 aoss_qmp: power-management@c300000 {
4946 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4947 reg = <0 0x0c300000 0 0x400>;
4948 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4949 mboxes = <&apss_shared 0>;
4954 #cooling-cells = <2>;
4958 #cooling-cells = <2>;
4963 compatible = "qcom,sdm845-rpmh-stats";
4964 reg = <0 0x0c3f0000 0 0x400>;
4967 spmi_bus: spmi@c440000 {
4968 compatible = "qcom,spmi-pmic-arb";
4969 reg = <0 0x0c440000 0 0x1100>,
4970 <0 0x0c600000 0 0x2000000>,
4971 <0 0x0e600000 0 0x100000>,
4972 <0 0x0e700000 0 0xa0000>,
4973 <0 0x0c40a000 0 0x26000>;
4974 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4975 interrupt-names = "periph_irq";
4976 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4979 #address-cells = <2>;
4981 interrupt-controller;
4982 #interrupt-cells = <4>;
4986 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
4987 reg = <0 0x146bf000 0 0x1000>;
4989 #address-cells = <1>;
4992 ranges = <0 0 0x146bf000 0x1000>;
4995 compatible = "qcom,pil-reloc-info";
5000 apps_smmu: iommu@15000000 {
5001 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5002 reg = <0 0x15000000 0 0x80000>;
5004 #global-interrupts = <1>;
5005 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5006 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5007 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5008 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5009 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5010 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5011 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5012 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5013 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5014 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5016 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5017 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5018 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5019 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5020 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5021 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5022 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5023 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5024 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5025 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5027 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5028 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5029 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5030 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5031 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5032 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5033 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5034 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5035 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5036 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5037 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5038 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5039 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5040 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5041 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5042 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5043 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5045 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5046 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5047 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5048 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5049 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5050 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5051 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5052 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5053 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5054 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5056 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5057 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5058 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5059 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5060 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5061 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5062 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5063 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5064 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5065 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5066 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5067 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5068 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5069 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5072 lpasscc: clock-controller@17014000 {
5073 compatible = "qcom,sdm845-lpasscc";
5074 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5075 reg-names = "cc", "qdsp6ss";
5077 status = "disabled";
5080 gladiator_noc: interconnect@17900000 {
5081 compatible = "qcom,sdm845-gladiator-noc";
5082 reg = <0 0x17900000 0 0xd080>;
5083 #interconnect-cells = <2>;
5084 qcom,bcm-voters = <&apps_bcm_voter>;
5088 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5089 reg = <0 0x17980000 0 0x1000>;
5090 clocks = <&sleep_clk>;
5091 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5094 apss_shared: mailbox@17990000 {
5095 compatible = "qcom,sdm845-apss-shared";
5096 reg = <0 0x17990000 0 0x1000>;
5100 apps_rsc: rsc@179c0000 {
5102 compatible = "qcom,rpmh-rsc";
5103 reg = <0 0x179c0000 0 0x10000>,
5104 <0 0x179d0000 0 0x10000>,
5105 <0 0x179e0000 0 0x10000>;
5106 reg-names = "drv-0", "drv-1", "drv-2";
5107 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5110 qcom,tcs-offset = <0xd00>;
5112 qcom,tcs-config = <ACTIVE_TCS 2>,
5116 power-domains = <&CLUSTER_PD>;
5118 apps_bcm_voter: bcm-voter {
5119 compatible = "qcom,bcm-voter";
5122 rpmhcc: clock-controller {
5123 compatible = "qcom,sdm845-rpmh-clk";
5126 clocks = <&xo_board>;
5129 rpmhpd: power-controller {
5130 compatible = "qcom,sdm845-rpmhpd";
5131 #power-domain-cells = <1>;
5132 operating-points-v2 = <&rpmhpd_opp_table>;
5134 rpmhpd_opp_table: opp-table {
5135 compatible = "operating-points-v2";
5137 rpmhpd_opp_ret: opp1 {
5138 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5141 rpmhpd_opp_min_svs: opp2 {
5142 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5145 rpmhpd_opp_low_svs: opp3 {
5146 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5149 rpmhpd_opp_svs: opp4 {
5150 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5153 rpmhpd_opp_svs_l1: opp5 {
5154 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5157 rpmhpd_opp_nom: opp6 {
5158 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5161 rpmhpd_opp_nom_l1: opp7 {
5162 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5165 rpmhpd_opp_nom_l2: opp8 {
5166 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5169 rpmhpd_opp_turbo: opp9 {
5170 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5173 rpmhpd_opp_turbo_l1: opp10 {
5174 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5180 intc: interrupt-controller@17a00000 {
5181 compatible = "arm,gic-v3";
5182 #address-cells = <2>;
5185 #interrupt-cells = <3>;
5186 interrupt-controller;
5187 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5188 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5189 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5191 msi-controller@17a40000 {
5192 compatible = "arm,gic-v3-its";
5195 reg = <0 0x17a40000 0 0x20000>;
5196 status = "disabled";
5200 slimbam: dma-controller@17184000 {
5201 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5202 qcom,controlled-remotely;
5203 reg = <0 0x17184000 0 0x2a000>;
5204 num-channels = <31>;
5205 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5209 iommus = <&apps_smmu 0x1806 0x0>;
5213 #address-cells = <1>;
5215 ranges = <0 0 0 0x20000000>;
5216 compatible = "arm,armv7-timer-mem";
5217 reg = <0 0x17c90000 0 0x1000>;
5221 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5222 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5223 reg = <0x17ca0000 0x1000>,
5224 <0x17cb0000 0x1000>;
5229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5230 reg = <0x17cc0000 0x1000>;
5231 status = "disabled";
5236 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5237 reg = <0x17cd0000 0x1000>;
5238 status = "disabled";
5243 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5244 reg = <0x17ce0000 0x1000>;
5245 status = "disabled";
5250 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5251 reg = <0x17cf0000 0x1000>;
5252 status = "disabled";
5257 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5258 reg = <0x17d00000 0x1000>;
5259 status = "disabled";
5264 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5265 reg = <0x17d10000 0x1000>;
5266 status = "disabled";
5270 osm_l3: interconnect@17d41000 {
5271 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5272 reg = <0 0x17d41000 0 0x1400>;
5274 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5275 clock-names = "xo", "alternate";
5277 #interconnect-cells = <1>;
5280 cpufreq_hw: cpufreq@17d43000 {
5281 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5282 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5283 reg-names = "freq-domain0", "freq-domain1";
5285 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5287 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5288 clock-names = "xo", "alternate";
5290 #freq-domain-cells = <1>;
5294 wifi: wifi@18800000 {
5295 compatible = "qcom,wcn3990-wifi";
5296 status = "disabled";
5297 reg = <0 0x18800000 0 0x800000>;
5298 reg-names = "membase";
5299 memory-region = <&wlan_msa_mem>;
5300 clock-names = "cxo_ref_clk_pin";
5301 clocks = <&rpmhcc RPMH_RF_CLK2>;
5303 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5304 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5305 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5306 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5307 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5308 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5309 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5310 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5311 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5312 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5313 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5314 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5315 iommus = <&apps_smmu 0x0040 0x1>;
5324 polling-delay-passive = <250>;
5325 polling-delay = <1000>;
5327 thermal-sensors = <&tsens0 1>;
5330 cpu0_alert0: trip-point0 {
5331 temperature = <90000>;
5332 hysteresis = <2000>;
5336 cpu0_alert1: trip-point1 {
5337 temperature = <95000>;
5338 hysteresis = <2000>;
5342 cpu0_crit: cpu-crit {
5343 temperature = <110000>;
5344 hysteresis = <1000>;
5351 polling-delay-passive = <250>;
5352 polling-delay = <1000>;
5354 thermal-sensors = <&tsens0 2>;
5357 cpu1_alert0: trip-point0 {
5358 temperature = <90000>;
5359 hysteresis = <2000>;
5363 cpu1_alert1: trip-point1 {
5364 temperature = <95000>;
5365 hysteresis = <2000>;
5369 cpu1_crit: cpu-crit {
5370 temperature = <110000>;
5371 hysteresis = <1000>;
5378 polling-delay-passive = <250>;
5379 polling-delay = <1000>;
5381 thermal-sensors = <&tsens0 3>;
5384 cpu2_alert0: trip-point0 {
5385 temperature = <90000>;
5386 hysteresis = <2000>;
5390 cpu2_alert1: trip-point1 {
5391 temperature = <95000>;
5392 hysteresis = <2000>;
5396 cpu2_crit: cpu-crit {
5397 temperature = <110000>;
5398 hysteresis = <1000>;
5405 polling-delay-passive = <250>;
5406 polling-delay = <1000>;
5408 thermal-sensors = <&tsens0 4>;
5411 cpu3_alert0: trip-point0 {
5412 temperature = <90000>;
5413 hysteresis = <2000>;
5417 cpu3_alert1: trip-point1 {
5418 temperature = <95000>;
5419 hysteresis = <2000>;
5423 cpu3_crit: cpu-crit {
5424 temperature = <110000>;
5425 hysteresis = <1000>;
5432 polling-delay-passive = <250>;
5433 polling-delay = <1000>;
5435 thermal-sensors = <&tsens0 7>;
5438 cpu4_alert0: trip-point0 {
5439 temperature = <90000>;
5440 hysteresis = <2000>;
5444 cpu4_alert1: trip-point1 {
5445 temperature = <95000>;
5446 hysteresis = <2000>;
5450 cpu4_crit: cpu-crit {
5451 temperature = <110000>;
5452 hysteresis = <1000>;
5459 polling-delay-passive = <250>;
5460 polling-delay = <1000>;
5462 thermal-sensors = <&tsens0 8>;
5465 cpu5_alert0: trip-point0 {
5466 temperature = <90000>;
5467 hysteresis = <2000>;
5471 cpu5_alert1: trip-point1 {
5472 temperature = <95000>;
5473 hysteresis = <2000>;
5477 cpu5_crit: cpu-crit {
5478 temperature = <110000>;
5479 hysteresis = <1000>;
5486 polling-delay-passive = <250>;
5487 polling-delay = <1000>;
5489 thermal-sensors = <&tsens0 9>;
5492 cpu6_alert0: trip-point0 {
5493 temperature = <90000>;
5494 hysteresis = <2000>;
5498 cpu6_alert1: trip-point1 {
5499 temperature = <95000>;
5500 hysteresis = <2000>;
5504 cpu6_crit: cpu-crit {
5505 temperature = <110000>;
5506 hysteresis = <1000>;
5513 polling-delay-passive = <250>;
5514 polling-delay = <1000>;
5516 thermal-sensors = <&tsens0 10>;
5519 cpu7_alert0: trip-point0 {
5520 temperature = <90000>;
5521 hysteresis = <2000>;
5525 cpu7_alert1: trip-point1 {
5526 temperature = <95000>;
5527 hysteresis = <2000>;
5531 cpu7_crit: cpu-crit {
5532 temperature = <110000>;
5533 hysteresis = <1000>;
5540 polling-delay-passive = <250>;
5541 polling-delay = <1000>;
5543 thermal-sensors = <&tsens0 0>;
5546 aoss0_alert0: trip-point0 {
5547 temperature = <90000>;
5548 hysteresis = <2000>;
5555 polling-delay-passive = <250>;
5556 polling-delay = <1000>;
5558 thermal-sensors = <&tsens0 5>;
5561 cluster0_alert0: trip-point0 {
5562 temperature = <90000>;
5563 hysteresis = <2000>;
5566 cluster0_crit: cluster0_crit {
5567 temperature = <110000>;
5568 hysteresis = <2000>;
5575 polling-delay-passive = <250>;
5576 polling-delay = <1000>;
5578 thermal-sensors = <&tsens0 6>;
5581 cluster1_alert0: trip-point0 {
5582 temperature = <90000>;
5583 hysteresis = <2000>;
5586 cluster1_crit: cluster1_crit {
5587 temperature = <110000>;
5588 hysteresis = <2000>;
5595 polling-delay-passive = <250>;
5596 polling-delay = <1000>;
5598 thermal-sensors = <&tsens0 11>;
5601 gpu1_alert0: trip-point0 {
5602 temperature = <90000>;
5603 hysteresis = <2000>;
5609 gpu-bottom-thermal {
5610 polling-delay-passive = <250>;
5611 polling-delay = <1000>;
5613 thermal-sensors = <&tsens0 12>;
5616 gpu2_alert0: trip-point0 {
5617 temperature = <90000>;
5618 hysteresis = <2000>;
5625 polling-delay-passive = <250>;
5626 polling-delay = <1000>;
5628 thermal-sensors = <&tsens1 0>;
5631 aoss1_alert0: trip-point0 {
5632 temperature = <90000>;
5633 hysteresis = <2000>;
5640 polling-delay-passive = <250>;
5641 polling-delay = <1000>;
5643 thermal-sensors = <&tsens1 1>;
5646 q6_modem_alert0: trip-point0 {
5647 temperature = <90000>;
5648 hysteresis = <2000>;
5655 polling-delay-passive = <250>;
5656 polling-delay = <1000>;
5658 thermal-sensors = <&tsens1 2>;
5661 mem_alert0: trip-point0 {
5662 temperature = <90000>;
5663 hysteresis = <2000>;
5670 polling-delay-passive = <250>;
5671 polling-delay = <1000>;
5673 thermal-sensors = <&tsens1 3>;
5676 wlan_alert0: trip-point0 {
5677 temperature = <90000>;
5678 hysteresis = <2000>;
5685 polling-delay-passive = <250>;
5686 polling-delay = <1000>;
5688 thermal-sensors = <&tsens1 4>;
5691 q6_hvx_alert0: trip-point0 {
5692 temperature = <90000>;
5693 hysteresis = <2000>;
5700 polling-delay-passive = <250>;
5701 polling-delay = <1000>;
5703 thermal-sensors = <&tsens1 5>;
5706 camera_alert0: trip-point0 {
5707 temperature = <90000>;
5708 hysteresis = <2000>;
5715 polling-delay-passive = <250>;
5716 polling-delay = <1000>;
5718 thermal-sensors = <&tsens1 6>;
5721 video_alert0: trip-point0 {
5722 temperature = <90000>;
5723 hysteresis = <2000>;
5730 polling-delay-passive = <250>;
5731 polling-delay = <1000>;
5733 thermal-sensors = <&tsens1 7>;
5736 modem_alert0: trip-point0 {
5737 temperature = <90000>;
5738 hysteresis = <2000>;
5746 compatible = "arm,armv8-timer";
5747 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5748 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5749 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5750 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;