1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
14 #include <dt-bindings/interconnect/qcom,sdm845.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
68 device_type = "memory";
69 /* We expect the bootloader to fill in the size */
70 reg = <0 0x80000000 0 0>;
78 hyp_mem: memory@85700000 {
79 reg = <0 0x85700000 0 0x600000>;
83 xbl_mem: memory@85e00000 {
84 reg = <0 0x85e00000 0 0x100000>;
88 aop_mem: memory@85fc0000 {
89 reg = <0 0x85fc0000 0 0x20000>;
93 aop_cmd_db_mem: memory@85fe0000 {
94 compatible = "qcom,cmd-db";
95 reg = <0x0 0x85fe0000 0 0x20000>;
99 smem_mem: memory@86000000 {
100 reg = <0x0 0x86000000 0 0x200000>;
104 tz_mem: memory@86200000 {
105 reg = <0 0x86200000 0 0x2d00000>;
109 rmtfs_mem: memory@88f00000 {
110 compatible = "qcom,rmtfs-mem";
111 reg = <0 0x88f00000 0 0x200000>;
114 qcom,client-id = <1>;
118 qseecom_mem: memory@8ab00000 {
119 reg = <0 0x8ab00000 0 0x1400000>;
123 camera_mem: memory@8bf00000 {
124 reg = <0 0x8bf00000 0 0x500000>;
128 ipa_fw_mem: memory@8c400000 {
129 reg = <0 0x8c400000 0 0x10000>;
133 ipa_gsi_mem: memory@8c410000 {
134 reg = <0 0x8c410000 0 0x5000>;
138 gpu_mem: memory@8c415000 {
139 reg = <0 0x8c415000 0 0x2000>;
143 adsp_mem: memory@8c500000 {
144 reg = <0 0x8c500000 0 0x1a00000>;
148 wlan_msa_mem: memory@8df00000 {
149 reg = <0 0x8df00000 0 0x100000>;
153 mpss_region: memory@8e000000 {
154 reg = <0 0x8e000000 0 0x7800000>;
158 venus_mem: memory@95800000 {
159 reg = <0 0x95800000 0 0x500000>;
163 cdsp_mem: memory@95d00000 {
164 reg = <0 0x95d00000 0 0x800000>;
168 mba_region: memory@96500000 {
169 reg = <0 0x96500000 0 0x200000>;
173 slpi_mem: memory@96700000 {
174 reg = <0 0x96700000 0 0x1400000>;
178 spss_mem: memory@97b00000 {
179 reg = <0 0x97b00000 0 0x100000>;
185 #address-cells = <2>;
190 compatible = "qcom,kryo385";
192 enable-method = "psci";
193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
196 capacity-dmips-mhz = <607>;
197 dynamic-power-coefficient = <100>;
198 qcom,freq-domain = <&cpufreq_hw 0>;
199 #cooling-cells = <2>;
200 next-level-cache = <&L2_0>;
202 compatible = "cache";
203 next-level-cache = <&L3_0>;
205 compatible = "cache";
212 compatible = "qcom,kryo385";
214 enable-method = "psci";
215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
218 capacity-dmips-mhz = <607>;
219 dynamic-power-coefficient = <100>;
220 qcom,freq-domain = <&cpufreq_hw 0>;
221 #cooling-cells = <2>;
222 next-level-cache = <&L2_100>;
224 compatible = "cache";
225 next-level-cache = <&L3_0>;
231 compatible = "qcom,kryo385";
233 enable-method = "psci";
234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
237 capacity-dmips-mhz = <607>;
238 dynamic-power-coefficient = <100>;
239 qcom,freq-domain = <&cpufreq_hw 0>;
240 #cooling-cells = <2>;
241 next-level-cache = <&L2_200>;
243 compatible = "cache";
244 next-level-cache = <&L3_0>;
250 compatible = "qcom,kryo385";
252 enable-method = "psci";
253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
256 capacity-dmips-mhz = <607>;
257 dynamic-power-coefficient = <100>;
258 qcom,freq-domain = <&cpufreq_hw 0>;
259 #cooling-cells = <2>;
260 next-level-cache = <&L2_300>;
262 compatible = "cache";
263 next-level-cache = <&L3_0>;
269 compatible = "qcom,kryo385";
271 enable-method = "psci";
272 capacity-dmips-mhz = <1024>;
273 cpu-idle-states = <&BIG_CPU_SLEEP_0
276 dynamic-power-coefficient = <396>;
277 qcom,freq-domain = <&cpufreq_hw 1>;
278 #cooling-cells = <2>;
279 next-level-cache = <&L2_400>;
281 compatible = "cache";
282 next-level-cache = <&L3_0>;
288 compatible = "qcom,kryo385";
290 enable-method = "psci";
291 capacity-dmips-mhz = <1024>;
292 cpu-idle-states = <&BIG_CPU_SLEEP_0
295 dynamic-power-coefficient = <396>;
296 qcom,freq-domain = <&cpufreq_hw 1>;
297 #cooling-cells = <2>;
298 next-level-cache = <&L2_500>;
300 compatible = "cache";
301 next-level-cache = <&L3_0>;
307 compatible = "qcom,kryo385";
309 enable-method = "psci";
310 capacity-dmips-mhz = <1024>;
311 cpu-idle-states = <&BIG_CPU_SLEEP_0
314 dynamic-power-coefficient = <396>;
315 qcom,freq-domain = <&cpufreq_hw 1>;
316 #cooling-cells = <2>;
317 next-level-cache = <&L2_600>;
319 compatible = "cache";
320 next-level-cache = <&L3_0>;
326 compatible = "qcom,kryo385";
328 enable-method = "psci";
329 capacity-dmips-mhz = <1024>;
330 cpu-idle-states = <&BIG_CPU_SLEEP_0
333 dynamic-power-coefficient = <396>;
334 qcom,freq-domain = <&cpufreq_hw 1>;
335 #cooling-cells = <2>;
336 next-level-cache = <&L2_700>;
338 compatible = "cache";
339 next-level-cache = <&L3_0>;
380 entry-method = "psci";
382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
383 compatible = "arm,idle-state";
384 idle-state-name = "little-power-down";
385 arm,psci-suspend-param = <0x40000003>;
386 entry-latency-us = <350>;
387 exit-latency-us = <461>;
388 min-residency-us = <1890>;
392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
393 compatible = "arm,idle-state";
394 idle-state-name = "little-rail-power-down";
395 arm,psci-suspend-param = <0x40000004>;
396 entry-latency-us = <360>;
397 exit-latency-us = <531>;
398 min-residency-us = <3934>;
402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
403 compatible = "arm,idle-state";
404 idle-state-name = "big-power-down";
405 arm,psci-suspend-param = <0x40000003>;
406 entry-latency-us = <264>;
407 exit-latency-us = <621>;
408 min-residency-us = <952>;
412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
413 compatible = "arm,idle-state";
414 idle-state-name = "big-rail-power-down";
415 arm,psci-suspend-param = <0x40000004>;
416 entry-latency-us = <702>;
417 exit-latency-us = <1061>;
418 min-residency-us = <4488>;
422 CLUSTER_SLEEP_0: cluster-sleep-0 {
423 compatible = "arm,idle-state";
424 idle-state-name = "cluster-power-down";
425 arm,psci-suspend-param = <0x400000F4>;
426 entry-latency-us = <3263>;
427 exit-latency-us = <6562>;
428 min-residency-us = <9987>;
435 compatible = "arm,armv8-pmuv3";
436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
440 compatible = "arm,armv8-timer";
441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
449 compatible = "fixed-clock";
451 clock-frequency = <38400000>;
452 clock-output-names = "xo_board";
455 sleep_clk: sleep-clk {
456 compatible = "fixed-clock";
458 clock-frequency = <32764>;
464 compatible = "qcom,scm-sdm845", "qcom,scm";
468 adsp_pas: remoteproc-adsp {
469 compatible = "qcom,sdm845-adsp-pas";
471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
476 interrupt-names = "wdog", "fatal", "ready",
477 "handover", "stop-ack";
479 clocks = <&rpmhcc RPMH_CXO_CLK>;
482 memory-region = <&adsp_mem>;
484 qcom,smem-states = <&adsp_smp2p_out 0>;
485 qcom,smem-state-names = "stop";
490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
492 qcom,remote-pid = <2>;
493 mboxes = <&apss_shared 8>;
495 compatible = "qcom,fastrpc";
496 qcom,glink-channels = "fastrpcglink-apps-dsp";
498 #address-cells = <1>;
502 compatible = "qcom,fastrpc-compute-cb";
504 iommus = <&apps_smmu 0x1823 0x0>;
508 compatible = "qcom,fastrpc-compute-cb";
510 iommus = <&apps_smmu 0x1824 0x0>;
516 cdsp_pas: remoteproc-cdsp {
517 compatible = "qcom,sdm845-cdsp-pas";
519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
524 interrupt-names = "wdog", "fatal", "ready",
525 "handover", "stop-ack";
527 clocks = <&rpmhcc RPMH_CXO_CLK>;
530 memory-region = <&cdsp_mem>;
532 qcom,smem-states = <&cdsp_smp2p_out 0>;
533 qcom,smem-state-names = "stop";
538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
540 qcom,remote-pid = <5>;
541 mboxes = <&apss_shared 4>;
543 compatible = "qcom,fastrpc";
544 qcom,glink-channels = "fastrpcglink-apps-dsp";
546 #address-cells = <1>;
550 compatible = "qcom,fastrpc-compute-cb";
552 iommus = <&apps_smmu 0x1401 0x30>;
556 compatible = "qcom,fastrpc-compute-cb";
558 iommus = <&apps_smmu 0x1402 0x30>;
562 compatible = "qcom,fastrpc-compute-cb";
564 iommus = <&apps_smmu 0x1403 0x30>;
568 compatible = "qcom,fastrpc-compute-cb";
570 iommus = <&apps_smmu 0x1404 0x30>;
574 compatible = "qcom,fastrpc-compute-cb";
576 iommus = <&apps_smmu 0x1405 0x30>;
580 compatible = "qcom,fastrpc-compute-cb";
582 iommus = <&apps_smmu 0x1406 0x30>;
586 compatible = "qcom,fastrpc-compute-cb";
588 iommus = <&apps_smmu 0x1407 0x30>;
592 compatible = "qcom,fastrpc-compute-cb";
594 iommus = <&apps_smmu 0x1408 0x30>;
601 compatible = "qcom,tcsr-mutex";
602 syscon = <&tcsr_mutex_regs 0 0x1000>;
607 compatible = "qcom,smem";
608 memory-region = <&smem_mem>;
609 hwlocks = <&tcsr_mutex 3>;
613 compatible = "qcom,smp2p";
614 qcom,smem = <94>, <432>;
616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
618 mboxes = <&apss_shared 6>;
620 qcom,local-pid = <0>;
621 qcom,remote-pid = <5>;
623 cdsp_smp2p_out: master-kernel {
624 qcom,entry-name = "master-kernel";
625 #qcom,smem-state-cells = <1>;
628 cdsp_smp2p_in: slave-kernel {
629 qcom,entry-name = "slave-kernel";
631 interrupt-controller;
632 #interrupt-cells = <2>;
637 compatible = "qcom,smp2p";
638 qcom,smem = <443>, <429>;
640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
642 mboxes = <&apss_shared 10>;
644 qcom,local-pid = <0>;
645 qcom,remote-pid = <2>;
647 adsp_smp2p_out: master-kernel {
648 qcom,entry-name = "master-kernel";
649 #qcom,smem-state-cells = <1>;
652 adsp_smp2p_in: slave-kernel {
653 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
661 compatible = "qcom,smp2p";
662 qcom,smem = <435>, <428>;
663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
664 mboxes = <&apss_shared 14>;
665 qcom,local-pid = <0>;
666 qcom,remote-pid = <1>;
668 modem_smp2p_out: master-kernel {
669 qcom,entry-name = "master-kernel";
670 #qcom,smem-state-cells = <1>;
673 modem_smp2p_in: slave-kernel {
674 qcom,entry-name = "slave-kernel";
675 interrupt-controller;
676 #interrupt-cells = <2>;
681 compatible = "qcom,smp2p";
682 qcom,smem = <481>, <430>;
683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
684 mboxes = <&apss_shared 26>;
685 qcom,local-pid = <0>;
686 qcom,remote-pid = <3>;
688 slpi_smp2p_out: master-kernel {
689 qcom,entry-name = "master-kernel";
690 #qcom,smem-state-cells = <1>;
693 slpi_smp2p_in: slave-kernel {
694 qcom,entry-name = "slave-kernel";
695 interrupt-controller;
696 #interrupt-cells = <2>;
701 compatible = "arm,psci-1.0";
706 #address-cells = <2>;
708 ranges = <0 0 0 0 0x10 0>;
709 dma-ranges = <0 0 0 0 0x10 0>;
710 compatible = "simple-bus";
712 gcc: clock-controller@100000 {
713 compatible = "qcom,gcc-sdm845";
714 reg = <0 0x00100000 0 0x1f0000>;
717 #power-domain-cells = <1>;
718 power-domains = <&rpmhpd SDM845_CX>;
722 compatible = "qcom,qfprom";
723 reg = <0 0x00784000 0 0x8ff>;
724 #address-cells = <1>;
727 qusb2p_hstx_trim: hstx-trim-primary@1eb {
732 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
739 compatible = "qcom,prng-ee";
740 reg = <0 0x00793000 0 0x1000>;
741 clocks = <&gcc GCC_PRNG_AHB_CLK>;
742 clock-names = "core";
745 qupv3_id_0: geniqup@8c0000 {
746 compatible = "qcom,geni-se-qup";
747 reg = <0 0x008c0000 0 0x6000>;
748 clock-names = "m-ahb", "s-ahb";
749 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
750 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
751 #address-cells = <2>;
757 compatible = "qcom,geni-i2c";
758 reg = <0 0x00880000 0 0x4000>;
760 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&qup_i2c0_default>;
763 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
764 #address-cells = <1>;
770 compatible = "qcom,geni-spi";
771 reg = <0 0x00880000 0 0x4000>;
773 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&qup_spi0_default>;
776 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
777 #address-cells = <1>;
782 uart0: serial@880000 {
783 compatible = "qcom,geni-uart";
784 reg = <0 0x00880000 0 0x4000>;
786 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&qup_uart0_default>;
789 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
794 compatible = "qcom,geni-i2c";
795 reg = <0 0x00884000 0 0x4000>;
797 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
798 pinctrl-names = "default";
799 pinctrl-0 = <&qup_i2c1_default>;
800 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
801 #address-cells = <1>;
807 compatible = "qcom,geni-spi";
808 reg = <0 0x00884000 0 0x4000>;
810 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
811 pinctrl-names = "default";
812 pinctrl-0 = <&qup_spi1_default>;
813 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
814 #address-cells = <1>;
819 uart1: serial@884000 {
820 compatible = "qcom,geni-uart";
821 reg = <0 0x00884000 0 0x4000>;
823 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&qup_uart1_default>;
826 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
831 compatible = "qcom,geni-i2c";
832 reg = <0 0x00888000 0 0x4000>;
834 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
835 pinctrl-names = "default";
836 pinctrl-0 = <&qup_i2c2_default>;
837 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
838 #address-cells = <1>;
844 compatible = "qcom,geni-spi";
845 reg = <0 0x00888000 0 0x4000>;
847 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&qup_spi2_default>;
850 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
851 #address-cells = <1>;
856 uart2: serial@888000 {
857 compatible = "qcom,geni-uart";
858 reg = <0 0x00888000 0 0x4000>;
860 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
861 pinctrl-names = "default";
862 pinctrl-0 = <&qup_uart2_default>;
863 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
868 compatible = "qcom,geni-i2c";
869 reg = <0 0x0088c000 0 0x4000>;
871 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
872 pinctrl-names = "default";
873 pinctrl-0 = <&qup_i2c3_default>;
874 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
875 #address-cells = <1>;
881 compatible = "qcom,geni-spi";
882 reg = <0 0x0088c000 0 0x4000>;
884 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
885 pinctrl-names = "default";
886 pinctrl-0 = <&qup_spi3_default>;
887 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
888 #address-cells = <1>;
893 uart3: serial@88c000 {
894 compatible = "qcom,geni-uart";
895 reg = <0 0x0088c000 0 0x4000>;
897 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
898 pinctrl-names = "default";
899 pinctrl-0 = <&qup_uart3_default>;
900 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
905 compatible = "qcom,geni-i2c";
906 reg = <0 0x00890000 0 0x4000>;
908 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
909 pinctrl-names = "default";
910 pinctrl-0 = <&qup_i2c4_default>;
911 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
912 #address-cells = <1>;
918 compatible = "qcom,geni-spi";
919 reg = <0 0x00890000 0 0x4000>;
921 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
922 pinctrl-names = "default";
923 pinctrl-0 = <&qup_spi4_default>;
924 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
925 #address-cells = <1>;
930 uart4: serial@890000 {
931 compatible = "qcom,geni-uart";
932 reg = <0 0x00890000 0 0x4000>;
934 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
935 pinctrl-names = "default";
936 pinctrl-0 = <&qup_uart4_default>;
937 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
942 compatible = "qcom,geni-i2c";
943 reg = <0 0x00894000 0 0x4000>;
945 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
946 pinctrl-names = "default";
947 pinctrl-0 = <&qup_i2c5_default>;
948 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
949 #address-cells = <1>;
955 compatible = "qcom,geni-spi";
956 reg = <0 0x00894000 0 0x4000>;
958 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&qup_spi5_default>;
961 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
962 #address-cells = <1>;
967 uart5: serial@894000 {
968 compatible = "qcom,geni-uart";
969 reg = <0 0x00894000 0 0x4000>;
971 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
972 pinctrl-names = "default";
973 pinctrl-0 = <&qup_uart5_default>;
974 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
979 compatible = "qcom,geni-i2c";
980 reg = <0 0x00898000 0 0x4000>;
982 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
983 pinctrl-names = "default";
984 pinctrl-0 = <&qup_i2c6_default>;
985 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
986 #address-cells = <1>;
992 compatible = "qcom,geni-spi";
993 reg = <0 0x00898000 0 0x4000>;
995 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
996 pinctrl-names = "default";
997 pinctrl-0 = <&qup_spi6_default>;
998 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
999 #address-cells = <1>;
1001 status = "disabled";
1004 uart6: serial@898000 {
1005 compatible = "qcom,geni-uart";
1006 reg = <0 0x00898000 0 0x4000>;
1008 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1009 pinctrl-names = "default";
1010 pinctrl-0 = <&qup_uart6_default>;
1011 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1012 status = "disabled";
1016 compatible = "qcom,geni-i2c";
1017 reg = <0 0x0089c000 0 0x4000>;
1019 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c7_default>;
1022 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1023 #address-cells = <1>;
1025 status = "disabled";
1029 compatible = "qcom,geni-spi";
1030 reg = <0 0x0089c000 0 0x4000>;
1032 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&qup_spi7_default>;
1035 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1036 #address-cells = <1>;
1038 status = "disabled";
1041 uart7: serial@89c000 {
1042 compatible = "qcom,geni-uart";
1043 reg = <0 0x0089c000 0 0x4000>;
1045 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_uart7_default>;
1048 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1049 status = "disabled";
1053 qupv3_id_1: geniqup@ac0000 {
1054 compatible = "qcom,geni-se-qup";
1055 reg = <0 0x00ac0000 0 0x6000>;
1056 clock-names = "m-ahb", "s-ahb";
1057 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1058 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1059 #address-cells = <2>;
1062 status = "disabled";
1065 compatible = "qcom,geni-i2c";
1066 reg = <0 0x00a80000 0 0x4000>;
1068 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_i2c8_default>;
1071 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1072 #address-cells = <1>;
1074 status = "disabled";
1078 compatible = "qcom,geni-spi";
1079 reg = <0 0x00a80000 0 0x4000>;
1081 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&qup_spi8_default>;
1084 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1085 #address-cells = <1>;
1087 status = "disabled";
1090 uart8: serial@a80000 {
1091 compatible = "qcom,geni-uart";
1092 reg = <0 0x00a80000 0 0x4000>;
1094 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&qup_uart8_default>;
1097 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1098 status = "disabled";
1102 compatible = "qcom,geni-i2c";
1103 reg = <0 0x00a84000 0 0x4000>;
1105 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&qup_i2c9_default>;
1108 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1109 #address-cells = <1>;
1111 status = "disabled";
1115 compatible = "qcom,geni-spi";
1116 reg = <0 0x00a84000 0 0x4000>;
1118 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&qup_spi9_default>;
1121 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1122 #address-cells = <1>;
1124 status = "disabled";
1127 uart9: serial@a84000 {
1128 compatible = "qcom,geni-debug-uart";
1129 reg = <0 0x00a84000 0 0x4000>;
1131 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_uart9_default>;
1134 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1135 status = "disabled";
1139 compatible = "qcom,geni-i2c";
1140 reg = <0 0x00a88000 0 0x4000>;
1142 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&qup_i2c10_default>;
1145 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1146 #address-cells = <1>;
1148 status = "disabled";
1152 compatible = "qcom,geni-spi";
1153 reg = <0 0x00a88000 0 0x4000>;
1155 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_spi10_default>;
1158 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1159 #address-cells = <1>;
1161 status = "disabled";
1164 uart10: serial@a88000 {
1165 compatible = "qcom,geni-uart";
1166 reg = <0 0x00a88000 0 0x4000>;
1168 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&qup_uart10_default>;
1171 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1172 status = "disabled";
1176 compatible = "qcom,geni-i2c";
1177 reg = <0 0x00a8c000 0 0x4000>;
1179 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&qup_i2c11_default>;
1182 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1183 #address-cells = <1>;
1185 status = "disabled";
1189 compatible = "qcom,geni-spi";
1190 reg = <0 0x00a8c000 0 0x4000>;
1192 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_spi11_default>;
1195 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1196 #address-cells = <1>;
1198 status = "disabled";
1201 uart11: serial@a8c000 {
1202 compatible = "qcom,geni-uart";
1203 reg = <0 0x00a8c000 0 0x4000>;
1205 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_uart11_default>;
1208 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1209 status = "disabled";
1213 compatible = "qcom,geni-i2c";
1214 reg = <0 0x00a90000 0 0x4000>;
1216 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1217 pinctrl-names = "default";
1218 pinctrl-0 = <&qup_i2c12_default>;
1219 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1220 #address-cells = <1>;
1222 status = "disabled";
1226 compatible = "qcom,geni-spi";
1227 reg = <0 0x00a90000 0 0x4000>;
1229 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1230 pinctrl-names = "default";
1231 pinctrl-0 = <&qup_spi12_default>;
1232 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1233 #address-cells = <1>;
1235 status = "disabled";
1238 uart12: serial@a90000 {
1239 compatible = "qcom,geni-uart";
1240 reg = <0 0x00a90000 0 0x4000>;
1242 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&qup_uart12_default>;
1245 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1246 status = "disabled";
1250 compatible = "qcom,geni-i2c";
1251 reg = <0 0x00a94000 0 0x4000>;
1253 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&qup_i2c13_default>;
1256 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1257 #address-cells = <1>;
1259 status = "disabled";
1263 compatible = "qcom,geni-spi";
1264 reg = <0 0x00a94000 0 0x4000>;
1266 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&qup_spi13_default>;
1269 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1270 #address-cells = <1>;
1272 status = "disabled";
1275 uart13: serial@a94000 {
1276 compatible = "qcom,geni-uart";
1277 reg = <0 0x00a94000 0 0x4000>;
1279 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_uart13_default>;
1282 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1283 status = "disabled";
1287 compatible = "qcom,geni-i2c";
1288 reg = <0 0x00a98000 0 0x4000>;
1290 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1291 pinctrl-names = "default";
1292 pinctrl-0 = <&qup_i2c14_default>;
1293 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1294 #address-cells = <1>;
1296 status = "disabled";
1300 compatible = "qcom,geni-spi";
1301 reg = <0 0x00a98000 0 0x4000>;
1303 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1304 pinctrl-names = "default";
1305 pinctrl-0 = <&qup_spi14_default>;
1306 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1307 #address-cells = <1>;
1309 status = "disabled";
1312 uart14: serial@a98000 {
1313 compatible = "qcom,geni-uart";
1314 reg = <0 0x00a98000 0 0x4000>;
1316 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1317 pinctrl-names = "default";
1318 pinctrl-0 = <&qup_uart14_default>;
1319 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1320 status = "disabled";
1324 compatible = "qcom,geni-i2c";
1325 reg = <0 0x00a9c000 0 0x4000>;
1327 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1328 pinctrl-names = "default";
1329 pinctrl-0 = <&qup_i2c15_default>;
1330 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1331 #address-cells = <1>;
1333 status = "disabled";
1337 compatible = "qcom,geni-spi";
1338 reg = <0 0x00a9c000 0 0x4000>;
1340 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&qup_spi15_default>;
1343 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1344 #address-cells = <1>;
1346 status = "disabled";
1349 uart15: serial@a9c000 {
1350 compatible = "qcom,geni-uart";
1351 reg = <0 0x00a9c000 0 0x4000>;
1353 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1354 pinctrl-names = "default";
1355 pinctrl-0 = <&qup_uart15_default>;
1356 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1357 status = "disabled";
1361 cache-controller@1100000 {
1362 compatible = "qcom,sdm845-llcc";
1363 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1364 reg-names = "llcc_base", "llcc_broadcast_base";
1365 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1368 ufs_mem_hc: ufshc@1d84000 {
1369 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1371 reg = <0 0x01d84000 0 0x2500>;
1372 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1373 phys = <&ufs_mem_phy_lanes>;
1374 phy-names = "ufsphy";
1375 lanes-per-direction = <2>;
1376 power-domains = <&gcc UFS_PHY_GDSC>;
1379 iommus = <&apps_smmu 0x100 0xf>;
1387 "tx_lane0_sync_clk",
1388 "rx_lane0_sync_clk",
1389 "rx_lane1_sync_clk";
1391 <&gcc GCC_UFS_PHY_AXI_CLK>,
1392 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1393 <&gcc GCC_UFS_PHY_AHB_CLK>,
1394 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1395 <&rpmhcc RPMH_CXO_CLK>,
1396 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1397 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1398 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1400 <50000000 200000000>,
1403 <37500000 150000000>,
1409 status = "disabled";
1412 ufs_mem_phy: phy@1d87000 {
1413 compatible = "qcom,sdm845-qmp-ufs-phy";
1414 reg = <0 0x01d87000 0 0x18c>;
1415 #address-cells = <2>;
1418 clock-names = "ref",
1420 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1421 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1423 resets = <&ufs_mem_hc 0>;
1424 reset-names = "ufsphy";
1425 status = "disabled";
1427 ufs_mem_phy_lanes: lanes@1d87400 {
1428 reg = <0 0x01d87400 0 0x108>,
1429 <0 0x01d87600 0 0x1e0>,
1430 <0 0x01d87c00 0 0x1dc>,
1431 <0 0x01d87800 0 0x108>,
1432 <0 0x01d87a00 0 0x1e0>;
1437 tcsr_mutex_regs: syscon@1f40000 {
1438 compatible = "syscon";
1439 reg = <0 0x01f40000 0 0x40000>;
1442 tlmm: pinctrl@3400000 {
1443 compatible = "qcom,sdm845-pinctrl";
1444 reg = <0 0x03400000 0 0xc00000>;
1445 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1448 interrupt-controller;
1449 #interrupt-cells = <2>;
1450 gpio-ranges = <&tlmm 0 0 150>;
1452 qspi_clk: qspi-clk {
1455 function = "qspi_clk";
1459 qspi_cs0: qspi-cs0 {
1462 function = "qspi_cs";
1466 qspi_cs1: qspi-cs1 {
1469 function = "qspi_cs";
1473 qspi_data01: qspi-data01 {
1475 pins = "gpio91", "gpio92";
1476 function = "qspi_data";
1480 qspi_data12: qspi-data12 {
1482 pins = "gpio93", "gpio94";
1483 function = "qspi_data";
1487 qup_i2c0_default: qup-i2c0-default {
1489 pins = "gpio0", "gpio1";
1494 qup_i2c1_default: qup-i2c1-default {
1496 pins = "gpio17", "gpio18";
1501 qup_i2c2_default: qup-i2c2-default {
1503 pins = "gpio27", "gpio28";
1508 qup_i2c3_default: qup-i2c3-default {
1510 pins = "gpio41", "gpio42";
1515 qup_i2c4_default: qup-i2c4-default {
1517 pins = "gpio89", "gpio90";
1522 qup_i2c5_default: qup-i2c5-default {
1524 pins = "gpio85", "gpio86";
1529 qup_i2c6_default: qup-i2c6-default {
1531 pins = "gpio45", "gpio46";
1536 qup_i2c7_default: qup-i2c7-default {
1538 pins = "gpio93", "gpio94";
1543 qup_i2c8_default: qup-i2c8-default {
1545 pins = "gpio65", "gpio66";
1550 qup_i2c9_default: qup-i2c9-default {
1552 pins = "gpio6", "gpio7";
1557 qup_i2c10_default: qup-i2c10-default {
1559 pins = "gpio55", "gpio56";
1564 qup_i2c11_default: qup-i2c11-default {
1566 pins = "gpio31", "gpio32";
1571 qup_i2c12_default: qup-i2c12-default {
1573 pins = "gpio49", "gpio50";
1578 qup_i2c13_default: qup-i2c13-default {
1580 pins = "gpio105", "gpio106";
1585 qup_i2c14_default: qup-i2c14-default {
1587 pins = "gpio33", "gpio34";
1592 qup_i2c15_default: qup-i2c15-default {
1594 pins = "gpio81", "gpio82";
1599 qup_spi0_default: qup-spi0-default {
1601 pins = "gpio0", "gpio1",
1607 qup_spi1_default: qup-spi1-default {
1609 pins = "gpio17", "gpio18",
1615 qup_spi2_default: qup-spi2-default {
1617 pins = "gpio27", "gpio28",
1623 qup_spi3_default: qup-spi3-default {
1625 pins = "gpio41", "gpio42",
1631 qup_spi4_default: qup-spi4-default {
1633 pins = "gpio89", "gpio90",
1639 qup_spi5_default: qup-spi5-default {
1641 pins = "gpio85", "gpio86",
1647 qup_spi6_default: qup-spi6-default {
1649 pins = "gpio45", "gpio46",
1655 qup_spi7_default: qup-spi7-default {
1657 pins = "gpio93", "gpio94",
1663 qup_spi8_default: qup-spi8-default {
1665 pins = "gpio65", "gpio66",
1671 qup_spi9_default: qup-spi9-default {
1673 pins = "gpio6", "gpio7",
1679 qup_spi10_default: qup-spi10-default {
1681 pins = "gpio55", "gpio56",
1687 qup_spi11_default: qup-spi11-default {
1689 pins = "gpio31", "gpio32",
1695 qup_spi12_default: qup-spi12-default {
1697 pins = "gpio49", "gpio50",
1703 qup_spi13_default: qup-spi13-default {
1705 pins = "gpio105", "gpio106",
1706 "gpio107", "gpio108";
1711 qup_spi14_default: qup-spi14-default {
1713 pins = "gpio33", "gpio34",
1719 qup_spi15_default: qup-spi15-default {
1721 pins = "gpio81", "gpio82",
1727 qup_uart0_default: qup-uart0-default {
1729 pins = "gpio2", "gpio3";
1734 qup_uart1_default: qup-uart1-default {
1736 pins = "gpio19", "gpio20";
1741 qup_uart2_default: qup-uart2-default {
1743 pins = "gpio29", "gpio30";
1748 qup_uart3_default: qup-uart3-default {
1750 pins = "gpio43", "gpio44";
1755 qup_uart4_default: qup-uart4-default {
1757 pins = "gpio91", "gpio92";
1762 qup_uart5_default: qup-uart5-default {
1764 pins = "gpio87", "gpio88";
1769 qup_uart6_default: qup-uart6-default {
1771 pins = "gpio47", "gpio48";
1776 qup_uart7_default: qup-uart7-default {
1778 pins = "gpio95", "gpio96";
1783 qup_uart8_default: qup-uart8-default {
1785 pins = "gpio67", "gpio68";
1790 qup_uart9_default: qup-uart9-default {
1792 pins = "gpio4", "gpio5";
1797 qup_uart10_default: qup-uart10-default {
1799 pins = "gpio53", "gpio54";
1804 qup_uart11_default: qup-uart11-default {
1806 pins = "gpio33", "gpio34";
1811 qup_uart12_default: qup-uart12-default {
1813 pins = "gpio51", "gpio52";
1818 qup_uart13_default: qup-uart13-default {
1820 pins = "gpio107", "gpio108";
1825 qup_uart14_default: qup-uart14-default {
1827 pins = "gpio31", "gpio32";
1832 qup_uart15_default: qup-uart15-default {
1834 pins = "gpio83", "gpio84";
1840 mss_pil: remoteproc@4080000 {
1841 compatible = "qcom,sdm845-mss-pil";
1842 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
1843 reg-names = "qdsp6", "rmb";
1845 interrupts-extended =
1846 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1847 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1848 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1849 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1850 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1851 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1852 interrupt-names = "wdog", "fatal", "ready",
1853 "handover", "stop-ack",
1856 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1857 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1858 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1859 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1860 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1861 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1862 <&gcc GCC_PRNG_AHB_CLK>,
1863 <&rpmhcc RPMH_CXO_CLK>;
1864 clock-names = "iface", "bus", "mem", "gpll0_mss",
1865 "snoc_axi", "mnoc_axi", "prng", "xo";
1867 qcom,smem-states = <&modem_smp2p_out 0>;
1868 qcom,smem-state-names = "stop";
1870 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1871 <&pdc_reset PDC_MODEM_SYNC_RESET>;
1872 reset-names = "mss_restart", "pdc_reset";
1874 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1876 power-domains = <&aoss_qmp 2>,
1877 <&rpmhpd SDM845_CX>,
1878 <&rpmhpd SDM845_MX>,
1879 <&rpmhpd SDM845_MSS>;
1880 power-domain-names = "load_state", "cx", "mx", "mss";
1883 memory-region = <&mba_region>;
1887 memory-region = <&mpss_region>;
1891 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1893 qcom,remote-pid = <1>;
1894 mboxes = <&apss_shared 12>;
1898 gpucc: clock-controller@5090000 {
1899 compatible = "qcom,sdm845-gpucc";
1900 reg = <0 0x05090000 0 0x9000>;
1903 #power-domain-cells = <1>;
1904 clocks = <&rpmhcc RPMH_CXO_CLK>;
1909 compatible = "arm,coresight-stm", "arm,primecell";
1910 reg = <0 0x06002000 0 0x1000>,
1911 <0 0x16280000 0 0x180000>;
1912 reg-names = "stm-base", "stm-stimulus-base";
1914 clocks = <&aoss_qmp>;
1915 clock-names = "apb_pclk";
1928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1929 reg = <0 0x06041000 0 0x1000>;
1931 clocks = <&aoss_qmp>;
1932 clock-names = "apb_pclk";
1936 funnel0_out: endpoint {
1938 <&merge_funnel_in0>;
1944 #address-cells = <1>;
1949 funnel0_in7: endpoint {
1950 remote-endpoint = <&stm_out>;
1957 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1958 reg = <0 0x06043000 0 0x1000>;
1960 clocks = <&aoss_qmp>;
1961 clock-names = "apb_pclk";
1965 funnel2_out: endpoint {
1967 <&merge_funnel_in2>;
1973 #address-cells = <1>;
1978 funnel2_in5: endpoint {
1980 <&apss_merge_funnel_out>;
1987 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1988 reg = <0 0x06045000 0 0x1000>;
1990 clocks = <&aoss_qmp>;
1991 clock-names = "apb_pclk";
1995 merge_funnel_out: endpoint {
1996 remote-endpoint = <&etf_in>;
2002 #address-cells = <1>;
2007 merge_funnel_in0: endpoint {
2015 merge_funnel_in2: endpoint {
2023 replicator@6046000 {
2024 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2025 reg = <0 0x06046000 0 0x1000>;
2027 clocks = <&aoss_qmp>;
2028 clock-names = "apb_pclk";
2032 replicator_out: endpoint {
2033 remote-endpoint = <&etr_in>;
2040 replicator_in: endpoint {
2041 remote-endpoint = <&etf_out>;
2048 compatible = "arm,coresight-tmc", "arm,primecell";
2049 reg = <0 0x06047000 0 0x1000>;
2051 clocks = <&aoss_qmp>;
2052 clock-names = "apb_pclk";
2064 #address-cells = <1>;
2071 <&merge_funnel_out>;
2078 compatible = "arm,coresight-tmc", "arm,primecell";
2079 reg = <0 0x06048000 0 0x1000>;
2081 clocks = <&aoss_qmp>;
2082 clock-names = "apb_pclk";
2096 compatible = "arm,coresight-etm4x", "arm,primecell";
2097 reg = <0 0x07040000 0 0x1000>;
2101 clocks = <&aoss_qmp>;
2102 clock-names = "apb_pclk";
2106 etm0_out: endpoint {
2115 compatible = "arm,coresight-etm4x", "arm,primecell";
2116 reg = <0 0x07140000 0 0x1000>;
2120 clocks = <&aoss_qmp>;
2121 clock-names = "apb_pclk";
2125 etm1_out: endpoint {
2134 compatible = "arm,coresight-etm4x", "arm,primecell";
2135 reg = <0 0x07240000 0 0x1000>;
2139 clocks = <&aoss_qmp>;
2140 clock-names = "apb_pclk";
2144 etm2_out: endpoint {
2153 compatible = "arm,coresight-etm4x", "arm,primecell";
2154 reg = <0 0x07340000 0 0x1000>;
2158 clocks = <&aoss_qmp>;
2159 clock-names = "apb_pclk";
2163 etm3_out: endpoint {
2172 compatible = "arm,coresight-etm4x", "arm,primecell";
2173 reg = <0 0x07440000 0 0x1000>;
2177 clocks = <&aoss_qmp>;
2178 clock-names = "apb_pclk";
2182 etm4_out: endpoint {
2191 compatible = "arm,coresight-etm4x", "arm,primecell";
2192 reg = <0 0x07540000 0 0x1000>;
2196 clocks = <&aoss_qmp>;
2197 clock-names = "apb_pclk";
2201 etm5_out: endpoint {
2210 compatible = "arm,coresight-etm4x", "arm,primecell";
2211 reg = <0 0x07640000 0 0x1000>;
2215 clocks = <&aoss_qmp>;
2216 clock-names = "apb_pclk";
2220 etm6_out: endpoint {
2229 compatible = "arm,coresight-etm4x", "arm,primecell";
2230 reg = <0 0x07740000 0 0x1000>;
2234 clocks = <&aoss_qmp>;
2235 clock-names = "apb_pclk";
2239 etm7_out: endpoint {
2247 funnel@7800000 { /* APSS Funnel */
2248 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2249 reg = <0 0x07800000 0 0x1000>;
2251 clocks = <&aoss_qmp>;
2252 clock-names = "apb_pclk";
2256 apss_funnel_out: endpoint {
2258 <&apss_merge_funnel_in>;
2264 #address-cells = <1>;
2269 apss_funnel_in0: endpoint {
2277 apss_funnel_in1: endpoint {
2285 apss_funnel_in2: endpoint {
2293 apss_funnel_in3: endpoint {
2301 apss_funnel_in4: endpoint {
2309 apss_funnel_in5: endpoint {
2317 apss_funnel_in6: endpoint {
2325 apss_funnel_in7: endpoint {
2334 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2335 reg = <0 0x07810000 0 0x1000>;
2337 clocks = <&aoss_qmp>;
2338 clock-names = "apb_pclk";
2342 apss_merge_funnel_out: endpoint {
2351 apss_merge_funnel_in: endpoint {
2359 sdhc_2: sdhci@8804000 {
2360 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
2361 reg = <0 0x08804000 0 0x1000>;
2363 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2364 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2365 interrupt-names = "hc_irq", "pwr_irq";
2367 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2368 <&gcc GCC_SDCC2_APPS_CLK>;
2369 clock-names = "iface", "core";
2370 iommus = <&apps_smmu 0xa0 0xf>;
2372 status = "disabled";
2376 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
2377 reg = <0 0x088df000 0 0x600>;
2378 #address-cells = <1>;
2380 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2381 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2382 <&gcc GCC_QSPI_CORE_CLK>;
2383 clock-names = "iface", "core";
2384 status = "disabled";
2387 usb_1_hsphy: phy@88e2000 {
2388 compatible = "qcom,sdm845-qusb2-phy";
2389 reg = <0 0x088e2000 0 0x400>;
2390 status = "disabled";
2393 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2394 <&rpmhcc RPMH_CXO_CLK>;
2395 clock-names = "cfg_ahb", "ref";
2397 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2399 nvmem-cells = <&qusb2p_hstx_trim>;
2402 usb_2_hsphy: phy@88e3000 {
2403 compatible = "qcom,sdm845-qusb2-phy";
2404 reg = <0 0x088e3000 0 0x400>;
2405 status = "disabled";
2408 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2409 <&rpmhcc RPMH_CXO_CLK>;
2410 clock-names = "cfg_ahb", "ref";
2412 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2414 nvmem-cells = <&qusb2s_hstx_trim>;
2417 usb_1_qmpphy: phy@88e9000 {
2418 compatible = "qcom,sdm845-qmp-usb3-phy";
2419 reg = <0 0x088e9000 0 0x18c>,
2420 <0 0x088e8000 0 0x10>;
2421 reg-names = "reg-base", "dp_com";
2422 status = "disabled";
2424 #address-cells = <2>;
2428 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2429 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2430 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2431 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2432 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2434 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2435 <&gcc GCC_USB3_PHY_PRIM_BCR>;
2436 reset-names = "phy", "common";
2438 usb_1_ssphy: lanes@88e9200 {
2439 reg = <0 0x088e9200 0 0x128>,
2440 <0 0x088e9400 0 0x200>,
2441 <0 0x088e9c00 0 0x218>,
2442 <0 0x088e9600 0 0x128>,
2443 <0 0x088e9800 0 0x200>,
2444 <0 0x088e9a00 0 0x100>;
2446 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2447 clock-names = "pipe0";
2448 clock-output-names = "usb3_phy_pipe_clk_src";
2452 usb_2_qmpphy: phy@88eb000 {
2453 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
2454 reg = <0 0x088eb000 0 0x18c>;
2455 status = "disabled";
2457 #address-cells = <2>;
2461 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2462 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2463 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2464 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2465 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2467 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2468 <&gcc GCC_USB3_PHY_SEC_BCR>;
2469 reset-names = "phy", "common";
2471 usb_2_ssphy: lane@88eb200 {
2472 reg = <0 0x088eb200 0 0x128>,
2473 <0 0x088eb400 0 0x1fc>,
2474 <0 0x088eb800 0 0x218>,
2475 <0 0x088eb600 0 0x70>;
2477 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2478 clock-names = "pipe0";
2479 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2483 usb_1: usb@a6f8800 {
2484 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2485 reg = <0 0x0a6f8800 0 0x400>;
2486 status = "disabled";
2487 #address-cells = <2>;
2492 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2493 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2494 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2495 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2496 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2497 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2500 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2501 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2502 assigned-clock-rates = <19200000>, <150000000>;
2504 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2505 <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2506 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
2507 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
2508 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2509 "dm_hs_phy_irq", "dp_hs_phy_irq";
2511 power-domains = <&gcc USB30_PRIM_GDSC>;
2513 resets = <&gcc GCC_USB30_PRIM_BCR>;
2515 usb_1_dwc3: dwc3@a600000 {
2516 compatible = "snps,dwc3";
2517 reg = <0 0x0a600000 0 0xcd00>;
2518 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2519 iommus = <&apps_smmu 0x740 0>;
2520 snps,dis_u2_susphy_quirk;
2521 snps,dis_enblslpm_quirk;
2522 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2523 phy-names = "usb2-phy", "usb3-phy";
2527 usb_2: usb@a8f8800 {
2528 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2529 reg = <0 0x0a8f8800 0 0x400>;
2530 status = "disabled";
2531 #address-cells = <2>;
2536 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2537 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2538 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2539 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2540 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
2541 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2544 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2545 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2546 assigned-clock-rates = <19200000>, <150000000>;
2548 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2549 <&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2550 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
2551 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
2552 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2553 "dm_hs_phy_irq", "dp_hs_phy_irq";
2555 power-domains = <&gcc USB30_SEC_GDSC>;
2557 resets = <&gcc GCC_USB30_SEC_BCR>;
2559 usb_2_dwc3: dwc3@a800000 {
2560 compatible = "snps,dwc3";
2561 reg = <0 0x0a800000 0 0xcd00>;
2562 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2563 iommus = <&apps_smmu 0x760 0>;
2564 snps,dis_u2_susphy_quirk;
2565 snps,dis_enblslpm_quirk;
2566 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2567 phy-names = "usb2-phy", "usb3-phy";
2571 video-codec@aa00000 {
2572 compatible = "qcom,sdm845-venus";
2573 reg = <0 0x0aa00000 0 0xff000>;
2574 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2575 power-domains = <&videocc VENUS_GDSC>;
2576 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2577 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2578 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2579 clock-names = "core", "iface", "bus";
2580 iommus = <&apps_smmu 0x10a0 0x8>,
2581 <&apps_smmu 0x10b0 0x0>;
2582 memory-region = <&venus_mem>;
2585 compatible = "venus-decoder";
2586 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2587 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2588 clock-names = "core", "bus";
2589 power-domains = <&videocc VCODEC0_GDSC>;
2593 compatible = "venus-encoder";
2594 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
2595 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
2596 clock-names = "core", "bus";
2597 power-domains = <&videocc VCODEC1_GDSC>;
2601 videocc: clock-controller@ab00000 {
2602 compatible = "qcom,sdm845-videocc";
2603 reg = <0 0x0ab00000 0 0x10000>;
2605 #power-domain-cells = <1>;
2609 mdss: mdss@ae00000 {
2610 compatible = "qcom,sdm845-mdss";
2611 reg = <0 0x0ae00000 0 0x1000>;
2614 power-domains = <&dispcc MDSS_GDSC>;
2616 clocks = <&gcc GCC_DISP_AHB_CLK>,
2617 <&gcc GCC_DISP_AXI_CLK>,
2618 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2619 clock-names = "iface", "bus", "core";
2621 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2622 assigned-clock-rates = <300000000>;
2624 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2625 interrupt-controller;
2626 #interrupt-cells = <1>;
2628 iommus = <&apps_smmu 0x880 0x8>,
2629 <&apps_smmu 0xc80 0x8>;
2631 status = "disabled";
2633 #address-cells = <2>;
2637 mdss_mdp: mdp@ae01000 {
2638 compatible = "qcom,sdm845-dpu";
2639 reg = <0 0x0ae01000 0 0x8f000>,
2640 <0 0x0aeb0000 0 0x2008>;
2641 reg-names = "mdp", "vbif";
2643 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2644 <&dispcc DISP_CC_MDSS_AXI_CLK>,
2645 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2646 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2647 clock-names = "iface", "bus", "core", "vsync";
2649 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2650 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2651 assigned-clock-rates = <300000000>,
2654 interrupt-parent = <&mdss>;
2655 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2657 status = "disabled";
2660 #address-cells = <1>;
2665 dpu_intf1_out: endpoint {
2666 remote-endpoint = <&dsi0_in>;
2672 dpu_intf2_out: endpoint {
2673 remote-endpoint = <&dsi1_in>;
2680 compatible = "qcom,mdss-dsi-ctrl";
2681 reg = <0 0x0ae94000 0 0x400>;
2682 reg-names = "dsi_ctrl";
2684 interrupt-parent = <&mdss>;
2685 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2687 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2688 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2689 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2690 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2691 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2692 <&dispcc DISP_CC_MDSS_AXI_CLK>;
2693 clock-names = "byte",
2703 status = "disabled";
2706 #address-cells = <1>;
2712 remote-endpoint = <&dpu_intf1_out>;
2718 dsi0_out: endpoint {
2724 dsi0_phy: dsi-phy@ae94400 {
2725 compatible = "qcom,dsi-phy-10nm";
2726 reg = <0 0x0ae94400 0 0x200>,
2727 <0 0x0ae94600 0 0x280>,
2728 <0 0x0ae94a00 0 0x1e0>;
2729 reg-names = "dsi_phy",
2736 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2737 <&rpmhcc RPMH_CXO_CLK>;
2738 clock-names = "iface", "ref";
2740 status = "disabled";
2744 compatible = "qcom,mdss-dsi-ctrl";
2745 reg = <0 0x0ae96000 0 0x400>;
2746 reg-names = "dsi_ctrl";
2748 interrupt-parent = <&mdss>;
2749 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2751 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2752 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2753 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2754 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2755 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2756 <&dispcc DISP_CC_MDSS_AXI_CLK>;
2757 clock-names = "byte",
2767 status = "disabled";
2770 #address-cells = <1>;
2776 remote-endpoint = <&dpu_intf2_out>;
2782 dsi1_out: endpoint {
2788 dsi1_phy: dsi-phy@ae96400 {
2789 compatible = "qcom,dsi-phy-10nm";
2790 reg = <0 0x0ae96400 0 0x200>,
2791 <0 0x0ae96600 0 0x280>,
2792 <0 0x0ae96a00 0 0x10e>;
2793 reg-names = "dsi_phy",
2800 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2801 <&rpmhcc RPMH_CXO_CLK>;
2802 clock-names = "iface", "ref";
2804 status = "disabled";
2809 compatible = "qcom,adreno-630.2", "qcom,adreno";
2810 #stream-id-cells = <16>;
2812 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
2813 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
2816 * Look ma, no clocks! The GPU clocks and power are
2817 * controlled entirely by the GMU
2820 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2822 iommus = <&adreno_smmu 0>;
2824 operating-points-v2 = <&gpu_opp_table>;
2828 zap_shader: zap-shader {
2829 memory-region = <&gpu_mem>;
2832 gpu_opp_table: opp-table {
2833 compatible = "operating-points-v2";
2836 opp-hz = /bits/ 64 <710000000>;
2837 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2841 opp-hz = /bits/ 64 <675000000>;
2842 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2846 opp-hz = /bits/ 64 <596000000>;
2847 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2851 opp-hz = /bits/ 64 <520000000>;
2852 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2856 opp-hz = /bits/ 64 <414000000>;
2857 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2861 opp-hz = /bits/ 64 <342000000>;
2862 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2866 opp-hz = /bits/ 64 <257000000>;
2867 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2872 adreno_smmu: iommu@5040000 {
2873 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
2874 reg = <0 0x5040000 0 0x10000>;
2876 #global-interrupts = <2>;
2877 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2878 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2879 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2880 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2881 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2882 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2883 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2884 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2885 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2886 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2887 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2888 <&gcc GCC_GPU_CFG_AHB_CLK>;
2889 clock-names = "bus", "iface";
2891 power-domains = <&gpucc GPU_CX_GDSC>;
2895 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
2897 reg = <0 0x506a000 0 0x30000>,
2898 <0 0xb280000 0 0x10000>,
2899 <0 0xb480000 0 0x10000>;
2900 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2902 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2903 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2904 interrupt-names = "hfi", "gmu";
2906 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2907 <&gpucc GPU_CC_CXO_CLK>,
2908 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2909 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2910 clock-names = "gmu", "cxo", "axi", "memnoc";
2912 power-domains = <&gpucc GPU_CX_GDSC>,
2913 <&gpucc GPU_GX_GDSC>;
2914 power-domain-names = "cx", "gx";
2916 iommus = <&adreno_smmu 5>;
2918 operating-points-v2 = <&gmu_opp_table>;
2920 gmu_opp_table: opp-table {
2921 compatible = "operating-points-v2";
2924 opp-hz = /bits/ 64 <400000000>;
2925 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2929 opp-hz = /bits/ 64 <200000000>;
2930 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2935 dispcc: clock-controller@af00000 {
2936 compatible = "qcom,sdm845-dispcc";
2937 reg = <0 0x0af00000 0 0x10000>;
2940 #power-domain-cells = <1>;
2943 pdc_intc: interrupt-controller@b220000 {
2944 compatible = "qcom,sdm845-pdc", "qcom,pdc";
2945 reg = <0 0x0b220000 0 0x30000>;
2946 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
2947 #interrupt-cells = <2>;
2948 interrupt-parent = <&intc>;
2949 interrupt-controller;
2952 pdc_reset: reset-controller@b2e0000 {
2953 compatible = "qcom,sdm845-pdc-global";
2954 reg = <0 0x0b2e0000 0 0x20000>;
2958 tsens0: thermal-sensor@c263000 {
2959 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2960 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2961 <0 0x0c222000 0 0x1ff>; /* SROT */
2962 #qcom,sensors = <13>;
2963 #thermal-sensor-cells = <1>;
2966 tsens1: thermal-sensor@c265000 {
2967 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2968 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2969 <0 0x0c223000 0 0x1ff>; /* SROT */
2970 #qcom,sensors = <8>;
2971 #thermal-sensor-cells = <1>;
2974 aoss_reset: reset-controller@c2a0000 {
2975 compatible = "qcom,sdm845-aoss-cc";
2976 reg = <0 0x0c2a0000 0 0x31000>;
2980 aoss_qmp: qmp@c300000 {
2981 compatible = "qcom,sdm845-aoss-qmp";
2982 reg = <0 0x0c300000 0 0x100000>;
2983 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
2984 mboxes = <&apss_shared 0>;
2987 #power-domain-cells = <1>;
2990 #cooling-cells = <2>;
2994 #cooling-cells = <2>;
2998 spmi_bus: spmi@c440000 {
2999 compatible = "qcom,spmi-pmic-arb";
3000 reg = <0 0x0c440000 0 0x1100>,
3001 <0 0x0c600000 0 0x2000000>,
3002 <0 0x0e600000 0 0x100000>,
3003 <0 0x0e700000 0 0xa0000>,
3004 <0 0x0c40a000 0 0x26000>;
3005 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3006 interrupt-names = "periph_irq";
3007 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3010 #address-cells = <2>;
3012 interrupt-controller;
3013 #interrupt-cells = <4>;
3017 apps_smmu: iommu@15000000 {
3018 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
3019 reg = <0 0x15000000 0 0x80000>;
3021 #global-interrupts = <1>;
3022 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3023 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3024 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3025 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3026 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3027 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3028 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3029 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3030 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3031 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3032 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3033 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3034 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3035 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3036 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3037 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3038 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3039 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3040 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3041 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3042 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3043 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3044 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3045 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3046 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3047 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3048 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3049 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3050 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3051 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3061 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3062 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3063 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3064 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3065 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3066 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3067 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3068 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3069 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3070 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3071 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3072 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3073 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3074 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3075 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3076 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3077 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3078 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3079 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3080 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3081 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3082 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3083 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3084 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3085 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3086 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
3089 lpasscc: clock-controller@17014000 {
3090 compatible = "qcom,sdm845-lpasscc";
3091 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
3092 reg-names = "cc", "qdsp6ss";
3094 status = "disabled";
3097 apss_shared: mailbox@17990000 {
3098 compatible = "qcom,sdm845-apss-shared";
3099 reg = <0 0x17990000 0 0x1000>;
3103 apps_rsc: rsc@179c0000 {
3105 compatible = "qcom,rpmh-rsc";
3106 reg = <0 0x179c0000 0 0x10000>,
3107 <0 0x179d0000 0 0x10000>,
3108 <0 0x179e0000 0 0x10000>;
3109 reg-names = "drv-0", "drv-1", "drv-2";
3110 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3111 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3112 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3113 qcom,tcs-offset = <0xd00>;
3115 qcom,tcs-config = <ACTIVE_TCS 2>,
3120 rpmhcc: clock-controller {
3121 compatible = "qcom,sdm845-rpmh-clk";
3124 clocks = <&xo_board>;
3127 rpmhpd: power-controller {
3128 compatible = "qcom,sdm845-rpmhpd";
3129 #power-domain-cells = <1>;
3130 operating-points-v2 = <&rpmhpd_opp_table>;
3132 rpmhpd_opp_table: opp-table {
3133 compatible = "operating-points-v2";
3135 rpmhpd_opp_ret: opp1 {
3136 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3139 rpmhpd_opp_min_svs: opp2 {
3140 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3143 rpmhpd_opp_low_svs: opp3 {
3144 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3147 rpmhpd_opp_svs: opp4 {
3148 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3151 rpmhpd_opp_svs_l1: opp5 {
3152 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3155 rpmhpd_opp_nom: opp6 {
3156 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3159 rpmhpd_opp_nom_l1: opp7 {
3160 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3163 rpmhpd_opp_nom_l2: opp8 {
3164 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3167 rpmhpd_opp_turbo: opp9 {
3168 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3171 rpmhpd_opp_turbo_l1: opp10 {
3172 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3177 rsc_hlos: interconnect {
3178 compatible = "qcom,sdm845-rsc-hlos";
3179 #interconnect-cells = <1>;
3183 intc: interrupt-controller@17a00000 {
3184 compatible = "arm,gic-v3";
3185 #address-cells = <2>;
3188 #interrupt-cells = <3>;
3189 interrupt-controller;
3190 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3191 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3192 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3195 compatible = "arm,gic-v3-its";
3198 reg = <0 0x17a40000 0 0x20000>;
3199 status = "disabled";
3204 #address-cells = <2>;
3207 compatible = "arm,armv7-timer-mem";
3208 reg = <0 0x17c90000 0 0x1000>;
3212 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
3213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3214 reg = <0 0x17ca0000 0 0x1000>,
3215 <0 0x17cb0000 0 0x1000>;
3220 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
3221 reg = <0 0x17cc0000 0 0x1000>;
3222 status = "disabled";
3227 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228 reg = <0 0x17cd0000 0 0x1000>;
3229 status = "disabled";
3234 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3235 reg = <0 0x17ce0000 0 0x1000>;
3236 status = "disabled";
3241 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3242 reg = <0 0x17cf0000 0 0x1000>;
3243 status = "disabled";
3248 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3249 reg = <0 0x17d00000 0 0x1000>;
3250 status = "disabled";
3255 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3256 reg = <0 0x17d10000 0 0x1000>;
3257 status = "disabled";
3261 cpufreq_hw: cpufreq@17d43000 {
3262 compatible = "qcom,cpufreq-hw";
3263 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
3264 reg-names = "freq-domain0", "freq-domain1";
3266 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3267 clock-names = "xo", "alternate";
3269 #freq-domain-cells = <1>;
3272 wifi: wifi@18800000 {
3273 compatible = "qcom,wcn3990-wifi";
3274 status = "disabled";
3275 reg = <0 0x18800000 0 0x800000>;
3276 reg-names = "membase";
3277 memory-region = <&wlan_msa_mem>;
3278 clock-names = "cxo_ref_clk_pin";
3279 clocks = <&rpmhcc RPMH_RF_CLK2>;
3281 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3282 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3283 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3284 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3285 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3286 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3287 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3288 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3289 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3290 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3291 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3292 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3293 iommus = <&apps_smmu 0x0040 0x1>;
3299 polling-delay-passive = <250>;
3300 polling-delay = <1000>;
3302 thermal-sensors = <&tsens0 1>;
3305 cpu0_alert0: trip-point0 {
3306 temperature = <90000>;
3307 hysteresis = <2000>;
3311 cpu0_alert1: trip-point1 {
3312 temperature = <95000>;
3313 hysteresis = <2000>;
3317 cpu0_crit: cpu_crit {
3318 temperature = <110000>;
3319 hysteresis = <1000>;
3326 trip = <&cpu0_alert0>;
3327 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3328 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3329 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3330 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3333 trip = <&cpu0_alert1>;
3334 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3335 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3336 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3337 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3343 polling-delay-passive = <250>;
3344 polling-delay = <1000>;
3346 thermal-sensors = <&tsens0 2>;
3349 cpu1_alert0: trip-point0 {
3350 temperature = <90000>;
3351 hysteresis = <2000>;
3355 cpu1_alert1: trip-point1 {
3356 temperature = <95000>;
3357 hysteresis = <2000>;
3361 cpu1_crit: cpu_crit {
3362 temperature = <110000>;
3363 hysteresis = <1000>;
3370 trip = <&cpu1_alert0>;
3371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3377 trip = <&cpu1_alert1>;
3378 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3379 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3380 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3381 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3387 polling-delay-passive = <250>;
3388 polling-delay = <1000>;
3390 thermal-sensors = <&tsens0 3>;
3393 cpu2_alert0: trip-point0 {
3394 temperature = <90000>;
3395 hysteresis = <2000>;
3399 cpu2_alert1: trip-point1 {
3400 temperature = <95000>;
3401 hysteresis = <2000>;
3405 cpu2_crit: cpu_crit {
3406 temperature = <110000>;
3407 hysteresis = <1000>;
3414 trip = <&cpu2_alert0>;
3415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3421 trip = <&cpu2_alert1>;
3422 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3423 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3424 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3425 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3431 polling-delay-passive = <250>;
3432 polling-delay = <1000>;
3434 thermal-sensors = <&tsens0 4>;
3437 cpu3_alert0: trip-point0 {
3438 temperature = <90000>;
3439 hysteresis = <2000>;
3443 cpu3_alert1: trip-point1 {
3444 temperature = <95000>;
3445 hysteresis = <2000>;
3449 cpu3_crit: cpu_crit {
3450 temperature = <110000>;
3451 hysteresis = <1000>;
3458 trip = <&cpu3_alert0>;
3459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3465 trip = <&cpu3_alert1>;
3466 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3467 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3468 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3469 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3475 polling-delay-passive = <250>;
3476 polling-delay = <1000>;
3478 thermal-sensors = <&tsens0 7>;
3481 cpu4_alert0: trip-point0 {
3482 temperature = <90000>;
3483 hysteresis = <2000>;
3487 cpu4_alert1: trip-point1 {
3488 temperature = <95000>;
3489 hysteresis = <2000>;
3493 cpu4_crit: cpu_crit {
3494 temperature = <110000>;
3495 hysteresis = <1000>;
3502 trip = <&cpu4_alert0>;
3503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3509 trip = <&cpu4_alert1>;
3510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3519 polling-delay-passive = <250>;
3520 polling-delay = <1000>;
3522 thermal-sensors = <&tsens0 8>;
3525 cpu5_alert0: trip-point0 {
3526 temperature = <90000>;
3527 hysteresis = <2000>;
3531 cpu5_alert1: trip-point1 {
3532 temperature = <95000>;
3533 hysteresis = <2000>;
3537 cpu5_crit: cpu_crit {
3538 temperature = <110000>;
3539 hysteresis = <1000>;
3546 trip = <&cpu5_alert0>;
3547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3553 trip = <&cpu5_alert1>;
3554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3563 polling-delay-passive = <250>;
3564 polling-delay = <1000>;
3566 thermal-sensors = <&tsens0 9>;
3569 cpu6_alert0: trip-point0 {
3570 temperature = <90000>;
3571 hysteresis = <2000>;
3575 cpu6_alert1: trip-point1 {
3576 temperature = <95000>;
3577 hysteresis = <2000>;
3581 cpu6_crit: cpu_crit {
3582 temperature = <110000>;
3583 hysteresis = <1000>;
3590 trip = <&cpu6_alert0>;
3591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3597 trip = <&cpu6_alert1>;
3598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3607 polling-delay-passive = <250>;
3608 polling-delay = <1000>;
3610 thermal-sensors = <&tsens0 10>;
3613 cpu7_alert0: trip-point0 {
3614 temperature = <90000>;
3615 hysteresis = <2000>;
3619 cpu7_alert1: trip-point1 {
3620 temperature = <95000>;
3621 hysteresis = <2000>;
3625 cpu7_crit: cpu_crit {
3626 temperature = <110000>;
3627 hysteresis = <1000>;
3634 trip = <&cpu7_alert0>;
3635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3641 trip = <&cpu7_alert1>;
3642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3651 polling-delay-passive = <250>;
3652 polling-delay = <1000>;
3654 thermal-sensors = <&tsens0 0>;
3657 aoss0_alert0: trip-point0 {
3658 temperature = <90000>;
3659 hysteresis = <2000>;
3666 polling-delay-passive = <250>;
3667 polling-delay = <1000>;
3669 thermal-sensors = <&tsens0 5>;
3672 cluster0_alert0: trip-point0 {
3673 temperature = <90000>;
3674 hysteresis = <2000>;
3677 cluster0_crit: cluster0_crit {
3678 temperature = <110000>;
3679 hysteresis = <2000>;
3686 polling-delay-passive = <250>;
3687 polling-delay = <1000>;
3689 thermal-sensors = <&tsens0 6>;
3692 cluster1_alert0: trip-point0 {
3693 temperature = <90000>;
3694 hysteresis = <2000>;
3697 cluster1_crit: cluster1_crit {
3698 temperature = <110000>;
3699 hysteresis = <2000>;
3706 polling-delay-passive = <250>;
3707 polling-delay = <1000>;
3709 thermal-sensors = <&tsens0 11>;
3712 gpu1_alert0: trip-point0 {
3713 temperature = <90000>;
3714 hysteresis = <2000>;
3720 gpu-thermal-bottom {
3721 polling-delay-passive = <250>;
3722 polling-delay = <1000>;
3724 thermal-sensors = <&tsens0 12>;
3727 gpu2_alert0: trip-point0 {
3728 temperature = <90000>;
3729 hysteresis = <2000>;
3736 polling-delay-passive = <250>;
3737 polling-delay = <1000>;
3739 thermal-sensors = <&tsens1 0>;
3742 aoss1_alert0: trip-point0 {
3743 temperature = <90000>;
3744 hysteresis = <2000>;
3751 polling-delay-passive = <250>;
3752 polling-delay = <1000>;
3754 thermal-sensors = <&tsens1 1>;
3757 q6_modem_alert0: trip-point0 {
3758 temperature = <90000>;
3759 hysteresis = <2000>;
3766 polling-delay-passive = <250>;
3767 polling-delay = <1000>;
3769 thermal-sensors = <&tsens1 2>;
3772 mem_alert0: trip-point0 {
3773 temperature = <90000>;
3774 hysteresis = <2000>;
3781 polling-delay-passive = <250>;
3782 polling-delay = <1000>;
3784 thermal-sensors = <&tsens1 3>;
3787 wlan_alert0: trip-point0 {
3788 temperature = <90000>;
3789 hysteresis = <2000>;
3796 polling-delay-passive = <250>;
3797 polling-delay = <1000>;
3799 thermal-sensors = <&tsens1 4>;
3802 q6_hvx_alert0: trip-point0 {
3803 temperature = <90000>;
3804 hysteresis = <2000>;
3811 polling-delay-passive = <250>;
3812 polling-delay = <1000>;
3814 thermal-sensors = <&tsens1 5>;
3817 camera_alert0: trip-point0 {
3818 temperature = <90000>;
3819 hysteresis = <2000>;
3826 polling-delay-passive = <250>;
3827 polling-delay = <1000>;
3829 thermal-sensors = <&tsens1 6>;
3832 video_alert0: trip-point0 {
3833 temperature = <90000>;
3834 hysteresis = <2000>;
3841 polling-delay-passive = <250>;
3842 polling-delay = <1000>;
3844 thermal-sensors = <&tsens1 7>;
3847 modem_alert0: trip-point0 {
3848 temperature = <90000>;
3849 hysteresis = <2000>;