arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  14 #include <dt-bindings/interconnect/qcom,sdm845.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  17 #include <dt-bindings/power/qcom-rpmpd.h>
  18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  21 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         aliases {
  31                 i2c0 = &i2c0;
  32                 i2c1 = &i2c1;
  33                 i2c2 = &i2c2;
  34                 i2c3 = &i2c3;
  35                 i2c4 = &i2c4;
  36                 i2c5 = &i2c5;
  37                 i2c6 = &i2c6;
  38                 i2c7 = &i2c7;
  39                 i2c8 = &i2c8;
  40                 i2c9 = &i2c9;
  41                 i2c10 = &i2c10;
  42                 i2c11 = &i2c11;
  43                 i2c12 = &i2c12;
  44                 i2c13 = &i2c13;
  45                 i2c14 = &i2c14;
  46                 i2c15 = &i2c15;
  47                 spi0 = &spi0;
  48                 spi1 = &spi1;
  49                 spi2 = &spi2;
  50                 spi3 = &spi3;
  51                 spi4 = &spi4;
  52                 spi5 = &spi5;
  53                 spi6 = &spi6;
  54                 spi7 = &spi7;
  55                 spi8 = &spi8;
  56                 spi9 = &spi9;
  57                 spi10 = &spi10;
  58                 spi11 = &spi11;
  59                 spi12 = &spi12;
  60                 spi13 = &spi13;
  61                 spi14 = &spi14;
  62                 spi15 = &spi15;
  63         };
  64
  65         chosen { };
  66
  67         memory@80000000 {
  68                 device_type = "memory";
  69                 /* We expect the bootloader to fill in the size */
  70                 reg = <0 0x80000000 0 0>;
  71         };
  72
  73         reserved-memory {
  74                 #address-cells = <2>;
  75                 #size-cells = <2>;
  76                 ranges;
  77
  78                 hyp_mem: memory@85700000 {
  79                         reg = <0 0x85700000 0 0x600000>;
  80                         no-map;
  81                 };
  82
  83                 xbl_mem: memory@85e00000 {
  84                         reg = <0 0x85e00000 0 0x100000>;
  85                         no-map;
  86                 };
  87
  88                 aop_mem: memory@85fc0000 {
  89                         reg = <0 0x85fc0000 0 0x20000>;
  90                         no-map;
  91                 };
  92
  93                 aop_cmd_db_mem: memory@85fe0000 {
  94                         compatible = "qcom,cmd-db";
  95                         reg = <0x0 0x85fe0000 0 0x20000>;
  96                         no-map;
  97                 };
  98
  99                 smem_mem: memory@86000000 {
 100                         reg = <0x0 0x86000000 0 0x200000>;
 101                         no-map;
 102                 };
 103
 104                 tz_mem: memory@86200000 {
 105                         reg = <0 0x86200000 0 0x2d00000>;
 106                         no-map;
 107                 };
 108
 109                 rmtfs_mem: memory@88f00000 {
 110                         compatible = "qcom,rmtfs-mem";
 111                         reg = <0 0x88f00000 0 0x200000>;
 112                         no-map;
 113
 114                         qcom,client-id = <1>;
 115                         qcom,vmid = <15>;
 116                 };
 117
 118                 qseecom_mem: memory@8ab00000 {
 119                         reg = <0 0x8ab00000 0 0x1400000>;
 120                         no-map;
 121                 };
 122
 123                 camera_mem: memory@8bf00000 {
 124                         reg = <0 0x8bf00000 0 0x500000>;
 125                         no-map;
 126                 };
 127
 128                 ipa_fw_mem: memory@8c400000 {
 129                         reg = <0 0x8c400000 0 0x10000>;
 130                         no-map;
 131                 };
 132
 133                 ipa_gsi_mem: memory@8c410000 {
 134                         reg = <0 0x8c410000 0 0x5000>;
 135                         no-map;
 136                 };
 137
 138                 gpu_mem: memory@8c415000 {
 139                         reg = <0 0x8c415000 0 0x2000>;
 140                         no-map;
 141                 };
 142
 143                 adsp_mem: memory@8c500000 {
 144                         reg = <0 0x8c500000 0 0x1a00000>;
 145                         no-map;
 146                 };
 147
 148                 wlan_msa_mem: memory@8df00000 {
 149                         reg = <0 0x8df00000 0 0x100000>;
 150                         no-map;
 151                 };
 152
 153                 mpss_region: memory@8e000000 {
 154                         reg = <0 0x8e000000 0 0x7800000>;
 155                         no-map;
 156                 };
 157
 158                 venus_mem: memory@95800000 {
 159                         reg = <0 0x95800000 0 0x500000>;
 160                         no-map;
 161                 };
 162
 163                 cdsp_mem: memory@95d00000 {
 164                         reg = <0 0x95d00000 0 0x800000>;
 165                         no-map;
 166                 };
 167
 168                 mba_region: memory@96500000 {
 169                         reg = <0 0x96500000 0 0x200000>;
 170                         no-map;
 171                 };
 172
 173                 slpi_mem: memory@96700000 {
 174                         reg = <0 0x96700000 0 0x1400000>;
 175                         no-map;
 176                 };
 177
 178                 spss_mem: memory@97b00000 {
 179                         reg = <0 0x97b00000 0 0x100000>;
 180                         no-map;
 181                 };
 182         };
 183
 184         cpus {
 185                 #address-cells = <2>;
 186                 #size-cells = <0>;
 187
 188                 CPU0: cpu@0 {
 189                         device_type = "cpu";
 190                         compatible = "qcom,kryo385";
 191                         reg = <0x0 0x0>;
 192                         enable-method = "psci";
 193                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 194                                            &LITTLE_CPU_SLEEP_1
 195                                            &CLUSTER_SLEEP_0>;
 196                         capacity-dmips-mhz = <607>;
 197                         dynamic-power-coefficient = <100>;
 198                         qcom,freq-domain = <&cpufreq_hw 0>;
 199                         #cooling-cells = <2>;
 200                         next-level-cache = <&L2_0>;
 201                         L2_0: l2-cache {
 202                                 compatible = "cache";
 203                                 next-level-cache = <&L3_0>;
 204                                 L3_0: l3-cache {
 205                                       compatible = "cache";
 206                                 };
 207                         };
 208                 };
 209
 210                 CPU1: cpu@100 {
 211                         device_type = "cpu";
 212                         compatible = "qcom,kryo385";
 213                         reg = <0x0 0x100>;
 214                         enable-method = "psci";
 215                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 216                                            &LITTLE_CPU_SLEEP_1
 217                                            &CLUSTER_SLEEP_0>;
 218                         capacity-dmips-mhz = <607>;
 219                         dynamic-power-coefficient = <100>;
 220                         qcom,freq-domain = <&cpufreq_hw 0>;
 221                         #cooling-cells = <2>;
 222                         next-level-cache = <&L2_100>;
 223                         L2_100: l2-cache {
 224                                 compatible = "cache";
 225                                 next-level-cache = <&L3_0>;
 226                         };
 227                 };
 228
 229                 CPU2: cpu@200 {
 230                         device_type = "cpu";
 231                         compatible = "qcom,kryo385";
 232                         reg = <0x0 0x200>;
 233                         enable-method = "psci";
 234                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 235                                            &LITTLE_CPU_SLEEP_1
 236                                            &CLUSTER_SLEEP_0>;
 237                         capacity-dmips-mhz = <607>;
 238                         dynamic-power-coefficient = <100>;
 239                         qcom,freq-domain = <&cpufreq_hw 0>;
 240                         #cooling-cells = <2>;
 241                         next-level-cache = <&L2_200>;
 242                         L2_200: l2-cache {
 243                                 compatible = "cache";
 244                                 next-level-cache = <&L3_0>;
 245                         };
 246                 };
 247
 248                 CPU3: cpu@300 {
 249                         device_type = "cpu";
 250                         compatible = "qcom,kryo385";
 251                         reg = <0x0 0x300>;
 252                         enable-method = "psci";
 253                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 254                                            &LITTLE_CPU_SLEEP_1
 255                                            &CLUSTER_SLEEP_0>;
 256                         capacity-dmips-mhz = <607>;
 257                         dynamic-power-coefficient = <100>;
 258                         qcom,freq-domain = <&cpufreq_hw 0>;
 259                         #cooling-cells = <2>;
 260                         next-level-cache = <&L2_300>;
 261                         L2_300: l2-cache {
 262                                 compatible = "cache";
 263                                 next-level-cache = <&L3_0>;
 264                         };
 265                 };
 266
 267                 CPU4: cpu@400 {
 268                         device_type = "cpu";
 269                         compatible = "qcom,kryo385";
 270                         reg = <0x0 0x400>;
 271                         enable-method = "psci";
 272                         capacity-dmips-mhz = <1024>;
 273                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 274                                            &BIG_CPU_SLEEP_1
 275                                            &CLUSTER_SLEEP_0>;
 276                         dynamic-power-coefficient = <396>;
 277                         qcom,freq-domain = <&cpufreq_hw 1>;
 278                         #cooling-cells = <2>;
 279                         next-level-cache = <&L2_400>;
 280                         L2_400: l2-cache {
 281                                 compatible = "cache";
 282                                 next-level-cache = <&L3_0>;
 283                         };
 284                 };
 285
 286                 CPU5: cpu@500 {
 287                         device_type = "cpu";
 288                         compatible = "qcom,kryo385";
 289                         reg = <0x0 0x500>;
 290                         enable-method = "psci";
 291                         capacity-dmips-mhz = <1024>;
 292                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 293                                            &BIG_CPU_SLEEP_1
 294                                            &CLUSTER_SLEEP_0>;
 295                         dynamic-power-coefficient = <396>;
 296                         qcom,freq-domain = <&cpufreq_hw 1>;
 297                         #cooling-cells = <2>;
 298                         next-level-cache = <&L2_500>;
 299                         L2_500: l2-cache {
 300                                 compatible = "cache";
 301                                 next-level-cache = <&L3_0>;
 302                         };
 303                 };
 304
 305                 CPU6: cpu@600 {
 306                         device_type = "cpu";
 307                         compatible = "qcom,kryo385";
 308                         reg = <0x0 0x600>;
 309                         enable-method = "psci";
 310                         capacity-dmips-mhz = <1024>;
 311                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 312                                            &BIG_CPU_SLEEP_1
 313                                            &CLUSTER_SLEEP_0>;
 314                         dynamic-power-coefficient = <396>;
 315                         qcom,freq-domain = <&cpufreq_hw 1>;
 316                         #cooling-cells = <2>;
 317                         next-level-cache = <&L2_600>;
 318                         L2_600: l2-cache {
 319                                 compatible = "cache";
 320                                 next-level-cache = <&L3_0>;
 321                         };
 322                 };
 323
 324                 CPU7: cpu@700 {
 325                         device_type = "cpu";
 326                         compatible = "qcom,kryo385";
 327                         reg = <0x0 0x700>;
 328                         enable-method = "psci";
 329                         capacity-dmips-mhz = <1024>;
 330                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 331                                            &BIG_CPU_SLEEP_1
 332                                            &CLUSTER_SLEEP_0>;
 333                         dynamic-power-coefficient = <396>;
 334                         qcom,freq-domain = <&cpufreq_hw 1>;
 335                         #cooling-cells = <2>;
 336                         next-level-cache = <&L2_700>;
 337                         L2_700: l2-cache {
 338                                 compatible = "cache";
 339                                 next-level-cache = <&L3_0>;
 340                         };
 341                 };
 342
 343                 cpu-map {
 344                         cluster0 {
 345                                 core0 {
 346                                         cpu = <&CPU0>;
 347                                 };
 348
 349                                 core1 {
 350                                         cpu = <&CPU1>;
 351                                 };
 352
 353                                 core2 {
 354                                         cpu = <&CPU2>;
 355                                 };
 356
 357                                 core3 {
 358                                         cpu = <&CPU3>;
 359                                 };
 360
 361                                 core4 {
 362                                         cpu = <&CPU4>;
 363                                 };
 364
 365                                 core5 {
 366                                         cpu = <&CPU5>;
 367                                 };
 368
 369                                 core6 {
 370                                         cpu = <&CPU6>;
 371                                 };
 372
 373                                 core7 {
 374                                         cpu = <&CPU7>;
 375                                 };
 376                         };
 377                 };
 378
 379                 idle-states {
 380                         entry-method = "psci";
 381
 382                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 383                                 compatible = "arm,idle-state";
 384                                 idle-state-name = "little-power-down";
 385                                 arm,psci-suspend-param = <0x40000003>;
 386                                 entry-latency-us = <350>;
 387                                 exit-latency-us = <461>;
 388                                 min-residency-us = <1890>;
 389                                 local-timer-stop;
 390                         };
 391
 392                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 393                                 compatible = "arm,idle-state";
 394                                 idle-state-name = "little-rail-power-down";
 395                                 arm,psci-suspend-param = <0x40000004>;
 396                                 entry-latency-us = <360>;
 397                                 exit-latency-us = <531>;
 398                                 min-residency-us = <3934>;
 399                                 local-timer-stop;
 400                         };
 401
 402                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 403                                 compatible = "arm,idle-state";
 404                                 idle-state-name = "big-power-down";
 405                                 arm,psci-suspend-param = <0x40000003>;
 406                                 entry-latency-us = <264>;
 407                                 exit-latency-us = <621>;
 408                                 min-residency-us = <952>;
 409                                 local-timer-stop;
 410                         };
 411
 412                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 413                                 compatible = "arm,idle-state";
 414                                 idle-state-name = "big-rail-power-down";
 415                                 arm,psci-suspend-param = <0x40000004>;
 416                                 entry-latency-us = <702>;
 417                                 exit-latency-us = <1061>;
 418                                 min-residency-us = <4488>;
 419                                 local-timer-stop;
 420                         };
 421
 422                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 423                                 compatible = "arm,idle-state";
 424                                 idle-state-name = "cluster-power-down";
 425                                 arm,psci-suspend-param = <0x400000F4>;
 426                                 entry-latency-us = <3263>;
 427                                 exit-latency-us = <6562>;
 428                                 min-residency-us = <9987>;
 429                                 local-timer-stop;
 430                         };
 431                 };
 432         };
 433
 434         pmu {
 435                 compatible = "arm,armv8-pmuv3";
 436                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 437         };
 438
 439         timer {
 440                 compatible = "arm,armv8-timer";
 441                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 442                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 443                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 444                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 445         };
 446
 447         clocks {
 448                 xo_board: xo-board {
 449                         compatible = "fixed-clock";
 450                         #clock-cells = <0>;
 451                         clock-frequency = <38400000>;
 452                         clock-output-names = "xo_board";
 453                 };
 454
 455                 sleep_clk: sleep-clk {
 456                         compatible = "fixed-clock";
 457                         #clock-cells = <0>;
 458                         clock-frequency = <32764>;
 459                 };
 460         };
 461
 462         firmware {
 463                 scm {
 464                         compatible = "qcom,scm-sdm845", "qcom,scm";
 465                 };
 466         };
 467
 468         adsp_pas: remoteproc-adsp {
 469                 compatible = "qcom,sdm845-adsp-pas";
 470
 471                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 472                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 473                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 474                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 475                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 476                 interrupt-names = "wdog", "fatal", "ready",
 477                                   "handover", "stop-ack";
 478
 479                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 480                 clock-names = "xo";
 481
 482                 memory-region = <&adsp_mem>;
 483
 484                 qcom,smem-states = <&adsp_smp2p_out 0>;
 485                 qcom,smem-state-names = "stop";
 486
 487                 status = "disabled";
 488
 489                 glink-edge {
 490                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 491                         label = "lpass";
 492                         qcom,remote-pid = <2>;
 493                         mboxes = <&apss_shared 8>;
 494                         fastrpc {
 495                                 compatible = "qcom,fastrpc";
 496                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 497                                 label = "adsp";
 498                                 #address-cells = <1>;
 499                                 #size-cells = <0>;
 500
 501                                 compute-cb@3 {
 502                                         compatible = "qcom,fastrpc-compute-cb";
 503                                         reg = <3>;
 504                                         iommus = <&apps_smmu 0x1823 0x0>;
 505                                 };
 506
 507                                 compute-cb@4 {
 508                                         compatible = "qcom,fastrpc-compute-cb";
 509                                         reg = <4>;
 510                                         iommus = <&apps_smmu 0x1824 0x0>;
 511                                 };
 512                         };
 513                 };
 514         };
 515
 516         cdsp_pas: remoteproc-cdsp {
 517                 compatible = "qcom,sdm845-cdsp-pas";
 518
 519                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 520                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 521                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 522                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 523                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 524                 interrupt-names = "wdog", "fatal", "ready",
 525                                   "handover", "stop-ack";
 526
 527                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 528                 clock-names = "xo";
 529
 530                 memory-region = <&cdsp_mem>;
 531
 532                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 533                 qcom,smem-state-names = "stop";
 534
 535                 status = "disabled";
 536
 537                 glink-edge {
 538                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 539                         label = "turing";
 540                         qcom,remote-pid = <5>;
 541                         mboxes = <&apss_shared 4>;
 542                         fastrpc {
 543                                 compatible = "qcom,fastrpc";
 544                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 545                                 label = "cdsp";
 546                                 #address-cells = <1>;
 547                                 #size-cells = <0>;
 548
 549                                 compute-cb@1 {
 550                                         compatible = "qcom,fastrpc-compute-cb";
 551                                         reg = <1>;
 552                                         iommus = <&apps_smmu 0x1401 0x30>;
 553                                 };
 554
 555                                 compute-cb@2 {
 556                                         compatible = "qcom,fastrpc-compute-cb";
 557                                         reg = <2>;
 558                                         iommus = <&apps_smmu 0x1402 0x30>;
 559                                 };
 560
 561                                 compute-cb@3 {
 562                                         compatible = "qcom,fastrpc-compute-cb";
 563                                         reg = <3>;
 564                                         iommus = <&apps_smmu 0x1403 0x30>;
 565                                 };
 566
 567                                 compute-cb@4 {
 568                                         compatible = "qcom,fastrpc-compute-cb";
 569                                         reg = <4>;
 570                                         iommus = <&apps_smmu 0x1404 0x30>;
 571                                 };
 572
 573                                 compute-cb@5 {
 574                                         compatible = "qcom,fastrpc-compute-cb";
 575                                         reg = <5>;
 576                                         iommus = <&apps_smmu 0x1405 0x30>;
 577                                 };
 578
 579                                 compute-cb@6 {
 580                                         compatible = "qcom,fastrpc-compute-cb";
 581                                         reg = <6>;
 582                                         iommus = <&apps_smmu 0x1406 0x30>;
 583                                 };
 584
 585                                 compute-cb@7 {
 586                                         compatible = "qcom,fastrpc-compute-cb";
 587                                         reg = <7>;
 588                                         iommus = <&apps_smmu 0x1407 0x30>;
 589                                 };
 590
 591                                 compute-cb@8 {
 592                                         compatible = "qcom,fastrpc-compute-cb";
 593                                         reg = <8>;
 594                                         iommus = <&apps_smmu 0x1408 0x30>;
 595                                 };
 596                         };
 597                 };
 598         };
 599
 600         tcsr_mutex: hwlock {
 601                 compatible = "qcom,tcsr-mutex";
 602                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 603                 #hwlock-cells = <1>;
 604         };
 605
 606         smem {
 607                 compatible = "qcom,smem";
 608                 memory-region = <&smem_mem>;
 609                 hwlocks = <&tcsr_mutex 3>;
 610         };
 611
 612         smp2p-cdsp {
 613                 compatible = "qcom,smp2p";
 614                 qcom,smem = <94>, <432>;
 615
 616                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 617
 618                 mboxes = <&apss_shared 6>;
 619
 620                 qcom,local-pid = <0>;
 621                 qcom,remote-pid = <5>;
 622
 623                 cdsp_smp2p_out: master-kernel {
 624                         qcom,entry-name = "master-kernel";
 625                         #qcom,smem-state-cells = <1>;
 626                 };
 627
 628                 cdsp_smp2p_in: slave-kernel {
 629                         qcom,entry-name = "slave-kernel";
 630
 631                         interrupt-controller;
 632                         #interrupt-cells = <2>;
 633                 };
 634         };
 635
 636         smp2p-lpass {
 637                 compatible = "qcom,smp2p";
 638                 qcom,smem = <443>, <429>;
 639
 640                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 641
 642                 mboxes = <&apss_shared 10>;
 643
 644                 qcom,local-pid = <0>;
 645                 qcom,remote-pid = <2>;
 646
 647                 adsp_smp2p_out: master-kernel {
 648                         qcom,entry-name = "master-kernel";
 649                         #qcom,smem-state-cells = <1>;
 650                 };
 651
 652                 adsp_smp2p_in: slave-kernel {
 653                         qcom,entry-name = "slave-kernel";
 654
 655                         interrupt-controller;
 656                         #interrupt-cells = <2>;
 657                 };
 658         };
 659
 660         smp2p-mpss {
 661                 compatible = "qcom,smp2p";
 662                 qcom,smem = <435>, <428>;
 663                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 664                 mboxes = <&apss_shared 14>;
 665                 qcom,local-pid = <0>;
 666                 qcom,remote-pid = <1>;
 667
 668                 modem_smp2p_out: master-kernel {
 669                         qcom,entry-name = "master-kernel";
 670                         #qcom,smem-state-cells = <1>;
 671                 };
 672
 673                 modem_smp2p_in: slave-kernel {
 674                         qcom,entry-name = "slave-kernel";
 675                         interrupt-controller;
 676                         #interrupt-cells = <2>;
 677                 };
 678         };
 679
 680         smp2p-slpi {
 681                 compatible = "qcom,smp2p";
 682                 qcom,smem = <481>, <430>;
 683                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 684                 mboxes = <&apss_shared 26>;
 685                 qcom,local-pid = <0>;
 686                 qcom,remote-pid = <3>;
 687
 688                 slpi_smp2p_out: master-kernel {
 689                         qcom,entry-name = "master-kernel";
 690                         #qcom,smem-state-cells = <1>;
 691                 };
 692
 693                 slpi_smp2p_in: slave-kernel {
 694                         qcom,entry-name = "slave-kernel";
 695                         interrupt-controller;
 696                         #interrupt-cells = <2>;
 697                 };
 698         };
 699
 700         psci {
 701                 compatible = "arm,psci-1.0";
 702                 method = "smc";
 703         };
 704
 705         soc: soc@0 {
 706                 #address-cells = <2>;
 707                 #size-cells = <2>;
 708                 ranges = <0 0 0 0 0x10 0>;
 709                 dma-ranges = <0 0 0 0 0x10 0>;
 710                 compatible = "simple-bus";
 711
 712                 gcc: clock-controller@100000 {
 713                         compatible = "qcom,gcc-sdm845";
 714                         reg = <0 0x00100000 0 0x1f0000>;
 715                         #clock-cells = <1>;
 716                         #reset-cells = <1>;
 717                         #power-domain-cells = <1>;
 718                         power-domains = <&rpmhpd SDM845_CX>;
 719                 };
 720
 721                 qfprom@784000 {
 722                         compatible = "qcom,qfprom";
 723                         reg = <0 0x00784000 0 0x8ff>;
 724                         #address-cells = <1>;
 725                         #size-cells = <1>;
 726
 727                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
 728                                 reg = <0x1eb 0x1>;
 729                                 bits = <1 4>;
 730                         };
 731
 732                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
 733                                 reg = <0x1eb 0x2>;
 734                                 bits = <6 4>;
 735                         };
 736                 };
 737
 738                 rng: rng@793000 {
 739                         compatible = "qcom,prng-ee";
 740                         reg = <0 0x00793000 0 0x1000>;
 741                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 742                         clock-names = "core";
 743                 };
 744
 745                 qupv3_id_0: geniqup@8c0000 {
 746                         compatible = "qcom,geni-se-qup";
 747                         reg = <0 0x008c0000 0 0x6000>;
 748                         clock-names = "m-ahb", "s-ahb";
 749                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 750                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 751                         #address-cells = <2>;
 752                         #size-cells = <2>;
 753                         ranges;
 754                         status = "disabled";
 755
 756                         i2c0: i2c@880000 {
 757                                 compatible = "qcom,geni-i2c";
 758                                 reg = <0 0x00880000 0 0x4000>;
 759                                 clock-names = "se";
 760                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 761                                 pinctrl-names = "default";
 762                                 pinctrl-0 = <&qup_i2c0_default>;
 763                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 status = "disabled";
 767                         };
 768
 769                         spi0: spi@880000 {
 770                                 compatible = "qcom,geni-spi";
 771                                 reg = <0 0x00880000 0 0x4000>;
 772                                 clock-names = "se";
 773                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 774                                 pinctrl-names = "default";
 775                                 pinctrl-0 = <&qup_spi0_default>;
 776                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 777                                 #address-cells = <1>;
 778                                 #size-cells = <0>;
 779                                 status = "disabled";
 780                         };
 781
 782                         uart0: serial@880000 {
 783                                 compatible = "qcom,geni-uart";
 784                                 reg = <0 0x00880000 0 0x4000>;
 785                                 clock-names = "se";
 786                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 787                                 pinctrl-names = "default";
 788                                 pinctrl-0 = <&qup_uart0_default>;
 789                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 790                                 status = "disabled";
 791                         };
 792
 793                         i2c1: i2c@884000 {
 794                                 compatible = "qcom,geni-i2c";
 795                                 reg = <0 0x00884000 0 0x4000>;
 796                                 clock-names = "se";
 797                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 798                                 pinctrl-names = "default";
 799                                 pinctrl-0 = <&qup_i2c1_default>;
 800                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803                                 status = "disabled";
 804                         };
 805
 806                         spi1: spi@884000 {
 807                                 compatible = "qcom,geni-spi";
 808                                 reg = <0 0x00884000 0 0x4000>;
 809                                 clock-names = "se";
 810                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 811                                 pinctrl-names = "default";
 812                                 pinctrl-0 = <&qup_spi1_default>;
 813                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 814                                 #address-cells = <1>;
 815                                 #size-cells = <0>;
 816                                 status = "disabled";
 817                         };
 818
 819                         uart1: serial@884000 {
 820                                 compatible = "qcom,geni-uart";
 821                                 reg = <0 0x00884000 0 0x4000>;
 822                                 clock-names = "se";
 823                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 824                                 pinctrl-names = "default";
 825                                 pinctrl-0 = <&qup_uart1_default>;
 826                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 827                                 status = "disabled";
 828                         };
 829
 830                         i2c2: i2c@888000 {
 831                                 compatible = "qcom,geni-i2c";
 832                                 reg = <0 0x00888000 0 0x4000>;
 833                                 clock-names = "se";
 834                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 835                                 pinctrl-names = "default";
 836                                 pinctrl-0 = <&qup_i2c2_default>;
 837                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 status = "disabled";
 841                         };
 842
 843                         spi2: spi@888000 {
 844                                 compatible = "qcom,geni-spi";
 845                                 reg = <0 0x00888000 0 0x4000>;
 846                                 clock-names = "se";
 847                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 848                                 pinctrl-names = "default";
 849                                 pinctrl-0 = <&qup_spi2_default>;
 850                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 851                                 #address-cells = <1>;
 852                                 #size-cells = <0>;
 853                                 status = "disabled";
 854                         };
 855
 856                         uart2: serial@888000 {
 857                                 compatible = "qcom,geni-uart";
 858                                 reg = <0 0x00888000 0 0x4000>;
 859                                 clock-names = "se";
 860                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 861                                 pinctrl-names = "default";
 862                                 pinctrl-0 = <&qup_uart2_default>;
 863                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 864                                 status = "disabled";
 865                         };
 866
 867                         i2c3: i2c@88c000 {
 868                                 compatible = "qcom,geni-i2c";
 869                                 reg = <0 0x0088c000 0 0x4000>;
 870                                 clock-names = "se";
 871                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 872                                 pinctrl-names = "default";
 873                                 pinctrl-0 = <&qup_i2c3_default>;
 874                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 875                                 #address-cells = <1>;
 876                                 #size-cells = <0>;
 877                                 status = "disabled";
 878                         };
 879
 880                         spi3: spi@88c000 {
 881                                 compatible = "qcom,geni-spi";
 882                                 reg = <0 0x0088c000 0 0x4000>;
 883                                 clock-names = "se";
 884                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 885                                 pinctrl-names = "default";
 886                                 pinctrl-0 = <&qup_spi3_default>;
 887                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 888                                 #address-cells = <1>;
 889                                 #size-cells = <0>;
 890                                 status = "disabled";
 891                         };
 892
 893                         uart3: serial@88c000 {
 894                                 compatible = "qcom,geni-uart";
 895                                 reg = <0 0x0088c000 0 0x4000>;
 896                                 clock-names = "se";
 897                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 898                                 pinctrl-names = "default";
 899                                 pinctrl-0 = <&qup_uart3_default>;
 900                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 901                                 status = "disabled";
 902                         };
 903
 904                         i2c4: i2c@890000 {
 905                                 compatible = "qcom,geni-i2c";
 906                                 reg = <0 0x00890000 0 0x4000>;
 907                                 clock-names = "se";
 908                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 909                                 pinctrl-names = "default";
 910                                 pinctrl-0 = <&qup_i2c4_default>;
 911                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 912                                 #address-cells = <1>;
 913                                 #size-cells = <0>;
 914                                 status = "disabled";
 915                         };
 916
 917                         spi4: spi@890000 {
 918                                 compatible = "qcom,geni-spi";
 919                                 reg = <0 0x00890000 0 0x4000>;
 920                                 clock-names = "se";
 921                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 922                                 pinctrl-names = "default";
 923                                 pinctrl-0 = <&qup_spi4_default>;
 924                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 status = "disabled";
 928                         };
 929
 930                         uart4: serial@890000 {
 931                                 compatible = "qcom,geni-uart";
 932                                 reg = <0 0x00890000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 935                                 pinctrl-names = "default";
 936                                 pinctrl-0 = <&qup_uart4_default>;
 937                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 938                                 status = "disabled";
 939                         };
 940
 941                         i2c5: i2c@894000 {
 942                                 compatible = "qcom,geni-i2c";
 943                                 reg = <0 0x00894000 0 0x4000>;
 944                                 clock-names = "se";
 945                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 946                                 pinctrl-names = "default";
 947                                 pinctrl-0 = <&qup_i2c5_default>;
 948                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 949                                 #address-cells = <1>;
 950                                 #size-cells = <0>;
 951                                 status = "disabled";
 952                         };
 953
 954                         spi5: spi@894000 {
 955                                 compatible = "qcom,geni-spi";
 956                                 reg = <0 0x00894000 0 0x4000>;
 957                                 clock-names = "se";
 958                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 959                                 pinctrl-names = "default";
 960                                 pinctrl-0 = <&qup_spi5_default>;
 961                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 962                                 #address-cells = <1>;
 963                                 #size-cells = <0>;
 964                                 status = "disabled";
 965                         };
 966
 967                         uart5: serial@894000 {
 968                                 compatible = "qcom,geni-uart";
 969                                 reg = <0 0x00894000 0 0x4000>;
 970                                 clock-names = "se";
 971                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 972                                 pinctrl-names = "default";
 973                                 pinctrl-0 = <&qup_uart5_default>;
 974                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 975                                 status = "disabled";
 976                         };
 977
 978                         i2c6: i2c@898000 {
 979                                 compatible = "qcom,geni-i2c";
 980                                 reg = <0 0x00898000 0 0x4000>;
 981                                 clock-names = "se";
 982                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 983                                 pinctrl-names = "default";
 984                                 pinctrl-0 = <&qup_i2c6_default>;
 985                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 986                                 #address-cells = <1>;
 987                                 #size-cells = <0>;
 988                                 status = "disabled";
 989                         };
 990
 991                         spi6: spi@898000 {
 992                                 compatible = "qcom,geni-spi";
 993                                 reg = <0 0x00898000 0 0x4000>;
 994                                 clock-names = "se";
 995                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 996                                 pinctrl-names = "default";
 997                                 pinctrl-0 = <&qup_spi6_default>;
 998                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 999                                 #address-cells = <1>;
1000                                 #size-cells = <0>;
1001                                 status = "disabled";
1002                         };
1003
1004                         uart6: serial@898000 {
1005                                 compatible = "qcom,geni-uart";
1006                                 reg = <0 0x00898000 0 0x4000>;
1007                                 clock-names = "se";
1008                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1009                                 pinctrl-names = "default";
1010                                 pinctrl-0 = <&qup_uart6_default>;
1011                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1012                                 status = "disabled";
1013                         };
1014
1015                         i2c7: i2c@89c000 {
1016                                 compatible = "qcom,geni-i2c";
1017                                 reg = <0 0x0089c000 0 0x4000>;
1018                                 clock-names = "se";
1019                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1020                                 pinctrl-names = "default";
1021                                 pinctrl-0 = <&qup_i2c7_default>;
1022                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1023                                 #address-cells = <1>;
1024                                 #size-cells = <0>;
1025                                 status = "disabled";
1026                         };
1027
1028                         spi7: spi@89c000 {
1029                                 compatible = "qcom,geni-spi";
1030                                 reg = <0 0x0089c000 0 0x4000>;
1031                                 clock-names = "se";
1032                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1033                                 pinctrl-names = "default";
1034                                 pinctrl-0 = <&qup_spi7_default>;
1035                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1036                                 #address-cells = <1>;
1037                                 #size-cells = <0>;
1038                                 status = "disabled";
1039                         };
1040
1041                         uart7: serial@89c000 {
1042                                 compatible = "qcom,geni-uart";
1043                                 reg = <0 0x0089c000 0 0x4000>;
1044                                 clock-names = "se";
1045                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1046                                 pinctrl-names = "default";
1047                                 pinctrl-0 = <&qup_uart7_default>;
1048                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1049                                 status = "disabled";
1050                         };
1051                 };
1052
1053                 qupv3_id_1: geniqup@ac0000 {
1054                         compatible = "qcom,geni-se-qup";
1055                         reg = <0 0x00ac0000 0 0x6000>;
1056                         clock-names = "m-ahb", "s-ahb";
1057                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1058                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1059                         #address-cells = <2>;
1060                         #size-cells = <2>;
1061                         ranges;
1062                         status = "disabled";
1063
1064                         i2c8: i2c@a80000 {
1065                                 compatible = "qcom,geni-i2c";
1066                                 reg = <0 0x00a80000 0 0x4000>;
1067                                 clock-names = "se";
1068                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1069                                 pinctrl-names = "default";
1070                                 pinctrl-0 = <&qup_i2c8_default>;
1071                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074                                 status = "disabled";
1075                         };
1076
1077                         spi8: spi@a80000 {
1078                                 compatible = "qcom,geni-spi";
1079                                 reg = <0 0x00a80000 0 0x4000>;
1080                                 clock-names = "se";
1081                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1082                                 pinctrl-names = "default";
1083                                 pinctrl-0 = <&qup_spi8_default>;
1084                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1085                                 #address-cells = <1>;
1086                                 #size-cells = <0>;
1087                                 status = "disabled";
1088                         };
1089
1090                         uart8: serial@a80000 {
1091                                 compatible = "qcom,geni-uart";
1092                                 reg = <0 0x00a80000 0 0x4000>;
1093                                 clock-names = "se";
1094                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1095                                 pinctrl-names = "default";
1096                                 pinctrl-0 = <&qup_uart8_default>;
1097                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1098                                 status = "disabled";
1099                         };
1100
1101                         i2c9: i2c@a84000 {
1102                                 compatible = "qcom,geni-i2c";
1103                                 reg = <0 0x00a84000 0 0x4000>;
1104                                 clock-names = "se";
1105                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1106                                 pinctrl-names = "default";
1107                                 pinctrl-0 = <&qup_i2c9_default>;
1108                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1109                                 #address-cells = <1>;
1110                                 #size-cells = <0>;
1111                                 status = "disabled";
1112                         };
1113
1114                         spi9: spi@a84000 {
1115                                 compatible = "qcom,geni-spi";
1116                                 reg = <0 0x00a84000 0 0x4000>;
1117                                 clock-names = "se";
1118                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1119                                 pinctrl-names = "default";
1120                                 pinctrl-0 = <&qup_spi9_default>;
1121                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1122                                 #address-cells = <1>;
1123                                 #size-cells = <0>;
1124                                 status = "disabled";
1125                         };
1126
1127                         uart9: serial@a84000 {
1128                                 compatible = "qcom,geni-debug-uart";
1129                                 reg = <0 0x00a84000 0 0x4000>;
1130                                 clock-names = "se";
1131                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1132                                 pinctrl-names = "default";
1133                                 pinctrl-0 = <&qup_uart9_default>;
1134                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1135                                 status = "disabled";
1136                         };
1137
1138                         i2c10: i2c@a88000 {
1139                                 compatible = "qcom,geni-i2c";
1140                                 reg = <0 0x00a88000 0 0x4000>;
1141                                 clock-names = "se";
1142                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1143                                 pinctrl-names = "default";
1144                                 pinctrl-0 = <&qup_i2c10_default>;
1145                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1146                                 #address-cells = <1>;
1147                                 #size-cells = <0>;
1148                                 status = "disabled";
1149                         };
1150
1151                         spi10: spi@a88000 {
1152                                 compatible = "qcom,geni-spi";
1153                                 reg = <0 0x00a88000 0 0x4000>;
1154                                 clock-names = "se";
1155                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1156                                 pinctrl-names = "default";
1157                                 pinctrl-0 = <&qup_spi10_default>;
1158                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161                                 status = "disabled";
1162                         };
1163
1164                         uart10: serial@a88000 {
1165                                 compatible = "qcom,geni-uart";
1166                                 reg = <0 0x00a88000 0 0x4000>;
1167                                 clock-names = "se";
1168                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1169                                 pinctrl-names = "default";
1170                                 pinctrl-0 = <&qup_uart10_default>;
1171                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1172                                 status = "disabled";
1173                         };
1174
1175                         i2c11: i2c@a8c000 {
1176                                 compatible = "qcom,geni-i2c";
1177                                 reg = <0 0x00a8c000 0 0x4000>;
1178                                 clock-names = "se";
1179                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1180                                 pinctrl-names = "default";
1181                                 pinctrl-0 = <&qup_i2c11_default>;
1182                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1183                                 #address-cells = <1>;
1184                                 #size-cells = <0>;
1185                                 status = "disabled";
1186                         };
1187
1188                         spi11: spi@a8c000 {
1189                                 compatible = "qcom,geni-spi";
1190                                 reg = <0 0x00a8c000 0 0x4000>;
1191                                 clock-names = "se";
1192                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1193                                 pinctrl-names = "default";
1194                                 pinctrl-0 = <&qup_spi11_default>;
1195                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1196                                 #address-cells = <1>;
1197                                 #size-cells = <0>;
1198                                 status = "disabled";
1199                         };
1200
1201                         uart11: serial@a8c000 {
1202                                 compatible = "qcom,geni-uart";
1203                                 reg = <0 0x00a8c000 0 0x4000>;
1204                                 clock-names = "se";
1205                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1206                                 pinctrl-names = "default";
1207                                 pinctrl-0 = <&qup_uart11_default>;
1208                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1209                                 status = "disabled";
1210                         };
1211
1212                         i2c12: i2c@a90000 {
1213                                 compatible = "qcom,geni-i2c";
1214                                 reg = <0 0x00a90000 0 0x4000>;
1215                                 clock-names = "se";
1216                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1217                                 pinctrl-names = "default";
1218                                 pinctrl-0 = <&qup_i2c12_default>;
1219                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1220                                 #address-cells = <1>;
1221                                 #size-cells = <0>;
1222                                 status = "disabled";
1223                         };
1224
1225                         spi12: spi@a90000 {
1226                                 compatible = "qcom,geni-spi";
1227                                 reg = <0 0x00a90000 0 0x4000>;
1228                                 clock-names = "se";
1229                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1230                                 pinctrl-names = "default";
1231                                 pinctrl-0 = <&qup_spi12_default>;
1232                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1233                                 #address-cells = <1>;
1234                                 #size-cells = <0>;
1235                                 status = "disabled";
1236                         };
1237
1238                         uart12: serial@a90000 {
1239                                 compatible = "qcom,geni-uart";
1240                                 reg = <0 0x00a90000 0 0x4000>;
1241                                 clock-names = "se";
1242                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&qup_uart12_default>;
1245                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1246                                 status = "disabled";
1247                         };
1248
1249                         i2c13: i2c@a94000 {
1250                                 compatible = "qcom,geni-i2c";
1251                                 reg = <0 0x00a94000 0 0x4000>;
1252                                 clock-names = "se";
1253                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1254                                 pinctrl-names = "default";
1255                                 pinctrl-0 = <&qup_i2c13_default>;
1256                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1257                                 #address-cells = <1>;
1258                                 #size-cells = <0>;
1259                                 status = "disabled";
1260                         };
1261
1262                         spi13: spi@a94000 {
1263                                 compatible = "qcom,geni-spi";
1264                                 reg = <0 0x00a94000 0 0x4000>;
1265                                 clock-names = "se";
1266                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1267                                 pinctrl-names = "default";
1268                                 pinctrl-0 = <&qup_spi13_default>;
1269                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1270                                 #address-cells = <1>;
1271                                 #size-cells = <0>;
1272                                 status = "disabled";
1273                         };
1274
1275                         uart13: serial@a94000 {
1276                                 compatible = "qcom,geni-uart";
1277                                 reg = <0 0x00a94000 0 0x4000>;
1278                                 clock-names = "se";
1279                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1280                                 pinctrl-names = "default";
1281                                 pinctrl-0 = <&qup_uart13_default>;
1282                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1283                                 status = "disabled";
1284                         };
1285
1286                         i2c14: i2c@a98000 {
1287                                 compatible = "qcom,geni-i2c";
1288                                 reg = <0 0x00a98000 0 0x4000>;
1289                                 clock-names = "se";
1290                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1291                                 pinctrl-names = "default";
1292                                 pinctrl-0 = <&qup_i2c14_default>;
1293                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1294                                 #address-cells = <1>;
1295                                 #size-cells = <0>;
1296                                 status = "disabled";
1297                         };
1298
1299                         spi14: spi@a98000 {
1300                                 compatible = "qcom,geni-spi";
1301                                 reg = <0 0x00a98000 0 0x4000>;
1302                                 clock-names = "se";
1303                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1304                                 pinctrl-names = "default";
1305                                 pinctrl-0 = <&qup_spi14_default>;
1306                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1307                                 #address-cells = <1>;
1308                                 #size-cells = <0>;
1309                                 status = "disabled";
1310                         };
1311
1312                         uart14: serial@a98000 {
1313                                 compatible = "qcom,geni-uart";
1314                                 reg = <0 0x00a98000 0 0x4000>;
1315                                 clock-names = "se";
1316                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1317                                 pinctrl-names = "default";
1318                                 pinctrl-0 = <&qup_uart14_default>;
1319                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1320                                 status = "disabled";
1321                         };
1322
1323                         i2c15: i2c@a9c000 {
1324                                 compatible = "qcom,geni-i2c";
1325                                 reg = <0 0x00a9c000 0 0x4000>;
1326                                 clock-names = "se";
1327                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1328                                 pinctrl-names = "default";
1329                                 pinctrl-0 = <&qup_i2c15_default>;
1330                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1331                                 #address-cells = <1>;
1332                                 #size-cells = <0>;
1333                                 status = "disabled";
1334                         };
1335
1336                         spi15: spi@a9c000 {
1337                                 compatible = "qcom,geni-spi";
1338                                 reg = <0 0x00a9c000 0 0x4000>;
1339                                 clock-names = "se";
1340                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1341                                 pinctrl-names = "default";
1342                                 pinctrl-0 = <&qup_spi15_default>;
1343                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1344                                 #address-cells = <1>;
1345                                 #size-cells = <0>;
1346                                 status = "disabled";
1347                         };
1348
1349                         uart15: serial@a9c000 {
1350                                 compatible = "qcom,geni-uart";
1351                                 reg = <0 0x00a9c000 0 0x4000>;
1352                                 clock-names = "se";
1353                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1354                                 pinctrl-names = "default";
1355                                 pinctrl-0 = <&qup_uart15_default>;
1356                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1357                                 status = "disabled";
1358                         };
1359                 };
1360
1361                 cache-controller@1100000 {
1362                         compatible = "qcom,sdm845-llcc";
1363                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
1364                         reg-names = "llcc_base", "llcc_broadcast_base";
1365                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1366                 };
1367
1368                 ufs_mem_hc: ufshc@1d84000 {
1369                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
1370                                      "jedec,ufs-2.0";
1371                         reg = <0 0x01d84000 0 0x2500>;
1372                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1373                         phys = <&ufs_mem_phy_lanes>;
1374                         phy-names = "ufsphy";
1375                         lanes-per-direction = <2>;
1376                         power-domains = <&gcc UFS_PHY_GDSC>;
1377                         #reset-cells = <1>;
1378
1379                         iommus = <&apps_smmu 0x100 0xf>;
1380
1381                         clock-names =
1382                                 "core_clk",
1383                                 "bus_aggr_clk",
1384                                 "iface_clk",
1385                                 "core_clk_unipro",
1386                                 "ref_clk",
1387                                 "tx_lane0_sync_clk",
1388                                 "rx_lane0_sync_clk",
1389                                 "rx_lane1_sync_clk";
1390                         clocks =
1391                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1392                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1393                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1394                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1395                                 <&rpmhcc RPMH_CXO_CLK>,
1396                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1397                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1398                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1399                         freq-table-hz =
1400                                 <50000000 200000000>,
1401                                 <0 0>,
1402                                 <0 0>,
1403                                 <37500000 150000000>,
1404                                 <0 0>,
1405                                 <0 0>,
1406                                 <0 0>,
1407                                 <0 0>;
1408
1409                         status = "disabled";
1410                 };
1411
1412                 ufs_mem_phy: phy@1d87000 {
1413                         compatible = "qcom,sdm845-qmp-ufs-phy";
1414                         reg = <0 0x01d87000 0 0x18c>;
1415                         #address-cells = <2>;
1416                         #size-cells = <2>;
1417                         ranges;
1418                         clock-names = "ref",
1419                                       "ref_aux";
1420                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1421                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1422
1423                         resets = <&ufs_mem_hc 0>;
1424                         reset-names = "ufsphy";
1425                         status = "disabled";
1426
1427                         ufs_mem_phy_lanes: lanes@1d87400 {
1428                                 reg = <0 0x01d87400 0 0x108>,
1429                                       <0 0x01d87600 0 0x1e0>,
1430                                       <0 0x01d87c00 0 0x1dc>,
1431                                       <0 0x01d87800 0 0x108>,
1432                                       <0 0x01d87a00 0 0x1e0>;
1433                                 #phy-cells = <0>;
1434                         };
1435                 };
1436
1437                 tcsr_mutex_regs: syscon@1f40000 {
1438                         compatible = "syscon";
1439                         reg = <0 0x01f40000 0 0x40000>;
1440                 };
1441
1442                 tlmm: pinctrl@3400000 {
1443                         compatible = "qcom,sdm845-pinctrl";
1444                         reg = <0 0x03400000 0 0xc00000>;
1445                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1446                         gpio-controller;
1447                         #gpio-cells = <2>;
1448                         interrupt-controller;
1449                         #interrupt-cells = <2>;
1450                         gpio-ranges = <&tlmm 0 0 150>;
1451
1452                         qspi_clk: qspi-clk {
1453                                 pinmux {
1454                                         pins = "gpio95";
1455                                         function = "qspi_clk";
1456                                 };
1457                         };
1458
1459                         qspi_cs0: qspi-cs0 {
1460                                 pinmux {
1461                                         pins = "gpio90";
1462                                         function = "qspi_cs";
1463                                 };
1464                         };
1465
1466                         qspi_cs1: qspi-cs1 {
1467                                 pinmux {
1468                                         pins = "gpio89";
1469                                         function = "qspi_cs";
1470                                 };
1471                         };
1472
1473                         qspi_data01: qspi-data01 {
1474                                 pinmux-data {
1475                                         pins = "gpio91", "gpio92";
1476                                         function = "qspi_data";
1477                                 };
1478                         };
1479
1480                         qspi_data12: qspi-data12 {
1481                                 pinmux-data {
1482                                         pins = "gpio93", "gpio94";
1483                                         function = "qspi_data";
1484                                 };
1485                         };
1486
1487                         qup_i2c0_default: qup-i2c0-default {
1488                                 pinmux {
1489                                         pins = "gpio0", "gpio1";
1490                                         function = "qup0";
1491                                 };
1492                         };
1493
1494                         qup_i2c1_default: qup-i2c1-default {
1495                                 pinmux {
1496                                         pins = "gpio17", "gpio18";
1497                                         function = "qup1";
1498                                 };
1499                         };
1500
1501                         qup_i2c2_default: qup-i2c2-default {
1502                                 pinmux {
1503                                         pins = "gpio27", "gpio28";
1504                                         function = "qup2";
1505                                 };
1506                         };
1507
1508                         qup_i2c3_default: qup-i2c3-default {
1509                                 pinmux {
1510                                         pins = "gpio41", "gpio42";
1511                                         function = "qup3";
1512                                 };
1513                         };
1514
1515                         qup_i2c4_default: qup-i2c4-default {
1516                                 pinmux {
1517                                         pins = "gpio89", "gpio90";
1518                                         function = "qup4";
1519                                 };
1520                         };
1521
1522                         qup_i2c5_default: qup-i2c5-default {
1523                                 pinmux {
1524                                         pins = "gpio85", "gpio86";
1525                                         function = "qup5";
1526                                 };
1527                         };
1528
1529                         qup_i2c6_default: qup-i2c6-default {
1530                                 pinmux {
1531                                         pins = "gpio45", "gpio46";
1532                                         function = "qup6";
1533                                 };
1534                         };
1535
1536                         qup_i2c7_default: qup-i2c7-default {
1537                                 pinmux {
1538                                         pins = "gpio93", "gpio94";
1539                                         function = "qup7";
1540                                 };
1541                         };
1542
1543                         qup_i2c8_default: qup-i2c8-default {
1544                                 pinmux {
1545                                         pins = "gpio65", "gpio66";
1546                                         function = "qup8";
1547                                 };
1548                         };
1549
1550                         qup_i2c9_default: qup-i2c9-default {
1551                                 pinmux {
1552                                         pins = "gpio6", "gpio7";
1553                                         function = "qup9";
1554                                 };
1555                         };
1556
1557                         qup_i2c10_default: qup-i2c10-default {
1558                                 pinmux {
1559                                         pins = "gpio55", "gpio56";
1560                                         function = "qup10";
1561                                 };
1562                         };
1563
1564                         qup_i2c11_default: qup-i2c11-default {
1565                                 pinmux {
1566                                         pins = "gpio31", "gpio32";
1567                                         function = "qup11";
1568                                 };
1569                         };
1570
1571                         qup_i2c12_default: qup-i2c12-default {
1572                                 pinmux {
1573                                         pins = "gpio49", "gpio50";
1574                                         function = "qup12";
1575                                 };
1576                         };
1577
1578                         qup_i2c13_default: qup-i2c13-default {
1579                                 pinmux {
1580                                         pins = "gpio105", "gpio106";
1581                                         function = "qup13";
1582                                 };
1583                         };
1584
1585                         qup_i2c14_default: qup-i2c14-default {
1586                                 pinmux {
1587                                         pins = "gpio33", "gpio34";
1588                                         function = "qup14";
1589                                 };
1590                         };
1591
1592                         qup_i2c15_default: qup-i2c15-default {
1593                                 pinmux {
1594                                         pins = "gpio81", "gpio82";
1595                                         function = "qup15";
1596                                 };
1597                         };
1598
1599                         qup_spi0_default: qup-spi0-default {
1600                                 pinmux {
1601                                         pins = "gpio0", "gpio1",
1602                                                "gpio2", "gpio3";
1603                                         function = "qup0";
1604                                 };
1605                         };
1606
1607                         qup_spi1_default: qup-spi1-default {
1608                                 pinmux {
1609                                         pins = "gpio17", "gpio18",
1610                                                "gpio19", "gpio20";
1611                                         function = "qup1";
1612                                 };
1613                         };
1614
1615                         qup_spi2_default: qup-spi2-default {
1616                                 pinmux {
1617                                         pins = "gpio27", "gpio28",
1618                                                "gpio29", "gpio30";
1619                                         function = "qup2";
1620                                 };
1621                         };
1622
1623                         qup_spi3_default: qup-spi3-default {
1624                                 pinmux {
1625                                         pins = "gpio41", "gpio42",
1626                                                "gpio43", "gpio44";
1627                                         function = "qup3";
1628                                 };
1629                         };
1630
1631                         qup_spi4_default: qup-spi4-default {
1632                                 pinmux {
1633                                         pins = "gpio89", "gpio90",
1634                                                "gpio91", "gpio92";
1635                                         function = "qup4";
1636                                 };
1637                         };
1638
1639                         qup_spi5_default: qup-spi5-default {
1640                                 pinmux {
1641                                         pins = "gpio85", "gpio86",
1642                                                "gpio87", "gpio88";
1643                                         function = "qup5";
1644                                 };
1645                         };
1646
1647                         qup_spi6_default: qup-spi6-default {
1648                                 pinmux {
1649                                         pins = "gpio45", "gpio46",
1650                                                "gpio47", "gpio48";
1651                                         function = "qup6";
1652                                 };
1653                         };
1654
1655                         qup_spi7_default: qup-spi7-default {
1656                                 pinmux {
1657                                         pins = "gpio93", "gpio94",
1658                                                "gpio95", "gpio96";
1659                                         function = "qup7";
1660                                 };
1661                         };
1662
1663                         qup_spi8_default: qup-spi8-default {
1664                                 pinmux {
1665                                         pins = "gpio65", "gpio66",
1666                                                "gpio67", "gpio68";
1667                                         function = "qup8";
1668                                 };
1669                         };
1670
1671                         qup_spi9_default: qup-spi9-default {
1672                                 pinmux {
1673                                         pins = "gpio6", "gpio7",
1674                                                "gpio4", "gpio5";
1675                                         function = "qup9";
1676                                 };
1677                         };
1678
1679                         qup_spi10_default: qup-spi10-default {
1680                                 pinmux {
1681                                         pins = "gpio55", "gpio56",
1682                                                "gpio53", "gpio54";
1683                                         function = "qup10";
1684                                 };
1685                         };
1686
1687                         qup_spi11_default: qup-spi11-default {
1688                                 pinmux {
1689                                         pins = "gpio31", "gpio32",
1690                                                "gpio33", "gpio34";
1691                                         function = "qup11";
1692                                 };
1693                         };
1694
1695                         qup_spi12_default: qup-spi12-default {
1696                                 pinmux {
1697                                         pins = "gpio49", "gpio50",
1698                                                "gpio51", "gpio52";
1699                                         function = "qup12";
1700                                 };
1701                         };
1702
1703                         qup_spi13_default: qup-spi13-default {
1704                                 pinmux {
1705                                         pins = "gpio105", "gpio106",
1706                                                "gpio107", "gpio108";
1707                                         function = "qup13";
1708                                 };
1709                         };
1710
1711                         qup_spi14_default: qup-spi14-default {
1712                                 pinmux {
1713                                         pins = "gpio33", "gpio34",
1714                                                "gpio31", "gpio32";
1715                                         function = "qup14";
1716                                 };
1717                         };
1718
1719                         qup_spi15_default: qup-spi15-default {
1720                                 pinmux {
1721                                         pins = "gpio81", "gpio82",
1722                                                "gpio83", "gpio84";
1723                                         function = "qup15";
1724                                 };
1725                         };
1726
1727                         qup_uart0_default: qup-uart0-default {
1728                                 pinmux {
1729                                         pins = "gpio2", "gpio3";
1730                                         function = "qup0";
1731                                 };
1732                         };
1733
1734                         qup_uart1_default: qup-uart1-default {
1735                                 pinmux {
1736                                         pins = "gpio19", "gpio20";
1737                                         function = "qup1";
1738                                 };
1739                         };
1740
1741                         qup_uart2_default: qup-uart2-default {
1742                                 pinmux {
1743                                         pins = "gpio29", "gpio30";
1744                                         function = "qup2";
1745                                 };
1746                         };
1747
1748                         qup_uart3_default: qup-uart3-default {
1749                                 pinmux {
1750                                         pins = "gpio43", "gpio44";
1751                                         function = "qup3";
1752                                 };
1753                         };
1754
1755                         qup_uart4_default: qup-uart4-default {
1756                                 pinmux {
1757                                         pins = "gpio91", "gpio92";
1758                                         function = "qup4";
1759                                 };
1760                         };
1761
1762                         qup_uart5_default: qup-uart5-default {
1763                                 pinmux {
1764                                         pins = "gpio87", "gpio88";
1765                                         function = "qup5";
1766                                 };
1767                         };
1768
1769                         qup_uart6_default: qup-uart6-default {
1770                                 pinmux {
1771                                         pins = "gpio47", "gpio48";
1772                                         function = "qup6";
1773                                 };
1774                         };
1775
1776                         qup_uart7_default: qup-uart7-default {
1777                                 pinmux {
1778                                         pins = "gpio95", "gpio96";
1779                                         function = "qup7";
1780                                 };
1781                         };
1782
1783                         qup_uart8_default: qup-uart8-default {
1784                                 pinmux {
1785                                         pins = "gpio67", "gpio68";
1786                                         function = "qup8";
1787                                 };
1788                         };
1789
1790                         qup_uart9_default: qup-uart9-default {
1791                                 pinmux {
1792                                         pins = "gpio4", "gpio5";
1793                                         function = "qup9";
1794                                 };
1795                         };
1796
1797                         qup_uart10_default: qup-uart10-default {
1798                                 pinmux {
1799                                         pins = "gpio53", "gpio54";
1800                                         function = "qup10";
1801                                 };
1802                         };
1803
1804                         qup_uart11_default: qup-uart11-default {
1805                                 pinmux {
1806                                         pins = "gpio33", "gpio34";
1807                                         function = "qup11";
1808                                 };
1809                         };
1810
1811                         qup_uart12_default: qup-uart12-default {
1812                                 pinmux {
1813                                         pins = "gpio51", "gpio52";
1814                                         function = "qup12";
1815                                 };
1816                         };
1817
1818                         qup_uart13_default: qup-uart13-default {
1819                                 pinmux {
1820                                         pins = "gpio107", "gpio108";
1821                                         function = "qup13";
1822                                 };
1823                         };
1824
1825                         qup_uart14_default: qup-uart14-default {
1826                                 pinmux {
1827                                         pins = "gpio31", "gpio32";
1828                                         function = "qup14";
1829                                 };
1830                         };
1831
1832                         qup_uart15_default: qup-uart15-default {
1833                                 pinmux {
1834                                         pins = "gpio83", "gpio84";
1835                                         function = "qup15";
1836                                 };
1837                         };
1838                 };
1839
1840                 mss_pil: remoteproc@4080000 {
1841                         compatible = "qcom,sdm845-mss-pil";
1842                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
1843                         reg-names = "qdsp6", "rmb";
1844
1845                         interrupts-extended =
1846                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1847                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1848                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1849                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1850                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1851                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1852                         interrupt-names = "wdog", "fatal", "ready",
1853                                           "handover", "stop-ack",
1854                                           "shutdown-ack";
1855
1856                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1857                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1858                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1859                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1860                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1861                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1862                                  <&gcc GCC_PRNG_AHB_CLK>,
1863                                  <&rpmhcc RPMH_CXO_CLK>;
1864                         clock-names = "iface", "bus", "mem", "gpll0_mss",
1865                                       "snoc_axi", "mnoc_axi", "prng", "xo";
1866
1867                         qcom,smem-states = <&modem_smp2p_out 0>;
1868                         qcom,smem-state-names = "stop";
1869
1870                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1871                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
1872                         reset-names = "mss_restart", "pdc_reset";
1873
1874                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1875
1876                         power-domains = <&aoss_qmp 2>,
1877                                         <&rpmhpd SDM845_CX>,
1878                                         <&rpmhpd SDM845_MX>,
1879                                         <&rpmhpd SDM845_MSS>;
1880                         power-domain-names = "load_state", "cx", "mx", "mss";
1881
1882                         mba {
1883                                 memory-region = <&mba_region>;
1884                         };
1885
1886                         mpss {
1887                                 memory-region = <&mpss_region>;
1888                         };
1889
1890                         glink-edge {
1891                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1892                                 label = "modem";
1893                                 qcom,remote-pid = <1>;
1894                                 mboxes = <&apss_shared 12>;
1895                         };
1896                 };
1897
1898                 gpucc: clock-controller@5090000 {
1899                         compatible = "qcom,sdm845-gpucc";
1900                         reg = <0 0x05090000 0 0x9000>;
1901                         #clock-cells = <1>;
1902                         #reset-cells = <1>;
1903                         #power-domain-cells = <1>;
1904                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1905                         clock-names = "xo";
1906                 };
1907
1908                 stm@6002000 {
1909                         compatible = "arm,coresight-stm", "arm,primecell";
1910                         reg = <0 0x06002000 0 0x1000>,
1911                               <0 0x16280000 0 0x180000>;
1912                         reg-names = "stm-base", "stm-stimulus-base";
1913
1914                         clocks = <&aoss_qmp>;
1915                         clock-names = "apb_pclk";
1916
1917                         out-ports {
1918                                 port {
1919                                         stm_out: endpoint {
1920                                                 remote-endpoint =
1921                                                   <&funnel0_in7>;
1922                                         };
1923                                 };
1924                         };
1925                 };
1926
1927                 funnel@6041000 {
1928                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1929                         reg = <0 0x06041000 0 0x1000>;
1930
1931                         clocks = <&aoss_qmp>;
1932                         clock-names = "apb_pclk";
1933
1934                         out-ports {
1935                                 port {
1936                                         funnel0_out: endpoint {
1937                                                 remote-endpoint =
1938                                                   <&merge_funnel_in0>;
1939                                         };
1940                                 };
1941                         };
1942
1943                         in-ports {
1944                                 #address-cells = <1>;
1945                                 #size-cells = <0>;
1946
1947                                 port@7 {
1948                                         reg = <7>;
1949                                         funnel0_in7: endpoint {
1950                                                 remote-endpoint = <&stm_out>;
1951                                         };
1952                                 };
1953                         };
1954                 };
1955
1956                 funnel@6043000 {
1957                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1958                         reg = <0 0x06043000 0 0x1000>;
1959
1960                         clocks = <&aoss_qmp>;
1961                         clock-names = "apb_pclk";
1962
1963                         out-ports {
1964                                 port {
1965                                         funnel2_out: endpoint {
1966                                                 remote-endpoint =
1967                                                   <&merge_funnel_in2>;
1968                                         };
1969                                 };
1970                         };
1971
1972                         in-ports {
1973                                 #address-cells = <1>;
1974                                 #size-cells = <0>;
1975
1976                                 port@5 {
1977                                         reg = <5>;
1978                                         funnel2_in5: endpoint {
1979                                                 remote-endpoint =
1980                                                   <&apss_merge_funnel_out>;
1981                                         };
1982                                 };
1983                         };
1984                 };
1985
1986                 funnel@6045000 {
1987                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1988                         reg = <0 0x06045000 0 0x1000>;
1989
1990                         clocks = <&aoss_qmp>;
1991                         clock-names = "apb_pclk";
1992
1993                         out-ports {
1994                                 port {
1995                                         merge_funnel_out: endpoint {
1996                                                 remote-endpoint = <&etf_in>;
1997                                         };
1998                                 };
1999                         };
2000
2001                         in-ports {
2002                                 #address-cells = <1>;
2003                                 #size-cells = <0>;
2004
2005                                 port@0 {
2006                                         reg = <0>;
2007                                         merge_funnel_in0: endpoint {
2008                                                 remote-endpoint =
2009                                                   <&funnel0_out>;
2010                                         };
2011                                 };
2012
2013                                 port@2 {
2014                                         reg = <2>;
2015                                         merge_funnel_in2: endpoint {
2016                                                 remote-endpoint =
2017                                                   <&funnel2_out>;
2018                                         };
2019                                 };
2020                         };
2021                 };
2022
2023                 replicator@6046000 {
2024                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2025                         reg = <0 0x06046000 0 0x1000>;
2026
2027                         clocks = <&aoss_qmp>;
2028                         clock-names = "apb_pclk";
2029
2030                         out-ports {
2031                                 port {
2032                                         replicator_out: endpoint {
2033                                                 remote-endpoint = <&etr_in>;
2034                                         };
2035                                 };
2036                         };
2037
2038                         in-ports {
2039                                 port {
2040                                         replicator_in: endpoint {
2041                                                 remote-endpoint = <&etf_out>;
2042                                         };
2043                                 };
2044                         };
2045                 };
2046
2047                 etf@6047000 {
2048                         compatible = "arm,coresight-tmc", "arm,primecell";
2049                         reg = <0 0x06047000 0 0x1000>;
2050
2051                         clocks = <&aoss_qmp>;
2052                         clock-names = "apb_pclk";
2053
2054                         out-ports {
2055                                 port {
2056                                         etf_out: endpoint {
2057                                                 remote-endpoint =
2058                                                   <&replicator_in>;
2059                                         };
2060                                 };
2061                         };
2062
2063                         in-ports {
2064                                 #address-cells = <1>;
2065                                 #size-cells = <0>;
2066
2067                                 port@1 {
2068                                         reg = <1>;
2069                                         etf_in: endpoint {
2070                                                 remote-endpoint =
2071                                                   <&merge_funnel_out>;
2072                                         };
2073                                 };
2074                         };
2075                 };
2076
2077                 etr@6048000 {
2078                         compatible = "arm,coresight-tmc", "arm,primecell";
2079                         reg = <0 0x06048000 0 0x1000>;
2080
2081                         clocks = <&aoss_qmp>;
2082                         clock-names = "apb_pclk";
2083                         arm,scatter-gather;
2084
2085                         in-ports {
2086                                 port {
2087                                         etr_in: endpoint {
2088                                                 remote-endpoint =
2089                                                   <&replicator_out>;
2090                                         };
2091                                 };
2092                         };
2093                 };
2094
2095                 etm@7040000 {
2096                         compatible = "arm,coresight-etm4x", "arm,primecell";
2097                         reg = <0 0x07040000 0 0x1000>;
2098
2099                         cpu = <&CPU0>;
2100
2101                         clocks = <&aoss_qmp>;
2102                         clock-names = "apb_pclk";
2103
2104                         out-ports {
2105                                 port {
2106                                         etm0_out: endpoint {
2107                                                 remote-endpoint =
2108                                                   <&apss_funnel_in0>;
2109                                         };
2110                                 };
2111                         };
2112                 };
2113
2114                 etm@7140000 {
2115                         compatible = "arm,coresight-etm4x", "arm,primecell";
2116                         reg = <0 0x07140000 0 0x1000>;
2117
2118                         cpu = <&CPU1>;
2119
2120                         clocks = <&aoss_qmp>;
2121                         clock-names = "apb_pclk";
2122
2123                         out-ports {
2124                                 port {
2125                                         etm1_out: endpoint {
2126                                                 remote-endpoint =
2127                                                   <&apss_funnel_in1>;
2128                                         };
2129                                 };
2130                         };
2131                 };
2132
2133                 etm@7240000 {
2134                         compatible = "arm,coresight-etm4x", "arm,primecell";
2135                         reg = <0 0x07240000 0 0x1000>;
2136
2137                         cpu = <&CPU2>;
2138
2139                         clocks = <&aoss_qmp>;
2140                         clock-names = "apb_pclk";
2141
2142                         out-ports {
2143                                 port {
2144                                         etm2_out: endpoint {
2145                                                 remote-endpoint =
2146                                                   <&apss_funnel_in2>;
2147                                         };
2148                                 };
2149                         };
2150                 };
2151
2152                 etm@7340000 {
2153                         compatible = "arm,coresight-etm4x", "arm,primecell";
2154                         reg = <0 0x07340000 0 0x1000>;
2155
2156                         cpu = <&CPU3>;
2157
2158                         clocks = <&aoss_qmp>;
2159                         clock-names = "apb_pclk";
2160
2161                         out-ports {
2162                                 port {
2163                                         etm3_out: endpoint {
2164                                                 remote-endpoint =
2165                                                   <&apss_funnel_in3>;
2166                                         };
2167                                 };
2168                         };
2169                 };
2170
2171                 etm@7440000 {
2172                         compatible = "arm,coresight-etm4x", "arm,primecell";
2173                         reg = <0 0x07440000 0 0x1000>;
2174
2175                         cpu = <&CPU4>;
2176
2177                         clocks = <&aoss_qmp>;
2178                         clock-names = "apb_pclk";
2179
2180                         out-ports {
2181                                 port {
2182                                         etm4_out: endpoint {
2183                                                 remote-endpoint =
2184                                                   <&apss_funnel_in4>;
2185                                         };
2186                                 };
2187                         };
2188                 };
2189
2190                 etm@7540000 {
2191                         compatible = "arm,coresight-etm4x", "arm,primecell";
2192                         reg = <0 0x07540000 0 0x1000>;
2193
2194                         cpu = <&CPU5>;
2195
2196                         clocks = <&aoss_qmp>;
2197                         clock-names = "apb_pclk";
2198
2199                         out-ports {
2200                                 port {
2201                                         etm5_out: endpoint {
2202                                                 remote-endpoint =
2203                                                   <&apss_funnel_in5>;
2204                                         };
2205                                 };
2206                         };
2207                 };
2208
2209                 etm@7640000 {
2210                         compatible = "arm,coresight-etm4x", "arm,primecell";
2211                         reg = <0 0x07640000 0 0x1000>;
2212
2213                         cpu = <&CPU6>;
2214
2215                         clocks = <&aoss_qmp>;
2216                         clock-names = "apb_pclk";
2217
2218                         out-ports {
2219                                 port {
2220                                         etm6_out: endpoint {
2221                                                 remote-endpoint =
2222                                                   <&apss_funnel_in6>;
2223                                         };
2224                                 };
2225                         };
2226                 };
2227
2228                 etm@7740000 {
2229                         compatible = "arm,coresight-etm4x", "arm,primecell";
2230                         reg = <0 0x07740000 0 0x1000>;
2231
2232                         cpu = <&CPU7>;
2233
2234                         clocks = <&aoss_qmp>;
2235                         clock-names = "apb_pclk";
2236
2237                         out-ports {
2238                                 port {
2239                                         etm7_out: endpoint {
2240                                                 remote-endpoint =
2241                                                   <&apss_funnel_in7>;
2242                                         };
2243                                 };
2244                         };
2245                 };
2246
2247                 funnel@7800000 { /* APSS Funnel */
2248                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2249                         reg = <0 0x07800000 0 0x1000>;
2250
2251                         clocks = <&aoss_qmp>;
2252                         clock-names = "apb_pclk";
2253
2254                         out-ports {
2255                                 port {
2256                                         apss_funnel_out: endpoint {
2257                                                 remote-endpoint =
2258                                                   <&apss_merge_funnel_in>;
2259                                         };
2260                                 };
2261                         };
2262
2263                         in-ports {
2264                                 #address-cells = <1>;
2265                                 #size-cells = <0>;
2266
2267                                 port@0 {
2268                                         reg = <0>;
2269                                         apss_funnel_in0: endpoint {
2270                                                 remote-endpoint =
2271                                                   <&etm0_out>;
2272                                         };
2273                                 };
2274
2275                                 port@1 {
2276                                         reg = <1>;
2277                                         apss_funnel_in1: endpoint {
2278                                                 remote-endpoint =
2279                                                   <&etm1_out>;
2280                                         };
2281                                 };
2282
2283                                 port@2 {
2284                                         reg = <2>;
2285                                         apss_funnel_in2: endpoint {
2286                                                 remote-endpoint =
2287                                                   <&etm2_out>;
2288                                         };
2289                                 };
2290
2291                                 port@3 {
2292                                         reg = <3>;
2293                                         apss_funnel_in3: endpoint {
2294                                                 remote-endpoint =
2295                                                   <&etm3_out>;
2296                                         };
2297                                 };
2298
2299                                 port@4 {
2300                                         reg = <4>;
2301                                         apss_funnel_in4: endpoint {
2302                                                 remote-endpoint =
2303                                                   <&etm4_out>;
2304                                         };
2305                                 };
2306
2307                                 port@5 {
2308                                         reg = <5>;
2309                                         apss_funnel_in5: endpoint {
2310                                                 remote-endpoint =
2311                                                   <&etm5_out>;
2312                                         };
2313                                 };
2314
2315                                 port@6 {
2316                                         reg = <6>;
2317                                         apss_funnel_in6: endpoint {
2318                                                 remote-endpoint =
2319                                                   <&etm6_out>;
2320                                         };
2321                                 };
2322
2323                                 port@7 {
2324                                         reg = <7>;
2325                                         apss_funnel_in7: endpoint {
2326                                                 remote-endpoint =
2327                                                   <&etm7_out>;
2328                                         };
2329                                 };
2330                         };
2331                 };
2332
2333                 funnel@7810000 {
2334                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2335                         reg = <0 0x07810000 0 0x1000>;
2336
2337                         clocks = <&aoss_qmp>;
2338                         clock-names = "apb_pclk";
2339
2340                         out-ports {
2341                                 port {
2342                                         apss_merge_funnel_out: endpoint {
2343                                                 remote-endpoint =
2344                                                   <&funnel2_in5>;
2345                                         };
2346                                 };
2347                         };
2348
2349                         in-ports {
2350                                 port {
2351                                         apss_merge_funnel_in: endpoint {
2352                                                 remote-endpoint =
2353                                                   <&apss_funnel_out>;
2354                                         };
2355                                 };
2356                         };
2357                 };
2358
2359                 sdhc_2: sdhci@8804000 {
2360                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
2361                         reg = <0 0x08804000 0 0x1000>;
2362
2363                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2364                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2365                         interrupt-names = "hc_irq", "pwr_irq";
2366
2367                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2368                                  <&gcc GCC_SDCC2_APPS_CLK>;
2369                         clock-names = "iface", "core";
2370                         iommus = <&apps_smmu 0xa0 0xf>;
2371
2372                         status = "disabled";
2373                 };
2374
2375                 qspi: spi@88df000 {
2376                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
2377                         reg = <0 0x088df000 0 0x600>;
2378                         #address-cells = <1>;
2379                         #size-cells = <0>;
2380                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
2381                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2382                                  <&gcc GCC_QSPI_CORE_CLK>;
2383                         clock-names = "iface", "core";
2384                         status = "disabled";
2385                 };
2386
2387                 usb_1_hsphy: phy@88e2000 {
2388                         compatible = "qcom,sdm845-qusb2-phy";
2389                         reg = <0 0x088e2000 0 0x400>;
2390                         status = "disabled";
2391                         #phy-cells = <0>;
2392
2393                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2394                                  <&rpmhcc RPMH_CXO_CLK>;
2395                         clock-names = "cfg_ahb", "ref";
2396
2397                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2398
2399                         nvmem-cells = <&qusb2p_hstx_trim>;
2400                 };
2401
2402                 usb_2_hsphy: phy@88e3000 {
2403                         compatible = "qcom,sdm845-qusb2-phy";
2404                         reg = <0 0x088e3000 0 0x400>;
2405                         status = "disabled";
2406                         #phy-cells = <0>;
2407
2408                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2409                                  <&rpmhcc RPMH_CXO_CLK>;
2410                         clock-names = "cfg_ahb", "ref";
2411
2412                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2413
2414                         nvmem-cells = <&qusb2s_hstx_trim>;
2415                 };
2416
2417                 usb_1_qmpphy: phy@88e9000 {
2418                         compatible = "qcom,sdm845-qmp-usb3-phy";
2419                         reg = <0 0x088e9000 0 0x18c>,
2420                               <0 0x088e8000 0 0x10>;
2421                         reg-names = "reg-base", "dp_com";
2422                         status = "disabled";
2423                         #clock-cells = <1>;
2424                         #address-cells = <2>;
2425                         #size-cells = <2>;
2426                         ranges;
2427
2428                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2429                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2430                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2431                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2432                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2433
2434                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2435                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2436                         reset-names = "phy", "common";
2437
2438                         usb_1_ssphy: lanes@88e9200 {
2439                                 reg = <0 0x088e9200 0 0x128>,
2440                                       <0 0x088e9400 0 0x200>,
2441                                       <0 0x088e9c00 0 0x218>,
2442                                       <0 0x088e9600 0 0x128>,
2443                                       <0 0x088e9800 0 0x200>,
2444                                       <0 0x088e9a00 0 0x100>;
2445                                 #phy-cells = <0>;
2446                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2447                                 clock-names = "pipe0";
2448                                 clock-output-names = "usb3_phy_pipe_clk_src";
2449                         };
2450                 };
2451
2452                 usb_2_qmpphy: phy@88eb000 {
2453                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
2454                         reg = <0 0x088eb000 0 0x18c>;
2455                         status = "disabled";
2456                         #clock-cells = <1>;
2457                         #address-cells = <2>;
2458                         #size-cells = <2>;
2459                         ranges;
2460
2461                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2462                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2463                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2464                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2465                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2466
2467                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2468                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2469                         reset-names = "phy", "common";
2470
2471                         usb_2_ssphy: lane@88eb200 {
2472                                 reg = <0 0x088eb200 0 0x128>,
2473                                       <0 0x088eb400 0 0x1fc>,
2474                                       <0 0x088eb800 0 0x218>,
2475                                       <0 0x088eb600 0 0x70>;
2476                                 #phy-cells = <0>;
2477                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2478                                 clock-names = "pipe0";
2479                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2480                         };
2481                 };
2482
2483                 usb_1: usb@a6f8800 {
2484                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2485                         reg = <0 0x0a6f8800 0 0x400>;
2486                         status = "disabled";
2487                         #address-cells = <2>;
2488                         #size-cells = <2>;
2489                         ranges;
2490                         dma-ranges;
2491
2492                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2493                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2494                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2495                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2496                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2497                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2498                                       "sleep";
2499
2500                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2501                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2502                         assigned-clock-rates = <19200000>, <150000000>;
2503
2504                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2505                                               <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2506                                               <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
2507                                               <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
2508                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2509                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2510
2511                         power-domains = <&gcc USB30_PRIM_GDSC>;
2512
2513                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2514
2515                         usb_1_dwc3: dwc3@a600000 {
2516                                 compatible = "snps,dwc3";
2517                                 reg = <0 0x0a600000 0 0xcd00>;
2518                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2519                                 iommus = <&apps_smmu 0x740 0>;
2520                                 snps,dis_u2_susphy_quirk;
2521                                 snps,dis_enblslpm_quirk;
2522                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2523                                 phy-names = "usb2-phy", "usb3-phy";
2524                         };
2525                 };
2526
2527                 usb_2: usb@a8f8800 {
2528                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
2529                         reg = <0 0x0a8f8800 0 0x400>;
2530                         status = "disabled";
2531                         #address-cells = <2>;
2532                         #size-cells = <2>;
2533                         ranges;
2534                         dma-ranges;
2535
2536                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2537                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2538                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2539                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2540                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
2541                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2542                                       "sleep";
2543
2544                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2545                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2546                         assigned-clock-rates = <19200000>, <150000000>;
2547
2548                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2549                                               <&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2550                                               <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
2551                                               <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
2552                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2553                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2554
2555                         power-domains = <&gcc USB30_SEC_GDSC>;
2556
2557                         resets = <&gcc GCC_USB30_SEC_BCR>;
2558
2559                         usb_2_dwc3: dwc3@a800000 {
2560                                 compatible = "snps,dwc3";
2561                                 reg = <0 0x0a800000 0 0xcd00>;
2562                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2563                                 iommus = <&apps_smmu 0x760 0>;
2564                                 snps,dis_u2_susphy_quirk;
2565                                 snps,dis_enblslpm_quirk;
2566                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2567                                 phy-names = "usb2-phy", "usb3-phy";
2568                         };
2569                 };
2570
2571                 video-codec@aa00000 {
2572                         compatible = "qcom,sdm845-venus";
2573                         reg = <0 0x0aa00000 0 0xff000>;
2574                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2575                         power-domains = <&videocc VENUS_GDSC>;
2576                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2577                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2578                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
2579                         clock-names = "core", "iface", "bus";
2580                         iommus = <&apps_smmu 0x10a0 0x8>,
2581                                  <&apps_smmu 0x10b0 0x0>;
2582                         memory-region = <&venus_mem>;
2583
2584                         video-core0 {
2585                                 compatible = "venus-decoder";
2586                                 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2587                                          <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2588                                 clock-names = "core", "bus";
2589                                 power-domains = <&videocc VCODEC0_GDSC>;
2590                         };
2591
2592                         video-core1 {
2593                                 compatible = "venus-encoder";
2594                                 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
2595                                          <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
2596                                 clock-names = "core", "bus";
2597                                 power-domains = <&videocc VCODEC1_GDSC>;
2598                         };
2599                 };
2600
2601                 videocc: clock-controller@ab00000 {
2602                         compatible = "qcom,sdm845-videocc";
2603                         reg = <0 0x0ab00000 0 0x10000>;
2604                         #clock-cells = <1>;
2605                         #power-domain-cells = <1>;
2606                         #reset-cells = <1>;
2607                 };
2608
2609                 mdss: mdss@ae00000 {
2610                         compatible = "qcom,sdm845-mdss";
2611                         reg = <0 0x0ae00000 0 0x1000>;
2612                         reg-names = "mdss";
2613
2614                         power-domains = <&dispcc MDSS_GDSC>;
2615
2616                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2617                                  <&gcc GCC_DISP_AXI_CLK>,
2618                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2619                         clock-names = "iface", "bus", "core";
2620
2621                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2622                         assigned-clock-rates = <300000000>;
2623
2624                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2625                         interrupt-controller;
2626                         #interrupt-cells = <1>;
2627
2628                         iommus = <&apps_smmu 0x880 0x8>,
2629                                  <&apps_smmu 0xc80 0x8>;
2630
2631                         status = "disabled";
2632
2633                         #address-cells = <2>;
2634                         #size-cells = <2>;
2635                         ranges;
2636
2637                         mdss_mdp: mdp@ae01000 {
2638                                 compatible = "qcom,sdm845-dpu";
2639                                 reg = <0 0x0ae01000 0 0x8f000>,
2640                                       <0 0x0aeb0000 0 0x2008>;
2641                                 reg-names = "mdp", "vbif";
2642
2643                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2644                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
2645                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2646                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2647                                 clock-names = "iface", "bus", "core", "vsync";
2648
2649                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2650                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2651                                 assigned-clock-rates = <300000000>,
2652                                                        <19200000>;
2653
2654                                 interrupt-parent = <&mdss>;
2655                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2656
2657                                 status = "disabled";
2658
2659                                 ports {
2660                                         #address-cells = <1>;
2661                                         #size-cells = <0>;
2662
2663                                         port@0 {
2664                                                 reg = <0>;
2665                                                 dpu_intf1_out: endpoint {
2666                                                         remote-endpoint = <&dsi0_in>;
2667                                                 };
2668                                         };
2669
2670                                         port@1 {
2671                                                 reg = <1>;
2672                                                 dpu_intf2_out: endpoint {
2673                                                         remote-endpoint = <&dsi1_in>;
2674                                                 };
2675                                         };
2676                                 };
2677                         };
2678
2679                         dsi0: dsi@ae94000 {
2680                                 compatible = "qcom,mdss-dsi-ctrl";
2681                                 reg = <0 0x0ae94000 0 0x400>;
2682                                 reg-names = "dsi_ctrl";
2683
2684                                 interrupt-parent = <&mdss>;
2685                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2686
2687                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2688                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2689                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2690                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2691                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2692                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
2693                                 clock-names = "byte",
2694                                               "byte_intf",
2695                                               "pixel",
2696                                               "core",
2697                                               "iface",
2698                                               "bus";
2699
2700                                 phys = <&dsi0_phy>;
2701                                 phy-names = "dsi";
2702
2703                                 status = "disabled";
2704
2705                                 ports {
2706                                         #address-cells = <1>;
2707                                         #size-cells = <0>;
2708
2709                                         port@0 {
2710                                                 reg = <0>;
2711                                                 dsi0_in: endpoint {
2712                                                         remote-endpoint = <&dpu_intf1_out>;
2713                                                 };
2714                                         };
2715
2716                                         port@1 {
2717                                                 reg = <1>;
2718                                                 dsi0_out: endpoint {
2719                                                 };
2720                                         };
2721                                 };
2722                         };
2723
2724                         dsi0_phy: dsi-phy@ae94400 {
2725                                 compatible = "qcom,dsi-phy-10nm";
2726                                 reg = <0 0x0ae94400 0 0x200>,
2727                                       <0 0x0ae94600 0 0x280>,
2728                                       <0 0x0ae94a00 0 0x1e0>;
2729                                 reg-names = "dsi_phy",
2730                                             "dsi_phy_lane",
2731                                             "dsi_pll";
2732
2733                                 #clock-cells = <1>;
2734                                 #phy-cells = <0>;
2735
2736                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2737                                          <&rpmhcc RPMH_CXO_CLK>;
2738                                 clock-names = "iface", "ref";
2739
2740                                 status = "disabled";
2741                         };
2742
2743                         dsi1: dsi@ae96000 {
2744                                 compatible = "qcom,mdss-dsi-ctrl";
2745                                 reg = <0 0x0ae96000 0 0x400>;
2746                                 reg-names = "dsi_ctrl";
2747
2748                                 interrupt-parent = <&mdss>;
2749                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2750
2751                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2752                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2753                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2754                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2755                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2756                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
2757                                 clock-names = "byte",
2758                                               "byte_intf",
2759                                               "pixel",
2760                                               "core",
2761                                               "iface",
2762                                               "bus";
2763
2764                                 phys = <&dsi1_phy>;
2765                                 phy-names = "dsi";
2766
2767                                 status = "disabled";
2768
2769                                 ports {
2770                                         #address-cells = <1>;
2771                                         #size-cells = <0>;
2772
2773                                         port@0 {
2774                                                 reg = <0>;
2775                                                 dsi1_in: endpoint {
2776                                                         remote-endpoint = <&dpu_intf2_out>;
2777                                                 };
2778                                         };
2779
2780                                         port@1 {
2781                                                 reg = <1>;
2782                                                 dsi1_out: endpoint {
2783                                                 };
2784                                         };
2785                                 };
2786                         };
2787
2788                         dsi1_phy: dsi-phy@ae96400 {
2789                                 compatible = "qcom,dsi-phy-10nm";
2790                                 reg = <0 0x0ae96400 0 0x200>,
2791                                       <0 0x0ae96600 0 0x280>,
2792                                       <0 0x0ae96a00 0 0x10e>;
2793                                 reg-names = "dsi_phy",
2794                                             "dsi_phy_lane",
2795                                             "dsi_pll";
2796
2797                                 #clock-cells = <1>;
2798                                 #phy-cells = <0>;
2799
2800                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2801                                          <&rpmhcc RPMH_CXO_CLK>;
2802                                 clock-names = "iface", "ref";
2803
2804                                 status = "disabled";
2805                         };
2806                 };
2807
2808                 gpu@5000000 {
2809                         compatible = "qcom,adreno-630.2", "qcom,adreno";
2810                         #stream-id-cells = <16>;
2811
2812                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
2813                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
2814
2815                         /*
2816                          * Look ma, no clocks! The GPU clocks and power are
2817                          * controlled entirely by the GMU
2818                          */
2819
2820                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2821
2822                         iommus = <&adreno_smmu 0>;
2823
2824                         operating-points-v2 = <&gpu_opp_table>;
2825
2826                         qcom,gmu = <&gmu>;
2827
2828                         zap_shader: zap-shader {
2829                                 memory-region = <&gpu_mem>;
2830                         };
2831
2832                         gpu_opp_table: opp-table {
2833                                 compatible = "operating-points-v2";
2834
2835                                 opp-710000000 {
2836                                         opp-hz = /bits/ 64 <710000000>;
2837                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2838                                 };
2839
2840                                 opp-675000000 {
2841                                         opp-hz = /bits/ 64 <675000000>;
2842                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2843                                 };
2844
2845                                 opp-596000000 {
2846                                         opp-hz = /bits/ 64 <596000000>;
2847                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2848                                 };
2849
2850                                 opp-520000000 {
2851                                         opp-hz = /bits/ 64 <520000000>;
2852                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2853                                 };
2854
2855                                 opp-414000000 {
2856                                         opp-hz = /bits/ 64 <414000000>;
2857                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2858                                 };
2859
2860                                 opp-342000000 {
2861                                         opp-hz = /bits/ 64 <342000000>;
2862                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2863                                 };
2864
2865                                 opp-257000000 {
2866                                         opp-hz = /bits/ 64 <257000000>;
2867                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2868                                 };
2869                         };
2870                 };
2871
2872                 adreno_smmu: iommu@5040000 {
2873                         compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
2874                         reg = <0 0x5040000 0 0x10000>;
2875                         #iommu-cells = <1>;
2876                         #global-interrupts = <2>;
2877                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2878                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2879                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2880                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2881                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2882                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2883                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2884                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2885                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2886                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2887                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2888                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
2889                         clock-names = "bus", "iface";
2890
2891                         power-domains = <&gpucc GPU_CX_GDSC>;
2892                 };
2893
2894                 gmu: gmu@506a000 {
2895                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
2896
2897                         reg = <0 0x506a000 0 0x30000>,
2898                               <0 0xb280000 0 0x10000>,
2899                               <0 0xb480000 0 0x10000>;
2900                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2901
2902                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2903                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2904                         interrupt-names = "hfi", "gmu";
2905
2906                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2907                                  <&gpucc GPU_CC_CXO_CLK>,
2908                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2909                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2910                         clock-names = "gmu", "cxo", "axi", "memnoc";
2911
2912                         power-domains = <&gpucc GPU_CX_GDSC>,
2913                                         <&gpucc GPU_GX_GDSC>;
2914                         power-domain-names = "cx", "gx";
2915
2916                         iommus = <&adreno_smmu 5>;
2917
2918                         operating-points-v2 = <&gmu_opp_table>;
2919
2920                         gmu_opp_table: opp-table {
2921                                 compatible = "operating-points-v2";
2922
2923                                 opp-400000000 {
2924                                         opp-hz = /bits/ 64 <400000000>;
2925                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2926                                 };
2927
2928                                 opp-200000000 {
2929                                         opp-hz = /bits/ 64 <200000000>;
2930                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2931                                 };
2932                         };
2933                 };
2934
2935                 dispcc: clock-controller@af00000 {
2936                         compatible = "qcom,sdm845-dispcc";
2937                         reg = <0 0x0af00000 0 0x10000>;
2938                         #clock-cells = <1>;
2939                         #reset-cells = <1>;
2940                         #power-domain-cells = <1>;
2941                 };
2942
2943                 pdc_intc: interrupt-controller@b220000 {
2944                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
2945                         reg = <0 0x0b220000 0 0x30000>;
2946                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
2947                         #interrupt-cells = <2>;
2948                         interrupt-parent = <&intc>;
2949                         interrupt-controller;
2950                 };
2951
2952                 pdc_reset: reset-controller@b2e0000 {
2953                         compatible = "qcom,sdm845-pdc-global";
2954                         reg = <0 0x0b2e0000 0 0x20000>;
2955                         #reset-cells = <1>;
2956                 };
2957
2958                 tsens0: thermal-sensor@c263000 {
2959                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2960                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
2961                               <0 0x0c222000 0 0x1ff>; /* SROT */
2962                         #qcom,sensors = <13>;
2963                         #thermal-sensor-cells = <1>;
2964                 };
2965
2966                 tsens1: thermal-sensor@c265000 {
2967                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
2968                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
2969                               <0 0x0c223000 0 0x1ff>; /* SROT */
2970                         #qcom,sensors = <8>;
2971                         #thermal-sensor-cells = <1>;
2972                 };
2973
2974                 aoss_reset: reset-controller@c2a0000 {
2975                         compatible = "qcom,sdm845-aoss-cc";
2976                         reg = <0 0x0c2a0000 0 0x31000>;
2977                         #reset-cells = <1>;
2978                 };
2979
2980                 aoss_qmp: qmp@c300000 {
2981                         compatible = "qcom,sdm845-aoss-qmp";
2982                         reg = <0 0x0c300000 0 0x100000>;
2983                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
2984                         mboxes = <&apss_shared 0>;
2985
2986                         #clock-cells = <0>;
2987                         #power-domain-cells = <1>;
2988
2989                         cx_cdev: cx {
2990                                 #cooling-cells = <2>;
2991                         };
2992
2993                         ebi_cdev: ebi {
2994                                 #cooling-cells = <2>;
2995                         };
2996                 };
2997
2998                 spmi_bus: spmi@c440000 {
2999                         compatible = "qcom,spmi-pmic-arb";
3000                         reg = <0 0x0c440000 0 0x1100>,
3001                               <0 0x0c600000 0 0x2000000>,
3002                               <0 0x0e600000 0 0x100000>,
3003                               <0 0x0e700000 0 0xa0000>,
3004                               <0 0x0c40a000 0 0x26000>;
3005                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3006                         interrupt-names = "periph_irq";
3007                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3008                         qcom,ee = <0>;
3009                         qcom,channel = <0>;
3010                         #address-cells = <2>;
3011                         #size-cells = <0>;
3012                         interrupt-controller;
3013                         #interrupt-cells = <4>;
3014                         cell-index = <0>;
3015                 };
3016
3017                 apps_smmu: iommu@15000000 {
3018                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
3019                         reg = <0 0x15000000 0 0x80000>;
3020                         #iommu-cells = <2>;
3021                         #global-interrupts = <1>;
3022                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3023                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3024                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3025                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3026                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3027                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3028                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3029                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3030                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3031                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3032                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3033                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3034                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3035                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3036                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3037                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3038                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3039                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3040                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3041                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3042                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3043                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3044                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3045                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3046                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3047                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3048                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3049                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3050                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3051                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3052                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3053                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3054                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3055                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3056                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3057                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3058                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3059                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3060                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3061                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3062                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3063                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3064                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3065                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3066                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3067                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3068                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3069                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3070                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3071                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3072                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3073                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3074                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3075                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3076                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3077                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3078                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3079                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3080                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3081                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3082                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3083                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3084                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3085                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3086                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
3087                 };
3088
3089                 lpasscc: clock-controller@17014000 {
3090                         compatible = "qcom,sdm845-lpasscc";
3091                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
3092                         reg-names = "cc", "qdsp6ss";
3093                         #clock-cells = <1>;
3094                         status = "disabled";
3095                 };
3096
3097                 apss_shared: mailbox@17990000 {
3098                         compatible = "qcom,sdm845-apss-shared";
3099                         reg = <0 0x17990000 0 0x1000>;
3100                         #mbox-cells = <1>;
3101                 };
3102
3103                 apps_rsc: rsc@179c0000 {
3104                         label = "apps_rsc";
3105                         compatible = "qcom,rpmh-rsc";
3106                         reg = <0 0x179c0000 0 0x10000>,
3107                               <0 0x179d0000 0 0x10000>,
3108                               <0 0x179e0000 0 0x10000>;
3109                         reg-names = "drv-0", "drv-1", "drv-2";
3110                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3111                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3112                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3113                         qcom,tcs-offset = <0xd00>;
3114                         qcom,drv-id = <2>;
3115                         qcom,tcs-config = <ACTIVE_TCS  2>,
3116                                           <SLEEP_TCS   3>,
3117                                           <WAKE_TCS    3>,
3118                                           <CONTROL_TCS 1>;
3119
3120                         rpmhcc: clock-controller {
3121                                 compatible = "qcom,sdm845-rpmh-clk";
3122                                 #clock-cells = <1>;
3123                                 clock-names = "xo";
3124                                 clocks = <&xo_board>;
3125                         };
3126
3127                         rpmhpd: power-controller {
3128                                 compatible = "qcom,sdm845-rpmhpd";
3129                                 #power-domain-cells = <1>;
3130                                 operating-points-v2 = <&rpmhpd_opp_table>;
3131
3132                                 rpmhpd_opp_table: opp-table {
3133                                         compatible = "operating-points-v2";
3134
3135                                         rpmhpd_opp_ret: opp1 {
3136                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3137                                         };
3138
3139                                         rpmhpd_opp_min_svs: opp2 {
3140                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3141                                         };
3142
3143                                         rpmhpd_opp_low_svs: opp3 {
3144                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3145                                         };
3146
3147                                         rpmhpd_opp_svs: opp4 {
3148                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3149                                         };
3150
3151                                         rpmhpd_opp_svs_l1: opp5 {
3152                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3153                                         };
3154
3155                                         rpmhpd_opp_nom: opp6 {
3156                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3157                                         };
3158
3159                                         rpmhpd_opp_nom_l1: opp7 {
3160                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3161                                         };
3162
3163                                         rpmhpd_opp_nom_l2: opp8 {
3164                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3165                                         };
3166
3167                                         rpmhpd_opp_turbo: opp9 {
3168                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3169                                         };
3170
3171                                         rpmhpd_opp_turbo_l1: opp10 {
3172                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3173                                         };
3174                                 };
3175                         };
3176
3177                         rsc_hlos: interconnect {
3178                                 compatible = "qcom,sdm845-rsc-hlos";
3179                                 #interconnect-cells = <1>;
3180                         };
3181                 };
3182
3183                 intc: interrupt-controller@17a00000 {
3184                         compatible = "arm,gic-v3";
3185                         #address-cells = <2>;
3186                         #size-cells = <2>;
3187                         ranges;
3188                         #interrupt-cells = <3>;
3189                         interrupt-controller;
3190                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3191                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3192                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3193
3194                         gic-its@17a40000 {
3195                                 compatible = "arm,gic-v3-its";
3196                                 msi-controller;
3197                                 #msi-cells = <1>;
3198                                 reg = <0 0x17a40000 0 0x20000>;
3199                                 status = "disabled";
3200                         };
3201                 };
3202
3203                 timer@17c90000 {
3204                         #address-cells = <2>;
3205                         #size-cells = <2>;
3206                         ranges;
3207                         compatible = "arm,armv7-timer-mem";
3208                         reg = <0 0x17c90000 0 0x1000>;
3209
3210                         frame@17ca0000 {
3211                                 frame-number = <0>;
3212                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
3213                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3214                                 reg = <0 0x17ca0000 0 0x1000>,
3215                                       <0 0x17cb0000 0 0x1000>;
3216                         };
3217
3218                         frame@17cc0000 {
3219                                 frame-number = <1>;
3220                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
3221                                 reg = <0 0x17cc0000 0 0x1000>;
3222                                 status = "disabled";
3223                         };
3224
3225                         frame@17cd0000 {
3226                                 frame-number = <2>;
3227                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228                                 reg = <0 0x17cd0000 0 0x1000>;
3229                                 status = "disabled";
3230                         };
3231
3232                         frame@17ce0000 {
3233                                 frame-number = <3>;
3234                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3235                                 reg = <0 0x17ce0000 0 0x1000>;
3236                                 status = "disabled";
3237                         };
3238
3239                         frame@17cf0000 {
3240                                 frame-number = <4>;
3241                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3242                                 reg = <0 0x17cf0000 0 0x1000>;
3243                                 status = "disabled";
3244                         };
3245
3246                         frame@17d00000 {
3247                                 frame-number = <5>;
3248                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3249                                 reg = <0 0x17d00000 0 0x1000>;
3250                                 status = "disabled";
3251                         };
3252
3253                         frame@17d10000 {
3254                                 frame-number = <6>;
3255                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3256                                 reg = <0 0x17d10000 0 0x1000>;
3257                                 status = "disabled";
3258                         };
3259                 };
3260
3261                 cpufreq_hw: cpufreq@17d43000 {
3262                         compatible = "qcom,cpufreq-hw";
3263                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
3264                         reg-names = "freq-domain0", "freq-domain1";
3265
3266                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3267                         clock-names = "xo", "alternate";
3268
3269                         #freq-domain-cells = <1>;
3270                 };
3271
3272                 wifi: wifi@18800000 {
3273                         compatible = "qcom,wcn3990-wifi";
3274                         status = "disabled";
3275                         reg = <0 0x18800000 0 0x800000>;
3276                         reg-names = "membase";
3277                         memory-region = <&wlan_msa_mem>;
3278                         clock-names = "cxo_ref_clk_pin";
3279                         clocks = <&rpmhcc RPMH_RF_CLK2>;
3280                         interrupts =
3281                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3282                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3283                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3284                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3285                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3286                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3287                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3288                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3289                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3290                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3291                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3292                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3293                         iommus = <&apps_smmu 0x0040 0x1>;
3294                 };
3295         };
3296
3297         thermal-zones {
3298                 cpu0-thermal {
3299                         polling-delay-passive = <250>;
3300                         polling-delay = <1000>;
3301
3302                         thermal-sensors = <&tsens0 1>;
3303
3304                         trips {
3305                                 cpu0_alert0: trip-point0 {
3306                                         temperature = <90000>;
3307                                         hysteresis = <2000>;
3308                                         type = "passive";
3309                                 };
3310
3311                                 cpu0_alert1: trip-point1 {
3312                                         temperature = <95000>;
3313                                         hysteresis = <2000>;
3314                                         type = "passive";
3315                                 };
3316
3317                                 cpu0_crit: cpu_crit {
3318                                         temperature = <110000>;
3319                                         hysteresis = <1000>;
3320                                         type = "critical";
3321                                 };
3322                         };
3323
3324                         cooling-maps {
3325                                 map0 {
3326                                         trip = <&cpu0_alert0>;
3327                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3328                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3329                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3330                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3331                                 };
3332                                 map1 {
3333                                         trip = <&cpu0_alert1>;
3334                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3335                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3336                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3337                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3338                                 };
3339                         };
3340                 };
3341
3342                 cpu1-thermal {
3343                         polling-delay-passive = <250>;
3344                         polling-delay = <1000>;
3345
3346                         thermal-sensors = <&tsens0 2>;
3347
3348                         trips {
3349                                 cpu1_alert0: trip-point0 {
3350                                         temperature = <90000>;
3351                                         hysteresis = <2000>;
3352                                         type = "passive";
3353                                 };
3354
3355                                 cpu1_alert1: trip-point1 {
3356                                         temperature = <95000>;
3357                                         hysteresis = <2000>;
3358                                         type = "passive";
3359                                 };
3360
3361                                 cpu1_crit: cpu_crit {
3362                                         temperature = <110000>;
3363                                         hysteresis = <1000>;
3364                                         type = "critical";
3365                                 };
3366                         };
3367
3368                         cooling-maps {
3369                                 map0 {
3370                                         trip = <&cpu1_alert0>;
3371                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3372                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3373                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3374                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3375                                 };
3376                                 map1 {
3377                                         trip = <&cpu1_alert1>;
3378                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3379                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3380                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3381                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3382                                 };
3383                         };
3384                 };
3385
3386                 cpu2-thermal {
3387                         polling-delay-passive = <250>;
3388                         polling-delay = <1000>;
3389
3390                         thermal-sensors = <&tsens0 3>;
3391
3392                         trips {
3393                                 cpu2_alert0: trip-point0 {
3394                                         temperature = <90000>;
3395                                         hysteresis = <2000>;
3396                                         type = "passive";
3397                                 };
3398
3399                                 cpu2_alert1: trip-point1 {
3400                                         temperature = <95000>;
3401                                         hysteresis = <2000>;
3402                                         type = "passive";
3403                                 };
3404
3405                                 cpu2_crit: cpu_crit {
3406                                         temperature = <110000>;
3407                                         hysteresis = <1000>;
3408                                         type = "critical";
3409                                 };
3410                         };
3411
3412                         cooling-maps {
3413                                 map0 {
3414                                         trip = <&cpu2_alert0>;
3415                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3416                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3417                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3418                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3419                                 };
3420                                 map1 {
3421                                         trip = <&cpu2_alert1>;
3422                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3423                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3424                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3425                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3426                                 };
3427                         };
3428                 };
3429
3430                 cpu3-thermal {
3431                         polling-delay-passive = <250>;
3432                         polling-delay = <1000>;
3433
3434                         thermal-sensors = <&tsens0 4>;
3435
3436                         trips {
3437                                 cpu3_alert0: trip-point0 {
3438                                         temperature = <90000>;
3439                                         hysteresis = <2000>;
3440                                         type = "passive";
3441                                 };
3442
3443                                 cpu3_alert1: trip-point1 {
3444                                         temperature = <95000>;
3445                                         hysteresis = <2000>;
3446                                         type = "passive";
3447                                 };
3448
3449                                 cpu3_crit: cpu_crit {
3450                                         temperature = <110000>;
3451                                         hysteresis = <1000>;
3452                                         type = "critical";
3453                                 };
3454                         };
3455
3456                         cooling-maps {
3457                                 map0 {
3458                                         trip = <&cpu3_alert0>;
3459                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3460                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3461                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3462                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3463                                 };
3464                                 map1 {
3465                                         trip = <&cpu3_alert1>;
3466                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3467                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3468                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3469                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3470                                 };
3471                         };
3472                 };
3473
3474                 cpu4-thermal {
3475                         polling-delay-passive = <250>;
3476                         polling-delay = <1000>;
3477
3478                         thermal-sensors = <&tsens0 7>;
3479
3480                         trips {
3481                                 cpu4_alert0: trip-point0 {
3482                                         temperature = <90000>;
3483                                         hysteresis = <2000>;
3484                                         type = "passive";
3485                                 };
3486
3487                                 cpu4_alert1: trip-point1 {
3488                                         temperature = <95000>;
3489                                         hysteresis = <2000>;
3490                                         type = "passive";
3491                                 };
3492
3493                                 cpu4_crit: cpu_crit {
3494                                         temperature = <110000>;
3495                                         hysteresis = <1000>;
3496                                         type = "critical";
3497                                 };
3498                         };
3499
3500                         cooling-maps {
3501                                 map0 {
3502                                         trip = <&cpu4_alert0>;
3503                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3504                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3505                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3506                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3507                                 };
3508                                 map1 {
3509                                         trip = <&cpu4_alert1>;
3510                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3511                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3512                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3513                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3514                                 };
3515                         };
3516                 };
3517
3518                 cpu5-thermal {
3519                         polling-delay-passive = <250>;
3520                         polling-delay = <1000>;
3521
3522                         thermal-sensors = <&tsens0 8>;
3523
3524                         trips {
3525                                 cpu5_alert0: trip-point0 {
3526                                         temperature = <90000>;
3527                                         hysteresis = <2000>;
3528                                         type = "passive";
3529                                 };
3530
3531                                 cpu5_alert1: trip-point1 {
3532                                         temperature = <95000>;
3533                                         hysteresis = <2000>;
3534                                         type = "passive";
3535                                 };
3536
3537                                 cpu5_crit: cpu_crit {
3538                                         temperature = <110000>;
3539                                         hysteresis = <1000>;
3540                                         type = "critical";
3541                                 };
3542                         };
3543
3544                         cooling-maps {
3545                                 map0 {
3546                                         trip = <&cpu5_alert0>;
3547                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3548                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3549                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3550                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3551                                 };
3552                                 map1 {
3553                                         trip = <&cpu5_alert1>;
3554                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3555                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3556                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3557                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3558                                 };
3559                         };
3560                 };
3561
3562                 cpu6-thermal {
3563                         polling-delay-passive = <250>;
3564                         polling-delay = <1000>;
3565
3566                         thermal-sensors = <&tsens0 9>;
3567
3568                         trips {
3569                                 cpu6_alert0: trip-point0 {
3570                                         temperature = <90000>;
3571                                         hysteresis = <2000>;
3572                                         type = "passive";
3573                                 };
3574
3575                                 cpu6_alert1: trip-point1 {
3576                                         temperature = <95000>;
3577                                         hysteresis = <2000>;
3578                                         type = "passive";
3579                                 };
3580
3581                                 cpu6_crit: cpu_crit {
3582                                         temperature = <110000>;
3583                                         hysteresis = <1000>;
3584                                         type = "critical";
3585                                 };
3586                         };
3587
3588                         cooling-maps {
3589                                 map0 {
3590                                         trip = <&cpu6_alert0>;
3591                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3592                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3593                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3594                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3595                                 };
3596                                 map1 {
3597                                         trip = <&cpu6_alert1>;
3598                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3599                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3600                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3601                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3602                                 };
3603                         };
3604                 };
3605
3606                 cpu7-thermal {
3607                         polling-delay-passive = <250>;
3608                         polling-delay = <1000>;
3609
3610                         thermal-sensors = <&tsens0 10>;
3611
3612                         trips {
3613                                 cpu7_alert0: trip-point0 {
3614                                         temperature = <90000>;
3615                                         hysteresis = <2000>;
3616                                         type = "passive";
3617                                 };
3618
3619                                 cpu7_alert1: trip-point1 {
3620                                         temperature = <95000>;
3621                                         hysteresis = <2000>;
3622                                         type = "passive";
3623                                 };
3624
3625                                 cpu7_crit: cpu_crit {
3626                                         temperature = <110000>;
3627                                         hysteresis = <1000>;
3628                                         type = "critical";
3629                                 };
3630                         };
3631
3632                         cooling-maps {
3633                                 map0 {
3634                                         trip = <&cpu7_alert0>;
3635                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3636                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3637                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3638                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3639                                 };
3640                                 map1 {
3641                                         trip = <&cpu7_alert1>;
3642                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3643                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3644                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3646                                 };
3647                         };
3648                 };
3649
3650                 aoss0-thermal {
3651                         polling-delay-passive = <250>;
3652                         polling-delay = <1000>;
3653
3654                         thermal-sensors = <&tsens0 0>;
3655
3656                         trips {
3657                                 aoss0_alert0: trip-point0 {
3658                                         temperature = <90000>;
3659                                         hysteresis = <2000>;
3660                                         type = "hot";
3661                                 };
3662                         };
3663                 };
3664
3665                 cluster0-thermal {
3666                         polling-delay-passive = <250>;
3667                         polling-delay = <1000>;
3668
3669                         thermal-sensors = <&tsens0 5>;
3670
3671                         trips {
3672                                 cluster0_alert0: trip-point0 {
3673                                         temperature = <90000>;
3674                                         hysteresis = <2000>;
3675                                         type = "hot";
3676                                 };
3677                                 cluster0_crit: cluster0_crit {
3678                                         temperature = <110000>;
3679                                         hysteresis = <2000>;
3680                                         type = "critical";
3681                                 };
3682                         };
3683                 };
3684
3685                 cluster1-thermal {
3686                         polling-delay-passive = <250>;
3687                         polling-delay = <1000>;
3688
3689                         thermal-sensors = <&tsens0 6>;
3690
3691                         trips {
3692                                 cluster1_alert0: trip-point0 {
3693                                         temperature = <90000>;
3694                                         hysteresis = <2000>;
3695                                         type = "hot";
3696                                 };
3697                                 cluster1_crit: cluster1_crit {
3698                                         temperature = <110000>;
3699                                         hysteresis = <2000>;
3700                                         type = "critical";
3701                                 };
3702                         };
3703                 };
3704
3705                 gpu-thermal-top {
3706                         polling-delay-passive = <250>;
3707                         polling-delay = <1000>;
3708
3709                         thermal-sensors = <&tsens0 11>;
3710
3711                         trips {
3712                                 gpu1_alert0: trip-point0 {
3713                                         temperature = <90000>;
3714                                         hysteresis = <2000>;
3715                                         type = "hot";
3716                                 };
3717                         };
3718                 };
3719
3720                 gpu-thermal-bottom {
3721                         polling-delay-passive = <250>;
3722                         polling-delay = <1000>;
3723
3724                         thermal-sensors = <&tsens0 12>;
3725
3726                         trips {
3727                                 gpu2_alert0: trip-point0 {
3728                                         temperature = <90000>;
3729                                         hysteresis = <2000>;
3730                                         type = "hot";
3731                                 };
3732                         };
3733                 };
3734
3735                 aoss1-thermal {
3736                         polling-delay-passive = <250>;
3737                         polling-delay = <1000>;
3738
3739                         thermal-sensors = <&tsens1 0>;
3740
3741                         trips {
3742                                 aoss1_alert0: trip-point0 {
3743                                         temperature = <90000>;
3744                                         hysteresis = <2000>;
3745                                         type = "hot";
3746                                 };
3747                         };
3748                 };
3749
3750                 q6-modem-thermal {
3751                         polling-delay-passive = <250>;
3752                         polling-delay = <1000>;
3753
3754                         thermal-sensors = <&tsens1 1>;
3755
3756                         trips {
3757                                 q6_modem_alert0: trip-point0 {
3758                                         temperature = <90000>;
3759                                         hysteresis = <2000>;
3760                                         type = "hot";
3761                                 };
3762                         };
3763                 };
3764
3765                 mem-thermal {
3766                         polling-delay-passive = <250>;
3767                         polling-delay = <1000>;
3768
3769                         thermal-sensors = <&tsens1 2>;
3770
3771                         trips {
3772                                 mem_alert0: trip-point0 {
3773                                         temperature = <90000>;
3774                                         hysteresis = <2000>;
3775                                         type = "hot";
3776                                 };
3777                         };
3778                 };
3779
3780                 wlan-thermal {
3781                         polling-delay-passive = <250>;
3782                         polling-delay = <1000>;
3783
3784                         thermal-sensors = <&tsens1 3>;
3785
3786                         trips {
3787                                 wlan_alert0: trip-point0 {
3788                                         temperature = <90000>;
3789                                         hysteresis = <2000>;
3790                                         type = "hot";
3791                                 };
3792                         };
3793                 };
3794
3795                 q6-hvx-thermal {
3796                         polling-delay-passive = <250>;
3797                         polling-delay = <1000>;
3798
3799                         thermal-sensors = <&tsens1 4>;
3800
3801                         trips {
3802                                 q6_hvx_alert0: trip-point0 {
3803                                         temperature = <90000>;
3804                                         hysteresis = <2000>;
3805                                         type = "hot";
3806                                 };
3807                         };
3808                 };
3809
3810                 camera-thermal {
3811                         polling-delay-passive = <250>;
3812                         polling-delay = <1000>;
3813
3814                         thermal-sensors = <&tsens1 5>;
3815
3816                         trips {
3817                                 camera_alert0: trip-point0 {
3818                                         temperature = <90000>;
3819                                         hysteresis = <2000>;
3820                                         type = "hot";
3821                                 };
3822                         };
3823                 };
3824
3825                 video-thermal {
3826                         polling-delay-passive = <250>;
3827                         polling-delay = <1000>;
3828
3829                         thermal-sensors = <&tsens1 6>;
3830
3831                         trips {
3832                                 video_alert0: trip-point0 {
3833                                         temperature = <90000>;
3834                                         hysteresis = <2000>;
3835                                         type = "hot";
3836                                 };
3837                         };
3838                 };
3839
3840                 modem-thermal {
3841                         polling-delay-passive = <250>;
3842                         polling-delay = <1000>;
3843
3844                         thermal-sensors = <&tsens1 7>;
3845
3846                         trips {
3847                                 modem_alert0: trip-point0 {
3848                                         temperature = <90000>;
3849                                         hysteresis = <2000>;
3850                                         type = "hot";
3851                                 };
3852                         };
3853                 };
3854         };
3855 };