arch/arm64/boot/dts/qcom/sdm845.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SDM845 SoC device tree source
   4  *
   5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
   9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
  10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
  12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
  15 #include <dt-bindings/dma/qcom-gpi.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  18 #include <dt-bindings/interconnect/qcom,sdm845.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,apr.h>
  25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  27 #include <dt-bindings/thermal/thermal.h>
  28
  29 / {
  30         interrupt-parent = <&intc>;
  31
  32         #address-cells = <2>;
  33         #size-cells = <2>;
  34
  35         aliases {
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 i2c12 = &i2c12;
  49                 i2c13 = &i2c13;
  50                 i2c14 = &i2c14;
  51                 i2c15 = &i2c15;
  52                 spi0 = &spi0;
  53                 spi1 = &spi1;
  54                 spi2 = &spi2;
  55                 spi3 = &spi3;
  56                 spi4 = &spi4;
  57                 spi5 = &spi5;
  58                 spi6 = &spi6;
  59                 spi7 = &spi7;
  60                 spi8 = &spi8;
  61                 spi9 = &spi9;
  62                 spi10 = &spi10;
  63                 spi11 = &spi11;
  64                 spi12 = &spi12;
  65                 spi13 = &spi13;
  66                 spi14 = &spi14;
  67                 spi15 = &spi15;
  68         };
  69
  70         chosen { };
  71
  72         memory@80000000 {
  73                 device_type = "memory";
  74                 /* We expect the bootloader to fill in the size */
  75                 reg = <0 0x80000000 0 0>;
  76         };
  77
  78         reserved-memory {
  79                 #address-cells = <2>;
  80                 #size-cells = <2>;
  81                 ranges;
  82
  83                 hyp_mem: hyp-mem@85700000 {
  84                         reg = <0 0x85700000 0 0x600000>;
  85                         no-map;
  86                 };
  87
  88                 xbl_mem: xbl-mem@85e00000 {
  89                         reg = <0 0x85e00000 0 0x100000>;
  90                         no-map;
  91                 };
  92
  93                 aop_mem: aop-mem@85fc0000 {
  94                         reg = <0 0x85fc0000 0 0x20000>;
  95                         no-map;
  96                 };
  97
  98                 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
  99                         compatible = "qcom,cmd-db";
 100                         reg = <0x0 0x85fe0000 0 0x20000>;
 101                         no-map;
 102                 };
 103
 104                 smem@86000000 {
 105                         compatible = "qcom,smem";
 106                         reg = <0x0 0x86000000 0 0x200000>;
 107                         no-map;
 108                         hwlocks = <&tcsr_mutex 3>;
 109                 };
 110
 111                 tz_mem: tz@86200000 {
 112                         reg = <0 0x86200000 0 0x2d00000>;
 113                         no-map;
 114                 };
 115
 116                 rmtfs_mem: rmtfs@88f00000 {
 117                         compatible = "qcom,rmtfs-mem";
 118                         reg = <0 0x88f00000 0 0x200000>;
 119                         no-map;
 120
 121                         qcom,client-id = <1>;
 122                         qcom,vmid = <15>;
 123                 };
 124
 125                 qseecom_mem: qseecom@8ab00000 {
 126                         reg = <0 0x8ab00000 0 0x1400000>;
 127                         no-map;
 128                 };
 129
 130                 camera_mem: camera-mem@8bf00000 {
 131                         reg = <0 0x8bf00000 0 0x500000>;
 132                         no-map;
 133                 };
 134
 135                 ipa_fw_mem: ipa-fw@8c400000 {
 136                         reg = <0 0x8c400000 0 0x10000>;
 137                         no-map;
 138                 };
 139
 140                 ipa_gsi_mem: ipa-gsi@8c410000 {
 141                         reg = <0 0x8c410000 0 0x5000>;
 142                         no-map;
 143                 };
 144
 145                 gpu_mem: gpu@8c415000 {
 146                         reg = <0 0x8c415000 0 0x2000>;
 147                         no-map;
 148                 };
 149
 150                 adsp_mem: adsp@8c500000 {
 151                         reg = <0 0x8c500000 0 0x1a00000>;
 152                         no-map;
 153                 };
 154
 155                 wlan_msa_mem: wlan-msa@8df00000 {
 156                         reg = <0 0x8df00000 0 0x100000>;
 157                         no-map;
 158                 };
 159
 160                 mpss_region: mpss@8e000000 {
 161                         reg = <0 0x8e000000 0 0x7800000>;
 162                         no-map;
 163                 };
 164
 165                 venus_mem: venus@95800000 {
 166                         reg = <0 0x95800000 0 0x500000>;
 167                         no-map;
 168                 };
 169
 170                 cdsp_mem: cdsp@95d00000 {
 171                         reg = <0 0x95d00000 0 0x800000>;
 172                         no-map;
 173                 };
 174
 175                 mba_region: mba@96500000 {
 176                         reg = <0 0x96500000 0 0x200000>;
 177                         no-map;
 178                 };
 179
 180                 slpi_mem: slpi@96700000 {
 181                         reg = <0 0x96700000 0 0x1400000>;
 182                         no-map;
 183                 };
 184
 185                 spss_mem: spss@97b00000 {
 186                         reg = <0 0x97b00000 0 0x100000>;
 187                         no-map;
 188                 };
 189         };
 190
 191         cpus: cpus {
 192                 #address-cells = <2>;
 193                 #size-cells = <0>;
 194
 195                 CPU0: cpu@0 {
 196                         device_type = "cpu";
 197                         compatible = "qcom,kryo385";
 198                         reg = <0x0 0x0>;
 199                         enable-method = "psci";
 200                         capacity-dmips-mhz = <611>;
 201                         dynamic-power-coefficient = <154>;
 202                         qcom,freq-domain = <&cpufreq_hw 0>;
 203                         operating-points-v2 = <&cpu0_opp_table>;
 204                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 205                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 206                         power-domains = <&CPU_PD0>;
 207                         power-domain-names = "psci";
 208                         #cooling-cells = <2>;
 209                         next-level-cache = <&L2_0>;
 210                         L2_0: l2-cache {
 211                                 compatible = "cache";
 212                                 next-level-cache = <&L3_0>;
 213                                 L3_0: l3-cache {
 214                                       compatible = "cache";
 215                                 };
 216                         };
 217                 };
 218
 219                 CPU1: cpu@100 {
 220                         device_type = "cpu";
 221                         compatible = "qcom,kryo385";
 222                         reg = <0x0 0x100>;
 223                         enable-method = "psci";
 224                         capacity-dmips-mhz = <611>;
 225                         dynamic-power-coefficient = <154>;
 226                         qcom,freq-domain = <&cpufreq_hw 0>;
 227                         operating-points-v2 = <&cpu0_opp_table>;
 228                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 229                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 230                         power-domains = <&CPU_PD1>;
 231                         power-domain-names = "psci";
 232                         #cooling-cells = <2>;
 233                         next-level-cache = <&L2_100>;
 234                         L2_100: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 CPU2: cpu@200 {
 241                         device_type = "cpu";
 242                         compatible = "qcom,kryo385";
 243                         reg = <0x0 0x200>;
 244                         enable-method = "psci";
 245                         capacity-dmips-mhz = <611>;
 246                         dynamic-power-coefficient = <154>;
 247                         qcom,freq-domain = <&cpufreq_hw 0>;
 248                         operating-points-v2 = <&cpu0_opp_table>;
 249                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 250                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 251                         power-domains = <&CPU_PD2>;
 252                         power-domain-names = "psci";
 253                         #cooling-cells = <2>;
 254                         next-level-cache = <&L2_200>;
 255                         L2_200: l2-cache {
 256                                 compatible = "cache";
 257                                 next-level-cache = <&L3_0>;
 258                         };
 259                 };
 260
 261                 CPU3: cpu@300 {
 262                         device_type = "cpu";
 263                         compatible = "qcom,kryo385";
 264                         reg = <0x0 0x300>;
 265                         enable-method = "psci";
 266                         capacity-dmips-mhz = <611>;
 267                         dynamic-power-coefficient = <154>;
 268                         qcom,freq-domain = <&cpufreq_hw 0>;
 269                         operating-points-v2 = <&cpu0_opp_table>;
 270                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 271                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 272                         #cooling-cells = <2>;
 273                         power-domains = <&CPU_PD3>;
 274                         power-domain-names = "psci";
 275                         next-level-cache = <&L2_300>;
 276                         L2_300: l2-cache {
 277                                 compatible = "cache";
 278                                 next-level-cache = <&L3_0>;
 279                         };
 280                 };
 281
 282                 CPU4: cpu@400 {
 283                         device_type = "cpu";
 284                         compatible = "qcom,kryo385";
 285                         reg = <0x0 0x400>;
 286                         enable-method = "psci";
 287                         capacity-dmips-mhz = <1024>;
 288                         dynamic-power-coefficient = <442>;
 289                         qcom,freq-domain = <&cpufreq_hw 1>;
 290                         operating-points-v2 = <&cpu4_opp_table>;
 291                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 292                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 293                         power-domains = <&CPU_PD4>;
 294                         power-domain-names = "psci";
 295                         #cooling-cells = <2>;
 296                         next-level-cache = <&L2_400>;
 297                         L2_400: l2-cache {
 298                                 compatible = "cache";
 299                                 next-level-cache = <&L3_0>;
 300                         };
 301                 };
 302
 303                 CPU5: cpu@500 {
 304                         device_type = "cpu";
 305                         compatible = "qcom,kryo385";
 306                         reg = <0x0 0x500>;
 307                         enable-method = "psci";
 308                         capacity-dmips-mhz = <1024>;
 309                         dynamic-power-coefficient = <442>;
 310                         qcom,freq-domain = <&cpufreq_hw 1>;
 311                         operating-points-v2 = <&cpu4_opp_table>;
 312                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 313                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 314                         power-domains = <&CPU_PD5>;
 315                         power-domain-names = "psci";
 316                         #cooling-cells = <2>;
 317                         next-level-cache = <&L2_500>;
 318                         L2_500: l2-cache {
 319                                 compatible = "cache";
 320                                 next-level-cache = <&L3_0>;
 321                         };
 322                 };
 323
 324                 CPU6: cpu@600 {
 325                         device_type = "cpu";
 326                         compatible = "qcom,kryo385";
 327                         reg = <0x0 0x600>;
 328                         enable-method = "psci";
 329                         capacity-dmips-mhz = <1024>;
 330                         dynamic-power-coefficient = <442>;
 331                         qcom,freq-domain = <&cpufreq_hw 1>;
 332                         operating-points-v2 = <&cpu4_opp_table>;
 333                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 334                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 335                         power-domains = <&CPU_PD6>;
 336                         power-domain-names = "psci";
 337                         #cooling-cells = <2>;
 338                         next-level-cache = <&L2_600>;
 339                         L2_600: l2-cache {
 340                                 compatible = "cache";
 341                                 next-level-cache = <&L3_0>;
 342                         };
 343                 };
 344
 345                 CPU7: cpu@700 {
 346                         device_type = "cpu";
 347                         compatible = "qcom,kryo385";
 348                         reg = <0x0 0x700>;
 349                         enable-method = "psci";
 350                         capacity-dmips-mhz = <1024>;
 351                         dynamic-power-coefficient = <442>;
 352                         qcom,freq-domain = <&cpufreq_hw 1>;
 353                         operating-points-v2 = <&cpu4_opp_table>;
 354                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
 355                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 356                         power-domains = <&CPU_PD7>;
 357                         power-domain-names = "psci";
 358                         #cooling-cells = <2>;
 359                         next-level-cache = <&L2_700>;
 360                         L2_700: l2-cache {
 361                                 compatible = "cache";
 362                                 next-level-cache = <&L3_0>;
 363                         };
 364                 };
 365
 366                 cpu-map {
 367                         cluster0 {
 368                                 core0 {
 369                                         cpu = <&CPU0>;
 370                                 };
 371
 372                                 core1 {
 373                                         cpu = <&CPU1>;
 374                                 };
 375
 376                                 core2 {
 377                                         cpu = <&CPU2>;
 378                                 };
 379
 380                                 core3 {
 381                                         cpu = <&CPU3>;
 382                                 };
 383
 384                                 core4 {
 385                                         cpu = <&CPU4>;
 386                                 };
 387
 388                                 core5 {
 389                                         cpu = <&CPU5>;
 390                                 };
 391
 392                                 core6 {
 393                                         cpu = <&CPU6>;
 394                                 };
 395
 396                                 core7 {
 397                                         cpu = <&CPU7>;
 398                                 };
 399                         };
 400                 };
 401
 402                 cpu_idle_states: idle-states {
 403                         entry-method = "psci";
 404
 405                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 406                                 compatible = "arm,idle-state";
 407                                 idle-state-name = "little-rail-power-collapse";
 408                                 arm,psci-suspend-param = <0x40000004>;
 409                                 entry-latency-us = <350>;
 410                                 exit-latency-us = <461>;
 411                                 min-residency-us = <1890>;
 412                                 local-timer-stop;
 413                         };
 414
 415                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 416                                 compatible = "arm,idle-state";
 417                                 idle-state-name = "big-rail-power-collapse";
 418                                 arm,psci-suspend-param = <0x40000004>;
 419                                 entry-latency-us = <264>;
 420                                 exit-latency-us = <621>;
 421                                 min-residency-us = <952>;
 422                                 local-timer-stop;
 423                         };
 424                 };
 425
 426                 domain-idle-states {
 427                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 428                                 compatible = "domain-idle-state";
 429                                 idle-state-name = "cluster-power-collapse";
 430                                 arm,psci-suspend-param = <0x4100c244>;
 431                                 entry-latency-us = <3263>;
 432                                 exit-latency-us = <6562>;
 433                                 min-residency-us = <9987>;
 434                                 local-timer-stop;
 435                         };
 436                 };
 437         };
 438
 439         cpu0_opp_table: opp-table-cpu0 {
 440                 compatible = "operating-points-v2";
 441                 opp-shared;
 442
 443                 cpu0_opp1: opp-300000000 {
 444                         opp-hz = /bits/ 64 <300000000>;
 445                         opp-peak-kBps = <800000 4800000>;
 446                 };
 447
 448                 cpu0_opp2: opp-403200000 {
 449                         opp-hz = /bits/ 64 <403200000>;
 450                         opp-peak-kBps = <800000 4800000>;
 451                 };
 452
 453                 cpu0_opp3: opp-480000000 {
 454                         opp-hz = /bits/ 64 <480000000>;
 455                         opp-peak-kBps = <800000 6451200>;
 456                 };
 457
 458                 cpu0_opp4: opp-576000000 {
 459                         opp-hz = /bits/ 64 <576000000>;
 460                         opp-peak-kBps = <800000 6451200>;
 461                 };
 462
 463                 cpu0_opp5: opp-652800000 {
 464                         opp-hz = /bits/ 64 <652800000>;
 465                         opp-peak-kBps = <800000 7680000>;
 466                 };
 467
 468                 cpu0_opp6: opp-748800000 {
 469                         opp-hz = /bits/ 64 <748800000>;
 470                         opp-peak-kBps = <1804000 9216000>;
 471                 };
 472
 473                 cpu0_opp7: opp-825600000 {
 474                         opp-hz = /bits/ 64 <825600000>;
 475                         opp-peak-kBps = <1804000 9216000>;
 476                 };
 477
 478                 cpu0_opp8: opp-902400000 {
 479                         opp-hz = /bits/ 64 <902400000>;
 480                         opp-peak-kBps = <1804000 10444800>;
 481                 };
 482
 483                 cpu0_opp9: opp-979200000 {
 484                         opp-hz = /bits/ 64 <979200000>;
 485                         opp-peak-kBps = <1804000 11980800>;
 486                 };
 487
 488                 cpu0_opp10: opp-1056000000 {
 489                         opp-hz = /bits/ 64 <1056000000>;
 490                         opp-peak-kBps = <1804000 11980800>;
 491                 };
 492
 493                 cpu0_opp11: opp-1132800000 {
 494                         opp-hz = /bits/ 64 <1132800000>;
 495                         opp-peak-kBps = <2188000 13516800>;
 496                 };
 497
 498                 cpu0_opp12: opp-1228800000 {
 499                         opp-hz = /bits/ 64 <1228800000>;
 500                         opp-peak-kBps = <2188000 15052800>;
 501                 };
 502
 503                 cpu0_opp13: opp-1324800000 {
 504                         opp-hz = /bits/ 64 <1324800000>;
 505                         opp-peak-kBps = <2188000 16588800>;
 506                 };
 507
 508                 cpu0_opp14: opp-1420800000 {
 509                         opp-hz = /bits/ 64 <1420800000>;
 510                         opp-peak-kBps = <3072000 18124800>;
 511                 };
 512
 513                 cpu0_opp15: opp-1516800000 {
 514                         opp-hz = /bits/ 64 <1516800000>;
 515                         opp-peak-kBps = <3072000 19353600>;
 516                 };
 517
 518                 cpu0_opp16: opp-1612800000 {
 519                         opp-hz = /bits/ 64 <1612800000>;
 520                         opp-peak-kBps = <4068000 19353600>;
 521                 };
 522
 523                 cpu0_opp17: opp-1689600000 {
 524                         opp-hz = /bits/ 64 <1689600000>;
 525                         opp-peak-kBps = <4068000 20889600>;
 526                 };
 527
 528                 cpu0_opp18: opp-1766400000 {
 529                         opp-hz = /bits/ 64 <1766400000>;
 530                         opp-peak-kBps = <4068000 22425600>;
 531                 };
 532         };
 533
 534         cpu4_opp_table: opp-table-cpu4 {
 535                 compatible = "operating-points-v2";
 536                 opp-shared;
 537
 538                 cpu4_opp1: opp-300000000 {
 539                         opp-hz = /bits/ 64 <300000000>;
 540                         opp-peak-kBps = <800000 4800000>;
 541                 };
 542
 543                 cpu4_opp2: opp-403200000 {
 544                         opp-hz = /bits/ 64 <403200000>;
 545                         opp-peak-kBps = <800000 4800000>;
 546                 };
 547
 548                 cpu4_opp3: opp-480000000 {
 549                         opp-hz = /bits/ 64 <480000000>;
 550                         opp-peak-kBps = <1804000 4800000>;
 551                 };
 552
 553                 cpu4_opp4: opp-576000000 {
 554                         opp-hz = /bits/ 64 <576000000>;
 555                         opp-peak-kBps = <1804000 4800000>;
 556                 };
 557
 558                 cpu4_opp5: opp-652800000 {
 559                         opp-hz = /bits/ 64 <652800000>;
 560                         opp-peak-kBps = <1804000 4800000>;
 561                 };
 562
 563                 cpu4_opp6: opp-748800000 {
 564                         opp-hz = /bits/ 64 <748800000>;
 565                         opp-peak-kBps = <1804000 4800000>;
 566                 };
 567
 568                 cpu4_opp7: opp-825600000 {
 569                         opp-hz = /bits/ 64 <825600000>;
 570                         opp-peak-kBps = <2188000 9216000>;
 571                 };
 572
 573                 cpu4_opp8: opp-902400000 {
 574                         opp-hz = /bits/ 64 <902400000>;
 575                         opp-peak-kBps = <2188000 9216000>;
 576                 };
 577
 578                 cpu4_opp9: opp-979200000 {
 579                         opp-hz = /bits/ 64 <979200000>;
 580                         opp-peak-kBps = <2188000 9216000>;
 581                 };
 582
 583                 cpu4_opp10: opp-1056000000 {
 584                         opp-hz = /bits/ 64 <1056000000>;
 585                         opp-peak-kBps = <3072000 9216000>;
 586                 };
 587
 588                 cpu4_opp11: opp-1132800000 {
 589                         opp-hz = /bits/ 64 <1132800000>;
 590                         opp-peak-kBps = <3072000 11980800>;
 591                 };
 592
 593                 cpu4_opp12: opp-1209600000 {
 594                         opp-hz = /bits/ 64 <1209600000>;
 595                         opp-peak-kBps = <4068000 11980800>;
 596                 };
 597
 598                 cpu4_opp13: opp-1286400000 {
 599                         opp-hz = /bits/ 64 <1286400000>;
 600                         opp-peak-kBps = <4068000 11980800>;
 601                 };
 602
 603                 cpu4_opp14: opp-1363200000 {
 604                         opp-hz = /bits/ 64 <1363200000>;
 605                         opp-peak-kBps = <4068000 15052800>;
 606                 };
 607
 608                 cpu4_opp15: opp-1459200000 {
 609                         opp-hz = /bits/ 64 <1459200000>;
 610                         opp-peak-kBps = <4068000 15052800>;
 611                 };
 612
 613                 cpu4_opp16: opp-1536000000 {
 614                         opp-hz = /bits/ 64 <1536000000>;
 615                         opp-peak-kBps = <5412000 15052800>;
 616                 };
 617
 618                 cpu4_opp17: opp-1612800000 {
 619                         opp-hz = /bits/ 64 <1612800000>;
 620                         opp-peak-kBps = <5412000 15052800>;
 621                 };
 622
 623                 cpu4_opp18: opp-1689600000 {
 624                         opp-hz = /bits/ 64 <1689600000>;
 625                         opp-peak-kBps = <5412000 19353600>;
 626                 };
 627
 628                 cpu4_opp19: opp-1766400000 {
 629                         opp-hz = /bits/ 64 <1766400000>;
 630                         opp-peak-kBps = <6220000 19353600>;
 631                 };
 632
 633                 cpu4_opp20: opp-1843200000 {
 634                         opp-hz = /bits/ 64 <1843200000>;
 635                         opp-peak-kBps = <6220000 19353600>;
 636                 };
 637
 638                 cpu4_opp21: opp-1920000000 {
 639                         opp-hz = /bits/ 64 <1920000000>;
 640                         opp-peak-kBps = <7216000 19353600>;
 641                 };
 642
 643                 cpu4_opp22: opp-1996800000 {
 644                         opp-hz = /bits/ 64 <1996800000>;
 645                         opp-peak-kBps = <7216000 20889600>;
 646                 };
 647
 648                 cpu4_opp23: opp-2092800000 {
 649                         opp-hz = /bits/ 64 <2092800000>;
 650                         opp-peak-kBps = <7216000 20889600>;
 651                 };
 652
 653                 cpu4_opp24: opp-2169600000 {
 654                         opp-hz = /bits/ 64 <2169600000>;
 655                         opp-peak-kBps = <7216000 20889600>;
 656                 };
 657
 658                 cpu4_opp25: opp-2246400000 {
 659                         opp-hz = /bits/ 64 <2246400000>;
 660                         opp-peak-kBps = <7216000 20889600>;
 661                 };
 662
 663                 cpu4_opp26: opp-2323200000 {
 664                         opp-hz = /bits/ 64 <2323200000>;
 665                         opp-peak-kBps = <7216000 20889600>;
 666                 };
 667
 668                 cpu4_opp27: opp-2400000000 {
 669                         opp-hz = /bits/ 64 <2400000000>;
 670                         opp-peak-kBps = <7216000 22425600>;
 671                 };
 672
 673                 cpu4_opp28: opp-2476800000 {
 674                         opp-hz = /bits/ 64 <2476800000>;
 675                         opp-peak-kBps = <7216000 22425600>;
 676                 };
 677
 678                 cpu4_opp29: opp-2553600000 {
 679                         opp-hz = /bits/ 64 <2553600000>;
 680                         opp-peak-kBps = <7216000 22425600>;
 681                 };
 682
 683                 cpu4_opp30: opp-2649600000 {
 684                         opp-hz = /bits/ 64 <2649600000>;
 685                         opp-peak-kBps = <7216000 22425600>;
 686                 };
 687
 688                 cpu4_opp31: opp-2745600000 {
 689                         opp-hz = /bits/ 64 <2745600000>;
 690                         opp-peak-kBps = <7216000 25497600>;
 691                 };
 692
 693                 cpu4_opp32: opp-2803200000 {
 694                         opp-hz = /bits/ 64 <2803200000>;
 695                         opp-peak-kBps = <7216000 25497600>;
 696                 };
 697         };
 698
 699         pmu {
 700                 compatible = "arm,armv8-pmuv3";
 701                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 702         };
 703
 704         timer {
 705                 compatible = "arm,armv8-timer";
 706                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 707                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 708                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 709                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 710         };
 711
 712         clocks {
 713                 xo_board: xo-board {
 714                         compatible = "fixed-clock";
 715                         #clock-cells = <0>;
 716                         clock-frequency = <38400000>;
 717                         clock-output-names = "xo_board";
 718                 };
 719
 720                 sleep_clk: sleep-clk {
 721                         compatible = "fixed-clock";
 722                         #clock-cells = <0>;
 723                         clock-frequency = <32764>;
 724                 };
 725         };
 726
 727         firmware {
 728                 scm {
 729                         compatible = "qcom,scm-sdm845", "qcom,scm";
 730                 };
 731         };
 732
 733         adsp_pas: remoteproc-adsp {
 734                 compatible = "qcom,sdm845-adsp-pas";
 735
 736                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 737                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 738                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 739                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 740                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 741                 interrupt-names = "wdog", "fatal", "ready",
 742                                   "handover", "stop-ack";
 743
 744                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 745                 clock-names = "xo";
 746
 747                 memory-region = <&adsp_mem>;
 748
 749                 qcom,qmp = <&aoss_qmp>;
 750
 751                 qcom,smem-states = <&adsp_smp2p_out 0>;
 752                 qcom,smem-state-names = "stop";
 753
 754                 status = "disabled";
 755
 756                 glink-edge {
 757                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 758                         label = "lpass";
 759                         qcom,remote-pid = <2>;
 760                         mboxes = <&apss_shared 8>;
 761
 762                         apr {
 763                                 compatible = "qcom,apr-v2";
 764                                 qcom,glink-channels = "apr_audio_svc";
 765                                 qcom,domain = <APR_DOMAIN_ADSP>;
 766                                 #address-cells = <1>;
 767                                 #size-cells = <0>;
 768                                 qcom,intents = <512 20>;
 769
 770                                 apr-service@3 {
 771                                         reg = <APR_SVC_ADSP_CORE>;
 772                                         compatible = "qcom,q6core";
 773                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 774                                 };
 775
 776                                 q6afe: apr-service@4 {
 777                                         compatible = "qcom,q6afe";
 778                                         reg = <APR_SVC_AFE>;
 779                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 780                                         q6afedai: dais {
 781                                                 compatible = "qcom,q6afe-dais";
 782                                                 #address-cells = <1>;
 783                                                 #size-cells = <0>;
 784                                                 #sound-dai-cells = <1>;
 785                                         };
 786                                 };
 787
 788                                 q6asm: apr-service@7 {
 789                                         compatible = "qcom,q6asm";
 790                                         reg = <APR_SVC_ASM>;
 791                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 792                                         q6asmdai: dais {
 793                                                 compatible = "qcom,q6asm-dais";
 794                                                 #address-cells = <1>;
 795                                                 #size-cells = <0>;
 796                                                 #sound-dai-cells = <1>;
 797                                                 iommus = <&apps_smmu 0x1821 0x0>;
 798                                         };
 799                                 };
 800
 801                                 q6adm: apr-service@8 {
 802                                         compatible = "qcom,q6adm";
 803                                         reg = <APR_SVC_ADM>;
 804                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
 805                                         q6routing: routing {
 806                                                 compatible = "qcom,q6adm-routing";
 807                                                 #sound-dai-cells = <0>;
 808                                         };
 809                                 };
 810                         };
 811
 812                         fastrpc {
 813                                 compatible = "qcom,fastrpc";
 814                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 815                                 label = "adsp";
 816                                 qcom,non-secure-domain;
 817                                 #address-cells = <1>;
 818                                 #size-cells = <0>;
 819
 820                                 compute-cb@3 {
 821                                         compatible = "qcom,fastrpc-compute-cb";
 822                                         reg = <3>;
 823                                         iommus = <&apps_smmu 0x1823 0x0>;
 824                                 };
 825
 826                                 compute-cb@4 {
 827                                         compatible = "qcom,fastrpc-compute-cb";
 828                                         reg = <4>;
 829                                         iommus = <&apps_smmu 0x1824 0x0>;
 830                                 };
 831                         };
 832                 };
 833         };
 834
 835         cdsp_pas: remoteproc-cdsp {
 836                 compatible = "qcom,sdm845-cdsp-pas";
 837
 838                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 839                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 840                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 841                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 842                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 843                 interrupt-names = "wdog", "fatal", "ready",
 844                                   "handover", "stop-ack";
 845
 846                 clocks = <&rpmhcc RPMH_CXO_CLK>;
 847                 clock-names = "xo";
 848
 849                 memory-region = <&cdsp_mem>;
 850
 851                 qcom,qmp = <&aoss_qmp>;
 852
 853                 qcom,smem-states = <&cdsp_smp2p_out 0>;
 854                 qcom,smem-state-names = "stop";
 855
 856                 status = "disabled";
 857
 858                 glink-edge {
 859                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 860                         label = "turing";
 861                         qcom,remote-pid = <5>;
 862                         mboxes = <&apss_shared 4>;
 863                         fastrpc {
 864                                 compatible = "qcom,fastrpc";
 865                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
 866                                 label = "cdsp";
 867                                 qcom,non-secure-domain;
 868                                 #address-cells = <1>;
 869                                 #size-cells = <0>;
 870
 871                                 compute-cb@1 {
 872                                         compatible = "qcom,fastrpc-compute-cb";
 873                                         reg = <1>;
 874                                         iommus = <&apps_smmu 0x1401 0x30>;
 875                                 };
 876
 877                                 compute-cb@2 {
 878                                         compatible = "qcom,fastrpc-compute-cb";
 879                                         reg = <2>;
 880                                         iommus = <&apps_smmu 0x1402 0x30>;
 881                                 };
 882
 883                                 compute-cb@3 {
 884                                         compatible = "qcom,fastrpc-compute-cb";
 885                                         reg = <3>;
 886                                         iommus = <&apps_smmu 0x1403 0x30>;
 887                                 };
 888
 889                                 compute-cb@4 {
 890                                         compatible = "qcom,fastrpc-compute-cb";
 891                                         reg = <4>;
 892                                         iommus = <&apps_smmu 0x1404 0x30>;
 893                                 };
 894
 895                                 compute-cb@5 {
 896                                         compatible = "qcom,fastrpc-compute-cb";
 897                                         reg = <5>;
 898                                         iommus = <&apps_smmu 0x1405 0x30>;
 899                                 };
 900
 901                                 compute-cb@6 {
 902                                         compatible = "qcom,fastrpc-compute-cb";
 903                                         reg = <6>;
 904                                         iommus = <&apps_smmu 0x1406 0x30>;
 905                                 };
 906
 907                                 compute-cb@7 {
 908                                         compatible = "qcom,fastrpc-compute-cb";
 909                                         reg = <7>;
 910                                         iommus = <&apps_smmu 0x1407 0x30>;
 911                                 };
 912
 913                                 compute-cb@8 {
 914                                         compatible = "qcom,fastrpc-compute-cb";
 915                                         reg = <8>;
 916                                         iommus = <&apps_smmu 0x1408 0x30>;
 917                                 };
 918                         };
 919                 };
 920         };
 921
 922         smp2p-cdsp {
 923                 compatible = "qcom,smp2p";
 924                 qcom,smem = <94>, <432>;
 925
 926                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 927
 928                 mboxes = <&apss_shared 6>;
 929
 930                 qcom,local-pid = <0>;
 931                 qcom,remote-pid = <5>;
 932
 933                 cdsp_smp2p_out: master-kernel {
 934                         qcom,entry-name = "master-kernel";
 935                         #qcom,smem-state-cells = <1>;
 936                 };
 937
 938                 cdsp_smp2p_in: slave-kernel {
 939                         qcom,entry-name = "slave-kernel";
 940
 941                         interrupt-controller;
 942                         #interrupt-cells = <2>;
 943                 };
 944         };
 945
 946         smp2p-lpass {
 947                 compatible = "qcom,smp2p";
 948                 qcom,smem = <443>, <429>;
 949
 950                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 951
 952                 mboxes = <&apss_shared 10>;
 953
 954                 qcom,local-pid = <0>;
 955                 qcom,remote-pid = <2>;
 956
 957                 adsp_smp2p_out: master-kernel {
 958                         qcom,entry-name = "master-kernel";
 959                         #qcom,smem-state-cells = <1>;
 960                 };
 961
 962                 adsp_smp2p_in: slave-kernel {
 963                         qcom,entry-name = "slave-kernel";
 964
 965                         interrupt-controller;
 966                         #interrupt-cells = <2>;
 967                 };
 968         };
 969
 970         smp2p-mpss {
 971                 compatible = "qcom,smp2p";
 972                 qcom,smem = <435>, <428>;
 973                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 974                 mboxes = <&apss_shared 14>;
 975                 qcom,local-pid = <0>;
 976                 qcom,remote-pid = <1>;
 977
 978                 modem_smp2p_out: master-kernel {
 979                         qcom,entry-name = "master-kernel";
 980                         #qcom,smem-state-cells = <1>;
 981                 };
 982
 983                 modem_smp2p_in: slave-kernel {
 984                         qcom,entry-name = "slave-kernel";
 985                         interrupt-controller;
 986                         #interrupt-cells = <2>;
 987                 };
 988
 989                 ipa_smp2p_out: ipa-ap-to-modem {
 990                         qcom,entry-name = "ipa";
 991                         #qcom,smem-state-cells = <1>;
 992                 };
 993
 994                 ipa_smp2p_in: ipa-modem-to-ap {
 995                         qcom,entry-name = "ipa";
 996                         interrupt-controller;
 997                         #interrupt-cells = <2>;
 998                 };
 999         };
1000
1001         smp2p-slpi {
1002                 compatible = "qcom,smp2p";
1003                 qcom,smem = <481>, <430>;
1004                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1005                 mboxes = <&apss_shared 26>;
1006                 qcom,local-pid = <0>;
1007                 qcom,remote-pid = <3>;
1008
1009                 slpi_smp2p_out: master-kernel {
1010                         qcom,entry-name = "master-kernel";
1011                         #qcom,smem-state-cells = <1>;
1012                 };
1013
1014                 slpi_smp2p_in: slave-kernel {
1015                         qcom,entry-name = "slave-kernel";
1016                         interrupt-controller;
1017                         #interrupt-cells = <2>;
1018                 };
1019         };
1020
1021         psci: psci {
1022                 compatible = "arm,psci-1.0";
1023                 method = "smc";
1024
1025                 CPU_PD0: power-domain-cpu0 {
1026                         #power-domain-cells = <0>;
1027                         power-domains = <&CLUSTER_PD>;
1028                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1029                 };
1030
1031                 CPU_PD1: power-domain-cpu1 {
1032                         #power-domain-cells = <0>;
1033                         power-domains = <&CLUSTER_PD>;
1034                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1035                 };
1036
1037                 CPU_PD2: power-domain-cpu2 {
1038                         #power-domain-cells = <0>;
1039                         power-domains = <&CLUSTER_PD>;
1040                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1041                 };
1042
1043                 CPU_PD3: power-domain-cpu3 {
1044                         #power-domain-cells = <0>;
1045                         power-domains = <&CLUSTER_PD>;
1046                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
1047                 };
1048
1049                 CPU_PD4: power-domain-cpu4 {
1050                         #power-domain-cells = <0>;
1051                         power-domains = <&CLUSTER_PD>;
1052                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
1053                 };
1054
1055                 CPU_PD5: power-domain-cpu5 {
1056                         #power-domain-cells = <0>;
1057                         power-domains = <&CLUSTER_PD>;
1058                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
1059                 };
1060
1061                 CPU_PD6: power-domain-cpu6 {
1062                         #power-domain-cells = <0>;
1063                         power-domains = <&CLUSTER_PD>;
1064                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
1065                 };
1066
1067                 CPU_PD7: power-domain-cpu7 {
1068                         #power-domain-cells = <0>;
1069                         power-domains = <&CLUSTER_PD>;
1070                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
1071                 };
1072
1073                 CLUSTER_PD: power-domain-cluster {
1074                         #power-domain-cells = <0>;
1075                         domain-idle-states = <&CLUSTER_SLEEP_0>;
1076                 };
1077         };
1078
1079         soc: soc@0 {
1080                 #address-cells = <2>;
1081                 #size-cells = <2>;
1082                 ranges = <0 0 0 0 0x10 0>;
1083                 dma-ranges = <0 0 0 0 0x10 0>;
1084                 compatible = "simple-bus";
1085
1086                 gcc: clock-controller@100000 {
1087                         compatible = "qcom,gcc-sdm845";
1088                         reg = <0 0x00100000 0 0x1f0000>;
1089                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1090                                  <&rpmhcc RPMH_CXO_CLK_A>,
1091                                  <&sleep_clk>,
1092                                  <&pcie0_lane>,
1093                                  <&pcie1_lane>;
1094                         clock-names = "bi_tcxo",
1095                                       "bi_tcxo_ao",
1096                                       "sleep_clk",
1097                                       "pcie_0_pipe_clk",
1098                                       "pcie_1_pipe_clk";
1099                         #clock-cells = <1>;
1100                         #reset-cells = <1>;
1101                         #power-domain-cells = <1>;
1102                         power-domains = <&rpmhpd SDM845_CX>;
1103                 };
1104
1105                 qfprom@784000 {
1106                         compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1107                         reg = <0 0x00784000 0 0x8ff>;
1108                         #address-cells = <1>;
1109                         #size-cells = <1>;
1110
1111                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1112                                 reg = <0x1eb 0x1>;
1113                                 bits = <1 4>;
1114                         };
1115
1116                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1117                                 reg = <0x1eb 0x2>;
1118                                 bits = <6 4>;
1119                         };
1120                 };
1121
1122                 rng: rng@793000 {
1123                         compatible = "qcom,prng-ee";
1124                         reg = <0 0x00793000 0 0x1000>;
1125                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1126                         clock-names = "core";
1127                 };
1128
1129                 qup_opp_table: opp-table-qup {
1130                         compatible = "operating-points-v2";
1131
1132                         opp-50000000 {
1133                                 opp-hz = /bits/ 64 <50000000>;
1134                                 required-opps = <&rpmhpd_opp_min_svs>;
1135                         };
1136
1137                         opp-75000000 {
1138                                 opp-hz = /bits/ 64 <75000000>;
1139                                 required-opps = <&rpmhpd_opp_low_svs>;
1140                         };
1141
1142                         opp-100000000 {
1143                                 opp-hz = /bits/ 64 <100000000>;
1144                                 required-opps = <&rpmhpd_opp_svs>;
1145                         };
1146
1147                         opp-128000000 {
1148                                 opp-hz = /bits/ 64 <128000000>;
1149                                 required-opps = <&rpmhpd_opp_nom>;
1150                         };
1151                 };
1152
1153                 gpi_dma0: dma-controller@800000 {
1154                         #dma-cells = <3>;
1155                         compatible = "qcom,sdm845-gpi-dma";
1156                         reg = <0 0x00800000 0 0x60000>;
1157                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1158                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1159                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1160                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1162                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1163                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1164                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1167                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1168                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1169                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1170                         dma-channels = <13>;
1171                         dma-channel-mask = <0xfa>;
1172                         iommus = <&apps_smmu 0x0016 0x0>;
1173                         status = "disabled";
1174                 };
1175
1176                 qupv3_id_0: geniqup@8c0000 {
1177                         compatible = "qcom,geni-se-qup";
1178                         reg = <0 0x008c0000 0 0x6000>;
1179                         clock-names = "m-ahb", "s-ahb";
1180                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1181                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1182                         iommus = <&apps_smmu 0x3 0x0>;
1183                         #address-cells = <2>;
1184                         #size-cells = <2>;
1185                         ranges;
1186                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1187                         interconnect-names = "qup-core";
1188                         status = "disabled";
1189
1190                         i2c0: i2c@880000 {
1191                                 compatible = "qcom,geni-i2c";
1192                                 reg = <0 0x00880000 0 0x4000>;
1193                                 clock-names = "se";
1194                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1195                                 pinctrl-names = "default";
1196                                 pinctrl-0 = <&qup_i2c0_default>;
1197                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1198                                 #address-cells = <1>;
1199                                 #size-cells = <0>;
1200                                 power-domains = <&rpmhpd SDM845_CX>;
1201                                 operating-points-v2 = <&qup_opp_table>;
1202                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1203                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1204                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1205                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1206                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1207                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1208                                 dma-names = "tx", "rx";
1209                                 status = "disabled";
1210                         };
1211
1212                         spi0: spi@880000 {
1213                                 compatible = "qcom,geni-spi";
1214                                 reg = <0 0x00880000 0 0x4000>;
1215                                 clock-names = "se";
1216                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1217                                 pinctrl-names = "default";
1218                                 pinctrl-0 = <&qup_spi0_default>;
1219                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1220                                 #address-cells = <1>;
1221                                 #size-cells = <0>;
1222                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1223                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1224                                 interconnect-names = "qup-core", "qup-config";
1225                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1226                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1227                                 dma-names = "tx", "rx";
1228                                 status = "disabled";
1229                         };
1230
1231                         uart0: serial@880000 {
1232                                 compatible = "qcom,geni-uart";
1233                                 reg = <0 0x00880000 0 0x4000>;
1234                                 clock-names = "se";
1235                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1236                                 pinctrl-names = "default";
1237                                 pinctrl-0 = <&qup_uart0_default>;
1238                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1239                                 power-domains = <&rpmhpd SDM845_CX>;
1240                                 operating-points-v2 = <&qup_opp_table>;
1241                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1242                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1243                                 interconnect-names = "qup-core", "qup-config";
1244                                 status = "disabled";
1245                         };
1246
1247                         i2c1: i2c@884000 {
1248                                 compatible = "qcom,geni-i2c";
1249                                 reg = <0 0x00884000 0 0x4000>;
1250                                 clock-names = "se";
1251                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1252                                 pinctrl-names = "default";
1253                                 pinctrl-0 = <&qup_i2c1_default>;
1254                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1255                                 #address-cells = <1>;
1256                                 #size-cells = <0>;
1257                                 power-domains = <&rpmhpd SDM845_CX>;
1258                                 operating-points-v2 = <&qup_opp_table>;
1259                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1260                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1261                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1262                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1263                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1264                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1265                                 dma-names = "tx", "rx";
1266                                 status = "disabled";
1267                         };
1268
1269                         spi1: spi@884000 {
1270                                 compatible = "qcom,geni-spi";
1271                                 reg = <0 0x00884000 0 0x4000>;
1272                                 clock-names = "se";
1273                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1274                                 pinctrl-names = "default";
1275                                 pinctrl-0 = <&qup_spi1_default>;
1276                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1277                                 #address-cells = <1>;
1278                                 #size-cells = <0>;
1279                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1280                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1281                                 interconnect-names = "qup-core", "qup-config";
1282                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1283                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1284                                 dma-names = "tx", "rx";
1285                                 status = "disabled";
1286                         };
1287
1288                         uart1: serial@884000 {
1289                                 compatible = "qcom,geni-uart";
1290                                 reg = <0 0x00884000 0 0x4000>;
1291                                 clock-names = "se";
1292                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1293                                 pinctrl-names = "default";
1294                                 pinctrl-0 = <&qup_uart1_default>;
1295                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1296                                 power-domains = <&rpmhpd SDM845_CX>;
1297                                 operating-points-v2 = <&qup_opp_table>;
1298                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1299                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1300                                 interconnect-names = "qup-core", "qup-config";
1301                                 status = "disabled";
1302                         };
1303
1304                         i2c2: i2c@888000 {
1305                                 compatible = "qcom,geni-i2c";
1306                                 reg = <0 0x00888000 0 0x4000>;
1307                                 clock-names = "se";
1308                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1309                                 pinctrl-names = "default";
1310                                 pinctrl-0 = <&qup_i2c2_default>;
1311                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314                                 power-domains = <&rpmhpd SDM845_CX>;
1315                                 operating-points-v2 = <&qup_opp_table>;
1316                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1317                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1318                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1319                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1320                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1321                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1322                                 dma-names = "tx", "rx";
1323                                 status = "disabled";
1324                         };
1325
1326                         spi2: spi@888000 {
1327                                 compatible = "qcom,geni-spi";
1328                                 reg = <0 0x00888000 0 0x4000>;
1329                                 clock-names = "se";
1330                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1331                                 pinctrl-names = "default";
1332                                 pinctrl-0 = <&qup_spi2_default>;
1333                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1334                                 #address-cells = <1>;
1335                                 #size-cells = <0>;
1336                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1337                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1338                                 interconnect-names = "qup-core", "qup-config";
1339                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1340                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1341                                 dma-names = "tx", "rx";
1342                                 status = "disabled";
1343                         };
1344
1345                         uart2: serial@888000 {
1346                                 compatible = "qcom,geni-uart";
1347                                 reg = <0 0x00888000 0 0x4000>;
1348                                 clock-names = "se";
1349                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1350                                 pinctrl-names = "default";
1351                                 pinctrl-0 = <&qup_uart2_default>;
1352                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1353                                 power-domains = <&rpmhpd SDM845_CX>;
1354                                 operating-points-v2 = <&qup_opp_table>;
1355                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1356                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1357                                 interconnect-names = "qup-core", "qup-config";
1358                                 status = "disabled";
1359                         };
1360
1361                         i2c3: i2c@88c000 {
1362                                 compatible = "qcom,geni-i2c";
1363                                 reg = <0 0x0088c000 0 0x4000>;
1364                                 clock-names = "se";
1365                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1366                                 pinctrl-names = "default";
1367                                 pinctrl-0 = <&qup_i2c3_default>;
1368                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1369                                 #address-cells = <1>;
1370                                 #size-cells = <0>;
1371                                 power-domains = <&rpmhpd SDM845_CX>;
1372                                 operating-points-v2 = <&qup_opp_table>;
1373                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1374                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1375                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1376                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1377                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1378                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1379                                 dma-names = "tx", "rx";
1380                                 status = "disabled";
1381                         };
1382
1383                         spi3: spi@88c000 {
1384                                 compatible = "qcom,geni-spi";
1385                                 reg = <0 0x0088c000 0 0x4000>;
1386                                 clock-names = "se";
1387                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1388                                 pinctrl-names = "default";
1389                                 pinctrl-0 = <&qup_spi3_default>;
1390                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1391                                 #address-cells = <1>;
1392                                 #size-cells = <0>;
1393                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1394                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1395                                 interconnect-names = "qup-core", "qup-config";
1396                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1397                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1398                                 dma-names = "tx", "rx";
1399                                 status = "disabled";
1400                         };
1401
1402                         uart3: serial@88c000 {
1403                                 compatible = "qcom,geni-uart";
1404                                 reg = <0 0x0088c000 0 0x4000>;
1405                                 clock-names = "se";
1406                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1407                                 pinctrl-names = "default";
1408                                 pinctrl-0 = <&qup_uart3_default>;
1409                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1410                                 power-domains = <&rpmhpd SDM845_CX>;
1411                                 operating-points-v2 = <&qup_opp_table>;
1412                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1413                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1414                                 interconnect-names = "qup-core", "qup-config";
1415                                 status = "disabled";
1416                         };
1417
1418                         i2c4: i2c@890000 {
1419                                 compatible = "qcom,geni-i2c";
1420                                 reg = <0 0x00890000 0 0x4000>;
1421                                 clock-names = "se";
1422                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1423                                 pinctrl-names = "default";
1424                                 pinctrl-0 = <&qup_i2c4_default>;
1425                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1426                                 #address-cells = <1>;
1427                                 #size-cells = <0>;
1428                                 power-domains = <&rpmhpd SDM845_CX>;
1429                                 operating-points-v2 = <&qup_opp_table>;
1430                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1431                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1432                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1433                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1434                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1435                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1436                                 dma-names = "tx", "rx";
1437                                 status = "disabled";
1438                         };
1439
1440                         spi4: spi@890000 {
1441                                 compatible = "qcom,geni-spi";
1442                                 reg = <0 0x00890000 0 0x4000>;
1443                                 clock-names = "se";
1444                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1445                                 pinctrl-names = "default";
1446                                 pinctrl-0 = <&qup_spi4_default>;
1447                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1448                                 #address-cells = <1>;
1449                                 #size-cells = <0>;
1450                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1451                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1452                                 interconnect-names = "qup-core", "qup-config";
1453                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1454                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1455                                 dma-names = "tx", "rx";
1456                                 status = "disabled";
1457                         };
1458
1459                         uart4: serial@890000 {
1460                                 compatible = "qcom,geni-uart";
1461                                 reg = <0 0x00890000 0 0x4000>;
1462                                 clock-names = "se";
1463                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1464                                 pinctrl-names = "default";
1465                                 pinctrl-0 = <&qup_uart4_default>;
1466                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1467                                 power-domains = <&rpmhpd SDM845_CX>;
1468                                 operating-points-v2 = <&qup_opp_table>;
1469                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1470                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1471                                 interconnect-names = "qup-core", "qup-config";
1472                                 status = "disabled";
1473                         };
1474
1475                         i2c5: i2c@894000 {
1476                                 compatible = "qcom,geni-i2c";
1477                                 reg = <0 0x00894000 0 0x4000>;
1478                                 clock-names = "se";
1479                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1480                                 pinctrl-names = "default";
1481                                 pinctrl-0 = <&qup_i2c5_default>;
1482                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1483                                 #address-cells = <1>;
1484                                 #size-cells = <0>;
1485                                 power-domains = <&rpmhpd SDM845_CX>;
1486                                 operating-points-v2 = <&qup_opp_table>;
1487                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1488                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1489                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1490                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1491                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1492                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1493                                 dma-names = "tx", "rx";
1494                                 status = "disabled";
1495                         };
1496
1497                         spi5: spi@894000 {
1498                                 compatible = "qcom,geni-spi";
1499                                 reg = <0 0x00894000 0 0x4000>;
1500                                 clock-names = "se";
1501                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1502                                 pinctrl-names = "default";
1503                                 pinctrl-0 = <&qup_spi5_default>;
1504                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1505                                 #address-cells = <1>;
1506                                 #size-cells = <0>;
1507                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1508                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1509                                 interconnect-names = "qup-core", "qup-config";
1510                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1511                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1512                                 dma-names = "tx", "rx";
1513                                 status = "disabled";
1514                         };
1515
1516                         uart5: serial@894000 {
1517                                 compatible = "qcom,geni-uart";
1518                                 reg = <0 0x00894000 0 0x4000>;
1519                                 clock-names = "se";
1520                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1521                                 pinctrl-names = "default";
1522                                 pinctrl-0 = <&qup_uart5_default>;
1523                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1524                                 power-domains = <&rpmhpd SDM845_CX>;
1525                                 operating-points-v2 = <&qup_opp_table>;
1526                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1527                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1528                                 interconnect-names = "qup-core", "qup-config";
1529                                 status = "disabled";
1530                         };
1531
1532                         i2c6: i2c@898000 {
1533                                 compatible = "qcom,geni-i2c";
1534                                 reg = <0 0x00898000 0 0x4000>;
1535                                 clock-names = "se";
1536                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1537                                 pinctrl-names = "default";
1538                                 pinctrl-0 = <&qup_i2c6_default>;
1539                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1540                                 #address-cells = <1>;
1541                                 #size-cells = <0>;
1542                                 power-domains = <&rpmhpd SDM845_CX>;
1543                                 operating-points-v2 = <&qup_opp_table>;
1544                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1545                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1546                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1547                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1548                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1549                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1550                                 dma-names = "tx", "rx";
1551                                 status = "disabled";
1552                         };
1553
1554                         spi6: spi@898000 {
1555                                 compatible = "qcom,geni-spi";
1556                                 reg = <0 0x00898000 0 0x4000>;
1557                                 clock-names = "se";
1558                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1559                                 pinctrl-names = "default";
1560                                 pinctrl-0 = <&qup_spi6_default>;
1561                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1562                                 #address-cells = <1>;
1563                                 #size-cells = <0>;
1564                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1565                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1566                                 interconnect-names = "qup-core", "qup-config";
1567                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1568                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1569                                 dma-names = "tx", "rx";
1570                                 status = "disabled";
1571                         };
1572
1573                         uart6: serial@898000 {
1574                                 compatible = "qcom,geni-uart";
1575                                 reg = <0 0x00898000 0 0x4000>;
1576                                 clock-names = "se";
1577                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1578                                 pinctrl-names = "default";
1579                                 pinctrl-0 = <&qup_uart6_default>;
1580                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1581                                 power-domains = <&rpmhpd SDM845_CX>;
1582                                 operating-points-v2 = <&qup_opp_table>;
1583                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1584                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1585                                 interconnect-names = "qup-core", "qup-config";
1586                                 status = "disabled";
1587                         };
1588
1589                         i2c7: i2c@89c000 {
1590                                 compatible = "qcom,geni-i2c";
1591                                 reg = <0 0x0089c000 0 0x4000>;
1592                                 clock-names = "se";
1593                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1594                                 pinctrl-names = "default";
1595                                 pinctrl-0 = <&qup_i2c7_default>;
1596                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1597                                 #address-cells = <1>;
1598                                 #size-cells = <0>;
1599                                 power-domains = <&rpmhpd SDM845_CX>;
1600                                 operating-points-v2 = <&qup_opp_table>;
1601                                 status = "disabled";
1602                         };
1603
1604                         spi7: spi@89c000 {
1605                                 compatible = "qcom,geni-spi";
1606                                 reg = <0 0x0089c000 0 0x4000>;
1607                                 clock-names = "se";
1608                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1609                                 pinctrl-names = "default";
1610                                 pinctrl-0 = <&qup_spi7_default>;
1611                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1612                                 #address-cells = <1>;
1613                                 #size-cells = <0>;
1614                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1615                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1616                                 interconnect-names = "qup-core", "qup-config";
1617                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1618                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1619                                 dma-names = "tx", "rx";
1620                                 status = "disabled";
1621                         };
1622
1623                         uart7: serial@89c000 {
1624                                 compatible = "qcom,geni-uart";
1625                                 reg = <0 0x0089c000 0 0x4000>;
1626                                 clock-names = "se";
1627                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1628                                 pinctrl-names = "default";
1629                                 pinctrl-0 = <&qup_uart7_default>;
1630                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1631                                 power-domains = <&rpmhpd SDM845_CX>;
1632                                 operating-points-v2 = <&qup_opp_table>;
1633                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1634                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1635                                 interconnect-names = "qup-core", "qup-config";
1636                                 status = "disabled";
1637                         };
1638                 };
1639
1640                 gpi_dma1: dma-controller@0xa00000 {
1641                         #dma-cells = <3>;
1642                         compatible = "qcom,sdm845-gpi-dma";
1643                         reg = <0 0x00a00000 0 0x60000>;
1644                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1645                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1646                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1647                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1648                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1649                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1650                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1651                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1652                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1653                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1654                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1655                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1656                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1657                         dma-channels = <13>;
1658                         dma-channel-mask = <0xfa>;
1659                         iommus = <&apps_smmu 0x06d6 0x0>;
1660                         status = "disabled";
1661                 };
1662
1663                 qupv3_id_1: geniqup@ac0000 {
1664                         compatible = "qcom,geni-se-qup";
1665                         reg = <0 0x00ac0000 0 0x6000>;
1666                         clock-names = "m-ahb", "s-ahb";
1667                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1668                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1669                         iommus = <&apps_smmu 0x6c3 0x0>;
1670                         #address-cells = <2>;
1671                         #size-cells = <2>;
1672                         ranges;
1673                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1674                         interconnect-names = "qup-core";
1675                         status = "disabled";
1676
1677                         i2c8: i2c@a80000 {
1678                                 compatible = "qcom,geni-i2c";
1679                                 reg = <0 0x00a80000 0 0x4000>;
1680                                 clock-names = "se";
1681                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1682                                 pinctrl-names = "default";
1683                                 pinctrl-0 = <&qup_i2c8_default>;
1684                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1685                                 #address-cells = <1>;
1686                                 #size-cells = <0>;
1687                                 power-domains = <&rpmhpd SDM845_CX>;
1688                                 operating-points-v2 = <&qup_opp_table>;
1689                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1690                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1691                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1692                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1693                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1694                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1695                                 dma-names = "tx", "rx";
1696                                 status = "disabled";
1697                         };
1698
1699                         spi8: spi@a80000 {
1700                                 compatible = "qcom,geni-spi";
1701                                 reg = <0 0x00a80000 0 0x4000>;
1702                                 clock-names = "se";
1703                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1704                                 pinctrl-names = "default";
1705                                 pinctrl-0 = <&qup_spi8_default>;
1706                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1707                                 #address-cells = <1>;
1708                                 #size-cells = <0>;
1709                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1710                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1711                                 interconnect-names = "qup-core", "qup-config";
1712                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1713                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1714                                 dma-names = "tx", "rx";
1715                                 status = "disabled";
1716                         };
1717
1718                         uart8: serial@a80000 {
1719                                 compatible = "qcom,geni-uart";
1720                                 reg = <0 0x00a80000 0 0x4000>;
1721                                 clock-names = "se";
1722                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1723                                 pinctrl-names = "default";
1724                                 pinctrl-0 = <&qup_uart8_default>;
1725                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1726                                 power-domains = <&rpmhpd SDM845_CX>;
1727                                 operating-points-v2 = <&qup_opp_table>;
1728                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1729                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1730                                 interconnect-names = "qup-core", "qup-config";
1731                                 status = "disabled";
1732                         };
1733
1734                         i2c9: i2c@a84000 {
1735                                 compatible = "qcom,geni-i2c";
1736                                 reg = <0 0x00a84000 0 0x4000>;
1737                                 clock-names = "se";
1738                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1739                                 pinctrl-names = "default";
1740                                 pinctrl-0 = <&qup_i2c9_default>;
1741                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1742                                 #address-cells = <1>;
1743                                 #size-cells = <0>;
1744                                 power-domains = <&rpmhpd SDM845_CX>;
1745                                 operating-points-v2 = <&qup_opp_table>;
1746                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1747                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1748                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1749                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1750                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1751                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1752                                 dma-names = "tx", "rx";
1753                                 status = "disabled";
1754                         };
1755
1756                         spi9: spi@a84000 {
1757                                 compatible = "qcom,geni-spi";
1758                                 reg = <0 0x00a84000 0 0x4000>;
1759                                 clock-names = "se";
1760                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1761                                 pinctrl-names = "default";
1762                                 pinctrl-0 = <&qup_spi9_default>;
1763                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1764                                 #address-cells = <1>;
1765                                 #size-cells = <0>;
1766                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1767                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1768                                 interconnect-names = "qup-core", "qup-config";
1769                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1770                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1771                                 dma-names = "tx", "rx";
1772                                 status = "disabled";
1773                         };
1774
1775                         uart9: serial@a84000 {
1776                                 compatible = "qcom,geni-debug-uart";
1777                                 reg = <0 0x00a84000 0 0x4000>;
1778                                 clock-names = "se";
1779                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1780                                 pinctrl-names = "default";
1781                                 pinctrl-0 = <&qup_uart9_default>;
1782                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1783                                 power-domains = <&rpmhpd SDM845_CX>;
1784                                 operating-points-v2 = <&qup_opp_table>;
1785                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1786                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1787                                 interconnect-names = "qup-core", "qup-config";
1788                                 status = "disabled";
1789                         };
1790
1791                         i2c10: i2c@a88000 {
1792                                 compatible = "qcom,geni-i2c";
1793                                 reg = <0 0x00a88000 0 0x4000>;
1794                                 clock-names = "se";
1795                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1796                                 pinctrl-names = "default";
1797                                 pinctrl-0 = <&qup_i2c10_default>;
1798                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1799                                 #address-cells = <1>;
1800                                 #size-cells = <0>;
1801                                 power-domains = <&rpmhpd SDM845_CX>;
1802                                 operating-points-v2 = <&qup_opp_table>;
1803                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1804                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1805                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1806                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1807                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1808                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1809                                 dma-names = "tx", "rx";
1810                                 status = "disabled";
1811                         };
1812
1813                         spi10: spi@a88000 {
1814                                 compatible = "qcom,geni-spi";
1815                                 reg = <0 0x00a88000 0 0x4000>;
1816                                 clock-names = "se";
1817                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1818                                 pinctrl-names = "default";
1819                                 pinctrl-0 = <&qup_spi10_default>;
1820                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1821                                 #address-cells = <1>;
1822                                 #size-cells = <0>;
1823                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1824                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1825                                 interconnect-names = "qup-core", "qup-config";
1826                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1827                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1828                                 dma-names = "tx", "rx";
1829                                 status = "disabled";
1830                         };
1831
1832                         uart10: serial@a88000 {
1833                                 compatible = "qcom,geni-uart";
1834                                 reg = <0 0x00a88000 0 0x4000>;
1835                                 clock-names = "se";
1836                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1837                                 pinctrl-names = "default";
1838                                 pinctrl-0 = <&qup_uart10_default>;
1839                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1840                                 power-domains = <&rpmhpd SDM845_CX>;
1841                                 operating-points-v2 = <&qup_opp_table>;
1842                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1843                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1844                                 interconnect-names = "qup-core", "qup-config";
1845                                 status = "disabled";
1846                         };
1847
1848                         i2c11: i2c@a8c000 {
1849                                 compatible = "qcom,geni-i2c";
1850                                 reg = <0 0x00a8c000 0 0x4000>;
1851                                 clock-names = "se";
1852                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1853                                 pinctrl-names = "default";
1854                                 pinctrl-0 = <&qup_i2c11_default>;
1855                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1856                                 #address-cells = <1>;
1857                                 #size-cells = <0>;
1858                                 power-domains = <&rpmhpd SDM845_CX>;
1859                                 operating-points-v2 = <&qup_opp_table>;
1860                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1861                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1862                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1863                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1864                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1865                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1866                                 dma-names = "tx", "rx";
1867                                 status = "disabled";
1868                         };
1869
1870                         spi11: spi@a8c000 {
1871                                 compatible = "qcom,geni-spi";
1872                                 reg = <0 0x00a8c000 0 0x4000>;
1873                                 clock-names = "se";
1874                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1875                                 pinctrl-names = "default";
1876                                 pinctrl-0 = <&qup_spi11_default>;
1877                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1878                                 #address-cells = <1>;
1879                                 #size-cells = <0>;
1880                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1881                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1882                                 interconnect-names = "qup-core", "qup-config";
1883                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1884                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1885                                 dma-names = "tx", "rx";
1886                                 status = "disabled";
1887                         };
1888
1889                         uart11: serial@a8c000 {
1890                                 compatible = "qcom,geni-uart";
1891                                 reg = <0 0x00a8c000 0 0x4000>;
1892                                 clock-names = "se";
1893                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1894                                 pinctrl-names = "default";
1895                                 pinctrl-0 = <&qup_uart11_default>;
1896                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1897                                 power-domains = <&rpmhpd SDM845_CX>;
1898                                 operating-points-v2 = <&qup_opp_table>;
1899                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1900                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1901                                 interconnect-names = "qup-core", "qup-config";
1902                                 status = "disabled";
1903                         };
1904
1905                         i2c12: i2c@a90000 {
1906                                 compatible = "qcom,geni-i2c";
1907                                 reg = <0 0x00a90000 0 0x4000>;
1908                                 clock-names = "se";
1909                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1910                                 pinctrl-names = "default";
1911                                 pinctrl-0 = <&qup_i2c12_default>;
1912                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1913                                 #address-cells = <1>;
1914                                 #size-cells = <0>;
1915                                 power-domains = <&rpmhpd SDM845_CX>;
1916                                 operating-points-v2 = <&qup_opp_table>;
1917                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1918                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1919                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1920                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1921                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1922                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1923                                 dma-names = "tx", "rx";
1924                                 status = "disabled";
1925                         };
1926
1927                         spi12: spi@a90000 {
1928                                 compatible = "qcom,geni-spi";
1929                                 reg = <0 0x00a90000 0 0x4000>;
1930                                 clock-names = "se";
1931                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1932                                 pinctrl-names = "default";
1933                                 pinctrl-0 = <&qup_spi12_default>;
1934                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1935                                 #address-cells = <1>;
1936                                 #size-cells = <0>;
1937                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1938                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1939                                 interconnect-names = "qup-core", "qup-config";
1940                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1941                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1942                                 dma-names = "tx", "rx";
1943                                 status = "disabled";
1944                         };
1945
1946                         uart12: serial@a90000 {
1947                                 compatible = "qcom,geni-uart";
1948                                 reg = <0 0x00a90000 0 0x4000>;
1949                                 clock-names = "se";
1950                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1951                                 pinctrl-names = "default";
1952                                 pinctrl-0 = <&qup_uart12_default>;
1953                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1954                                 power-domains = <&rpmhpd SDM845_CX>;
1955                                 operating-points-v2 = <&qup_opp_table>;
1956                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1957                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1958                                 interconnect-names = "qup-core", "qup-config";
1959                                 status = "disabled";
1960                         };
1961
1962                         i2c13: i2c@a94000 {
1963                                 compatible = "qcom,geni-i2c";
1964                                 reg = <0 0x00a94000 0 0x4000>;
1965                                 clock-names = "se";
1966                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1967                                 pinctrl-names = "default";
1968                                 pinctrl-0 = <&qup_i2c13_default>;
1969                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1970                                 #address-cells = <1>;
1971                                 #size-cells = <0>;
1972                                 power-domains = <&rpmhpd SDM845_CX>;
1973                                 operating-points-v2 = <&qup_opp_table>;
1974                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1975                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1976                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1977                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1978                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1979                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1980                                 dma-names = "tx", "rx";
1981                                 status = "disabled";
1982                         };
1983
1984                         spi13: spi@a94000 {
1985                                 compatible = "qcom,geni-spi";
1986                                 reg = <0 0x00a94000 0 0x4000>;
1987                                 clock-names = "se";
1988                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1989                                 pinctrl-names = "default";
1990                                 pinctrl-0 = <&qup_spi13_default>;
1991                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1992                                 #address-cells = <1>;
1993                                 #size-cells = <0>;
1994                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1995                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1996                                 interconnect-names = "qup-core", "qup-config";
1997                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1998                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1999                                 dma-names = "tx", "rx";
2000                                 status = "disabled";
2001                         };
2002
2003                         uart13: serial@a94000 {
2004                                 compatible = "qcom,geni-uart";
2005                                 reg = <0 0x00a94000 0 0x4000>;
2006                                 clock-names = "se";
2007                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2008                                 pinctrl-names = "default";
2009                                 pinctrl-0 = <&qup_uart13_default>;
2010                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2011                                 power-domains = <&rpmhpd SDM845_CX>;
2012                                 operating-points-v2 = <&qup_opp_table>;
2013                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2014                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2015                                 interconnect-names = "qup-core", "qup-config";
2016                                 status = "disabled";
2017                         };
2018
2019                         i2c14: i2c@a98000 {
2020                                 compatible = "qcom,geni-i2c";
2021                                 reg = <0 0x00a98000 0 0x4000>;
2022                                 clock-names = "se";
2023                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2024                                 pinctrl-names = "default";
2025                                 pinctrl-0 = <&qup_i2c14_default>;
2026                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2027                                 #address-cells = <1>;
2028                                 #size-cells = <0>;
2029                                 power-domains = <&rpmhpd SDM845_CX>;
2030                                 operating-points-v2 = <&qup_opp_table>;
2031                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2032                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2033                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2034                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2035                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2036                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2037                                 dma-names = "tx", "rx";
2038                                 status = "disabled";
2039                         };
2040
2041                         spi14: spi@a98000 {
2042                                 compatible = "qcom,geni-spi";
2043                                 reg = <0 0x00a98000 0 0x4000>;
2044                                 clock-names = "se";
2045                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2046                                 pinctrl-names = "default";
2047                                 pinctrl-0 = <&qup_spi14_default>;
2048                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2049                                 #address-cells = <1>;
2050                                 #size-cells = <0>;
2051                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2052                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2053                                 interconnect-names = "qup-core", "qup-config";
2054                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2055                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2056                                 dma-names = "tx", "rx";
2057                                 status = "disabled";
2058                         };
2059
2060                         uart14: serial@a98000 {
2061                                 compatible = "qcom,geni-uart";
2062                                 reg = <0 0x00a98000 0 0x4000>;
2063                                 clock-names = "se";
2064                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2065                                 pinctrl-names = "default";
2066                                 pinctrl-0 = <&qup_uart14_default>;
2067                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2068                                 power-domains = <&rpmhpd SDM845_CX>;
2069                                 operating-points-v2 = <&qup_opp_table>;
2070                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2071                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2072                                 interconnect-names = "qup-core", "qup-config";
2073                                 status = "disabled";
2074                         };
2075
2076                         i2c15: i2c@a9c000 {
2077                                 compatible = "qcom,geni-i2c";
2078                                 reg = <0 0x00a9c000 0 0x4000>;
2079                                 clock-names = "se";
2080                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2081                                 pinctrl-names = "default";
2082                                 pinctrl-0 = <&qup_i2c15_default>;
2083                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2084                                 #address-cells = <1>;
2085                                 #size-cells = <0>;
2086                                 power-domains = <&rpmhpd SDM845_CX>;
2087                                 operating-points-v2 = <&qup_opp_table>;
2088                                 status = "disabled";
2089                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2090                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2091                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2092                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2093                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2094                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2095                                 dma-names = "tx", "rx";
2096                         };
2097
2098                         spi15: spi@a9c000 {
2099                                 compatible = "qcom,geni-spi";
2100                                 reg = <0 0x00a9c000 0 0x4000>;
2101                                 clock-names = "se";
2102                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2103                                 pinctrl-names = "default";
2104                                 pinctrl-0 = <&qup_spi15_default>;
2105                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2106                                 #address-cells = <1>;
2107                                 #size-cells = <0>;
2108                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2109                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2110                                 interconnect-names = "qup-core", "qup-config";
2111                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2112                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2113                                 dma-names = "tx", "rx";
2114                                 status = "disabled";
2115                         };
2116
2117                         uart15: serial@a9c000 {
2118                                 compatible = "qcom,geni-uart";
2119                                 reg = <0 0x00a9c000 0 0x4000>;
2120                                 clock-names = "se";
2121                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2122                                 pinctrl-names = "default";
2123                                 pinctrl-0 = <&qup_uart15_default>;
2124                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2125                                 power-domains = <&rpmhpd SDM845_CX>;
2126                                 operating-points-v2 = <&qup_opp_table>;
2127                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2128                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2129                                 interconnect-names = "qup-core", "qup-config";
2130                                 status = "disabled";
2131                         };
2132                 };
2133
2134                 llcc: system-cache-controller@1100000 {
2135                         compatible = "qcom,sdm845-llcc";
2136                         reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2137                         reg-names = "llcc_base", "llcc_broadcast_base";
2138                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2139                 };
2140
2141                 pmu@114a000 {
2142                         compatible = "qcom,sdm845-llcc-bwmon";
2143                         reg = <0 0x0114a000 0 0x1000>;
2144                         interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2145                         interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2146
2147                         operating-points-v2 = <&llcc_bwmon_opp_table>;
2148
2149                         llcc_bwmon_opp_table: opp-table {
2150                                 compatible = "operating-points-v2";
2151
2152                                 /*
2153                                  * The interconnect path bandwidth taken from
2154                                  * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2155                                  * interconnect.  This also matches the
2156                                  * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2157                                  * bus width: 4 bytes) from msm-4.9 downstream
2158                                  * kernel.
2159                                  */
2160                                 opp-0 {
2161                                         opp-peak-kBps = <800000>;
2162                                 };
2163                                 opp-1 {
2164                                         opp-peak-kBps = <1804000>;
2165                                 };
2166                                 opp-2 {
2167                                         opp-peak-kBps = <3072000>;
2168                                 };
2169                                 opp-3 {
2170                                         opp-peak-kBps = <5412000>;
2171                                 };
2172                                 opp-4 {
2173                                         opp-peak-kBps = <7216000>;
2174                                 };
2175                         };
2176                 };
2177
2178                 pmu@1436400 {
2179                         compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
2180                         reg = <0 0x01436400 0 0x600>;
2181                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2182                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2183
2184                         operating-points-v2 = <&cpu_bwmon_opp_table>;
2185
2186                         cpu_bwmon_opp_table: opp-table {
2187                                 compatible = "operating-points-v2";
2188
2189                                 /*
2190                                  * The interconnect path bandwidth taken from
2191                                  * cpu4_opp_table bandwidth for OSM L3
2192                                  * interconnect.  This also matches the OSM L3
2193                                  * from bandwidth table of qcom,cpu4-l3lat-mon
2194                                  * (qcom,core-dev-table, bus width: 16 bytes)
2195                                  * from msm-4.9 downstream kernel.
2196                                  */
2197                                 opp-0 {
2198                                         opp-peak-kBps = <4800000>;
2199                                 };
2200                                 opp-1 {
2201                                         opp-peak-kBps = <9216000>;
2202                                 };
2203                                 opp-2 {
2204                                         opp-peak-kBps = <15052800>;
2205                                 };
2206                                 opp-3 {
2207                                         opp-peak-kBps = <20889600>;
2208                                 };
2209                                 opp-4 {
2210                                         opp-peak-kBps = <25497600>;
2211                                 };
2212                         };
2213                 };
2214
2215                 pcie0: pci@1c00000 {
2216                         compatible = "qcom,pcie-sdm845";
2217                         reg = <0 0x01c00000 0 0x2000>,
2218                               <0 0x60000000 0 0xf1d>,
2219                               <0 0x60000f20 0 0xa8>,
2220                               <0 0x60100000 0 0x100000>;
2221                         reg-names = "parf", "dbi", "elbi", "config";
2222                         device_type = "pci";
2223                         linux,pci-domain = <0>;
2224                         bus-range = <0x00 0xff>;
2225                         num-lanes = <1>;
2226
2227                         #address-cells = <3>;
2228                         #size-cells = <2>;
2229
2230                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2231                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2232
2233                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2234                         interrupt-names = "msi";
2235                         #interrupt-cells = <1>;
2236                         interrupt-map-mask = <0 0 0 0x7>;
2237                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2238                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2239                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2240                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2241
2242                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2243                                  <&gcc GCC_PCIE_0_AUX_CLK>,
2244                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2245                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2246                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2247                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2248                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2249                         clock-names = "pipe",
2250                                       "aux",
2251                                       "cfg",
2252                                       "bus_master",
2253                                       "bus_slave",
2254                                       "slave_q2a",
2255                                       "tbu";
2256
2257                         iommus = <&apps_smmu 0x1c10 0xf>;
2258                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
2259                                     <0x100 &apps_smmu 0x1c11 0x1>,
2260                                     <0x200 &apps_smmu 0x1c12 0x1>,
2261                                     <0x300 &apps_smmu 0x1c13 0x1>,
2262                                     <0x400 &apps_smmu 0x1c14 0x1>,
2263                                     <0x500 &apps_smmu 0x1c15 0x1>,
2264                                     <0x600 &apps_smmu 0x1c16 0x1>,
2265                                     <0x700 &apps_smmu 0x1c17 0x1>,
2266                                     <0x800 &apps_smmu 0x1c18 0x1>,
2267                                     <0x900 &apps_smmu 0x1c19 0x1>,
2268                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
2269                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
2270                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
2271                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
2272                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
2273                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
2274
2275                         resets = <&gcc GCC_PCIE_0_BCR>;
2276                         reset-names = "pci";
2277
2278                         power-domains = <&gcc PCIE_0_GDSC>;
2279
2280                         phys = <&pcie0_lane>;
2281                         phy-names = "pciephy";
2282
2283                         status = "disabled";
2284                 };
2285
2286                 pcie0_phy: phy@1c06000 {
2287                         compatible = "qcom,sdm845-qmp-pcie-phy";
2288                         reg = <0 0x01c06000 0 0x18c>;
2289                         #address-cells = <2>;
2290                         #size-cells = <2>;
2291                         ranges;
2292                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2293                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2294                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
2295                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2296                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2297
2298                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2299                         reset-names = "phy";
2300
2301                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2302                         assigned-clock-rates = <100000000>;
2303
2304                         status = "disabled";
2305
2306                         pcie0_lane: phy@1c06200 {
2307                                 reg = <0 0x01c06200 0 0x128>,
2308                                       <0 0x01c06400 0 0x1fc>,
2309                                       <0 0x01c06800 0 0x218>,
2310                                       <0 0x01c06600 0 0x70>;
2311                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
2312                                 clock-names = "pipe0";
2313
2314                                 #clock-cells = <0>;
2315                                 #phy-cells = <0>;
2316                                 clock-output-names = "pcie_0_pipe_clk";
2317                         };
2318                 };
2319
2320                 pcie1: pci@1c08000 {
2321                         compatible = "qcom,pcie-sdm845";
2322                         reg = <0 0x01c08000 0 0x2000>,
2323                               <0 0x40000000 0 0xf1d>,
2324                               <0 0x40000f20 0 0xa8>,
2325                               <0 0x40100000 0 0x100000>;
2326                         reg-names = "parf", "dbi", "elbi", "config";
2327                         device_type = "pci";
2328                         linux,pci-domain = <1>;
2329                         bus-range = <0x00 0xff>;
2330                         num-lanes = <1>;
2331
2332                         #address-cells = <3>;
2333                         #size-cells = <2>;
2334
2335                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2336                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2337
2338                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2339                         interrupt-names = "msi";
2340                         #interrupt-cells = <1>;
2341                         interrupt-map-mask = <0 0 0 0x7>;
2342                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2343                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2344                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2345                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2346
2347                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2348                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2349                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2350                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2351                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2352                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2353                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2354                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2355                         clock-names = "pipe",
2356                                       "aux",
2357                                       "cfg",
2358                                       "bus_master",
2359                                       "bus_slave",
2360                                       "slave_q2a",
2361                                       "ref",
2362                                       "tbu";
2363
2364                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2365                         assigned-clock-rates = <19200000>;
2366
2367                         iommus = <&apps_smmu 0x1c00 0xf>;
2368                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2369                                     <0x100 &apps_smmu 0x1c01 0x1>,
2370                                     <0x200 &apps_smmu 0x1c02 0x1>,
2371                                     <0x300 &apps_smmu 0x1c03 0x1>,
2372                                     <0x400 &apps_smmu 0x1c04 0x1>,
2373                                     <0x500 &apps_smmu 0x1c05 0x1>,
2374                                     <0x600 &apps_smmu 0x1c06 0x1>,
2375                                     <0x700 &apps_smmu 0x1c07 0x1>,
2376                                     <0x800 &apps_smmu 0x1c08 0x1>,
2377                                     <0x900 &apps_smmu 0x1c09 0x1>,
2378                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
2379                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
2380                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
2381                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
2382                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
2383                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
2384
2385                         resets = <&gcc GCC_PCIE_1_BCR>;
2386                         reset-names = "pci";
2387
2388                         power-domains = <&gcc PCIE_1_GDSC>;
2389
2390                         phys = <&pcie1_lane>;
2391                         phy-names = "pciephy";
2392
2393                         status = "disabled";
2394                 };
2395
2396                 pcie1_phy: phy@1c0a000 {
2397                         compatible = "qcom,sdm845-qhp-pcie-phy";
2398                         reg = <0 0x01c0a000 0 0x800>;
2399                         #address-cells = <2>;
2400                         #size-cells = <2>;
2401                         ranges;
2402                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2403                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2404                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2405                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2406                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2407
2408                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2409                         reset-names = "phy";
2410
2411                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2412                         assigned-clock-rates = <100000000>;
2413
2414                         status = "disabled";
2415
2416                         pcie1_lane: phy@1c06200 {
2417                                 reg = <0 0x01c0a800 0 0x800>,
2418                                       <0 0x01c0a800 0 0x800>,
2419                                       <0 0x01c0b800 0 0x400>;
2420                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2421                                 clock-names = "pipe0";
2422
2423                                 #clock-cells = <0>;
2424                                 #phy-cells = <0>;
2425                                 clock-output-names = "pcie_1_pipe_clk";
2426                         };
2427                 };
2428
2429                 mem_noc: interconnect@1380000 {
2430                         compatible = "qcom,sdm845-mem-noc";
2431                         reg = <0 0x01380000 0 0x27200>;
2432                         #interconnect-cells = <2>;
2433                         qcom,bcm-voters = <&apps_bcm_voter>;
2434                 };
2435
2436                 dc_noc: interconnect@14e0000 {
2437                         compatible = "qcom,sdm845-dc-noc";
2438                         reg = <0 0x014e0000 0 0x400>;
2439                         #interconnect-cells = <2>;
2440                         qcom,bcm-voters = <&apps_bcm_voter>;
2441                 };
2442
2443                 config_noc: interconnect@1500000 {
2444                         compatible = "qcom,sdm845-config-noc";
2445                         reg = <0 0x01500000 0 0x5080>;
2446                         #interconnect-cells = <2>;
2447                         qcom,bcm-voters = <&apps_bcm_voter>;
2448                 };
2449
2450                 system_noc: interconnect@1620000 {
2451                         compatible = "qcom,sdm845-system-noc";
2452                         reg = <0 0x01620000 0 0x18080>;
2453                         #interconnect-cells = <2>;
2454                         qcom,bcm-voters = <&apps_bcm_voter>;
2455                 };
2456
2457                 aggre1_noc: interconnect@16e0000 {
2458                         compatible = "qcom,sdm845-aggre1-noc";
2459                         reg = <0 0x016e0000 0 0x15080>;
2460                         #interconnect-cells = <2>;
2461                         qcom,bcm-voters = <&apps_bcm_voter>;
2462                 };
2463
2464                 aggre2_noc: interconnect@1700000 {
2465                         compatible = "qcom,sdm845-aggre2-noc";
2466                         reg = <0 0x01700000 0 0x1f300>;
2467                         #interconnect-cells = <2>;
2468                         qcom,bcm-voters = <&apps_bcm_voter>;
2469                 };
2470
2471                 mmss_noc: interconnect@1740000 {
2472                         compatible = "qcom,sdm845-mmss-noc";
2473                         reg = <0 0x01740000 0 0x1c100>;
2474                         #interconnect-cells = <2>;
2475                         qcom,bcm-voters = <&apps_bcm_voter>;
2476                 };
2477
2478                 ufs_mem_hc: ufshc@1d84000 {
2479                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2480                                      "jedec,ufs-2.0";
2481                         reg = <0 0x01d84000 0 0x2500>,
2482                               <0 0x01d90000 0 0x8000>;
2483                         reg-names = "std", "ice";
2484                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2485                         phys = <&ufs_mem_phy_lanes>;
2486                         phy-names = "ufsphy";
2487                         lanes-per-direction = <2>;
2488                         power-domains = <&gcc UFS_PHY_GDSC>;
2489                         #reset-cells = <1>;
2490                         resets = <&gcc GCC_UFS_PHY_BCR>;
2491                         reset-names = "rst";
2492
2493                         iommus = <&apps_smmu 0x100 0xf>;
2494
2495                         clock-names =
2496                                 "core_clk",
2497                                 "bus_aggr_clk",
2498                                 "iface_clk",
2499                                 "core_clk_unipro",
2500                                 "ref_clk",
2501                                 "tx_lane0_sync_clk",
2502                                 "rx_lane0_sync_clk",
2503                                 "rx_lane1_sync_clk",
2504                                 "ice_core_clk";
2505                         clocks =
2506                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2507                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2508                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2509                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2510                                 <&rpmhcc RPMH_CXO_CLK>,
2511                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2512                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2513                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2514                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2515                         freq-table-hz =
2516                                 <50000000 200000000>,
2517                                 <0 0>,
2518                                 <0 0>,
2519                                 <37500000 150000000>,
2520                                 <0 0>,
2521                                 <0 0>,
2522                                 <0 0>,
2523                                 <0 0>,
2524                                 <75000000 300000000>;
2525
2526                         status = "disabled";
2527                 };
2528
2529                 ufs_mem_phy: phy@1d87000 {
2530                         compatible = "qcom,sdm845-qmp-ufs-phy";
2531                         reg = <0 0x01d87000 0 0x18c>;
2532                         #address-cells = <2>;
2533                         #size-cells = <2>;
2534                         ranges;
2535                         clock-names = "ref",
2536                                       "ref_aux";
2537                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2538                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2539
2540                         resets = <&ufs_mem_hc 0>;
2541                         reset-names = "ufsphy";
2542                         status = "disabled";
2543
2544                         ufs_mem_phy_lanes: phy@1d87400 {
2545                                 reg = <0 0x01d87400 0 0x108>,
2546                                       <0 0x01d87600 0 0x1e0>,
2547                                       <0 0x01d87c00 0 0x1dc>,
2548                                       <0 0x01d87800 0 0x108>,
2549                                       <0 0x01d87a00 0 0x1e0>;
2550                                 #phy-cells = <0>;
2551                         };
2552                 };
2553
2554                 cryptobam: dma-controller@1dc4000 {
2555                         compatible = "qcom,bam-v1.7.0";
2556                         reg = <0 0x01dc4000 0 0x24000>;
2557                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2558                         clocks = <&rpmhcc RPMH_CE_CLK>;
2559                         clock-names = "bam_clk";
2560                         #dma-cells = <1>;
2561                         qcom,ee = <0>;
2562                         qcom,controlled-remotely;
2563                         iommus = <&apps_smmu 0x704 0x1>,
2564                                  <&apps_smmu 0x706 0x1>,
2565                                  <&apps_smmu 0x714 0x1>,
2566                                  <&apps_smmu 0x716 0x1>;
2567                 };
2568
2569                 crypto: crypto@1dfa000 {
2570                         compatible = "qcom,crypto-v5.4";
2571                         reg = <0 0x01dfa000 0 0x6000>;
2572                         clocks = <&gcc GCC_CE1_AHB_CLK>,
2573                                  <&gcc GCC_CE1_AXI_CLK>,
2574                                  <&rpmhcc RPMH_CE_CLK>;
2575                         clock-names = "iface", "bus", "core";
2576                         dmas = <&cryptobam 6>, <&cryptobam 7>;
2577                         dma-names = "rx", "tx";
2578                         iommus = <&apps_smmu 0x704 0x1>,
2579                                  <&apps_smmu 0x706 0x1>,
2580                                  <&apps_smmu 0x714 0x1>,
2581                                  <&apps_smmu 0x716 0x1>;
2582                 };
2583
2584                 ipa: ipa@1e40000 {
2585                         compatible = "qcom,sdm845-ipa";
2586
2587                         iommus = <&apps_smmu 0x720 0x0>,
2588                                  <&apps_smmu 0x722 0x0>;
2589                         reg = <0 0x1e40000 0 0x7000>,
2590                               <0 0x1e47000 0 0x2000>,
2591                               <0 0x1e04000 0 0x2c000>;
2592                         reg-names = "ipa-reg",
2593                                     "ipa-shared",
2594                                     "gsi";
2595
2596                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2597                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2598                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2599                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2600                         interrupt-names = "ipa",
2601                                           "gsi",
2602                                           "ipa-clock-query",
2603                                           "ipa-setup-ready";
2604
2605                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2606                         clock-names = "core";
2607
2608                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2609                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2610                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2611                         interconnect-names = "memory",
2612                                              "imem",
2613                                              "config";
2614
2615                         qcom,smem-states = <&ipa_smp2p_out 0>,
2616                                            <&ipa_smp2p_out 1>;
2617                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2618                                                 "ipa-clock-enabled";
2619
2620                         status = "disabled";
2621                 };
2622
2623                 tcsr_mutex: hwlock@1f40000 {
2624                         compatible = "qcom,tcsr-mutex";
2625                         reg = <0 0x01f40000 0 0x20000>;
2626                         #hwlock-cells = <1>;
2627                 };
2628
2629                 tcsr_regs_1: syscon@1f60000 {
2630                         compatible = "qcom,sdm845-tcsr", "syscon";
2631                         reg = <0 0x01f60000 0 0x20000>;
2632                 };
2633
2634                 tlmm: pinctrl@3400000 {
2635                         compatible = "qcom,sdm845-pinctrl";
2636                         reg = <0 0x03400000 0 0xc00000>;
2637                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2638                         gpio-controller;
2639                         #gpio-cells = <2>;
2640                         interrupt-controller;
2641                         #interrupt-cells = <2>;
2642                         gpio-ranges = <&tlmm 0 0 151>;
2643                         wakeup-parent = <&pdc_intc>;
2644
2645                         cci0_default: cci0-default {
2646                                 /* SDA, SCL */
2647                                 pins = "gpio17", "gpio18";
2648                                 function = "cci_i2c";
2649
2650                                 bias-pull-up;
2651                                 drive-strength = <2>; /* 2 mA */
2652                         };
2653
2654                         cci0_sleep: cci0-sleep {
2655                                 /* SDA, SCL */
2656                                 pins = "gpio17", "gpio18";
2657                                 function = "cci_i2c";
2658
2659                                 drive-strength = <2>; /* 2 mA */
2660                                 bias-pull-down;
2661                         };
2662
2663                         cci1_default: cci1-default {
2664                                 /* SDA, SCL */
2665                                 pins = "gpio19", "gpio20";
2666                                 function = "cci_i2c";
2667
2668                                 bias-pull-up;
2669                                 drive-strength = <2>; /* 2 mA */
2670                         };
2671
2672                         cci1_sleep: cci1-sleep {
2673                                 /* SDA, SCL */
2674                                 pins = "gpio19", "gpio20";
2675                                 function = "cci_i2c";
2676
2677                                 drive-strength = <2>; /* 2 mA */
2678                                 bias-pull-down;
2679                         };
2680
2681                         qspi_clk: qspi-clk {
2682                                 pinmux {
2683                                         pins = "gpio95";
2684                                         function = "qspi_clk";
2685                                 };
2686                         };
2687
2688                         qspi_cs0: qspi-cs0 {
2689                                 pinmux {
2690                                         pins = "gpio90";
2691                                         function = "qspi_cs";
2692                                 };
2693                         };
2694
2695                         qspi_cs1: qspi-cs1 {
2696                                 pinmux {
2697                                         pins = "gpio89";
2698                                         function = "qspi_cs";
2699                                 };
2700                         };
2701
2702                         qspi_data01: qspi-data01 {
2703                                 pinmux-data {
2704                                         pins = "gpio91", "gpio92";
2705                                         function = "qspi_data";
2706                                 };
2707                         };
2708
2709                         qspi_data12: qspi-data12 {
2710                                 pinmux-data {
2711                                         pins = "gpio93", "gpio94";
2712                                         function = "qspi_data";
2713                                 };
2714                         };
2715
2716                         qup_i2c0_default: qup-i2c0-default {
2717                                 pinmux {
2718                                         pins = "gpio0", "gpio1";
2719                                         function = "qup0";
2720                                 };
2721                         };
2722
2723                         qup_i2c1_default: qup-i2c1-default {
2724                                 pinmux {
2725                                         pins = "gpio17", "gpio18";
2726                                         function = "qup1";
2727                                 };
2728                         };
2729
2730                         qup_i2c2_default: qup-i2c2-default {
2731                                 pinmux {
2732                                         pins = "gpio27", "gpio28";
2733                                         function = "qup2";
2734                                 };
2735                         };
2736
2737                         qup_i2c3_default: qup-i2c3-default {
2738                                 pinmux {
2739                                         pins = "gpio41", "gpio42";
2740                                         function = "qup3";
2741                                 };
2742                         };
2743
2744                         qup_i2c4_default: qup-i2c4-default {
2745                                 pinmux {
2746                                         pins = "gpio89", "gpio90";
2747                                         function = "qup4";
2748                                 };
2749                         };
2750
2751                         qup_i2c5_default: qup-i2c5-default {
2752                                 pinmux {
2753                                         pins = "gpio85", "gpio86";
2754                                         function = "qup5";
2755                                 };
2756                         };
2757
2758                         qup_i2c6_default: qup-i2c6-default {
2759                                 pinmux {
2760                                         pins = "gpio45", "gpio46";
2761                                         function = "qup6";
2762                                 };
2763                         };
2764
2765                         qup_i2c7_default: qup-i2c7-default {
2766                                 pinmux {
2767                                         pins = "gpio93", "gpio94";
2768                                         function = "qup7";
2769                                 };
2770                         };
2771
2772                         qup_i2c8_default: qup-i2c8-default {
2773                                 pinmux {
2774                                         pins = "gpio65", "gpio66";
2775                                         function = "qup8";
2776                                 };
2777                         };
2778
2779                         qup_i2c9_default: qup-i2c9-default {
2780                                 pinmux {
2781                                         pins = "gpio6", "gpio7";
2782                                         function = "qup9";
2783                                 };
2784                         };
2785
2786                         qup_i2c10_default: qup-i2c10-default {
2787                                 pinmux {
2788                                         pins = "gpio55", "gpio56";
2789                                         function = "qup10";
2790                                 };
2791                         };
2792
2793                         qup_i2c11_default: qup-i2c11-default {
2794                                 pinmux {
2795                                         pins = "gpio31", "gpio32";
2796                                         function = "qup11";
2797                                 };
2798                         };
2799
2800                         qup_i2c12_default: qup-i2c12-default {
2801                                 pinmux {
2802                                         pins = "gpio49", "gpio50";
2803                                         function = "qup12";
2804                                 };
2805                         };
2806
2807                         qup_i2c13_default: qup-i2c13-default {
2808                                 pinmux {
2809                                         pins = "gpio105", "gpio106";
2810                                         function = "qup13";
2811                                 };
2812                         };
2813
2814                         qup_i2c14_default: qup-i2c14-default {
2815                                 pinmux {
2816                                         pins = "gpio33", "gpio34";
2817                                         function = "qup14";
2818                                 };
2819                         };
2820
2821                         qup_i2c15_default: qup-i2c15-default {
2822                                 pinmux {
2823                                         pins = "gpio81", "gpio82";
2824                                         function = "qup15";
2825                                 };
2826                         };
2827
2828                         qup_spi0_default: qup-spi0-default {
2829                                 pinmux {
2830                                         pins = "gpio0", "gpio1",
2831                                                "gpio2", "gpio3";
2832                                         function = "qup0";
2833                                 };
2834
2835                                 config {
2836                                         pins = "gpio0", "gpio1",
2837                                                "gpio2", "gpio3";
2838                                         drive-strength = <6>;
2839                                         bias-disable;
2840                                 };
2841                         };
2842
2843                         qup_spi1_default: qup-spi1-default {
2844                                 pinmux {
2845                                         pins = "gpio17", "gpio18",
2846                                                "gpio19", "gpio20";
2847                                         function = "qup1";
2848                                 };
2849                         };
2850
2851                         qup_spi2_default: qup-spi2-default {
2852                                 pinmux {
2853                                         pins = "gpio27", "gpio28",
2854                                                "gpio29", "gpio30";
2855                                         function = "qup2";
2856                                 };
2857                         };
2858
2859                         qup_spi3_default: qup-spi3-default {
2860                                 pinmux {
2861                                         pins = "gpio41", "gpio42",
2862                                                "gpio43", "gpio44";
2863                                         function = "qup3";
2864                                 };
2865                         };
2866
2867                         qup_spi4_default: qup-spi4-default {
2868                                 pinmux {
2869                                         pins = "gpio89", "gpio90",
2870                                                "gpio91", "gpio92";
2871                                         function = "qup4";
2872                                 };
2873                         };
2874
2875                         qup_spi5_default: qup-spi5-default {
2876                                 pinmux {
2877                                         pins = "gpio85", "gpio86",
2878                                                "gpio87", "gpio88";
2879                                         function = "qup5";
2880                                 };
2881                         };
2882
2883                         qup_spi6_default: qup-spi6-default {
2884                                 pinmux {
2885                                         pins = "gpio45", "gpio46",
2886                                                "gpio47", "gpio48";
2887                                         function = "qup6";
2888                                 };
2889                         };
2890
2891                         qup_spi7_default: qup-spi7-default {
2892                                 pinmux {
2893                                         pins = "gpio93", "gpio94",
2894                                                "gpio95", "gpio96";
2895                                         function = "qup7";
2896                                 };
2897                         };
2898
2899                         qup_spi8_default: qup-spi8-default {
2900                                 pinmux {
2901                                         pins = "gpio65", "gpio66",
2902                                                "gpio67", "gpio68";
2903                                         function = "qup8";
2904                                 };
2905                         };
2906
2907                         qup_spi9_default: qup-spi9-default {
2908                                 pinmux {
2909                                         pins = "gpio6", "gpio7",
2910                                                "gpio4", "gpio5";
2911                                         function = "qup9";
2912                                 };
2913                         };
2914
2915                         qup_spi10_default: qup-spi10-default {
2916                                 pinmux {
2917                                         pins = "gpio55", "gpio56",
2918                                                "gpio53", "gpio54";
2919                                         function = "qup10";
2920                                 };
2921                         };
2922
2923                         qup_spi11_default: qup-spi11-default {
2924                                 pinmux {
2925                                         pins = "gpio31", "gpio32",
2926                                                "gpio33", "gpio34";
2927                                         function = "qup11";
2928                                 };
2929                         };
2930
2931                         qup_spi12_default: qup-spi12-default {
2932                                 pinmux {
2933                                         pins = "gpio49", "gpio50",
2934                                                "gpio51", "gpio52";
2935                                         function = "qup12";
2936                                 };
2937                         };
2938
2939                         qup_spi13_default: qup-spi13-default {
2940                                 pinmux {
2941                                         pins = "gpio105", "gpio106",
2942                                                "gpio107", "gpio108";
2943                                         function = "qup13";
2944                                 };
2945                         };
2946
2947                         qup_spi14_default: qup-spi14-default {
2948                                 pinmux {
2949                                         pins = "gpio33", "gpio34",
2950                                                "gpio31", "gpio32";
2951                                         function = "qup14";
2952                                 };
2953                         };
2954
2955                         qup_spi15_default: qup-spi15-default {
2956                                 pinmux {
2957                                         pins = "gpio81", "gpio82",
2958                                                "gpio83", "gpio84";
2959                                         function = "qup15";
2960                                 };
2961                         };
2962
2963                         qup_uart0_default: qup-uart0-default {
2964                                 pinmux {
2965                                         pins = "gpio2", "gpio3";
2966                                         function = "qup0";
2967                                 };
2968                         };
2969
2970                         qup_uart1_default: qup-uart1-default {
2971                                 pinmux {
2972                                         pins = "gpio19", "gpio20";
2973                                         function = "qup1";
2974                                 };
2975                         };
2976
2977                         qup_uart2_default: qup-uart2-default {
2978                                 pinmux {
2979                                         pins = "gpio29", "gpio30";
2980                                         function = "qup2";
2981                                 };
2982                         };
2983
2984                         qup_uart3_default: qup-uart3-default {
2985                                 pinmux {
2986                                         pins = "gpio43", "gpio44";
2987                                         function = "qup3";
2988                                 };
2989                         };
2990
2991                         qup_uart4_default: qup-uart4-default {
2992                                 pinmux {
2993                                         pins = "gpio91", "gpio92";
2994                                         function = "qup4";
2995                                 };
2996                         };
2997
2998                         qup_uart5_default: qup-uart5-default {
2999                                 pinmux {
3000                                         pins = "gpio87", "gpio88";
3001                                         function = "qup5";
3002                                 };
3003                         };
3004
3005                         qup_uart6_default: qup-uart6-default {
3006                                 pinmux {
3007                                         pins = "gpio47", "gpio48";
3008                                         function = "qup6";
3009                                 };
3010                         };
3011
3012                         qup_uart7_default: qup-uart7-default {
3013                                 pinmux {
3014                                         pins = "gpio95", "gpio96";
3015                                         function = "qup7";
3016                                 };
3017                         };
3018
3019                         qup_uart8_default: qup-uart8-default {
3020                                 pinmux {
3021                                         pins = "gpio67", "gpio68";
3022                                         function = "qup8";
3023                                 };
3024                         };
3025
3026                         qup_uart9_default: qup-uart9-default {
3027                                 pinmux {
3028                                         pins = "gpio4", "gpio5";
3029                                         function = "qup9";
3030                                 };
3031                         };
3032
3033                         qup_uart10_default: qup-uart10-default {
3034                                 pinmux {
3035                                         pins = "gpio53", "gpio54";
3036                                         function = "qup10";
3037                                 };
3038                         };
3039
3040                         qup_uart11_default: qup-uart11-default {
3041                                 pinmux {
3042                                         pins = "gpio33", "gpio34";
3043                                         function = "qup11";
3044                                 };
3045                         };
3046
3047                         qup_uart12_default: qup-uart12-default {
3048                                 pinmux {
3049                                         pins = "gpio51", "gpio52";
3050                                         function = "qup12";
3051                                 };
3052                         };
3053
3054                         qup_uart13_default: qup-uart13-default {
3055                                 pinmux {
3056                                         pins = "gpio107", "gpio108";
3057                                         function = "qup13";
3058                                 };
3059                         };
3060
3061                         qup_uart14_default: qup-uart14-default {
3062                                 pinmux {
3063                                         pins = "gpio31", "gpio32";
3064                                         function = "qup14";
3065                                 };
3066                         };
3067
3068                         qup_uart15_default: qup-uart15-default {
3069                                 pinmux {
3070                                         pins = "gpio83", "gpio84";
3071                                         function = "qup15";
3072                                 };
3073                         };
3074
3075                         quat_mi2s_sleep: quat_mi2s_sleep {
3076                                 mux {
3077                                         pins = "gpio58", "gpio59";
3078                                         function = "gpio";
3079                                 };
3080
3081                                 config {
3082                                         pins = "gpio58", "gpio59";
3083                                         drive-strength = <2>;
3084                                         bias-pull-down;
3085                                         input-enable;
3086                                 };
3087                         };
3088
3089                         quat_mi2s_active: quat_mi2s_active {
3090                                 mux {
3091                                         pins = "gpio58", "gpio59";
3092                                         function = "qua_mi2s";
3093                                 };
3094
3095                                 config {
3096                                         pins = "gpio58", "gpio59";
3097                                         drive-strength = <8>;
3098                                         bias-disable;
3099                                         output-high;
3100                                 };
3101                         };
3102
3103                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3104                                 mux {
3105                                         pins = "gpio60";
3106                                         function = "gpio";
3107                                 };
3108
3109                                 config {
3110                                         pins = "gpio60";
3111                                         drive-strength = <2>;
3112                                         bias-pull-down;
3113                                         input-enable;
3114                                 };
3115                         };
3116
3117                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3118                                 mux {
3119                                         pins = "gpio60";
3120                                         function = "qua_mi2s";
3121                                 };
3122
3123                                 config {
3124                                         pins = "gpio60";
3125                                         drive-strength = <8>;
3126                                         bias-disable;
3127                                 };
3128                         };
3129
3130                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3131                                 mux {
3132                                         pins = "gpio61";
3133                                         function = "gpio";
3134                                 };
3135
3136                                 config {
3137                                         pins = "gpio61";
3138                                         drive-strength = <2>;
3139                                         bias-pull-down;
3140                                         input-enable;
3141                                 };
3142                         };
3143
3144                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3145                                 mux {
3146                                         pins = "gpio61";
3147                                         function = "qua_mi2s";
3148                                 };
3149
3150                                 config {
3151                                         pins = "gpio61";
3152                                         drive-strength = <8>;
3153                                         bias-disable;
3154                                 };
3155                         };
3156
3157                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3158                                 mux {
3159                                         pins = "gpio62";
3160                                         function = "gpio";
3161                                 };
3162
3163                                 config {
3164                                         pins = "gpio62";
3165                                         drive-strength = <2>;
3166                                         bias-pull-down;
3167                                         input-enable;
3168                                 };
3169                         };
3170
3171                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3172                                 mux {
3173                                         pins = "gpio62";
3174                                         function = "qua_mi2s";
3175                                 };
3176
3177                                 config {
3178                                         pins = "gpio62";
3179                                         drive-strength = <8>;
3180                                         bias-disable;
3181                                 };
3182                         };
3183
3184                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3185                                 mux {
3186                                         pins = "gpio63";
3187                                         function = "gpio";
3188                                 };
3189
3190                                 config {
3191                                         pins = "gpio63";
3192                                         drive-strength = <2>;
3193                                         bias-pull-down;
3194                                         input-enable;
3195                                 };
3196                         };
3197
3198                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3199                                 mux {
3200                                         pins = "gpio63";
3201                                         function = "qua_mi2s";
3202                                 };
3203
3204                                 config {
3205                                         pins = "gpio63";
3206                                         drive-strength = <8>;
3207                                         bias-disable;
3208                                 };
3209                         };
3210                 };
3211
3212                 mss_pil: remoteproc@4080000 {
3213                         compatible = "qcom,sdm845-mss-pil";
3214                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3215                         reg-names = "qdsp6", "rmb";
3216
3217                         interrupts-extended =
3218                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3219                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3220                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3221                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3222                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3223                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3224                         interrupt-names = "wdog", "fatal", "ready",
3225                                           "handover", "stop-ack",
3226                                           "shutdown-ack";
3227
3228                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3229                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3230                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
3231                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3232                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
3233                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3234                                  <&gcc GCC_PRNG_AHB_CLK>,
3235                                  <&rpmhcc RPMH_CXO_CLK>;
3236                         clock-names = "iface", "bus", "mem", "gpll0_mss",
3237                                       "snoc_axi", "mnoc_axi", "prng", "xo";
3238
3239                         qcom,qmp = <&aoss_qmp>;
3240
3241                         qcom,smem-states = <&modem_smp2p_out 0>;
3242                         qcom,smem-state-names = "stop";
3243
3244                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3245                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
3246                         reset-names = "mss_restart", "pdc_reset";
3247
3248                         qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3249
3250                         power-domains = <&rpmhpd SDM845_CX>,
3251                                         <&rpmhpd SDM845_MX>,
3252                                         <&rpmhpd SDM845_MSS>;
3253                         power-domain-names = "cx", "mx", "mss";
3254
3255                         status = "disabled";
3256
3257                         mba {
3258                                 memory-region = <&mba_region>;
3259                         };
3260
3261                         mpss {
3262                                 memory-region = <&mpss_region>;
3263                         };
3264
3265                         glink-edge {
3266                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3267                                 label = "modem";
3268                                 qcom,remote-pid = <1>;
3269                                 mboxes = <&apss_shared 12>;
3270                         };
3271                 };
3272
3273                 gpucc: clock-controller@5090000 {
3274                         compatible = "qcom,sdm845-gpucc";
3275                         reg = <0 0x05090000 0 0x9000>;
3276                         #clock-cells = <1>;
3277                         #reset-cells = <1>;
3278                         #power-domain-cells = <1>;
3279                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3280                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3281                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3282                         clock-names = "bi_tcxo",
3283                                       "gcc_gpu_gpll0_clk_src",
3284                                       "gcc_gpu_gpll0_div_clk_src";
3285                 };
3286
3287                 stm@6002000 {
3288                         compatible = "arm,coresight-stm", "arm,primecell";
3289                         reg = <0 0x06002000 0 0x1000>,
3290                               <0 0x16280000 0 0x180000>;
3291                         reg-names = "stm-base", "stm-stimulus-base";
3292
3293                         clocks = <&aoss_qmp>;
3294                         clock-names = "apb_pclk";
3295
3296                         out-ports {
3297                                 port {
3298                                         stm_out: endpoint {
3299                                                 remote-endpoint =
3300                                                   <&funnel0_in7>;
3301                                         };
3302                                 };
3303                         };
3304                 };
3305
3306                 funnel@6041000 {
3307                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3308                         reg = <0 0x06041000 0 0x1000>;
3309
3310                         clocks = <&aoss_qmp>;
3311                         clock-names = "apb_pclk";
3312
3313                         out-ports {
3314                                 port {
3315                                         funnel0_out: endpoint {
3316                                                 remote-endpoint =
3317                                                   <&merge_funnel_in0>;
3318                                         };
3319                                 };
3320                         };
3321
3322                         in-ports {
3323                                 #address-cells = <1>;
3324                                 #size-cells = <0>;
3325
3326                                 port@7 {
3327                                         reg = <7>;
3328                                         funnel0_in7: endpoint {
3329                                                 remote-endpoint = <&stm_out>;
3330                                         };
3331                                 };
3332                         };
3333                 };
3334
3335                 funnel@6043000 {
3336                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3337                         reg = <0 0x06043000 0 0x1000>;
3338
3339                         clocks = <&aoss_qmp>;
3340                         clock-names = "apb_pclk";
3341
3342                         out-ports {
3343                                 port {
3344                                         funnel2_out: endpoint {
3345                                                 remote-endpoint =
3346                                                   <&merge_funnel_in2>;
3347                                         };
3348                                 };
3349                         };
3350
3351                         in-ports {
3352                                 #address-cells = <1>;
3353                                 #size-cells = <0>;
3354
3355                                 port@5 {
3356                                         reg = <5>;
3357                                         funnel2_in5: endpoint {
3358                                                 remote-endpoint =
3359                                                   <&apss_merge_funnel_out>;
3360                                         };
3361                                 };
3362                         };
3363                 };
3364
3365                 funnel@6045000 {
3366                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3367                         reg = <0 0x06045000 0 0x1000>;
3368
3369                         clocks = <&aoss_qmp>;
3370                         clock-names = "apb_pclk";
3371
3372                         out-ports {
3373                                 port {
3374                                         merge_funnel_out: endpoint {
3375                                                 remote-endpoint = <&etf_in>;
3376                                         };
3377                                 };
3378                         };
3379
3380                         in-ports {
3381                                 #address-cells = <1>;
3382                                 #size-cells = <0>;
3383
3384                                 port@0 {
3385                                         reg = <0>;
3386                                         merge_funnel_in0: endpoint {
3387                                                 remote-endpoint =
3388                                                   <&funnel0_out>;
3389                                         };
3390                                 };
3391
3392                                 port@2 {
3393                                         reg = <2>;
3394                                         merge_funnel_in2: endpoint {
3395                                                 remote-endpoint =
3396                                                   <&funnel2_out>;
3397                                         };
3398                                 };
3399                         };
3400                 };
3401
3402                 replicator@6046000 {
3403                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3404                         reg = <0 0x06046000 0 0x1000>;
3405
3406                         clocks = <&aoss_qmp>;
3407                         clock-names = "apb_pclk";
3408
3409                         out-ports {
3410                                 port {
3411                                         replicator_out: endpoint {
3412                                                 remote-endpoint = <&etr_in>;
3413                                         };
3414                                 };
3415                         };
3416
3417                         in-ports {
3418                                 port {
3419                                         replicator_in: endpoint {
3420                                                 remote-endpoint = <&etf_out>;
3421                                         };
3422                                 };
3423                         };
3424                 };
3425
3426                 etf@6047000 {
3427                         compatible = "arm,coresight-tmc", "arm,primecell";
3428                         reg = <0 0x06047000 0 0x1000>;
3429
3430                         clocks = <&aoss_qmp>;
3431                         clock-names = "apb_pclk";
3432
3433                         out-ports {
3434                                 port {
3435                                         etf_out: endpoint {
3436                                                 remote-endpoint =
3437                                                   <&replicator_in>;
3438                                         };
3439                                 };
3440                         };
3441
3442                         in-ports {
3443                                 #address-cells = <1>;
3444                                 #size-cells = <0>;
3445
3446                                 port@1 {
3447                                         reg = <1>;
3448                                         etf_in: endpoint {
3449                                                 remote-endpoint =
3450                                                   <&merge_funnel_out>;
3451                                         };
3452                                 };
3453                         };
3454                 };
3455
3456                 etr@6048000 {
3457                         compatible = "arm,coresight-tmc", "arm,primecell";
3458                         reg = <0 0x06048000 0 0x1000>;
3459
3460                         clocks = <&aoss_qmp>;
3461                         clock-names = "apb_pclk";
3462                         arm,scatter-gather;
3463
3464                         in-ports {
3465                                 port {
3466                                         etr_in: endpoint {
3467                                                 remote-endpoint =
3468                                                   <&replicator_out>;
3469                                         };
3470                                 };
3471                         };
3472                 };
3473
3474                 etm@7040000 {
3475                         compatible = "arm,coresight-etm4x", "arm,primecell";
3476                         reg = <0 0x07040000 0 0x1000>;
3477
3478                         cpu = <&CPU0>;
3479
3480                         clocks = <&aoss_qmp>;
3481                         clock-names = "apb_pclk";
3482                         arm,coresight-loses-context-with-cpu;
3483
3484                         out-ports {
3485                                 port {
3486                                         etm0_out: endpoint {
3487                                                 remote-endpoint =
3488                                                   <&apss_funnel_in0>;
3489                                         };
3490                                 };
3491                         };
3492                 };
3493
3494                 etm@7140000 {
3495                         compatible = "arm,coresight-etm4x", "arm,primecell";
3496                         reg = <0 0x07140000 0 0x1000>;
3497
3498                         cpu = <&CPU1>;
3499
3500                         clocks = <&aoss_qmp>;
3501                         clock-names = "apb_pclk";
3502                         arm,coresight-loses-context-with-cpu;
3503
3504                         out-ports {
3505                                 port {
3506                                         etm1_out: endpoint {
3507                                                 remote-endpoint =
3508                                                   <&apss_funnel_in1>;
3509                                         };
3510                                 };
3511                         };
3512                 };
3513
3514                 etm@7240000 {
3515                         compatible = "arm,coresight-etm4x", "arm,primecell";
3516                         reg = <0 0x07240000 0 0x1000>;
3517
3518                         cpu = <&CPU2>;
3519
3520                         clocks = <&aoss_qmp>;
3521                         clock-names = "apb_pclk";
3522                         arm,coresight-loses-context-with-cpu;
3523
3524                         out-ports {
3525                                 port {
3526                                         etm2_out: endpoint {
3527                                                 remote-endpoint =
3528                                                   <&apss_funnel_in2>;
3529                                         };
3530                                 };
3531                         };
3532                 };
3533
3534                 etm@7340000 {
3535                         compatible = "arm,coresight-etm4x", "arm,primecell";
3536                         reg = <0 0x07340000 0 0x1000>;
3537
3538                         cpu = <&CPU3>;
3539
3540                         clocks = <&aoss_qmp>;
3541                         clock-names = "apb_pclk";
3542                         arm,coresight-loses-context-with-cpu;
3543
3544                         out-ports {
3545                                 port {
3546                                         etm3_out: endpoint {
3547                                                 remote-endpoint =
3548                                                   <&apss_funnel_in3>;
3549                                         };
3550                                 };
3551                         };
3552                 };
3553
3554                 etm@7440000 {
3555                         compatible = "arm,coresight-etm4x", "arm,primecell";
3556                         reg = <0 0x07440000 0 0x1000>;
3557
3558                         cpu = <&CPU4>;
3559
3560                         clocks = <&aoss_qmp>;
3561                         clock-names = "apb_pclk";
3562                         arm,coresight-loses-context-with-cpu;
3563
3564                         out-ports {
3565                                 port {
3566                                         etm4_out: endpoint {
3567                                                 remote-endpoint =
3568                                                   <&apss_funnel_in4>;
3569                                         };
3570                                 };
3571                         };
3572                 };
3573
3574                 etm@7540000 {
3575                         compatible = "arm,coresight-etm4x", "arm,primecell";
3576                         reg = <0 0x07540000 0 0x1000>;
3577
3578                         cpu = <&CPU5>;
3579
3580                         clocks = <&aoss_qmp>;
3581                         clock-names = "apb_pclk";
3582                         arm,coresight-loses-context-with-cpu;
3583
3584                         out-ports {
3585                                 port {
3586                                         etm5_out: endpoint {
3587                                                 remote-endpoint =
3588                                                   <&apss_funnel_in5>;
3589                                         };
3590                                 };
3591                         };
3592                 };
3593
3594                 etm@7640000 {
3595                         compatible = "arm,coresight-etm4x", "arm,primecell";
3596                         reg = <0 0x07640000 0 0x1000>;
3597
3598                         cpu = <&CPU6>;
3599
3600                         clocks = <&aoss_qmp>;
3601                         clock-names = "apb_pclk";
3602                         arm,coresight-loses-context-with-cpu;
3603
3604                         out-ports {
3605                                 port {
3606                                         etm6_out: endpoint {
3607                                                 remote-endpoint =
3608                                                   <&apss_funnel_in6>;
3609                                         };
3610                                 };
3611                         };
3612                 };
3613
3614                 etm@7740000 {
3615                         compatible = "arm,coresight-etm4x", "arm,primecell";
3616                         reg = <0 0x07740000 0 0x1000>;
3617
3618                         cpu = <&CPU7>;
3619
3620                         clocks = <&aoss_qmp>;
3621                         clock-names = "apb_pclk";
3622                         arm,coresight-loses-context-with-cpu;
3623
3624                         out-ports {
3625                                 port {
3626                                         etm7_out: endpoint {
3627                                                 remote-endpoint =
3628                                                   <&apss_funnel_in7>;
3629                                         };
3630                                 };
3631                         };
3632                 };
3633
3634                 funnel@7800000 { /* APSS Funnel */
3635                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3636                         reg = <0 0x07800000 0 0x1000>;
3637
3638                         clocks = <&aoss_qmp>;
3639                         clock-names = "apb_pclk";
3640
3641                         out-ports {
3642                                 port {
3643                                         apss_funnel_out: endpoint {
3644                                                 remote-endpoint =
3645                                                   <&apss_merge_funnel_in>;
3646                                         };
3647                                 };
3648                         };
3649
3650                         in-ports {
3651                                 #address-cells = <1>;
3652                                 #size-cells = <0>;
3653
3654                                 port@0 {
3655                                         reg = <0>;
3656                                         apss_funnel_in0: endpoint {
3657                                                 remote-endpoint =
3658                                                   <&etm0_out>;
3659                                         };
3660                                 };
3661
3662                                 port@1 {
3663                                         reg = <1>;
3664                                         apss_funnel_in1: endpoint {
3665                                                 remote-endpoint =
3666                                                   <&etm1_out>;
3667                                         };
3668                                 };
3669
3670                                 port@2 {
3671                                         reg = <2>;
3672                                         apss_funnel_in2: endpoint {
3673                                                 remote-endpoint =
3674                                                   <&etm2_out>;
3675                                         };
3676                                 };
3677
3678                                 port@3 {
3679                                         reg = <3>;
3680                                         apss_funnel_in3: endpoint {
3681                                                 remote-endpoint =
3682                                                   <&etm3_out>;
3683                                         };
3684                                 };
3685
3686                                 port@4 {
3687                                         reg = <4>;
3688                                         apss_funnel_in4: endpoint {
3689                                                 remote-endpoint =
3690                                                   <&etm4_out>;
3691                                         };
3692                                 };
3693
3694                                 port@5 {
3695                                         reg = <5>;
3696                                         apss_funnel_in5: endpoint {
3697                                                 remote-endpoint =
3698                                                   <&etm5_out>;
3699                                         };
3700                                 };
3701
3702                                 port@6 {
3703                                         reg = <6>;
3704                                         apss_funnel_in6: endpoint {
3705                                                 remote-endpoint =
3706                                                   <&etm6_out>;
3707                                         };
3708                                 };
3709
3710                                 port@7 {
3711                                         reg = <7>;
3712                                         apss_funnel_in7: endpoint {
3713                                                 remote-endpoint =
3714                                                   <&etm7_out>;
3715                                         };
3716                                 };
3717                         };
3718                 };
3719
3720                 funnel@7810000 {
3721                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3722                         reg = <0 0x07810000 0 0x1000>;
3723
3724                         clocks = <&aoss_qmp>;
3725                         clock-names = "apb_pclk";
3726
3727                         out-ports {
3728                                 port {
3729                                         apss_merge_funnel_out: endpoint {
3730                                                 remote-endpoint =
3731                                                   <&funnel2_in5>;
3732                                         };
3733                                 };
3734                         };
3735
3736                         in-ports {
3737                                 port {
3738                                         apss_merge_funnel_in: endpoint {
3739                                                 remote-endpoint =
3740                                                   <&apss_funnel_out>;
3741                                         };
3742                                 };
3743                         };
3744                 };
3745
3746                 sdhc_2: mmc@8804000 {
3747                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3748                         reg = <0 0x08804000 0 0x1000>;
3749
3750                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3751                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3752                         interrupt-names = "hc_irq", "pwr_irq";
3753
3754                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3755                                  <&gcc GCC_SDCC2_APPS_CLK>,
3756                                  <&rpmhcc RPMH_CXO_CLK>;
3757                         clock-names = "iface", "core", "xo";
3758                         iommus = <&apps_smmu 0xa0 0xf>;
3759                         power-domains = <&rpmhpd SDM845_CX>;
3760                         operating-points-v2 = <&sdhc2_opp_table>;
3761
3762                         status = "disabled";
3763
3764                         sdhc2_opp_table: opp-table {
3765                                 compatible = "operating-points-v2";
3766
3767                                 opp-9600000 {
3768                                         opp-hz = /bits/ 64 <9600000>;
3769                                         required-opps = <&rpmhpd_opp_min_svs>;
3770                                 };
3771
3772                                 opp-19200000 {
3773                                         opp-hz = /bits/ 64 <19200000>;
3774                                         required-opps = <&rpmhpd_opp_low_svs>;
3775                                 };
3776
3777                                 opp-100000000 {
3778                                         opp-hz = /bits/ 64 <100000000>;
3779                                         required-opps = <&rpmhpd_opp_svs>;
3780                                 };
3781
3782                                 opp-201500000 {
3783                                         opp-hz = /bits/ 64 <201500000>;
3784                                         required-opps = <&rpmhpd_opp_svs_l1>;
3785                                 };
3786                         };
3787                 };
3788
3789                 qspi_opp_table: opp-table-qspi {
3790                         compatible = "operating-points-v2";
3791
3792                         opp-19200000 {
3793                                 opp-hz = /bits/ 64 <19200000>;
3794                                 required-opps = <&rpmhpd_opp_min_svs>;
3795                         };
3796
3797                         opp-100000000 {
3798                                 opp-hz = /bits/ 64 <100000000>;
3799                                 required-opps = <&rpmhpd_opp_low_svs>;
3800                         };
3801
3802                         opp-150000000 {
3803                                 opp-hz = /bits/ 64 <150000000>;
3804                                 required-opps = <&rpmhpd_opp_svs>;
3805                         };
3806
3807                         opp-300000000 {
3808                                 opp-hz = /bits/ 64 <300000000>;
3809                                 required-opps = <&rpmhpd_opp_nom>;
3810                         };
3811                 };
3812
3813                 qspi: spi@88df000 {
3814                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3815                         reg = <0 0x088df000 0 0x600>;
3816                         #address-cells = <1>;
3817                         #size-cells = <0>;
3818                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3819                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3820                                  <&gcc GCC_QSPI_CORE_CLK>;
3821                         clock-names = "iface", "core";
3822                         power-domains = <&rpmhpd SDM845_CX>;
3823                         operating-points-v2 = <&qspi_opp_table>;
3824                         status = "disabled";
3825                 };
3826
3827                 slim: slim@171c0000 {
3828                         compatible = "qcom,slim-ngd-v2.1.0";
3829                         reg = <0 0x171c0000 0 0x2c000>;
3830                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3831
3832                         qcom,apps-ch-pipes = <0x780000>;
3833                         qcom,ea-pc = <0x270>;
3834                         status = "okay";
3835                         dmas = <&slimbam 3>, <&slimbam 4>,
3836                                 <&slimbam 5>, <&slimbam 6>;
3837                         dma-names = "rx", "tx", "tx2", "rx2";
3838
3839                         iommus = <&apps_smmu 0x1806 0x0>;
3840                         #address-cells = <1>;
3841                         #size-cells = <0>;
3842
3843                         ngd@1 {
3844                                 reg = <1>;
3845                                 #address-cells = <2>;
3846                                 #size-cells = <0>;
3847
3848                                 wcd9340_ifd: ifd@0{
3849                                         compatible = "slim217,250";
3850                                         reg = <0 0>;
3851                                 };
3852
3853                                 wcd9340: codec@1{
3854                                         compatible = "slim217,250";
3855                                         reg = <1 0>;
3856                                         slim-ifc-dev = <&wcd9340_ifd>;
3857
3858                                         #sound-dai-cells = <1>;
3859
3860                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
3861                                         interrupt-controller;
3862                                         #interrupt-cells = <1>;
3863
3864                                         #clock-cells = <0>;
3865                                         clock-frequency = <9600000>;
3866                                         clock-output-names = "mclk";
3867                                         qcom,micbias1-microvolt = <1800000>;
3868                                         qcom,micbias2-microvolt = <1800000>;
3869                                         qcom,micbias3-microvolt = <1800000>;
3870                                         qcom,micbias4-microvolt = <1800000>;
3871
3872                                         #address-cells = <1>;
3873                                         #size-cells = <1>;
3874
3875                                         wcdgpio: gpio-controller@42 {
3876                                                 compatible = "qcom,wcd9340-gpio";
3877                                                 gpio-controller;
3878                                                 #gpio-cells = <2>;
3879                                                 reg = <0x42 0x2>;
3880                                         };
3881
3882                                         swm: swm@c85 {
3883                                                 compatible = "qcom,soundwire-v1.3.0";
3884                                                 reg = <0xc85 0x40>;
3885                                                 interrupts-extended = <&wcd9340 20>;
3886
3887                                                 qcom,dout-ports = <6>;
3888                                                 qcom,din-ports = <2>;
3889                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
3890                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
3891                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
3892
3893                                                 #sound-dai-cells = <1>;
3894                                                 clocks = <&wcd9340>;
3895                                                 clock-names = "iface";
3896                                                 #address-cells = <2>;
3897                                                 #size-cells = <0>;
3898
3899
3900                                         };
3901                                 };
3902                         };
3903                 };
3904
3905                 lmh_cluster1: lmh@17d70800 {
3906                         compatible = "qcom,sdm845-lmh";
3907                         reg = <0 0x17d70800 0 0x400>;
3908                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3909                         cpus = <&CPU4>;
3910                         qcom,lmh-temp-arm-millicelsius = <65000>;
3911                         qcom,lmh-temp-low-millicelsius = <94500>;
3912                         qcom,lmh-temp-high-millicelsius = <95000>;
3913                         interrupt-controller;
3914                         #interrupt-cells = <1>;
3915                 };
3916
3917                 lmh_cluster0: lmh@17d78800 {
3918                         compatible = "qcom,sdm845-lmh";
3919                         reg = <0 0x17d78800 0 0x400>;
3920                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3921                         cpus = <&CPU0>;
3922                         qcom,lmh-temp-arm-millicelsius = <65000>;
3923                         qcom,lmh-temp-low-millicelsius = <94500>;
3924                         qcom,lmh-temp-high-millicelsius = <95000>;
3925                         interrupt-controller;
3926                         #interrupt-cells = <1>;
3927                 };
3928
3929                 sound: sound {
3930                 };
3931
3932                 usb_1_hsphy: phy@88e2000 {
3933                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3934                         reg = <0 0x088e2000 0 0x400>;
3935                         status = "disabled";
3936                         #phy-cells = <0>;
3937
3938                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3939                                  <&rpmhcc RPMH_CXO_CLK>;
3940                         clock-names = "cfg_ahb", "ref";
3941
3942                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3943
3944                         nvmem-cells = <&qusb2p_hstx_trim>;
3945                 };
3946
3947                 usb_2_hsphy: phy@88e3000 {
3948                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3949                         reg = <0 0x088e3000 0 0x400>;
3950                         status = "disabled";
3951                         #phy-cells = <0>;
3952
3953                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3954                                  <&rpmhcc RPMH_CXO_CLK>;
3955                         clock-names = "cfg_ahb", "ref";
3956
3957                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3958
3959                         nvmem-cells = <&qusb2s_hstx_trim>;
3960                 };
3961
3962                 usb_1_qmpphy: phy@88e9000 {
3963                         compatible = "qcom,sdm845-qmp-usb3-phy";
3964                         reg = <0 0x088e9000 0 0x18c>,
3965                               <0 0x088e8000 0 0x10>;
3966                         status = "disabled";
3967                         #address-cells = <2>;
3968                         #size-cells = <2>;
3969                         ranges;
3970
3971                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3972                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3973                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3974                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3975                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
3976
3977                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3978                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3979                         reset-names = "phy", "common";
3980
3981                         usb_1_ssphy: phy@88e9200 {
3982                                 reg = <0 0x088e9200 0 0x128>,
3983                                       <0 0x088e9400 0 0x200>,
3984                                       <0 0x088e9c00 0 0x218>,
3985                                       <0 0x088e9600 0 0x128>,
3986                                       <0 0x088e9800 0 0x200>,
3987                                       <0 0x088e9a00 0 0x100>;
3988                                 #clock-cells = <0>;
3989                                 #phy-cells = <0>;
3990                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3991                                 clock-names = "pipe0";
3992                                 clock-output-names = "usb3_phy_pipe_clk_src";
3993                         };
3994                 };
3995
3996                 usb_2_qmpphy: phy@88eb000 {
3997                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
3998                         reg = <0 0x088eb000 0 0x18c>;
3999                         status = "disabled";
4000                         #address-cells = <2>;
4001                         #size-cells = <2>;
4002                         ranges;
4003
4004                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4005                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4006                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4007                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4008                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4009
4010                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4011                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
4012                         reset-names = "phy", "common";
4013
4014                         usb_2_ssphy: phy@88eb200 {
4015                                 reg = <0 0x088eb200 0 0x128>,
4016                                       <0 0x088eb400 0 0x1fc>,
4017                                       <0 0x088eb800 0 0x218>,
4018                                       <0 0x088eb600 0 0x70>;
4019                                 #clock-cells = <0>;
4020                                 #phy-cells = <0>;
4021                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4022                                 clock-names = "pipe0";
4023                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4024                         };
4025                 };
4026
4027                 usb_1: usb@a6f8800 {
4028                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4029                         reg = <0 0x0a6f8800 0 0x400>;
4030                         status = "disabled";
4031                         #address-cells = <2>;
4032                         #size-cells = <2>;
4033                         ranges;
4034                         dma-ranges;
4035
4036                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4037                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4038                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4039                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4040                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4041                         clock-names = "cfg_noc",
4042                                       "core",
4043                                       "iface",
4044                                       "sleep",
4045                                       "mock_utmi";
4046
4047                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4048                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4049                         assigned-clock-rates = <19200000>, <150000000>;
4050
4051                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4052                                               <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>,
4053                                               <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
4054                                               <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
4055                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
4056                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
4057
4058                         power-domains = <&gcc USB30_PRIM_GDSC>;
4059
4060                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4061
4062                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4063                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4064                         interconnect-names = "usb-ddr", "apps-usb";
4065
4066                         usb_1_dwc3: usb@a600000 {
4067                                 compatible = "snps,dwc3";
4068                                 reg = <0 0x0a600000 0 0xcd00>;
4069                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4070                                 iommus = <&apps_smmu 0x740 0>;
4071                                 snps,dis_u2_susphy_quirk;
4072                                 snps,dis_enblslpm_quirk;
4073                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4074                                 phy-names = "usb2-phy", "usb3-phy";
4075                         };
4076                 };
4077
4078                 usb_2: usb@a8f8800 {
4079                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4080                         reg = <0 0x0a8f8800 0 0x400>;
4081                         status = "disabled";
4082                         #address-cells = <2>;
4083                         #size-cells = <2>;
4084                         ranges;
4085                         dma-ranges;
4086
4087                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4088                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
4089                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4090                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4091                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4092                         clock-names = "cfg_noc",
4093                                       "core",
4094                                       "iface",
4095                                       "sleep",
4096                                       "mock_utmi";
4097
4098                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4099                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
4100                         assigned-clock-rates = <19200000>, <150000000>;
4101
4102                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4103                                               <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>,
4104                                               <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
4105                                               <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
4106                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
4107                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
4108
4109                         power-domains = <&gcc USB30_SEC_GDSC>;
4110
4111                         resets = <&gcc GCC_USB30_SEC_BCR>;
4112
4113                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4114                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4115                         interconnect-names = "usb-ddr", "apps-usb";
4116
4117                         usb_2_dwc3: usb@a800000 {
4118                                 compatible = "snps,dwc3";
4119                                 reg = <0 0x0a800000 0 0xcd00>;
4120                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4121                                 iommus = <&apps_smmu 0x760 0>;
4122                                 snps,dis_u2_susphy_quirk;
4123                                 snps,dis_enblslpm_quirk;
4124                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4125                                 phy-names = "usb2-phy", "usb3-phy";
4126                         };
4127                 };
4128
4129                 venus: video-codec@aa00000 {
4130                         compatible = "qcom,sdm845-venus-v2";
4131                         reg = <0 0x0aa00000 0 0xff000>;
4132                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4133                         power-domains = <&videocc VENUS_GDSC>,
4134                                         <&videocc VCODEC0_GDSC>,
4135                                         <&videocc VCODEC1_GDSC>,
4136                                         <&rpmhpd SDM845_CX>;
4137                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4138                         operating-points-v2 = <&venus_opp_table>;
4139                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4140                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4141                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4142                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4143                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4144                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4145                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4146                         clock-names = "core", "iface", "bus",
4147                                       "vcodec0_core", "vcodec0_bus",
4148                                       "vcodec1_core", "vcodec1_bus";
4149                         iommus = <&apps_smmu 0x10a0 0x8>,
4150                                  <&apps_smmu 0x10b0 0x0>;
4151                         memory-region = <&venus_mem>;
4152                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4153                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4154                         interconnect-names = "video-mem", "cpu-cfg";
4155
4156                         status = "disabled";
4157
4158                         video-core0 {
4159                                 compatible = "venus-decoder";
4160                         };
4161
4162                         video-core1 {
4163                                 compatible = "venus-encoder";
4164                         };
4165
4166                         venus_opp_table: opp-table {
4167                                 compatible = "operating-points-v2";
4168
4169                                 opp-100000000 {
4170                                         opp-hz = /bits/ 64 <100000000>;
4171                                         required-opps = <&rpmhpd_opp_min_svs>;
4172                                 };
4173
4174                                 opp-200000000 {
4175                                         opp-hz = /bits/ 64 <200000000>;
4176                                         required-opps = <&rpmhpd_opp_low_svs>;
4177                                 };
4178
4179                                 opp-320000000 {
4180                                         opp-hz = /bits/ 64 <320000000>;
4181                                         required-opps = <&rpmhpd_opp_svs>;
4182                                 };
4183
4184                                 opp-380000000 {
4185                                         opp-hz = /bits/ 64 <380000000>;
4186                                         required-opps = <&rpmhpd_opp_svs_l1>;
4187                                 };
4188
4189                                 opp-444000000 {
4190                                         opp-hz = /bits/ 64 <444000000>;
4191                                         required-opps = <&rpmhpd_opp_nom>;
4192                                 };
4193
4194                                 opp-533000097 {
4195                                         opp-hz = /bits/ 64 <533000097>;
4196                                         required-opps = <&rpmhpd_opp_turbo>;
4197                                 };
4198                         };
4199                 };
4200
4201                 videocc: clock-controller@ab00000 {
4202                         compatible = "qcom,sdm845-videocc";
4203                         reg = <0 0x0ab00000 0 0x10000>;
4204                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4205                         clock-names = "bi_tcxo";
4206                         #clock-cells = <1>;
4207                         #power-domain-cells = <1>;
4208                         #reset-cells = <1>;
4209                 };
4210
4211                 camss: camss@acb3000 {
4212                         compatible = "qcom,sdm845-camss";
4213
4214                         reg = <0 0xacb3000 0 0x1000>,
4215                                 <0 0xacba000 0 0x1000>,
4216                                 <0 0xacc8000 0 0x1000>,
4217                                 <0 0xac65000 0 0x1000>,
4218                                 <0 0xac66000 0 0x1000>,
4219                                 <0 0xac67000 0 0x1000>,
4220                                 <0 0xac68000 0 0x1000>,
4221                                 <0 0xacaf000 0 0x4000>,
4222                                 <0 0xacb6000 0 0x4000>,
4223                                 <0 0xacc4000 0 0x4000>;
4224                         reg-names = "csid0",
4225                                 "csid1",
4226                                 "csid2",
4227                                 "csiphy0",
4228                                 "csiphy1",
4229                                 "csiphy2",
4230                                 "csiphy3",
4231                                 "vfe0",
4232                                 "vfe1",
4233                                 "vfe_lite";
4234
4235                         interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4236                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4237                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4238                                 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4239                                 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4240                                 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4241                                 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4242                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4243                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4244                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4245                         interrupt-names = "csid0",
4246                                 "csid1",
4247                                 "csid2",
4248                                 "csiphy0",
4249                                 "csiphy1",
4250                                 "csiphy2",
4251                                 "csiphy3",
4252                                 "vfe0",
4253                                 "vfe1",
4254                                 "vfe_lite";
4255
4256                         power-domains = <&clock_camcc IFE_0_GDSC>,
4257                                 <&clock_camcc IFE_1_GDSC>,
4258                                 <&clock_camcc TITAN_TOP_GDSC>;
4259
4260                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4261                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4262                                 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4263                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4264                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4265                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4266                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4267                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4268                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4269                                 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4270                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4271                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4272                                 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4273                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4274                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4275                                 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4276                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4277                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4278                                 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4279                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4280                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4281                                 <&gcc GCC_CAMERA_AHB_CLK>,
4282                                 <&gcc GCC_CAMERA_AXI_CLK>,
4283                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4284                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4285                                 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4286                                 <&clock_camcc CAM_CC_IFE_0_CLK>,
4287                                 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4288                                 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4289                                 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4290                                 <&clock_camcc CAM_CC_IFE_1_CLK>,
4291                                 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4292                                 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4293                                 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4294                                 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4295                                 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4296                         clock-names = "camnoc_axi",
4297                                 "cpas_ahb",
4298                                 "cphy_rx_src",
4299                                 "csi0",
4300                                 "csi0_src",
4301                                 "csi1",
4302                                 "csi1_src",
4303                                 "csi2",
4304                                 "csi2_src",
4305                                 "csiphy0",
4306                                 "csiphy0_timer",
4307                                 "csiphy0_timer_src",
4308                                 "csiphy1",
4309                                 "csiphy1_timer",
4310                                 "csiphy1_timer_src",
4311                                 "csiphy2",
4312                                 "csiphy2_timer",
4313                                 "csiphy2_timer_src",
4314                                 "csiphy3",
4315                                 "csiphy3_timer",
4316                                 "csiphy3_timer_src",
4317                                 "gcc_camera_ahb",
4318                                 "gcc_camera_axi",
4319                                 "slow_ahb_src",
4320                                 "soc_ahb",
4321                                 "vfe0_axi",
4322                                 "vfe0",
4323                                 "vfe0_cphy_rx",
4324                                 "vfe0_src",
4325                                 "vfe1_axi",
4326                                 "vfe1",
4327                                 "vfe1_cphy_rx",
4328                                 "vfe1_src",
4329                                 "vfe_lite",
4330                                 "vfe_lite_cphy_rx",
4331                                 "vfe_lite_src";
4332
4333                         iommus = <&apps_smmu 0x0808 0x0>,
4334                                  <&apps_smmu 0x0810 0x8>,
4335                                  <&apps_smmu 0x0c08 0x0>,
4336                                  <&apps_smmu 0x0c10 0x8>;
4337
4338                         status = "disabled";
4339
4340                         ports {
4341                                 #address-cells = <1>;
4342                                 #size-cells = <0>;
4343                         };
4344                 };
4345
4346                 cci: cci@ac4a000 {
4347                         compatible = "qcom,sdm845-cci";
4348                         #address-cells = <1>;
4349                         #size-cells = <0>;
4350
4351                         reg = <0 0x0ac4a000 0 0x4000>;
4352                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4353                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4354
4355                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4356                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4357                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4358                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4359                                 <&clock_camcc CAM_CC_CCI_CLK>,
4360                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4361                         clock-names = "camnoc_axi",
4362                                 "soc_ahb",
4363                                 "slow_ahb_src",
4364                                 "cpas_ahb",
4365                                 "cci",
4366                                 "cci_src";
4367
4368                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4369                                 <&clock_camcc CAM_CC_CCI_CLK>;
4370                         assigned-clock-rates = <80000000>, <37500000>;
4371
4372                         pinctrl-names = "default", "sleep";
4373                         pinctrl-0 = <&cci0_default &cci1_default>;
4374                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4375
4376                         status = "disabled";
4377
4378                         cci_i2c0: i2c-bus@0 {
4379                                 reg = <0>;
4380                                 clock-frequency = <1000000>;
4381                                 #address-cells = <1>;
4382                                 #size-cells = <0>;
4383                         };
4384
4385                         cci_i2c1: i2c-bus@1 {
4386                                 reg = <1>;
4387                                 clock-frequency = <1000000>;
4388                                 #address-cells = <1>;
4389                                 #size-cells = <0>;
4390                         };
4391                 };
4392
4393                 clock_camcc: clock-controller@ad00000 {
4394                         compatible = "qcom,sdm845-camcc";
4395                         reg = <0 0x0ad00000 0 0x10000>;
4396                         #clock-cells = <1>;
4397                         #reset-cells = <1>;
4398                         #power-domain-cells = <1>;
4399                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4400                         clock-names = "bi_tcxo";
4401                 };
4402
4403                 dsi_opp_table: opp-table-dsi {
4404                         compatible = "operating-points-v2";
4405
4406                         opp-19200000 {
4407                                 opp-hz = /bits/ 64 <19200000>;
4408                                 required-opps = <&rpmhpd_opp_min_svs>;
4409                         };
4410
4411                         opp-180000000 {
4412                                 opp-hz = /bits/ 64 <180000000>;
4413                                 required-opps = <&rpmhpd_opp_low_svs>;
4414                         };
4415
4416                         opp-275000000 {
4417                                 opp-hz = /bits/ 64 <275000000>;
4418                                 required-opps = <&rpmhpd_opp_svs>;
4419                         };
4420
4421                         opp-328580000 {
4422                                 opp-hz = /bits/ 64 <328580000>;
4423                                 required-opps = <&rpmhpd_opp_svs_l1>;
4424                         };
4425
4426                         opp-358000000 {
4427                                 opp-hz = /bits/ 64 <358000000>;
4428                                 required-opps = <&rpmhpd_opp_nom>;
4429                         };
4430                 };
4431
4432                 mdss: mdss@ae00000 {
4433                         compatible = "qcom,sdm845-mdss";
4434                         reg = <0 0x0ae00000 0 0x1000>;
4435                         reg-names = "mdss";
4436
4437                         power-domains = <&dispcc MDSS_GDSC>;
4438
4439                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4440                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4441                         clock-names = "iface", "core";
4442
4443                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4444                         interrupt-controller;
4445                         #interrupt-cells = <1>;
4446
4447                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4448                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4449                         interconnect-names = "mdp0-mem", "mdp1-mem";
4450
4451                         iommus = <&apps_smmu 0x880 0x8>,
4452                                  <&apps_smmu 0xc80 0x8>;
4453
4454                         status = "disabled";
4455
4456                         #address-cells = <2>;
4457                         #size-cells = <2>;
4458                         ranges;
4459
4460                         mdss_mdp: display-controller@ae01000 {
4461                                 compatible = "qcom,sdm845-dpu";
4462                                 reg = <0 0x0ae01000 0 0x8f000>,
4463                                       <0 0x0aeb0000 0 0x2008>;
4464                                 reg-names = "mdp", "vbif";
4465
4466                                 clocks = <&gcc GCC_DISP_AXI_CLK>,
4467                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4468                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
4469                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4470                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4471                                 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4472
4473                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4474                                 assigned-clock-rates = <19200000>;
4475                                 operating-points-v2 = <&mdp_opp_table>;
4476                                 power-domains = <&rpmhpd SDM845_CX>;
4477
4478                                 interrupt-parent = <&mdss>;
4479                                 interrupts = <0>;
4480
4481                                 ports {
4482                                         #address-cells = <1>;
4483                                         #size-cells = <0>;
4484
4485                                         port@0 {
4486                                                 reg = <0>;
4487                                                 dpu_intf1_out: endpoint {
4488                                                         remote-endpoint = <&dsi0_in>;
4489                                                 };
4490                                         };
4491
4492                                         port@1 {
4493                                                 reg = <1>;
4494                                                 dpu_intf2_out: endpoint {
4495                                                         remote-endpoint = <&dsi1_in>;
4496                                                 };
4497                                         };
4498                                 };
4499
4500                                 mdp_opp_table: opp-table {
4501                                         compatible = "operating-points-v2";
4502
4503                                         opp-19200000 {
4504                                                 opp-hz = /bits/ 64 <19200000>;
4505                                                 required-opps = <&rpmhpd_opp_min_svs>;
4506                                         };
4507
4508                                         opp-171428571 {
4509                                                 opp-hz = /bits/ 64 <171428571>;
4510                                                 required-opps = <&rpmhpd_opp_low_svs>;
4511                                         };
4512
4513                                         opp-344000000 {
4514                                                 opp-hz = /bits/ 64 <344000000>;
4515                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4516                                         };
4517
4518                                         opp-430000000 {
4519                                                 opp-hz = /bits/ 64 <430000000>;
4520                                                 required-opps = <&rpmhpd_opp_nom>;
4521                                         };
4522                                 };
4523                         };
4524
4525                         dsi0: dsi@ae94000 {
4526                                 compatible = "qcom,mdss-dsi-ctrl";
4527                                 reg = <0 0x0ae94000 0 0x400>;
4528                                 reg-names = "dsi_ctrl";
4529
4530                                 interrupt-parent = <&mdss>;
4531                                 interrupts = <4>;
4532
4533                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4534                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4535                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4536                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4537                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4538                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4539                                 clock-names = "byte",
4540                                               "byte_intf",
4541                                               "pixel",
4542                                               "core",
4543                                               "iface",
4544                                               "bus";
4545                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4546                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4547
4548                                 operating-points-v2 = <&dsi_opp_table>;
4549                                 power-domains = <&rpmhpd SDM845_CX>;
4550
4551                                 phys = <&dsi0_phy>;
4552                                 phy-names = "dsi";
4553
4554                                 status = "disabled";
4555
4556                                 #address-cells = <1>;
4557                                 #size-cells = <0>;
4558
4559                                 ports {
4560                                         #address-cells = <1>;
4561                                         #size-cells = <0>;
4562
4563                                         port@0 {
4564                                                 reg = <0>;
4565                                                 dsi0_in: endpoint {
4566                                                         remote-endpoint = <&dpu_intf1_out>;
4567                                                 };
4568                                         };
4569
4570                                         port@1 {
4571                                                 reg = <1>;
4572                                                 dsi0_out: endpoint {
4573                                                 };
4574                                         };
4575                                 };
4576                         };
4577
4578                         dsi0_phy: dsi-phy@ae94400 {
4579                                 compatible = "qcom,dsi-phy-10nm";
4580                                 reg = <0 0x0ae94400 0 0x200>,
4581                                       <0 0x0ae94600 0 0x280>,
4582                                       <0 0x0ae94a00 0 0x1e0>;
4583                                 reg-names = "dsi_phy",
4584                                             "dsi_phy_lane",
4585                                             "dsi_pll";
4586
4587                                 #clock-cells = <1>;
4588                                 #phy-cells = <0>;
4589
4590                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4591                                          <&rpmhcc RPMH_CXO_CLK>;
4592                                 clock-names = "iface", "ref";
4593
4594                                 status = "disabled";
4595                         };
4596
4597                         dsi1: dsi@ae96000 {
4598                                 compatible = "qcom,mdss-dsi-ctrl";
4599                                 reg = <0 0x0ae96000 0 0x400>;
4600                                 reg-names = "dsi_ctrl";
4601
4602                                 interrupt-parent = <&mdss>;
4603                                 interrupts = <5>;
4604
4605                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4606                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4607                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4608                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4609                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4610                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4611                                 clock-names = "byte",
4612                                               "byte_intf",
4613                                               "pixel",
4614                                               "core",
4615                                               "iface",
4616                                               "bus";
4617                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4618                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4619
4620                                 operating-points-v2 = <&dsi_opp_table>;
4621                                 power-domains = <&rpmhpd SDM845_CX>;
4622
4623                                 phys = <&dsi1_phy>;
4624                                 phy-names = "dsi";
4625
4626                                 status = "disabled";
4627
4628                                 #address-cells = <1>;
4629                                 #size-cells = <0>;
4630
4631                                 ports {
4632                                         #address-cells = <1>;
4633                                         #size-cells = <0>;
4634
4635                                         port@0 {
4636                                                 reg = <0>;
4637                                                 dsi1_in: endpoint {
4638                                                         remote-endpoint = <&dpu_intf2_out>;
4639                                                 };
4640                                         };
4641
4642                                         port@1 {
4643                                                 reg = <1>;
4644                                                 dsi1_out: endpoint {
4645                                                 };
4646                                         };
4647                                 };
4648                         };
4649
4650                         dsi1_phy: dsi-phy@ae96400 {
4651                                 compatible = "qcom,dsi-phy-10nm";
4652                                 reg = <0 0x0ae96400 0 0x200>,
4653                                       <0 0x0ae96600 0 0x280>,
4654                                       <0 0x0ae96a00 0 0x10e>;
4655                                 reg-names = "dsi_phy",
4656                                             "dsi_phy_lane",
4657                                             "dsi_pll";
4658
4659                                 #clock-cells = <1>;
4660                                 #phy-cells = <0>;
4661
4662                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4663                                          <&rpmhcc RPMH_CXO_CLK>;
4664                                 clock-names = "iface", "ref";
4665
4666                                 status = "disabled";
4667                         };
4668                 };
4669
4670                 gpu: gpu@5000000 {
4671                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4672
4673                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4674                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4675
4676                         /*
4677                          * Look ma, no clocks! The GPU clocks and power are
4678                          * controlled entirely by the GMU
4679                          */
4680
4681                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4682
4683                         iommus = <&adreno_smmu 0>;
4684
4685                         operating-points-v2 = <&gpu_opp_table>;
4686
4687                         qcom,gmu = <&gmu>;
4688
4689                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4690                         interconnect-names = "gfx-mem";
4691
4692                         status = "disabled";
4693
4694                         gpu_opp_table: opp-table {
4695                                 compatible = "operating-points-v2";
4696
4697                                 opp-710000000 {
4698                                         opp-hz = /bits/ 64 <710000000>;
4699                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4700                                         opp-peak-kBps = <7216000>;
4701                                 };
4702
4703                                 opp-675000000 {
4704                                         opp-hz = /bits/ 64 <675000000>;
4705                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4706                                         opp-peak-kBps = <7216000>;
4707                                 };
4708
4709                                 opp-596000000 {
4710                                         opp-hz = /bits/ 64 <596000000>;
4711                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4712                                         opp-peak-kBps = <6220000>;
4713                                 };
4714
4715                                 opp-520000000 {
4716                                         opp-hz = /bits/ 64 <520000000>;
4717                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4718                                         opp-peak-kBps = <6220000>;
4719                                 };
4720
4721                                 opp-414000000 {
4722                                         opp-hz = /bits/ 64 <414000000>;
4723                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4724                                         opp-peak-kBps = <4068000>;
4725                                 };
4726
4727                                 opp-342000000 {
4728                                         opp-hz = /bits/ 64 <342000000>;
4729                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4730                                         opp-peak-kBps = <2724000>;
4731                                 };
4732
4733                                 opp-257000000 {
4734                                         opp-hz = /bits/ 64 <257000000>;
4735                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4736                                         opp-peak-kBps = <1648000>;
4737                                 };
4738                         };
4739                 };
4740
4741                 adreno_smmu: iommu@5040000 {
4742                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4743                         reg = <0 0x5040000 0 0x10000>;
4744                         #iommu-cells = <1>;
4745                         #global-interrupts = <2>;
4746                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4747                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4748                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4749                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4750                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4751                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4752                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4753                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4754                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4755                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4756                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4757                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4758                         clock-names = "bus", "iface";
4759
4760                         power-domains = <&gpucc GPU_CX_GDSC>;
4761                 };
4762
4763                 gmu: gmu@506a000 {
4764                         compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4765
4766                         reg = <0 0x506a000 0 0x30000>,
4767                               <0 0xb280000 0 0x10000>,
4768                               <0 0xb480000 0 0x10000>;
4769                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4770
4771                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4772                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4773                         interrupt-names = "hfi", "gmu";
4774
4775                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4776                                  <&gpucc GPU_CC_CXO_CLK>,
4777                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4778                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4779                         clock-names = "gmu", "cxo", "axi", "memnoc";
4780
4781                         power-domains = <&gpucc GPU_CX_GDSC>,
4782                                         <&gpucc GPU_GX_GDSC>;
4783                         power-domain-names = "cx", "gx";
4784
4785                         iommus = <&adreno_smmu 5>;
4786
4787                         operating-points-v2 = <&gmu_opp_table>;
4788
4789                         status = "disabled";
4790
4791                         gmu_opp_table: opp-table {
4792                                 compatible = "operating-points-v2";
4793
4794                                 opp-400000000 {
4795                                         opp-hz = /bits/ 64 <400000000>;
4796                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4797                                 };
4798
4799                                 opp-200000000 {
4800                                         opp-hz = /bits/ 64 <200000000>;
4801                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4802                                 };
4803                         };
4804                 };
4805
4806                 dispcc: clock-controller@af00000 {
4807                         compatible = "qcom,sdm845-dispcc";
4808                         reg = <0 0x0af00000 0 0x10000>;
4809                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4810                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4811                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4812                                  <&dsi0_phy 0>,
4813                                  <&dsi0_phy 1>,
4814                                  <&dsi1_phy 0>,
4815                                  <&dsi1_phy 1>,
4816                                  <0>,
4817                                  <0>;
4818                         clock-names = "bi_tcxo",
4819                                       "gcc_disp_gpll0_clk_src",
4820                                       "gcc_disp_gpll0_div_clk_src",
4821                                       "dsi0_phy_pll_out_byteclk",
4822                                       "dsi0_phy_pll_out_dsiclk",
4823                                       "dsi1_phy_pll_out_byteclk",
4824                                       "dsi1_phy_pll_out_dsiclk",
4825                                       "dp_link_clk_divsel_ten",
4826                                       "dp_vco_divided_clk_src_mux";
4827                         #clock-cells = <1>;
4828                         #reset-cells = <1>;
4829                         #power-domain-cells = <1>;
4830                 };
4831
4832                 pdc_intc: interrupt-controller@b220000 {
4833                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4834                         reg = <0 0x0b220000 0 0x30000>;
4835                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4836                         #interrupt-cells = <2>;
4837                         interrupt-parent = <&intc>;
4838                         interrupt-controller;
4839                 };
4840
4841                 pdc_reset: reset-controller@b2e0000 {
4842                         compatible = "qcom,sdm845-pdc-global";
4843                         reg = <0 0x0b2e0000 0 0x20000>;
4844                         #reset-cells = <1>;
4845                 };
4846
4847                 tsens0: thermal-sensor@c263000 {
4848                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4849                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4850                               <0 0x0c222000 0 0x1ff>; /* SROT */
4851                         #qcom,sensors = <13>;
4852                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4853                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4854                         interrupt-names = "uplow", "critical";
4855                         #thermal-sensor-cells = <1>;
4856                 };
4857
4858                 tsens1: thermal-sensor@c265000 {
4859                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4860                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4861                               <0 0x0c223000 0 0x1ff>; /* SROT */
4862                         #qcom,sensors = <8>;
4863                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4864                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4865                         interrupt-names = "uplow", "critical";
4866                         #thermal-sensor-cells = <1>;
4867                 };
4868
4869                 aoss_reset: reset-controller@c2a0000 {
4870                         compatible = "qcom,sdm845-aoss-cc";
4871                         reg = <0 0x0c2a0000 0 0x31000>;
4872                         #reset-cells = <1>;
4873                 };
4874
4875                 aoss_qmp: power-controller@c300000 {
4876                         compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4877                         reg = <0 0x0c300000 0 0x400>;
4878                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4879                         mboxes = <&apss_shared 0>;
4880
4881                         #clock-cells = <0>;
4882
4883                         cx_cdev: cx {
4884                                 #cooling-cells = <2>;
4885                         };
4886
4887                         ebi_cdev: ebi {
4888                                 #cooling-cells = <2>;
4889                         };
4890                 };
4891
4892                 sram@c3f0000 {
4893                         compatible = "qcom,sdm845-rpmh-stats";
4894                         reg = <0 0x0c3f0000 0 0x400>;
4895                 };
4896
4897                 spmi_bus: spmi@c440000 {
4898                         compatible = "qcom,spmi-pmic-arb";
4899                         reg = <0 0x0c440000 0 0x1100>,
4900                               <0 0x0c600000 0 0x2000000>,
4901                               <0 0x0e600000 0 0x100000>,
4902                               <0 0x0e700000 0 0xa0000>,
4903                               <0 0x0c40a000 0 0x26000>;
4904                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4905                         interrupt-names = "periph_irq";
4906                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4907                         qcom,ee = <0>;
4908                         qcom,channel = <0>;
4909                         #address-cells = <2>;
4910                         #size-cells = <0>;
4911                         interrupt-controller;
4912                         #interrupt-cells = <4>;
4913                         cell-index = <0>;
4914                 };
4915
4916                 sram@146bf000 {
4917                         compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
4918                         reg = <0 0x146bf000 0 0x1000>;
4919
4920                         #address-cells = <1>;
4921                         #size-cells = <1>;
4922
4923                         ranges = <0 0 0x146bf000 0x1000>;
4924
4925                         pil-reloc@94c {
4926                                 compatible = "qcom,pil-reloc-info";
4927                                 reg = <0x94c 0xc8>;
4928                         };
4929                 };
4930
4931                 apps_smmu: iommu@15000000 {
4932                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
4933                         reg = <0 0x15000000 0 0x80000>;
4934                         #iommu-cells = <2>;
4935                         #global-interrupts = <1>;
4936                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4937                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4938                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4939                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4940                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4941                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4942                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4943                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4944                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4945                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4946                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4947                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4948                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4949                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4950                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4951                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4952                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4953                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4954                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4955                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4956                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4957                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4958                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4959                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4960                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4961                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4962                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4963                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4964                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4965                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4966                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4967                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4968                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4969                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4970                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4971                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4972                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4973                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4974                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4975                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4976                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4977                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4978                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4979                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4980                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4981                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4982                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4983                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4984                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4985                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4986                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4987                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4988                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4989                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4990                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4991                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4992                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4993                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4994                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4995                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4996                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4997                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4998                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4999                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5000                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5001                 };
5002
5003                 lpasscc: clock-controller@17014000 {
5004                         compatible = "qcom,sdm845-lpasscc";
5005                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5006                         reg-names = "cc", "qdsp6ss";
5007                         #clock-cells = <1>;
5008                         status = "disabled";
5009                 };
5010
5011                 gladiator_noc: interconnect@17900000 {
5012                         compatible = "qcom,sdm845-gladiator-noc";
5013                         reg = <0 0x17900000 0 0xd080>;
5014                         #interconnect-cells = <2>;
5015                         qcom,bcm-voters = <&apps_bcm_voter>;
5016                 };
5017
5018                 watchdog@17980000 {
5019                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5020                         reg = <0 0x17980000 0 0x1000>;
5021                         clocks = <&sleep_clk>;
5022                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5023                 };
5024
5025                 apss_shared: mailbox@17990000 {
5026                         compatible = "qcom,sdm845-apss-shared";
5027                         reg = <0 0x17990000 0 0x1000>;
5028                         #mbox-cells = <1>;
5029                 };
5030
5031                 apps_rsc: rsc@179c0000 {
5032                         label = "apps_rsc";
5033                         compatible = "qcom,rpmh-rsc";
5034                         reg = <0 0x179c0000 0 0x10000>,
5035                               <0 0x179d0000 0 0x10000>,
5036                               <0 0x179e0000 0 0x10000>;
5037                         reg-names = "drv-0", "drv-1", "drv-2";
5038                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5039                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5040                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5041                         qcom,tcs-offset = <0xd00>;
5042                         qcom,drv-id = <2>;
5043                         qcom,tcs-config = <ACTIVE_TCS  2>,
5044                                           <SLEEP_TCS   3>,
5045                                           <WAKE_TCS    3>,
5046                                           <CONTROL_TCS 1>;
5047                         power-domains = <&CLUSTER_PD>;
5048
5049                         apps_bcm_voter: bcm-voter {
5050                                 compatible = "qcom,bcm-voter";
5051                         };
5052
5053                         rpmhcc: clock-controller {
5054                                 compatible = "qcom,sdm845-rpmh-clk";
5055                                 #clock-cells = <1>;
5056                                 clock-names = "xo";
5057                                 clocks = <&xo_board>;
5058                         };
5059
5060                         rpmhpd: power-controller {
5061                                 compatible = "qcom,sdm845-rpmhpd";
5062                                 #power-domain-cells = <1>;
5063                                 operating-points-v2 = <&rpmhpd_opp_table>;
5064
5065                                 rpmhpd_opp_table: opp-table {
5066                                         compatible = "operating-points-v2";
5067
5068                                         rpmhpd_opp_ret: opp1 {
5069                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5070                                         };
5071
5072                                         rpmhpd_opp_min_svs: opp2 {
5073                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5074                                         };
5075
5076                                         rpmhpd_opp_low_svs: opp3 {
5077                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5078                                         };
5079
5080                                         rpmhpd_opp_svs: opp4 {
5081                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5082                                         };
5083
5084                                         rpmhpd_opp_svs_l1: opp5 {
5085                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5086                                         };
5087
5088                                         rpmhpd_opp_nom: opp6 {
5089                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5090                                         };
5091
5092                                         rpmhpd_opp_nom_l1: opp7 {
5093                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5094                                         };
5095
5096                                         rpmhpd_opp_nom_l2: opp8 {
5097                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5098                                         };
5099
5100                                         rpmhpd_opp_turbo: opp9 {
5101                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5102                                         };
5103
5104                                         rpmhpd_opp_turbo_l1: opp10 {
5105                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5106                                         };
5107                                 };
5108                         };
5109                 };
5110
5111                 intc: interrupt-controller@17a00000 {
5112                         compatible = "arm,gic-v3";
5113                         #address-cells = <2>;
5114                         #size-cells = <2>;
5115                         ranges;
5116                         #interrupt-cells = <3>;
5117                         interrupt-controller;
5118                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
5119                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
5120                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5121
5122                         msi-controller@17a40000 {
5123                                 compatible = "arm,gic-v3-its";
5124                                 msi-controller;
5125                                 #msi-cells = <1>;
5126                                 reg = <0 0x17a40000 0 0x20000>;
5127                                 status = "disabled";
5128                         };
5129                 };
5130
5131                 slimbam: dma-controller@17184000 {
5132                         compatible = "qcom,bam-v1.7.0";
5133                         qcom,controlled-remotely;
5134                         reg = <0 0x17184000 0 0x2a000>;
5135                         num-channels = <31>;
5136                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5137                         #dma-cells = <1>;
5138                         qcom,ee = <1>;
5139                         qcom,num-ees = <2>;
5140                         iommus = <&apps_smmu 0x1806 0x0>;
5141                 };
5142
5143                 timer@17c90000 {
5144                         #address-cells = <1>;
5145                         #size-cells = <1>;
5146                         ranges = <0 0 0 0x20000000>;
5147                         compatible = "arm,armv7-timer-mem";
5148                         reg = <0 0x17c90000 0 0x1000>;
5149
5150                         frame@17ca0000 {
5151                                 frame-number = <0>;
5152                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5153                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5154                                 reg = <0x17ca0000 0x1000>,
5155                                       <0x17cb0000 0x1000>;
5156                         };
5157
5158                         frame@17cc0000 {
5159                                 frame-number = <1>;
5160                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5161                                 reg = <0x17cc0000 0x1000>;
5162                                 status = "disabled";
5163                         };
5164
5165                         frame@17cd0000 {
5166                                 frame-number = <2>;
5167                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5168                                 reg = <0x17cd0000 0x1000>;
5169                                 status = "disabled";
5170                         };
5171
5172                         frame@17ce0000 {
5173                                 frame-number = <3>;
5174                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5175                                 reg = <0x17ce0000 0x1000>;
5176                                 status = "disabled";
5177                         };
5178
5179                         frame@17cf0000 {
5180                                 frame-number = <4>;
5181                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5182                                 reg = <0x17cf0000 0x1000>;
5183                                 status = "disabled";
5184                         };
5185
5186                         frame@17d00000 {
5187                                 frame-number = <5>;
5188                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5189                                 reg = <0x17d00000 0x1000>;
5190                                 status = "disabled";
5191                         };
5192
5193                         frame@17d10000 {
5194                                 frame-number = <6>;
5195                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5196                                 reg = <0x17d10000 0x1000>;
5197                                 status = "disabled";
5198                         };
5199                 };
5200
5201                 osm_l3: interconnect@17d41000 {
5202                         compatible = "qcom,sdm845-osm-l3";
5203                         reg = <0 0x17d41000 0 0x1400>;
5204
5205                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5206                         clock-names = "xo", "alternate";
5207
5208                         #interconnect-cells = <1>;
5209                 };
5210
5211                 cpufreq_hw: cpufreq@17d43000 {
5212                         compatible = "qcom,cpufreq-hw";
5213                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5214                         reg-names = "freq-domain0", "freq-domain1";
5215
5216                         interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5217
5218                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5219                         clock-names = "xo", "alternate";
5220
5221                         #freq-domain-cells = <1>;
5222                 };
5223
5224                 wifi: wifi@18800000 {
5225                         compatible = "qcom,wcn3990-wifi";
5226                         status = "disabled";
5227                         reg = <0 0x18800000 0 0x800000>;
5228                         reg-names = "membase";
5229                         memory-region = <&wlan_msa_mem>;
5230                         clock-names = "cxo_ref_clk_pin";
5231                         clocks = <&rpmhcc RPMH_RF_CLK2>;
5232                         interrupts =
5233                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5234                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5235                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5236                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5237                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5238                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5239                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5240                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5241                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5242                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5243                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5244                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5245                         iommus = <&apps_smmu 0x0040 0x1>;
5246                 };
5247         };
5248
5249         thermal-zones {
5250                 cpu0-thermal {
5251                         polling-delay-passive = <250>;
5252                         polling-delay = <1000>;
5253
5254                         thermal-sensors = <&tsens0 1>;
5255
5256                         trips {
5257                                 cpu0_alert0: trip-point0 {
5258                                         temperature = <90000>;
5259                                         hysteresis = <2000>;
5260                                         type = "passive";
5261                                 };
5262
5263                                 cpu0_alert1: trip-point1 {
5264                                         temperature = <95000>;
5265                                         hysteresis = <2000>;
5266                                         type = "passive";
5267                                 };
5268
5269                                 cpu0_crit: cpu_crit {
5270                                         temperature = <110000>;
5271                                         hysteresis = <1000>;
5272                                         type = "critical";
5273                                 };
5274                         };
5275                 };
5276
5277                 cpu1-thermal {
5278                         polling-delay-passive = <250>;
5279                         polling-delay = <1000>;
5280
5281                         thermal-sensors = <&tsens0 2>;
5282
5283                         trips {
5284                                 cpu1_alert0: trip-point0 {
5285                                         temperature = <90000>;
5286                                         hysteresis = <2000>;
5287                                         type = "passive";
5288                                 };
5289
5290                                 cpu1_alert1: trip-point1 {
5291                                         temperature = <95000>;
5292                                         hysteresis = <2000>;
5293                                         type = "passive";
5294                                 };
5295
5296                                 cpu1_crit: cpu_crit {
5297                                         temperature = <110000>;
5298                                         hysteresis = <1000>;
5299                                         type = "critical";
5300                                 };
5301                         };
5302                 };
5303
5304                 cpu2-thermal {
5305                         polling-delay-passive = <250>;
5306                         polling-delay = <1000>;
5307
5308                         thermal-sensors = <&tsens0 3>;
5309
5310                         trips {
5311                                 cpu2_alert0: trip-point0 {
5312                                         temperature = <90000>;
5313                                         hysteresis = <2000>;
5314                                         type = "passive";
5315                                 };
5316
5317                                 cpu2_alert1: trip-point1 {
5318                                         temperature = <95000>;
5319                                         hysteresis = <2000>;
5320                                         type = "passive";
5321                                 };
5322
5323                                 cpu2_crit: cpu_crit {
5324                                         temperature = <110000>;
5325                                         hysteresis = <1000>;
5326                                         type = "critical";
5327                                 };
5328                         };
5329                 };
5330
5331                 cpu3-thermal {
5332                         polling-delay-passive = <250>;
5333                         polling-delay = <1000>;
5334
5335                         thermal-sensors = <&tsens0 4>;
5336
5337                         trips {
5338                                 cpu3_alert0: trip-point0 {
5339                                         temperature = <90000>;
5340                                         hysteresis = <2000>;
5341                                         type = "passive";
5342                                 };
5343
5344                                 cpu3_alert1: trip-point1 {
5345                                         temperature = <95000>;
5346                                         hysteresis = <2000>;
5347                                         type = "passive";
5348                                 };
5349
5350                                 cpu3_crit: cpu_crit {
5351                                         temperature = <110000>;
5352                                         hysteresis = <1000>;
5353                                         type = "critical";
5354                                 };
5355                         };
5356                 };
5357
5358                 cpu4-thermal {
5359                         polling-delay-passive = <250>;
5360                         polling-delay = <1000>;
5361
5362                         thermal-sensors = <&tsens0 7>;
5363
5364                         trips {
5365                                 cpu4_alert0: trip-point0 {
5366                                         temperature = <90000>;
5367                                         hysteresis = <2000>;
5368                                         type = "passive";
5369                                 };
5370
5371                                 cpu4_alert1: trip-point1 {
5372                                         temperature = <95000>;
5373                                         hysteresis = <2000>;
5374                                         type = "passive";
5375                                 };
5376
5377                                 cpu4_crit: cpu_crit {
5378                                         temperature = <110000>;
5379                                         hysteresis = <1000>;
5380                                         type = "critical";
5381                                 };
5382                         };
5383                 };
5384
5385                 cpu5-thermal {
5386                         polling-delay-passive = <250>;
5387                         polling-delay = <1000>;
5388
5389                         thermal-sensors = <&tsens0 8>;
5390
5391                         trips {
5392                                 cpu5_alert0: trip-point0 {
5393                                         temperature = <90000>;
5394                                         hysteresis = <2000>;
5395                                         type = "passive";
5396                                 };
5397
5398                                 cpu5_alert1: trip-point1 {
5399                                         temperature = <95000>;
5400                                         hysteresis = <2000>;
5401                                         type = "passive";
5402                                 };
5403
5404                                 cpu5_crit: cpu_crit {
5405                                         temperature = <110000>;
5406                                         hysteresis = <1000>;
5407                                         type = "critical";
5408                                 };
5409                         };
5410                 };
5411
5412                 cpu6-thermal {
5413                         polling-delay-passive = <250>;
5414                         polling-delay = <1000>;
5415
5416                         thermal-sensors = <&tsens0 9>;
5417
5418                         trips {
5419                                 cpu6_alert0: trip-point0 {
5420                                         temperature = <90000>;
5421                                         hysteresis = <2000>;
5422                                         type = "passive";
5423                                 };
5424
5425                                 cpu6_alert1: trip-point1 {
5426                                         temperature = <95000>;
5427                                         hysteresis = <2000>;
5428                                         type = "passive";
5429                                 };
5430
5431                                 cpu6_crit: cpu_crit {
5432                                         temperature = <110000>;
5433                                         hysteresis = <1000>;
5434                                         type = "critical";
5435                                 };
5436                         };
5437                 };
5438
5439                 cpu7-thermal {
5440                         polling-delay-passive = <250>;
5441                         polling-delay = <1000>;
5442
5443                         thermal-sensors = <&tsens0 10>;
5444
5445                         trips {
5446                                 cpu7_alert0: trip-point0 {
5447                                         temperature = <90000>;
5448                                         hysteresis = <2000>;
5449                                         type = "passive";
5450                                 };
5451
5452                                 cpu7_alert1: trip-point1 {
5453                                         temperature = <95000>;
5454                                         hysteresis = <2000>;
5455                                         type = "passive";
5456                                 };
5457
5458                                 cpu7_crit: cpu_crit {
5459                                         temperature = <110000>;
5460                                         hysteresis = <1000>;
5461                                         type = "critical";
5462                                 };
5463                         };
5464                 };
5465
5466                 aoss0-thermal {
5467                         polling-delay-passive = <250>;
5468                         polling-delay = <1000>;
5469
5470                         thermal-sensors = <&tsens0 0>;
5471
5472                         trips {
5473                                 aoss0_alert0: trip-point0 {
5474                                         temperature = <90000>;
5475                                         hysteresis = <2000>;
5476                                         type = "hot";
5477                                 };
5478                         };
5479                 };
5480
5481                 cluster0-thermal {
5482                         polling-delay-passive = <250>;
5483                         polling-delay = <1000>;
5484
5485                         thermal-sensors = <&tsens0 5>;
5486
5487                         trips {
5488                                 cluster0_alert0: trip-point0 {
5489                                         temperature = <90000>;
5490                                         hysteresis = <2000>;
5491                                         type = "hot";
5492                                 };
5493                                 cluster0_crit: cluster0_crit {
5494                                         temperature = <110000>;
5495                                         hysteresis = <2000>;
5496                                         type = "critical";
5497                                 };
5498                         };
5499                 };
5500
5501                 cluster1-thermal {
5502                         polling-delay-passive = <250>;
5503                         polling-delay = <1000>;
5504
5505                         thermal-sensors = <&tsens0 6>;
5506
5507                         trips {
5508                                 cluster1_alert0: trip-point0 {
5509                                         temperature = <90000>;
5510                                         hysteresis = <2000>;
5511                                         type = "hot";
5512                                 };
5513                                 cluster1_crit: cluster1_crit {
5514                                         temperature = <110000>;
5515                                         hysteresis = <2000>;
5516                                         type = "critical";
5517                                 };
5518                         };
5519                 };
5520
5521                 gpu-top-thermal {
5522                         polling-delay-passive = <250>;
5523                         polling-delay = <1000>;
5524
5525                         thermal-sensors = <&tsens0 11>;
5526
5527                         trips {
5528                                 gpu1_alert0: trip-point0 {
5529                                         temperature = <90000>;
5530                                         hysteresis = <2000>;
5531                                         type = "hot";
5532                                 };
5533                         };
5534                 };
5535
5536                 gpu-bottom-thermal {
5537                         polling-delay-passive = <250>;
5538                         polling-delay = <1000>;
5539
5540                         thermal-sensors = <&tsens0 12>;
5541
5542                         trips {
5543                                 gpu2_alert0: trip-point0 {
5544                                         temperature = <90000>;
5545                                         hysteresis = <2000>;
5546                                         type = "hot";
5547                                 };
5548                         };
5549                 };
5550
5551                 aoss1-thermal {
5552                         polling-delay-passive = <250>;
5553                         polling-delay = <1000>;
5554
5555                         thermal-sensors = <&tsens1 0>;
5556
5557                         trips {
5558                                 aoss1_alert0: trip-point0 {
5559                                         temperature = <90000>;
5560                                         hysteresis = <2000>;
5561                                         type = "hot";
5562                                 };
5563                         };
5564                 };
5565
5566                 q6-modem-thermal {
5567                         polling-delay-passive = <250>;
5568                         polling-delay = <1000>;
5569
5570                         thermal-sensors = <&tsens1 1>;
5571
5572                         trips {
5573                                 q6_modem_alert0: trip-point0 {
5574                                         temperature = <90000>;
5575                                         hysteresis = <2000>;
5576                                         type = "hot";
5577                                 };
5578                         };
5579                 };
5580
5581                 mem-thermal {
5582                         polling-delay-passive = <250>;
5583                         polling-delay = <1000>;
5584
5585                         thermal-sensors = <&tsens1 2>;
5586
5587                         trips {
5588                                 mem_alert0: trip-point0 {
5589                                         temperature = <90000>;
5590                                         hysteresis = <2000>;
5591                                         type = "hot";
5592                                 };
5593                         };
5594                 };
5595
5596                 wlan-thermal {
5597                         polling-delay-passive = <250>;
5598                         polling-delay = <1000>;
5599
5600                         thermal-sensors = <&tsens1 3>;
5601
5602                         trips {
5603                                 wlan_alert0: trip-point0 {
5604                                         temperature = <90000>;
5605                                         hysteresis = <2000>;
5606                                         type = "hot";
5607                                 };
5608                         };
5609                 };
5610
5611                 q6-hvx-thermal {
5612                         polling-delay-passive = <250>;
5613                         polling-delay = <1000>;
5614
5615                         thermal-sensors = <&tsens1 4>;
5616
5617                         trips {
5618                                 q6_hvx_alert0: trip-point0 {
5619                                         temperature = <90000>;
5620                                         hysteresis = <2000>;
5621                                         type = "hot";
5622                                 };
5623                         };
5624                 };
5625
5626                 camera-thermal {
5627                         polling-delay-passive = <250>;
5628                         polling-delay = <1000>;
5629
5630                         thermal-sensors = <&tsens1 5>;
5631
5632                         trips {
5633                                 camera_alert0: trip-point0 {
5634                                         temperature = <90000>;
5635                                         hysteresis = <2000>;
5636                                         type = "hot";
5637                                 };
5638                         };
5639                 };
5640
5641                 video-thermal {
5642                         polling-delay-passive = <250>;
5643                         polling-delay = <1000>;
5644
5645                         thermal-sensors = <&tsens1 6>;
5646
5647                         trips {
5648                                 video_alert0: trip-point0 {
5649                                         temperature = <90000>;
5650                                         hysteresis = <2000>;
5651                                         type = "hot";
5652                                 };
5653                         };
5654                 };
5655
5656                 modem-thermal {
5657                         polling-delay-passive = <250>;
5658                         polling-delay = <1000>;
5659
5660                         thermal-sensors = <&tsens1 7>;
5661
5662                         trips {
5663                                 modem_alert0: trip-point0 {
5664                                         temperature = <90000>;
5665                                         hysteresis = <2000>;
5666                                         type = "hot";
5667                                 };
5668                         };
5669                 };
5670         };
5671 };