1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/soc/qcom,apr.h>
19 interrupt-parent = <&intc>;
33 compatible = "fixed-clock";
35 clock-frequency = <19200000>;
36 clock-output-names = "xo_board";
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
42 clock-frequency = <32764>;
43 clock-output-names = "sleep_clk";
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&PERF_CPU_SLEEP_0
60 &PERF_CLUSTER_SLEEP_2>;
61 capacity-dmips-mhz = <1126>;
63 next-level-cache = <&L2_1>;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 cpu-idle-states = <&PERF_CPU_SLEEP_0
80 &PERF_CLUSTER_SLEEP_2>;
81 capacity-dmips-mhz = <1126>;
83 next-level-cache = <&L2_1>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 cpu-idle-states = <&PERF_CPU_SLEEP_0
95 &PERF_CLUSTER_SLEEP_2>;
96 capacity-dmips-mhz = <1126>;
98 next-level-cache = <&L2_1>;
103 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 &PERF_CLUSTER_SLEEP_0
109 &PERF_CLUSTER_SLEEP_1
110 &PERF_CLUSTER_SLEEP_2>;
111 capacity-dmips-mhz = <1126>;
112 #cooling-cells = <2>;
113 next-level-cache = <&L2_1>;
118 compatible = "arm,cortex-a53";
120 enable-method = "psci";
121 cpu-idle-states = <&PWR_CPU_SLEEP_0
125 &PWR_CLUSTER_SLEEP_2>;
126 capacity-dmips-mhz = <1024>;
127 #cooling-cells = <2>;
128 next-level-cache = <&L2_0>;
130 compatible = "cache";
138 compatible = "arm,cortex-a53";
140 enable-method = "psci";
141 cpu-idle-states = <&PWR_CPU_SLEEP_0
145 &PWR_CLUSTER_SLEEP_2>;
146 capacity-dmips-mhz = <1024>;
147 #cooling-cells = <2>;
148 next-level-cache = <&L2_0>;
153 compatible = "arm,cortex-a53";
155 enable-method = "psci";
156 cpu-idle-states = <&PWR_CPU_SLEEP_0
160 &PWR_CLUSTER_SLEEP_2>;
161 capacity-dmips-mhz = <1024>;
162 #cooling-cells = <2>;
163 next-level-cache = <&L2_0>;
168 compatible = "arm,cortex-a53";
170 enable-method = "psci";
171 cpu-idle-states = <&PWR_CPU_SLEEP_0
175 &PWR_CLUSTER_SLEEP_2>;
176 capacity-dmips-mhz = <1024>;
177 #cooling-cells = <2>;
178 next-level-cache = <&L2_0>;
220 entry-method = "psci";
222 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
223 compatible = "arm,idle-state";
224 idle-state-name = "pwr-retention";
225 arm,psci-suspend-param = <0x40000002>;
226 entry-latency-us = <338>;
227 exit-latency-us = <423>;
228 min-residency-us = <200>;
231 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
232 compatible = "arm,idle-state";
233 idle-state-name = "pwr-power-collapse";
234 arm,psci-suspend-param = <0x40000003>;
235 entry-latency-us = <515>;
236 exit-latency-us = <1821>;
237 min-residency-us = <1000>;
241 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
242 compatible = "arm,idle-state";
243 idle-state-name = "perf-retention";
244 arm,psci-suspend-param = <0x40000002>;
245 entry-latency-us = <154>;
246 exit-latency-us = <87>;
247 min-residency-us = <200>;
250 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
251 compatible = "arm,idle-state";
252 idle-state-name = "perf-power-collapse";
253 arm,psci-suspend-param = <0x40000003>;
254 entry-latency-us = <262>;
255 exit-latency-us = <301>;
256 min-residency-us = <1000>;
260 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
261 compatible = "arm,idle-state";
262 idle-state-name = "pwr-cluster-dynamic-retention";
263 arm,psci-suspend-param = <0x400000F2>;
264 entry-latency-us = <284>;
265 exit-latency-us = <384>;
266 min-residency-us = <9987>;
270 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
271 compatible = "arm,idle-state";
272 idle-state-name = "pwr-cluster-retention";
273 arm,psci-suspend-param = <0x400000F3>;
274 entry-latency-us = <338>;
275 exit-latency-us = <423>;
276 min-residency-us = <9987>;
280 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
281 compatible = "arm,idle-state";
282 idle-state-name = "pwr-cluster-retention";
283 arm,psci-suspend-param = <0x400000F4>;
284 entry-latency-us = <515>;
285 exit-latency-us = <1821>;
286 min-residency-us = <9987>;
290 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
291 compatible = "arm,idle-state";
292 idle-state-name = "perf-cluster-dynamic-retention";
293 arm,psci-suspend-param = <0x400000F2>;
294 entry-latency-us = <272>;
295 exit-latency-us = <329>;
296 min-residency-us = <9987>;
300 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
301 compatible = "arm,idle-state";
302 idle-state-name = "perf-cluster-retention";
303 arm,psci-suspend-param = <0x400000F3>;
304 entry-latency-us = <332>;
305 exit-latency-us = <368>;
306 min-residency-us = <9987>;
310 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
311 compatible = "arm,idle-state";
312 idle-state-name = "perf-cluster-retention";
313 arm,psci-suspend-param = <0x400000F4>;
314 entry-latency-us = <545>;
315 exit-latency-us = <1609>;
316 min-residency-us = <9987>;
324 compatible = "qcom,scm-msm8998", "qcom,scm";
329 device_type = "memory";
330 /* We expect the bootloader to fill in the reg */
331 reg = <0x0 0x80000000 0x0 0x0>;
334 dsi_opp_table: opp-table-dsi {
335 compatible = "operating-points-v2";
338 opp-hz = /bits/ 64 <131250000>;
339 required-opps = <&rpmpd_opp_svs>;
343 opp-hz = /bits/ 64 <210000000>;
344 required-opps = <&rpmpd_opp_svs_plus>;
348 opp-hz = /bits/ 64 <262500000>;
349 required-opps = <&rpmpd_opp_nom>;
354 compatible = "arm,armv8-pmuv3";
355 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
359 compatible = "arm,psci-1.0";
364 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
367 compatible = "qcom,glink-rpm";
369 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
370 qcom,rpm-msg-ram = <&rpm_msg_ram>;
371 mboxes = <&apcs_glb 0>;
373 rpm_requests: rpm-requests {
374 compatible = "qcom,rpm-sdm660";
375 qcom,glink-channels = "rpm_requests";
377 rpmcc: clock-controller {
378 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
382 rpmpd: power-controller {
383 compatible = "qcom,sdm660-rpmpd";
384 #power-domain-cells = <1>;
385 operating-points-v2 = <&rpmpd_opp_table>;
387 rpmpd_opp_table: opp-table {
388 compatible = "operating-points-v2";
390 rpmpd_opp_ret: opp1 {
391 opp-level = <RPM_SMD_LEVEL_RETENTION>;
394 rpmpd_opp_ret_plus: opp2 {
395 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
398 rpmpd_opp_min_svs: opp3 {
399 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
402 rpmpd_opp_low_svs: opp4 {
403 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
406 rpmpd_opp_svs: opp5 {
407 opp-level = <RPM_SMD_LEVEL_SVS>;
410 rpmpd_opp_svs_plus: opp6 {
411 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
414 rpmpd_opp_nom: opp7 {
415 opp-level = <RPM_SMD_LEVEL_NOM>;
418 rpmpd_opp_nom_plus: opp8 {
419 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
422 rpmpd_opp_turbo: opp9 {
423 opp-level = <RPM_SMD_LEVEL_TURBO>;
432 #address-cells = <2>;
436 wlan_msa_guard: wlan-msa-guard@85600000 {
437 reg = <0x0 0x85600000 0x0 0x100000>;
441 wlan_msa_mem: wlan-msa-mem@85700000 {
442 reg = <0x0 0x85700000 0x0 0x100000>;
446 qhee_code: qhee-code@85800000 {
447 reg = <0x0 0x85800000 0x0 0x600000>;
451 rmtfs_mem: memory@85e00000 {
452 compatible = "qcom,rmtfs-mem";
453 reg = <0x0 0x85e00000 0x0 0x200000>;
456 qcom,client-id = <1>;
457 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
460 smem_region: smem-mem@86000000 {
461 reg = <0 0x86000000 0 0x200000>;
465 tz_mem: memory@86200000 {
466 reg = <0x0 0x86200000 0x0 0x3300000>;
470 mpss_region: mpss@8ac00000 {
471 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
475 adsp_region: adsp@92a00000 {
476 reg = <0x0 0x92a00000 0x0 0x1e00000>;
480 mba_region: mba@94800000 {
481 reg = <0x0 0x94800000 0x0 0x200000>;
485 buffer_mem: tzbuffer@94a00000 {
486 reg = <0x0 0x94a00000 0x0 0x100000>;
490 venus_region: venus@9f800000 {
491 reg = <0x0 0x9f800000 0x0 0x800000>;
495 adsp_mem: adsp-region@f6000000 {
496 reg = <0x0 0xf6000000 0x0 0x800000>;
500 qseecom_mem: qseecom-region@f6800000 {
501 reg = <0x0 0xf6800000 0x0 0x1400000>;
505 zap_shader_region: gpu@fed00000 {
506 compatible = "shared-dma-pool";
507 reg = <0x0 0xfed00000 0x0 0xa00000>;
513 compatible = "qcom,smem";
514 memory-region = <&smem_region>;
515 hwlocks = <&tcsr_mutex 3>;
519 compatible = "qcom,smp2p";
520 qcom,smem = <443>, <429>;
521 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
522 mboxes = <&apcs_glb 10>;
523 qcom,local-pid = <0>;
524 qcom,remote-pid = <2>;
526 adsp_smp2p_out: master-kernel {
527 qcom,entry-name = "master-kernel";
528 #qcom,smem-state-cells = <1>;
531 adsp_smp2p_in: slave-kernel {
532 qcom,entry-name = "slave-kernel";
533 interrupt-controller;
534 #interrupt-cells = <2>;
539 compatible = "qcom,smp2p";
540 qcom,smem = <435>, <428>;
541 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
542 mboxes = <&apcs_glb 14>;
543 qcom,local-pid = <0>;
544 qcom,remote-pid = <1>;
546 modem_smp2p_out: master-kernel {
547 qcom,entry-name = "master-kernel";
548 #qcom,smem-state-cells = <1>;
551 modem_smp2p_in: slave-kernel {
552 qcom,entry-name = "slave-kernel";
553 interrupt-controller;
554 #interrupt-cells = <2>;
559 #address-cells = <1>;
561 ranges = <0 0 0 0xffffffff>;
562 compatible = "simple-bus";
564 gcc: clock-controller@100000 {
565 compatible = "qcom,gcc-sdm630";
568 #power-domain-cells = <1>;
569 reg = <0x00100000 0x94000>;
571 clock-names = "xo", "sleep_clk";
572 clocks = <&xo_board>,
576 rpm_msg_ram: sram@778000 {
577 compatible = "qcom,rpm-msg-ram";
578 reg = <0x00778000 0x7000>;
581 qfprom: qfprom@780000 {
582 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
583 reg = <0x00780000 0x621c>;
584 #address-cells = <1>;
587 qusb2_hstx_trim: hstx-trim@240 {
592 gpu_speed_bin: gpu-speed-bin@41a0 {
599 compatible = "qcom,prng-ee";
600 reg = <0x00793000 0x1000>;
601 clocks = <&gcc GCC_PRNG_AHB_CLK>;
602 clock-names = "core";
605 bimc: interconnect@1008000 {
606 compatible = "qcom,sdm660-bimc";
607 reg = <0x01008000 0x78000>;
608 #interconnect-cells = <1>;
609 clock-names = "bus", "bus_a";
610 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
611 <&rpmcc RPM_SMD_BIMC_A_CLK>;
615 compatible = "qcom,pshold";
616 reg = <0x010ac000 0x4>;
619 cnoc: interconnect@1500000 {
620 compatible = "qcom,sdm660-cnoc";
621 reg = <0x01500000 0x10000>;
622 #interconnect-cells = <1>;
623 clock-names = "bus", "bus_a";
624 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
625 <&rpmcc RPM_SMD_CNOC_A_CLK>;
628 snoc: interconnect@1626000 {
629 compatible = "qcom,sdm660-snoc";
630 reg = <0x01626000 0x7090>;
631 #interconnect-cells = <1>;
632 clock-names = "bus", "bus_a";
633 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
634 <&rpmcc RPM_SMD_SNOC_A_CLK>;
637 anoc2_smmu: iommu@16c0000 {
638 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
639 reg = <0x016c0000 0x40000>;
641 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
642 assigned-clock-rates = <1000>;
643 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
645 #global-interrupts = <2>;
649 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
654 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
655 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
656 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
657 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
658 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
685 a2noc: interconnect@1704000 {
686 compatible = "qcom,sdm660-a2noc";
687 reg = <0x01704000 0xc100>;
688 #interconnect-cells = <1>;
696 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
697 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
698 <&rpmcc RPM_SMD_IPA_CLK>,
699 <&gcc GCC_UFS_AXI_CLK>,
700 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
701 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
702 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
705 mnoc: interconnect@1745000 {
706 compatible = "qcom,sdm660-mnoc";
707 reg = <0x01745000 0xa010>;
708 #interconnect-cells = <1>;
709 clock-names = "bus", "bus_a", "iface";
710 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
711 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
715 tsens: thermal-sensor@10ae000 {
716 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
717 reg = <0x010ae000 0x1000>, /* TM */
718 <0x010ad000 0x1000>; /* SROT */
719 #qcom,sensors = <12>;
720 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
722 interrupt-names = "uplow", "critical";
723 #thermal-sensor-cells = <1>;
726 tcsr_mutex: hwlock@1f40000 {
727 compatible = "qcom,tcsr-mutex";
728 reg = <0x01f40000 0x20000>;
732 tcsr_regs_1: syscon@1f60000 {
733 compatible = "qcom,sdm630-tcsr", "syscon";
734 reg = <0x01f60000 0x20000>;
737 tlmm: pinctrl@3100000 {
738 compatible = "qcom,sdm630-pinctrl";
739 reg = <0x03100000 0x400000>,
740 <0x03500000 0x400000>,
741 <0x03900000 0x400000>;
742 reg-names = "south", "center", "north";
743 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
745 gpio-ranges = <&tlmm 0 0 114>;
747 interrupt-controller;
748 #interrupt-cells = <2>;
750 blsp1_uart1_default: blsp1-uart1-default-state {
751 pins = "gpio0", "gpio1", "gpio2", "gpio3";
752 function = "blsp_uart1";
753 drive-strength = <2>;
757 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
758 pins = "gpio0", "gpio1", "gpio2", "gpio3";
760 drive-strength = <2>;
764 blsp1_uart2_default: blsp1-uart2-default-state {
765 pins = "gpio4", "gpio5";
766 function = "blsp_uart2";
767 drive-strength = <2>;
771 blsp2_uart1_default: blsp2-uart1-active-state {
773 pins = "gpio16", "gpio19";
774 function = "blsp_uart5";
775 drive-strength = <2>;
781 * Avoid garbage data while BT module
782 * is powered off or not driving signal
785 function = "blsp_uart5";
786 drive-strength = <2>;
791 /* Match the pull of the BT module */
793 function = "blsp_uart5";
794 drive-strength = <2>;
799 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
803 drive-strength = <2>;
808 pins = "gpio17", "gpio18", "gpio19";
810 drive-strength = <2>;
815 i2c1_default: i2c1-default-state {
816 pins = "gpio2", "gpio3";
817 function = "blsp_i2c1";
818 drive-strength = <2>;
822 i2c1_sleep: i2c1-sleep-state {
823 pins = "gpio2", "gpio3";
824 function = "blsp_i2c1";
825 drive-strength = <2>;
829 i2c2_default: i2c2-default-state {
830 pins = "gpio6", "gpio7";
831 function = "blsp_i2c2";
832 drive-strength = <2>;
836 i2c2_sleep: i2c2-sleep-state {
837 pins = "gpio6", "gpio7";
838 function = "blsp_i2c2";
839 drive-strength = <2>;
843 i2c3_default: i2c3-default-state {
844 pins = "gpio10", "gpio11";
845 function = "blsp_i2c3";
846 drive-strength = <2>;
850 i2c3_sleep: i2c3-sleep-state {
851 pins = "gpio10", "gpio11";
852 function = "blsp_i2c3";
853 drive-strength = <2>;
857 i2c4_default: i2c4-default-state {
858 pins = "gpio14", "gpio15";
859 function = "blsp_i2c4";
860 drive-strength = <2>;
864 i2c4_sleep: i2c4-sleep-state {
865 pins = "gpio14", "gpio15";
866 function = "blsp_i2c4";
867 drive-strength = <2>;
871 i2c5_default: i2c5-default-state {
872 pins = "gpio18", "gpio19";
873 function = "blsp_i2c5";
874 drive-strength = <2>;
878 i2c5_sleep: i2c5-sleep-state {
879 pins = "gpio18", "gpio19";
880 function = "blsp_i2c5";
881 drive-strength = <2>;
885 i2c6_default: i2c6-default-state {
886 pins = "gpio22", "gpio23";
887 function = "blsp_i2c6";
888 drive-strength = <2>;
892 i2c6_sleep: i2c6-sleep-state {
893 pins = "gpio22", "gpio23";
894 function = "blsp_i2c6";
895 drive-strength = <2>;
899 i2c7_default: i2c7-default-state {
900 pins = "gpio26", "gpio27";
901 function = "blsp_i2c7";
902 drive-strength = <2>;
906 i2c7_sleep: i2c7-sleep-state {
907 pins = "gpio26", "gpio27";
908 function = "blsp_i2c7";
909 drive-strength = <2>;
913 i2c8_default: i2c8-default-state {
914 pins = "gpio30", "gpio31";
915 function = "blsp_i2c8_a";
916 drive-strength = <2>;
920 i2c8_sleep: i2c8-sleep-state {
921 pins = "gpio30", "gpio31";
922 function = "blsp_i2c8_a";
923 drive-strength = <2>;
927 cci0_default: cci0-default-state {
928 pins = "gpio36","gpio37";
929 function = "cci_i2c";
931 drive-strength = <2>;
934 cci1_default: cci1-default-state {
935 pins = "gpio38","gpio39";
936 function = "cci_i2c";
938 drive-strength = <2>;
941 sdc1_state_on: sdc1-on-state {
945 drive-strength = <16>;
951 drive-strength = <10>;
957 drive-strength = <10>;
966 sdc1_state_off: sdc1-off-state {
970 drive-strength = <2>;
976 drive-strength = <2>;
982 drive-strength = <2>;
991 sdc2_state_on: sdc2-on-state {
995 drive-strength = <16>;
1001 drive-strength = <10>;
1007 drive-strength = <10>;
1011 sdc2_state_off: sdc2-off-state {
1015 drive-strength = <2>;
1021 drive-strength = <2>;
1027 drive-strength = <2>;
1032 remoteproc_mss: remoteproc@4080000 {
1033 compatible = "qcom,sdm660-mss-pil";
1034 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1035 reg-names = "qdsp6", "rmb";
1037 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1038 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1039 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1040 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1041 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1042 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1043 interrupt-names = "wdog",
1050 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1051 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1052 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1053 <&gcc GPLL0_OUT_MSSCC>,
1054 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1055 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1056 <&rpmcc RPM_SMD_QDSS_CLK>,
1057 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1058 clock-names = "iface",
1067 qcom,smem-states = <&modem_smp2p_out 0>;
1068 qcom,smem-state-names = "stop";
1070 resets = <&gcc GCC_MSS_RESTART>;
1071 reset-names = "mss_restart";
1073 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1075 power-domains = <&rpmpd SDM660_VDDCX>,
1076 <&rpmpd SDM660_VDDMX>;
1077 power-domain-names = "cx", "mx";
1079 memory-region = <&mba_region>, <&mpss_region>;
1081 status = "disabled";
1084 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1086 qcom,remote-pid = <1>;
1087 mboxes = <&apcs_glb 15>;
1091 adreno_gpu: gpu@5000000 {
1092 compatible = "qcom,adreno-508.0", "qcom,adreno";
1094 reg = <0x05000000 0x40000>;
1095 reg-names = "kgsl_3d0_reg_memory";
1097 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1099 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1100 <&gpucc GPUCC_RBBMTIMER_CLK>,
1101 <&gcc GCC_BIMC_GFX_CLK>,
1102 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1103 <&gpucc GPUCC_RBCPR_CLK>,
1104 <&gpucc GPUCC_GFX3D_CLK>;
1106 clock-names = "iface",
1113 power-domains = <&rpmpd SDM660_VDDMX>;
1114 iommus = <&kgsl_smmu 0>;
1116 nvmem-cells = <&gpu_speed_bin>;
1117 nvmem-cell-names = "speed_bin";
1119 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1120 interconnect-names = "gfx-mem";
1122 operating-points-v2 = <&gpu_sdm630_opp_table>;
1124 status = "disabled";
1126 gpu_sdm630_opp_table: opp-table {
1127 compatible = "operating-points-v2";
1129 opp-hz = /bits/ 64 <775000000>;
1130 opp-level = <RPM_SMD_LEVEL_TURBO>;
1131 opp-peak-kBps = <5412000>;
1132 opp-supported-hw = <0xa2>;
1135 opp-hz = /bits/ 64 <647000000>;
1136 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1137 opp-peak-kBps = <4068000>;
1138 opp-supported-hw = <0xff>;
1141 opp-hz = /bits/ 64 <588000000>;
1142 opp-level = <RPM_SMD_LEVEL_NOM>;
1143 opp-peak-kBps = <3072000>;
1144 opp-supported-hw = <0xff>;
1147 opp-hz = /bits/ 64 <465000000>;
1148 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1149 opp-peak-kBps = <2724000>;
1150 opp-supported-hw = <0xff>;
1153 opp-hz = /bits/ 64 <370000000>;
1154 opp-level = <RPM_SMD_LEVEL_SVS>;
1155 opp-peak-kBps = <2188000>;
1156 opp-supported-hw = <0xff>;
1159 opp-hz = /bits/ 64 <240000000>;
1160 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1161 opp-peak-kBps = <1648000>;
1162 opp-supported-hw = <0xff>;
1165 opp-hz = /bits/ 64 <160000000>;
1166 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1167 opp-peak-kBps = <1200000>;
1168 opp-supported-hw = <0xff>;
1173 kgsl_smmu: iommu@5040000 {
1174 compatible = "qcom,sdm630-smmu-v2",
1175 "qcom,adreno-smmu", "qcom,smmu-v2";
1176 reg = <0x05040000 0x10000>;
1179 * GX GDSC parent is CX. We need to bring up CX for SMMU
1180 * but we need both up for Adreno. On the other hand, we
1181 * need to manage the GX rpmpd domain in the adreno driver.
1182 * Enable CX/GX GDSCs here so that we can manage just the GX
1183 * RPM Power Domain in the Adreno driver.
1185 power-domains = <&gpucc GPU_GX_GDSC>;
1186 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1187 <&gcc GCC_BIMC_GFX_CLK>,
1188 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1189 clock-names = "iface", "mem", "mem_iface";
1190 #global-interrupts = <2>;
1194 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1206 status = "disabled";
1209 gpucc: clock-controller@5065000 {
1210 compatible = "qcom,gpucc-sdm630";
1213 #power-domain-cells = <1>;
1214 reg = <0x05065000 0x9038>;
1216 clocks = <&xo_board>,
1217 <&gcc GCC_GPU_GPLL0_CLK>,
1218 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1220 "gcc_gpu_gpll0_clk",
1221 "gcc_gpu_gpll0_div_clk";
1222 status = "disabled";
1225 lpass_smmu: iommu@5100000 {
1226 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1227 reg = <0x05100000 0x40000>;
1230 #global-interrupts = <2>;
1232 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1253 status = "disabled";
1257 compatible = "qcom,rpm-stats";
1258 reg = <0x00290000 0x10000>;
1261 spmi_bus: spmi@800f000 {
1262 compatible = "qcom,spmi-pmic-arb";
1263 reg = <0x0800f000 0x1000>,
1264 <0x08400000 0x1000000>,
1265 <0x09400000 0x1000000>,
1266 <0x0a400000 0x220000>,
1267 <0x0800a000 0x3000>;
1268 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1269 interrupt-names = "periph_irq";
1270 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1273 #address-cells = <2>;
1275 interrupt-controller;
1276 #interrupt-cells = <4>;
1280 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1281 reg = <0x0a8f8800 0x400>;
1282 status = "disabled";
1283 #address-cells = <1>;
1287 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1288 <&gcc GCC_USB30_MASTER_CLK>,
1289 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1290 <&gcc GCC_USB30_SLEEP_CLK>,
1291 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1292 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1293 clock-names = "cfg_noc",
1300 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1301 <&gcc GCC_USB30_MASTER_CLK>,
1302 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1303 assigned-clock-rates = <19200000>, <120000000>,
1306 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1308 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1310 power-domains = <&gcc USB_30_GDSC>;
1311 qcom,select-utmi-as-pipe-clk;
1313 resets = <&gcc GCC_USB_30_BCR>;
1315 usb3_dwc3: usb@a800000 {
1316 compatible = "snps,dwc3";
1317 reg = <0x0a800000 0xc8d0>;
1318 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1319 snps,dis_u2_susphy_quirk;
1320 snps,dis_enblslpm_quirk;
1323 * SDM630 technically supports USB3 but I
1324 * haven't seen any devices making use of it.
1326 maximum-speed = "high-speed";
1327 phys = <&qusb2phy0>;
1328 phy-names = "usb2-phy";
1329 snps,hird-threshold = /bits/ 8 <0>;
1333 qusb2phy0: phy@c012000 {
1334 compatible = "qcom,sdm660-qusb2-phy";
1335 reg = <0x0c012000 0x180>;
1338 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1339 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1340 clock-names = "cfg_ahb", "ref";
1342 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1343 nvmem-cells = <&qusb2_hstx_trim>;
1344 status = "disabled";
1347 qusb2phy1: phy@c014000 {
1348 compatible = "qcom,sdm660-qusb2-phy";
1349 reg = <0x0c014000 0x180>;
1352 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1353 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1354 clock-names = "cfg_ahb", "ref";
1356 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1357 nvmem-cells = <&qusb2_hstx_trim>;
1358 status = "disabled";
1361 sdhc_2: mmc@c084000 {
1362 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1363 reg = <0x0c084000 0x1000>;
1366 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-names = "hc_irq", "pwr_irq";
1372 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1373 <&gcc GCC_SDCC2_APPS_CLK>,
1375 clock-names = "iface", "core", "xo";
1378 interconnects = <&a2noc 3 &a2noc 10>,
1380 interconnect-names = "sdhc-ddr","cpu-sdhc";
1381 operating-points-v2 = <&sdhc2_opp_table>;
1383 pinctrl-names = "default", "sleep";
1384 pinctrl-0 = <&sdc2_state_on>;
1385 pinctrl-1 = <&sdc2_state_off>;
1386 power-domains = <&rpmpd SDM660_VDDCX>;
1388 status = "disabled";
1390 sdhc2_opp_table: opp-table {
1391 compatible = "operating-points-v2";
1394 opp-hz = /bits/ 64 <50000000>;
1395 required-opps = <&rpmpd_opp_low_svs>;
1396 opp-peak-kBps = <200000 140000>;
1397 opp-avg-kBps = <130718 133320>;
1400 opp-hz = /bits/ 64 <100000000>;
1401 required-opps = <&rpmpd_opp_svs>;
1402 opp-peak-kBps = <250000 160000>;
1403 opp-avg-kBps = <196078 150000>;
1406 opp-hz = /bits/ 64 <200000000>;
1407 required-opps = <&rpmpd_opp_nom>;
1408 opp-peak-kBps = <4096000 4096000>;
1409 opp-avg-kBps = <1338562 1338562>;
1414 sdhc_1: mmc@c0c4000 {
1415 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1416 reg = <0x0c0c4000 0x1000>,
1417 <0x0c0c5000 0x1000>,
1418 <0x0c0c8000 0x8000>;
1419 reg-names = "hc", "cqhci", "ice";
1421 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1423 interrupt-names = "hc_irq", "pwr_irq";
1425 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1426 <&gcc GCC_SDCC1_APPS_CLK>,
1428 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1429 clock-names = "iface", "core", "xo", "ice";
1431 interconnects = <&a2noc 2 &a2noc 10>,
1433 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1434 operating-points-v2 = <&sdhc1_opp_table>;
1435 pinctrl-names = "default", "sleep";
1436 pinctrl-0 = <&sdc1_state_on>;
1437 pinctrl-1 = <&sdc1_state_off>;
1438 power-domains = <&rpmpd SDM660_VDDCX>;
1443 status = "disabled";
1445 sdhc1_opp_table: opp-table {
1446 compatible = "operating-points-v2";
1449 opp-hz = /bits/ 64 <50000000>;
1450 required-opps = <&rpmpd_opp_low_svs>;
1451 opp-peak-kBps = <200000 140000>;
1452 opp-avg-kBps = <130718 133320>;
1455 opp-hz = /bits/ 64 <100000000>;
1456 required-opps = <&rpmpd_opp_svs>;
1457 opp-peak-kBps = <250000 160000>;
1458 opp-avg-kBps = <196078 150000>;
1461 opp-hz = /bits/ 64 <384000000>;
1462 required-opps = <&rpmpd_opp_nom>;
1463 opp-peak-kBps = <4096000 4096000>;
1464 opp-avg-kBps = <1338562 1338562>;
1470 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1471 reg = <0x0c2f8800 0x400>;
1472 status = "disabled";
1473 #address-cells = <1>;
1477 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1478 <&gcc GCC_USB20_MASTER_CLK>,
1479 <&gcc GCC_USB20_SLEEP_CLK>,
1480 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1481 clock-names = "cfg_noc", "core",
1482 "sleep", "mock_utmi";
1484 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1485 <&gcc GCC_USB20_MASTER_CLK>;
1486 assigned-clock-rates = <19200000>, <60000000>;
1488 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1489 interrupt-names = "hs_phy_irq";
1491 qcom,select-utmi-as-pipe-clk;
1493 resets = <&gcc GCC_USB_20_BCR>;
1495 usb2_dwc3: usb@c200000 {
1496 compatible = "snps,dwc3";
1497 reg = <0x0c200000 0xc8d0>;
1498 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1499 snps,dis_u2_susphy_quirk;
1500 snps,dis_enblslpm_quirk;
1502 /* This is the HS-only host */
1503 maximum-speed = "high-speed";
1504 phys = <&qusb2phy1>;
1505 phy-names = "usb2-phy";
1506 snps,hird-threshold = /bits/ 8 <0>;
1510 mmcc: clock-controller@c8c0000 {
1511 compatible = "qcom,mmcc-sdm630";
1512 reg = <0x0c8c0000 0x40000>;
1515 #power-domain-cells = <1>;
1524 "dp_link_2x_clk_divsel_five",
1525 "dp_vco_divided_clk_src_mux";
1526 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1528 <&gcc GCC_MMSS_GPLL0_CLK>,
1529 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1538 mdss: display-subsystem@c900000 {
1539 compatible = "qcom,mdss";
1540 reg = <0x0c900000 0x1000>,
1541 <0x0c9b0000 0x1040>;
1542 reg-names = "mdss_phys", "vbif_phys";
1544 power-domains = <&mmcc MDSS_GDSC>;
1546 clocks = <&mmcc MDSS_AHB_CLK>,
1547 <&mmcc MDSS_AXI_CLK>,
1548 <&mmcc MDSS_VSYNC_CLK>,
1549 <&mmcc MDSS_MDP_CLK>;
1550 clock-names = "iface",
1555 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1557 interrupt-controller;
1558 #interrupt-cells = <1>;
1560 #address-cells = <1>;
1563 status = "disabled";
1565 mdp: display-controller@c901000 {
1566 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1567 reg = <0x0c901000 0x89000>;
1568 reg-names = "mdp_phys";
1570 interrupt-parent = <&mdss>;
1573 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1574 <&mmcc MDSS_VSYNC_CLK>;
1575 assigned-clock-rates = <300000000>,
1577 clocks = <&mmcc MDSS_AHB_CLK>,
1578 <&mmcc MDSS_AXI_CLK>,
1579 <&mmcc MDSS_MDP_CLK>,
1580 <&mmcc MDSS_VSYNC_CLK>;
1581 clock-names = "iface",
1586 interconnects = <&mnoc 2 &bimc 5>,
1589 interconnect-names = "mdp0-mem",
1592 iommus = <&mmss_smmu 0>;
1593 operating-points-v2 = <&mdp_opp_table>;
1594 power-domains = <&rpmpd SDM660_VDDCX>;
1597 #address-cells = <1>;
1602 mdp5_intf1_out: endpoint {
1603 remote-endpoint = <&mdss_dsi0_in>;
1608 mdp_opp_table: opp-table {
1609 compatible = "operating-points-v2";
1612 opp-hz = /bits/ 64 <150000000>;
1613 opp-peak-kBps = <320000 320000 76800>;
1614 required-opps = <&rpmpd_opp_low_svs>;
1617 opp-hz = /bits/ 64 <275000000>;
1618 opp-peak-kBps = <6400000 6400000 160000>;
1619 required-opps = <&rpmpd_opp_svs>;
1622 opp-hz = /bits/ 64 <300000000>;
1623 opp-peak-kBps = <6400000 6400000 190000>;
1624 required-opps = <&rpmpd_opp_svs_plus>;
1627 opp-hz = /bits/ 64 <330000000>;
1628 opp-peak-kBps = <6400000 6400000 240000>;
1629 required-opps = <&rpmpd_opp_nom>;
1632 opp-hz = /bits/ 64 <412500000>;
1633 opp-peak-kBps = <6400000 6400000 320000>;
1634 required-opps = <&rpmpd_opp_turbo>;
1639 mdss_dsi0: dsi@c994000 {
1640 compatible = "qcom,sdm660-dsi-ctrl",
1641 "qcom,mdss-dsi-ctrl";
1642 reg = <0x0c994000 0x400>;
1643 reg-names = "dsi_ctrl";
1645 operating-points-v2 = <&dsi_opp_table>;
1646 power-domains = <&rpmpd SDM660_VDDCX>;
1648 interrupt-parent = <&mdss>;
1651 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1652 <&mmcc PCLK0_CLK_SRC>;
1653 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1656 clocks = <&mmcc MDSS_MDP_CLK>,
1657 <&mmcc MDSS_BYTE0_CLK>,
1658 <&mmcc MDSS_BYTE0_INTF_CLK>,
1659 <&mmcc MNOC_AHB_CLK>,
1660 <&mmcc MDSS_AHB_CLK>,
1661 <&mmcc MDSS_AXI_CLK>,
1662 <&mmcc MISC_AHB_CLK>,
1663 <&mmcc MDSS_PCLK0_CLK>,
1664 <&mmcc MDSS_ESC0_CLK>;
1665 clock-names = "mdp_core",
1675 phys = <&mdss_dsi0_phy>;
1677 status = "disabled";
1680 #address-cells = <1>;
1685 mdss_dsi0_in: endpoint {
1686 remote-endpoint = <&mdp5_intf1_out>;
1692 mdss_dsi0_out: endpoint {
1698 mdss_dsi0_phy: phy@c994400 {
1699 compatible = "qcom,dsi-phy-14nm-660";
1700 reg = <0x0c994400 0x100>,
1703 reg-names = "dsi_phy",
1710 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1711 clock-names = "iface", "ref";
1712 status = "disabled";
1716 blsp1_dma: dma-controller@c144000 {
1717 compatible = "qcom,bam-v1.7.0";
1718 reg = <0x0c144000 0x1f000>;
1719 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1720 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1721 clock-names = "bam_clk";
1724 qcom,controlled-remotely;
1725 num-channels = <18>;
1729 blsp1_uart1: serial@c16f000 {
1730 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1731 reg = <0x0c16f000 0x200>;
1732 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1733 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1734 <&gcc GCC_BLSP1_AHB_CLK>;
1735 clock-names = "core", "iface";
1736 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1737 dma-names = "tx", "rx";
1738 pinctrl-names = "default", "sleep";
1739 pinctrl-0 = <&blsp1_uart1_default>;
1740 pinctrl-1 = <&blsp1_uart1_sleep>;
1741 status = "disabled";
1744 blsp1_uart2: serial@c170000 {
1745 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1746 reg = <0x0c170000 0x1000>;
1747 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1748 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1749 <&gcc GCC_BLSP1_AHB_CLK>;
1750 clock-names = "core", "iface";
1751 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1752 dma-names = "tx", "rx";
1753 pinctrl-names = "default";
1754 pinctrl-0 = <&blsp1_uart2_default>;
1755 status = "disabled";
1758 blsp_i2c1: i2c@c175000 {
1759 compatible = "qcom,i2c-qup-v2.2.1";
1760 reg = <0x0c175000 0x600>;
1761 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1763 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1764 <&gcc GCC_BLSP1_AHB_CLK>;
1765 clock-names = "core", "iface";
1766 clock-frequency = <400000>;
1767 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1768 dma-names = "tx", "rx";
1770 pinctrl-names = "default", "sleep";
1771 pinctrl-0 = <&i2c1_default>;
1772 pinctrl-1 = <&i2c1_sleep>;
1773 #address-cells = <1>;
1775 status = "disabled";
1778 blsp_i2c2: i2c@c176000 {
1779 compatible = "qcom,i2c-qup-v2.2.1";
1780 reg = <0x0c176000 0x600>;
1781 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1783 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1784 <&gcc GCC_BLSP1_AHB_CLK>;
1785 clock-names = "core", "iface";
1786 clock-frequency = <400000>;
1787 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1788 dma-names = "tx", "rx";
1790 pinctrl-names = "default", "sleep";
1791 pinctrl-0 = <&i2c2_default>;
1792 pinctrl-1 = <&i2c2_sleep>;
1793 #address-cells = <1>;
1795 status = "disabled";
1798 blsp_i2c3: i2c@c177000 {
1799 compatible = "qcom,i2c-qup-v2.2.1";
1800 reg = <0x0c177000 0x600>;
1801 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1803 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1804 <&gcc GCC_BLSP1_AHB_CLK>;
1805 clock-names = "core", "iface";
1806 clock-frequency = <400000>;
1807 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1808 dma-names = "tx", "rx";
1810 pinctrl-names = "default", "sleep";
1811 pinctrl-0 = <&i2c3_default>;
1812 pinctrl-1 = <&i2c3_sleep>;
1813 #address-cells = <1>;
1815 status = "disabled";
1818 blsp_i2c4: i2c@c178000 {
1819 compatible = "qcom,i2c-qup-v2.2.1";
1820 reg = <0x0c178000 0x600>;
1821 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1823 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1824 <&gcc GCC_BLSP1_AHB_CLK>;
1825 clock-names = "core", "iface";
1826 clock-frequency = <400000>;
1827 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1828 dma-names = "tx", "rx";
1830 pinctrl-names = "default", "sleep";
1831 pinctrl-0 = <&i2c4_default>;
1832 pinctrl-1 = <&i2c4_sleep>;
1833 #address-cells = <1>;
1835 status = "disabled";
1838 blsp2_dma: dma-controller@c184000 {
1839 compatible = "qcom,bam-v1.7.0";
1840 reg = <0x0c184000 0x1f000>;
1841 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1842 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1843 clock-names = "bam_clk";
1846 qcom,controlled-remotely;
1847 num-channels = <18>;
1851 blsp2_uart1: serial@c1af000 {
1852 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1853 reg = <0x0c1af000 0x200>;
1854 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1855 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1856 <&gcc GCC_BLSP2_AHB_CLK>;
1857 clock-names = "core", "iface";
1858 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1859 dma-names = "tx", "rx";
1860 pinctrl-names = "default", "sleep";
1861 pinctrl-0 = <&blsp2_uart1_default>;
1862 pinctrl-1 = <&blsp2_uart1_sleep>;
1863 status = "disabled";
1866 blsp_i2c5: i2c@c1b5000 {
1867 compatible = "qcom,i2c-qup-v2.2.1";
1868 reg = <0x0c1b5000 0x600>;
1869 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1871 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1872 <&gcc GCC_BLSP2_AHB_CLK>;
1873 clock-names = "core", "iface";
1874 clock-frequency = <400000>;
1875 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1876 dma-names = "tx", "rx";
1878 pinctrl-names = "default", "sleep";
1879 pinctrl-0 = <&i2c5_default>;
1880 pinctrl-1 = <&i2c5_sleep>;
1881 #address-cells = <1>;
1883 status = "disabled";
1886 blsp_i2c6: i2c@c1b6000 {
1887 compatible = "qcom,i2c-qup-v2.2.1";
1888 reg = <0x0c1b6000 0x600>;
1889 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1891 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1892 <&gcc GCC_BLSP2_AHB_CLK>;
1893 clock-names = "core", "iface";
1894 clock-frequency = <400000>;
1895 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1896 dma-names = "tx", "rx";
1898 pinctrl-names = "default", "sleep";
1899 pinctrl-0 = <&i2c6_default>;
1900 pinctrl-1 = <&i2c6_sleep>;
1901 #address-cells = <1>;
1903 status = "disabled";
1906 blsp_i2c7: i2c@c1b7000 {
1907 compatible = "qcom,i2c-qup-v2.2.1";
1908 reg = <0x0c1b7000 0x600>;
1909 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1911 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1912 <&gcc GCC_BLSP2_AHB_CLK>;
1913 clock-names = "core", "iface";
1914 clock-frequency = <400000>;
1915 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1916 dma-names = "tx", "rx";
1918 pinctrl-names = "default", "sleep";
1919 pinctrl-0 = <&i2c7_default>;
1920 pinctrl-1 = <&i2c7_sleep>;
1921 #address-cells = <1>;
1923 status = "disabled";
1926 blsp_i2c8: i2c@c1b8000 {
1927 compatible = "qcom,i2c-qup-v2.2.1";
1928 reg = <0x0c1b8000 0x600>;
1929 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1931 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1932 <&gcc GCC_BLSP2_AHB_CLK>;
1933 clock-names = "core", "iface";
1934 clock-frequency = <400000>;
1935 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1936 dma-names = "tx", "rx";
1938 pinctrl-names = "default", "sleep";
1939 pinctrl-0 = <&i2c8_default>;
1940 pinctrl-1 = <&i2c8_sleep>;
1941 #address-cells = <1>;
1943 status = "disabled";
1947 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1948 reg = <0x146bf000 0x1000>;
1950 #address-cells = <1>;
1953 ranges = <0 0x146bf000 0x1000>;
1956 compatible = "qcom,pil-reloc-info";
1961 camss: camss@ca00020 {
1962 compatible = "qcom,sdm660-camss";
1963 reg = <0x0ca00020 0x10>,
1968 <0x0c824000 0x1000>,
1970 <0x0c825000 0x1000>,
1972 <0x0c826000 0x1000>,
1975 <0x0ca10000 0x1000>,
1976 <0x0ca14000 0x1000>;
1977 reg-names = "csi_clk_mux",
1991 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1992 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1993 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1994 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1995 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1996 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1997 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1998 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1999 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2000 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2001 interrupt-names = "csid0",
2011 clocks = <&mmcc CAMSS_AHB_CLK>,
2012 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2013 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2014 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2015 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2016 <&mmcc CAMSS_CSI0_AHB_CLK>,
2017 <&mmcc CAMSS_CSI0_CLK>,
2018 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2019 <&mmcc CAMSS_CSI0PIX_CLK>,
2020 <&mmcc CAMSS_CSI0RDI_CLK>,
2021 <&mmcc CAMSS_CSI1_AHB_CLK>,
2022 <&mmcc CAMSS_CSI1_CLK>,
2023 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2024 <&mmcc CAMSS_CSI1PIX_CLK>,
2025 <&mmcc CAMSS_CSI1RDI_CLK>,
2026 <&mmcc CAMSS_CSI2_AHB_CLK>,
2027 <&mmcc CAMSS_CSI2_CLK>,
2028 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2029 <&mmcc CAMSS_CSI2PIX_CLK>,
2030 <&mmcc CAMSS_CSI2RDI_CLK>,
2031 <&mmcc CAMSS_CSI3_AHB_CLK>,
2032 <&mmcc CAMSS_CSI3_CLK>,
2033 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2034 <&mmcc CAMSS_CSI3PIX_CLK>,
2035 <&mmcc CAMSS_CSI3RDI_CLK>,
2036 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2037 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2038 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2039 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2040 <&mmcc CAMSS_CSI_VFE0_CLK>,
2041 <&mmcc CAMSS_CSI_VFE1_CLK>,
2042 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2043 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2044 <&mmcc CAMSS_TOP_AHB_CLK>,
2045 <&mmcc CAMSS_VFE0_AHB_CLK>,
2046 <&mmcc CAMSS_VFE0_CLK>,
2047 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2048 <&mmcc CAMSS_VFE1_AHB_CLK>,
2049 <&mmcc CAMSS_VFE1_CLK>,
2050 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2051 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2052 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2053 clock-names = "ahb",
2095 interconnects = <&mnoc 5 &bimc 5>;
2096 interconnect-names = "vfe-mem";
2097 iommus = <&mmss_smmu 0xc00>,
2101 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2102 <&mmcc CAMSS_VFE1_GDSC>;
2103 status = "disabled";
2106 #address-cells = <1>;
2112 compatible = "qcom,msm8996-cci";
2113 #address-cells = <1>;
2115 reg = <0x0ca0c000 0x1000>;
2116 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2118 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2119 <&mmcc CAMSS_CCI_CLK>;
2120 assigned-clock-rates = <80800000>, <37500000>;
2121 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2122 <&mmcc CAMSS_CCI_AHB_CLK>,
2123 <&mmcc CAMSS_CCI_CLK>,
2124 <&mmcc CAMSS_AHB_CLK>;
2125 clock-names = "camss_top_ahb",
2130 pinctrl-names = "default";
2131 pinctrl-0 = <&cci0_default &cci1_default>;
2132 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2133 status = "disabled";
2135 cci_i2c0: i2c-bus@0 {
2137 clock-frequency = <400000>;
2138 #address-cells = <1>;
2142 cci_i2c1: i2c-bus@1 {
2144 clock-frequency = <400000>;
2145 #address-cells = <1>;
2150 venus: video-codec@cc00000 {
2151 compatible = "qcom,sdm660-venus";
2152 reg = <0x0cc00000 0xff000>;
2153 clocks = <&mmcc VIDEO_CORE_CLK>,
2154 <&mmcc VIDEO_AHB_CLK>,
2155 <&mmcc VIDEO_AXI_CLK>,
2156 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2157 clock-names = "core", "iface", "bus", "bus_throttle";
2158 interconnects = <&gnoc 0 &mnoc 13>,
2160 interconnect-names = "cpu-cfg", "video-mem";
2161 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2162 iommus = <&mmss_smmu 0x400>,
2182 memory-region = <&venus_region>;
2183 power-domains = <&mmcc VENUS_GDSC>;
2184 status = "disabled";
2187 compatible = "venus-decoder";
2188 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2189 clock-names = "vcodec0_core";
2190 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2194 compatible = "venus-encoder";
2195 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2196 clock-names = "vcodec0_core";
2197 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2201 mmss_smmu: iommu@cd00000 {
2202 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2203 reg = <0x0cd00000 0x40000>;
2205 clocks = <&mmcc MNOC_AHB_CLK>,
2206 <&mmcc BIMC_SMMU_AHB_CLK>,
2207 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2208 <&mmcc BIMC_SMMU_AXI_CLK>;
2209 clock-names = "iface-mm", "iface-smmu",
2210 "bus-mm", "bus-smmu";
2211 #global-interrupts = <2>;
2215 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2216 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2218 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2219 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2220 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2221 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2222 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2223 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2224 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2226 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2227 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2243 status = "disabled";
2246 adsp_pil: remoteproc@15700000 {
2247 compatible = "qcom,sdm660-adsp-pas";
2248 reg = <0x15700000 0x4040>;
2250 interrupts-extended =
2251 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2252 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2253 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2254 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2255 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2256 interrupt-names = "wdog", "fatal", "ready",
2257 "handover", "stop-ack";
2259 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2262 memory-region = <&adsp_region>;
2263 power-domains = <&rpmpd SDM660_VDDCX>;
2264 power-domain-names = "cx";
2266 qcom,smem-states = <&adsp_smp2p_out 0>;
2267 qcom,smem-state-names = "stop";
2270 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2273 mboxes = <&apcs_glb 9>;
2274 qcom,remote-pid = <2>;
2277 compatible = "qcom,apr-v2";
2278 qcom,glink-channels = "apr_audio_svc";
2279 qcom,domain = <APR_DOMAIN_ADSP>;
2280 #address-cells = <1>;
2284 reg = <APR_SVC_ADSP_CORE>;
2285 compatible = "qcom,q6core";
2289 compatible = "qcom,q6afe";
2290 reg = <APR_SVC_AFE>;
2292 compatible = "qcom,q6afe-dais";
2293 #address-cells = <1>;
2295 #sound-dai-cells = <1>;
2300 compatible = "qcom,q6asm";
2301 reg = <APR_SVC_ASM>;
2303 compatible = "qcom,q6asm-dais";
2304 #address-cells = <1>;
2306 #sound-dai-cells = <1>;
2307 iommus = <&lpass_smmu 1>;
2312 compatible = "qcom,q6adm";
2313 reg = <APR_SVC_ADM>;
2314 q6routing: routing {
2315 compatible = "qcom,q6adm-routing";
2316 #sound-dai-cells = <0>;
2323 gnoc: interconnect@17900000 {
2324 compatible = "qcom,sdm660-gnoc";
2325 reg = <0x17900000 0xe000>;
2326 #interconnect-cells = <1>;
2328 * This one apparently features no clocks,
2329 * so let's not mess with the driver needlessly
2331 clock-names = "bus", "bus_a";
2332 clocks = <&xo_board>, <&xo_board>;
2335 apcs_glb: mailbox@17911000 {
2336 compatible = "qcom,sdm660-apcs-hmss-global",
2337 "qcom,msm8994-apcs-kpss-global";
2338 reg = <0x17911000 0x1000>;
2344 #address-cells = <1>;
2347 compatible = "arm,armv7-timer-mem";
2348 reg = <0x17920000 0x1000>;
2349 clock-frequency = <19200000>;
2353 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2354 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2355 reg = <0x17921000 0x1000>,
2356 <0x17922000 0x1000>;
2361 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2362 reg = <0x17923000 0x1000>;
2363 status = "disabled";
2368 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2369 reg = <0x17924000 0x1000>;
2370 status = "disabled";
2375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2376 reg = <0x17925000 0x1000>;
2377 status = "disabled";
2382 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2383 reg = <0x17926000 0x1000>;
2384 status = "disabled";
2389 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2390 reg = <0x17927000 0x1000>;
2391 status = "disabled";
2396 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2397 reg = <0x17928000 0x1000>;
2398 status = "disabled";
2402 intc: interrupt-controller@17a00000 {
2403 compatible = "arm,gic-v3";
2404 reg = <0x17a00000 0x10000>, /* GICD */
2405 <0x17b00000 0x100000>; /* GICR * 8 */
2406 #interrupt-cells = <3>;
2407 #address-cells = <1>;
2410 interrupt-controller;
2411 #redistributor-regions = <1>;
2412 redistributor-stride = <0x0 0x20000>;
2413 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2422 polling-delay-passive = <250>;
2423 polling-delay = <1000>;
2425 thermal-sensors = <&tsens 0>;
2428 aoss_alert0: trip-point0 {
2429 temperature = <105000>;
2430 hysteresis = <1000>;
2437 polling-delay-passive = <250>;
2438 polling-delay = <1000>;
2440 thermal-sensors = <&tsens 1>;
2443 cpuss0_alert0: trip-point0 {
2444 temperature = <125000>;
2445 hysteresis = <1000>;
2452 polling-delay-passive = <250>;
2453 polling-delay = <1000>;
2455 thermal-sensors = <&tsens 2>;
2458 cpuss1_alert0: trip-point0 {
2459 temperature = <125000>;
2460 hysteresis = <1000>;
2467 polling-delay-passive = <250>;
2468 polling-delay = <1000>;
2470 thermal-sensors = <&tsens 3>;
2473 cpu0_alert0: trip-point0 {
2474 temperature = <70000>;
2475 hysteresis = <1000>;
2479 cpu0_crit: cpu-crit {
2480 temperature = <110000>;
2481 hysteresis = <1000>;
2488 polling-delay-passive = <250>;
2489 polling-delay = <1000>;
2491 thermal-sensors = <&tsens 4>;
2494 cpu1_alert0: trip-point0 {
2495 temperature = <70000>;
2496 hysteresis = <1000>;
2500 cpu1_crit: cpu-crit {
2501 temperature = <110000>;
2502 hysteresis = <1000>;
2509 polling-delay-passive = <250>;
2510 polling-delay = <1000>;
2512 thermal-sensors = <&tsens 5>;
2515 cpu2_alert0: trip-point0 {
2516 temperature = <70000>;
2517 hysteresis = <1000>;
2521 cpu2_crit: cpu-crit {
2522 temperature = <110000>;
2523 hysteresis = <1000>;
2530 polling-delay-passive = <250>;
2531 polling-delay = <1000>;
2533 thermal-sensors = <&tsens 6>;
2536 cpu3_alert0: trip-point0 {
2537 temperature = <70000>;
2538 hysteresis = <1000>;
2542 cpu3_crit: cpu-crit {
2543 temperature = <110000>;
2544 hysteresis = <1000>;
2551 * According to what downstream DTS says,
2552 * the entire power efficient cluster has
2553 * only a single thermal sensor.
2556 pwr-cluster-thermal {
2557 polling-delay-passive = <250>;
2558 polling-delay = <1000>;
2560 thermal-sensors = <&tsens 7>;
2563 pwr_cluster_alert0: trip-point0 {
2564 temperature = <70000>;
2565 hysteresis = <1000>;
2569 pwr_cluster_crit: cpu-crit {
2570 temperature = <110000>;
2571 hysteresis = <1000>;
2578 polling-delay-passive = <250>;
2579 polling-delay = <1000>;
2581 thermal-sensors = <&tsens 8>;
2584 gpu_alert0: trip-point0 {
2585 temperature = <90000>;
2586 hysteresis = <1000>;
2594 compatible = "arm,armv8-timer";
2595 interrupts = <GIC_PPI 1 0xf08>,