arch/arm64/boot/dts/qcom/sc8280xp.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-rpmpd.h>
  13 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         clocks {
  23                 xo_board_clk: xo-board-clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                 };
  27
  28                 sleep_clk: sleep-clk {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                         clock-frequency = <32764>;
  32                 };
  33         };
  34
  35         cpu0_opp_table: cpu0-opp-table {
  36                 compatible = "operating-points-v2";
  37                 opp-shared;
  38
  39                 opp-300000000 {
  40                         opp-hz = /bits/ 64 <300000000>;
  41                 };
  42                 opp-403200000 {
  43                         opp-hz = /bits/ 64 <403200000>;
  44                 };
  45                 opp-499200000 {
  46                         opp-hz = /bits/ 64 <499200000>;
  47                 };
  48                 opp-595200000 {
  49                         opp-hz = /bits/ 64 <595200000>;
  50                 };
  51                 opp-691200000 {
  52                         opp-hz = /bits/ 64 <691200000>;
  53                 };
  54                 opp-806400000 {
  55                         opp-hz = /bits/ 64 <806400000>;
  56                 };
  57                 opp-902400000 {
  58                         opp-hz = /bits/ 64 <902400000>;
  59                 };
  60                 opp-1017600000 {
  61                         opp-hz = /bits/ 64 <1017600000>;
  62                 };
  63                 opp-1113600000 {
  64                         opp-hz = /bits/ 64 <1113600000>;
  65                 };
  66                 opp-1209600000 {
  67                         opp-hz = /bits/ 64 <1209600000>;
  68                 };
  69                 opp-1324800000 {
  70                         opp-hz = /bits/ 64 <1324800000>;
  71                 };
  72                 opp-1440000000 {
  73                         opp-hz = /bits/ 64 <1440000000>;
  74                 };
  75                 opp-1555200000 {
  76                         opp-hz = /bits/ 64 <1555200000>;
  77                 };
  78                 opp-1670400000 {
  79                         opp-hz = /bits/ 64 <1670400000>;
  80                 };
  81                 opp-1785600000 {
  82                         opp-hz = /bits/ 64 <1785600000>;
  83                 };
  84                 opp-1881600000 {
  85                         opp-hz = /bits/ 64 <1881600000>;
  86                 };
  87                 opp-1996800000 {
  88                         opp-hz = /bits/ 64 <1996800000>;
  89                 };
  90                 opp-2112000000 {
  91                         opp-hz = /bits/ 64 <2112000000>;
  92                 };
  93                 opp-2227200000 {
  94                         opp-hz = /bits/ 64 <2227200000>;
  95                 };
  96                 opp-2342400000 {
  97                         opp-hz = /bits/ 64 <2342400000>;
  98                 };
  99                 opp-2438400000 {
 100                         opp-hz = /bits/ 64 <2438400000>;
 101                 };
 102         };
 103
 104         cpu4_opp_table: cpu4-opp-table {
 105                 compatible = "operating-points-v2";
 106                 opp-shared;
 107
 108                 opp-825600000 {
 109                         opp-hz = /bits/ 64 <825600000>;
 110                 };
 111                 opp-940800000 {
 112                         opp-hz = /bits/ 64 <940800000>;
 113                 };
 114                 opp-1056000000 {
 115                         opp-hz = /bits/ 64 <1056000000>;
 116                 };
 117                 opp-1171200000 {
 118                         opp-hz = /bits/ 64 <1171200000>;
 119                 };
 120                 opp-1286400000 {
 121                         opp-hz = /bits/ 64 <1286400000>;
 122                 };
 123                 opp-1401600000 {
 124                         opp-hz = /bits/ 64 <1401600000>;
 125                 };
 126                 opp-1516800000 {
 127                         opp-hz = /bits/ 64 <1516800000>;
 128                 };
 129                 opp-1632000000 {
 130                         opp-hz = /bits/ 64 <1632000000>;
 131                 };
 132                 opp-1747200000 {
 133                         opp-hz = /bits/ 64 <1747200000>;
 134                 };
 135                 opp-1862400000 {
 136                         opp-hz = /bits/ 64 <1862400000>;
 137                 };
 138                 opp-1977600000 {
 139                         opp-hz = /bits/ 64 <1977600000>;
 140                 };
 141                 opp-2073600000 {
 142                         opp-hz = /bits/ 64 <2073600000>;
 143                 };
 144                 opp-2169600000 {
 145                         opp-hz = /bits/ 64 <2169600000>;
 146                 };
 147                 opp-2284800000 {
 148                         opp-hz = /bits/ 64 <2284800000>;
 149                 };
 150                 opp-2400000000 {
 151                         opp-hz = /bits/ 64 <2400000000>;
 152                 };
 153                 opp-2496000000 {
 154                         opp-hz = /bits/ 64 <2496000000>;
 155                 };
 156                 opp-2592000000 {
 157                         opp-hz = /bits/ 64 <2592000000>;
 158                 };
 159                 opp-2688000000 {
 160                         opp-hz = /bits/ 64 <2688000000>;
 161                 };
 162                 opp-2803200000 {
 163                         opp-hz = /bits/ 64 <2803200000>;
 164                 };
 165                 opp-2899200000 {
 166                         opp-hz = /bits/ 64 <2899200000>;
 167                 };
 168                 opp-2995200000 {
 169                         opp-hz = /bits/ 64 <2995200000>;
 170                 };
 171         };
 172
 173         cpus {
 174                 #address-cells = <2>;
 175                 #size-cells = <0>;
 176
 177                 CPU0: cpu@0 {
 178                         device_type = "cpu";
 179                         compatible = "qcom,kryo";
 180                         reg = <0x0 0x0>;
 181                         enable-method = "psci";
 182                         capacity-dmips-mhz = <602>;
 183                         next-level-cache = <&L2_0>;
 184                         power-domains = <&CPU_PD0>;
 185                         power-domain-names = "psci";
 186                         qcom,freq-domain = <&cpufreq_hw 0>;
 187                         operating-points-v2 = <&cpu0_opp_table>;
 188                         #cooling-cells = <2>;
 189                         L2_0: l2-cache {
 190                                 compatible = "cache";
 191                                 next-level-cache = <&L3_0>;
 192                                 L3_0: l3-cache {
 193                                       compatible = "cache";
 194                                 };
 195                         };
 196                 };
 197
 198                 CPU1: cpu@100 {
 199                         device_type = "cpu";
 200                         compatible = "qcom,kryo";
 201                         reg = <0x0 0x100>;
 202                         enable-method = "psci";
 203                         capacity-dmips-mhz = <602>;
 204                         next-level-cache = <&L2_100>;
 205                         power-domains = <&CPU_PD1>;
 206                         power-domain-names = "psci";
 207                         qcom,freq-domain = <&cpufreq_hw 0>;
 208                         operating-points-v2 = <&cpu0_opp_table>;
 209                         #cooling-cells = <2>;
 210                         L2_100: l2-cache {
 211                                 compatible = "cache";
 212                                 next-level-cache = <&L3_0>;
 213                         };
 214                 };
 215
 216                 CPU2: cpu@200 {
 217                         device_type = "cpu";
 218                         compatible = "qcom,kryo";
 219                         reg = <0x0 0x200>;
 220                         enable-method = "psci";
 221                         capacity-dmips-mhz = <602>;
 222                         next-level-cache = <&L2_200>;
 223                         power-domains = <&CPU_PD2>;
 224                         power-domain-names = "psci";
 225                         qcom,freq-domain = <&cpufreq_hw 0>;
 226                         operating-points-v2 = <&cpu0_opp_table>;
 227                         #cooling-cells = <2>;
 228                         L2_200: l2-cache {
 229                                 compatible = "cache";
 230                                 next-level-cache = <&L3_0>;
 231                         };
 232                 };
 233
 234                 CPU3: cpu@300 {
 235                         device_type = "cpu";
 236                         compatible = "qcom,kryo";
 237                         reg = <0x0 0x300>;
 238                         enable-method = "psci";
 239                         capacity-dmips-mhz = <602>;
 240                         next-level-cache = <&L2_300>;
 241                         power-domains = <&CPU_PD3>;
 242                         power-domain-names = "psci";
 243                         qcom,freq-domain = <&cpufreq_hw 0>;
 244                         operating-points-v2 = <&cpu0_opp_table>;
 245                         #cooling-cells = <2>;
 246                         L2_300: l2-cache {
 247                                 compatible = "cache";
 248                                 next-level-cache = <&L3_0>;
 249                         };
 250                 };
 251
 252                 CPU4: cpu@400 {
 253                         device_type = "cpu";
 254                         compatible = "qcom,kryo";
 255                         reg = <0x0 0x400>;
 256                         enable-method = "psci";
 257                         capacity-dmips-mhz = <1024>;
 258                         next-level-cache = <&L2_400>;
 259                         power-domains = <&CPU_PD4>;
 260                         power-domain-names = "psci";
 261                         qcom,freq-domain = <&cpufreq_hw 1>;
 262                         operating-points-v2 = <&cpu4_opp_table>;
 263                         #cooling-cells = <2>;
 264                         L2_400: l2-cache {
 265                                 compatible = "cache";
 266                                 next-level-cache = <&L3_0>;
 267                         };
 268                 };
 269
 270                 CPU5: cpu@500 {
 271                         device_type = "cpu";
 272                         compatible = "qcom,kryo";
 273                         reg = <0x0 0x500>;
 274                         enable-method = "psci";
 275                         capacity-dmips-mhz = <1024>;
 276                         next-level-cache = <&L2_500>;
 277                         power-domains = <&CPU_PD5>;
 278                         power-domain-names = "psci";
 279                         qcom,freq-domain = <&cpufreq_hw 1>;
 280                         operating-points-v2 = <&cpu4_opp_table>;
 281                         #cooling-cells = <2>;
 282                         L2_500: l2-cache {
 283                                 compatible = "cache";
 284                                 next-level-cache = <&L3_0>;
 285                         };
 286                 };
 287
 288                 CPU6: cpu@600 {
 289                         device_type = "cpu";
 290                         compatible = "qcom,kryo";
 291                         reg = <0x0 0x600>;
 292                         enable-method = "psci";
 293                         capacity-dmips-mhz = <1024>;
 294                         next-level-cache = <&L2_600>;
 295                         power-domains = <&CPU_PD6>;
 296                         power-domain-names = "psci";
 297                         qcom,freq-domain = <&cpufreq_hw 1>;
 298                         operating-points-v2 = <&cpu4_opp_table>;
 299                         #cooling-cells = <2>;
 300                         L2_600: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 CPU7: cpu@700 {
 307                         device_type = "cpu";
 308                         compatible = "qcom,kryo";
 309                         reg = <0x0 0x700>;
 310                         enable-method = "psci";
 311                         capacity-dmips-mhz = <1024>;
 312                         next-level-cache = <&L2_700>;
 313                         power-domains = <&CPU_PD7>;
 314                         power-domain-names = "psci";
 315                         qcom,freq-domain = <&cpufreq_hw 1>;
 316                         operating-points-v2 = <&cpu4_opp_table>;
 317                         #cooling-cells = <2>;
 318                         L2_700: l2-cache {
 319                                 compatible = "cache";
 320                                 next-level-cache = <&L3_0>;
 321                         };
 322                 };
 323
 324                 cpu-map {
 325                         cluster0 {
 326                                 core0 {
 327                                         cpu = <&CPU0>;
 328                                 };
 329
 330                                 core1 {
 331                                         cpu = <&CPU1>;
 332                                 };
 333
 334                                 core2 {
 335                                         cpu = <&CPU2>;
 336                                 };
 337
 338                                 core3 {
 339                                         cpu = <&CPU3>;
 340                                 };
 341
 342                                 core4 {
 343                                         cpu = <&CPU4>;
 344                                 };
 345
 346                                 core5 {
 347                                         cpu = <&CPU5>;
 348                                 };
 349
 350                                 core6 {
 351                                         cpu = <&CPU6>;
 352                                 };
 353
 354                                 core7 {
 355                                         cpu = <&CPU7>;
 356                                 };
 357                         };
 358                 };
 359
 360                 idle-states {
 361                         entry-method = "psci";
 362
 363                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 364                                 compatible = "arm,idle-state";
 365                                 idle-state-name = "little-rail-power-collapse";
 366                                 arm,psci-suspend-param = <0x40000004>;
 367                                 entry-latency-us = <355>;
 368                                 exit-latency-us = <909>;
 369                                 min-residency-us = <3934>;
 370                                 local-timer-stop;
 371                         };
 372
 373                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 374                                 compatible = "arm,idle-state";
 375                                 idle-state-name = "big-rail-power-collapse";
 376                                 arm,psci-suspend-param = <0x40000004>;
 377                                 entry-latency-us = <241>;
 378                                 exit-latency-us = <1461>;
 379                                 min-residency-us = <4488>;
 380                                 local-timer-stop;
 381                         };
 382                 };
 383
 384                 domain-idle-states {
 385                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 386                                 compatible = "domain-idle-state";
 387                                 idle-state-name = "cluster-power-collapse";
 388                                 arm,psci-suspend-param = <0x4100c344>;
 389                                 entry-latency-us = <3263>;
 390                                 exit-latency-us = <6562>;
 391                                 min-residency-us = <9987>;
 392                         };
 393                 };
 394         };
 395
 396         firmware {
 397                 scm: scm {
 398                         compatible = "qcom,scm-sc8280xp", "qcom,scm";
 399                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 400                 };
 401         };
 402
 403         aggre1_noc: interconnect-aggre1-noc {
 404                 compatible = "qcom,sc8280xp-aggre1-noc";
 405                 #interconnect-cells = <2>;
 406                 qcom,bcm-voters = <&apps_bcm_voter>;
 407         };
 408
 409         aggre2_noc: interconnect-aggre2-noc {
 410                 compatible = "qcom,sc8280xp-aggre2-noc";
 411                 #interconnect-cells = <2>;
 412                 qcom,bcm-voters = <&apps_bcm_voter>;
 413         };
 414
 415         clk_virt: interconnect-clk-virt {
 416                 compatible = "qcom,sc8280xp-clk-virt";
 417                 #interconnect-cells = <2>;
 418                 qcom,bcm-voters = <&apps_bcm_voter>;
 419         };
 420
 421         config_noc: interconnect-config-noc {
 422                 compatible = "qcom,sc8280xp-config-noc";
 423                 #interconnect-cells = <2>;
 424                 qcom,bcm-voters = <&apps_bcm_voter>;
 425         };
 426
 427         dc_noc: interconnect-dc-noc {
 428                 compatible = "qcom,sc8280xp-dc-noc";
 429                 #interconnect-cells = <2>;
 430                 qcom,bcm-voters = <&apps_bcm_voter>;
 431         };
 432
 433         gem_noc: interconnect-gem-noc {
 434                 compatible = "qcom,sc8280xp-gem-noc";
 435                 #interconnect-cells = <2>;
 436                 qcom,bcm-voters = <&apps_bcm_voter>;
 437         };
 438
 439         lpass_noc: interconnect-lpass-ag-noc {
 440                 compatible = "qcom,sc8280xp-lpass-ag-noc";
 441                 #interconnect-cells = <2>;
 442                 qcom,bcm-voters = <&apps_bcm_voter>;
 443         };
 444
 445         mc_virt: interconnect-mc-virt {
 446                 compatible = "qcom,sc8280xp-mc-virt";
 447                 #interconnect-cells = <2>;
 448                 qcom,bcm-voters = <&apps_bcm_voter>;
 449         };
 450
 451         mmss_noc: interconnect-mmss-noc {
 452                 compatible = "qcom,sc8280xp-mmss-noc";
 453                 #interconnect-cells = <2>;
 454                 qcom,bcm-voters = <&apps_bcm_voter>;
 455         };
 456
 457         nspa_noc: interconnect-nspa-noc {
 458                 compatible = "qcom,sc8280xp-nspa-noc";
 459                 #interconnect-cells = <2>;
 460                 qcom,bcm-voters = <&apps_bcm_voter>;
 461         };
 462
 463         nspb_noc: interconnect-nspb-noc {
 464                 compatible = "qcom,sc8280xp-nspb-noc";
 465                 #interconnect-cells = <2>;
 466                 qcom,bcm-voters = <&apps_bcm_voter>;
 467         };
 468
 469         system_noc: interconnect-system-noc {
 470                 compatible = "qcom,sc8280xp-system-noc";
 471                 #interconnect-cells = <2>;
 472                 qcom,bcm-voters = <&apps_bcm_voter>;
 473         };
 474
 475         memory@80000000 {
 476                 device_type = "memory";
 477                 /* We expect the bootloader to fill in the size */
 478                 reg = <0x0 0x80000000 0x0 0x0>;
 479         };
 480
 481         pmu {
 482                 compatible = "arm,armv8-pmuv3";
 483                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 484         };
 485
 486         psci {
 487                 compatible = "arm,psci-1.0";
 488                 method = "smc";
 489
 490                 CPU_PD0: cpu0 {
 491                         #power-domain-cells = <0>;
 492                         power-domains = <&CLUSTER_PD>;
 493                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 494                 };
 495
 496                 CPU_PD1: cpu1 {
 497                         #power-domain-cells = <0>;
 498                         power-domains = <&CLUSTER_PD>;
 499                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 500                 };
 501
 502                 CPU_PD2: cpu2 {
 503                         #power-domain-cells = <0>;
 504                         power-domains = <&CLUSTER_PD>;
 505                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 506                 };
 507
 508                 CPU_PD3: cpu3 {
 509                         #power-domain-cells = <0>;
 510                         power-domains = <&CLUSTER_PD>;
 511                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 512                 };
 513
 514                 CPU_PD4: cpu4 {
 515                         #power-domain-cells = <0>;
 516                         power-domains = <&CLUSTER_PD>;
 517                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 518                 };
 519
 520                 CPU_PD5: cpu5 {
 521                         #power-domain-cells = <0>;
 522                         power-domains = <&CLUSTER_PD>;
 523                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 524                 };
 525
 526                 CPU_PD6: cpu6 {
 527                         #power-domain-cells = <0>;
 528                         power-domains = <&CLUSTER_PD>;
 529                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 530                 };
 531
 532                 CPU_PD7: cpu7 {
 533                         #power-domain-cells = <0>;
 534                         power-domains = <&CLUSTER_PD>;
 535                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 536                 };
 537
 538                 CLUSTER_PD: cpu-cluster0 {
 539                         #power-domain-cells = <0>;
 540                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 541                 };
 542         };
 543
 544         qup_opp_table_100mhz: qup-100mhz-opp-table {
 545                 compatible = "operating-points-v2";
 546
 547                 opp-75000000 {
 548                         opp-hz = /bits/ 64 <75000000>;
 549                         required-opps = <&rpmhpd_opp_low_svs>;
 550                 };
 551
 552                 opp-100000000 {
 553                         opp-hz = /bits/ 64 <100000000>;
 554                         required-opps = <&rpmhpd_opp_svs>;
 555                 };
 556         };
 557
 558         reserved-memory {
 559                 #address-cells = <2>;
 560                 #size-cells = <2>;
 561                 ranges;
 562
 563                 reserved-region@80000000 {
 564                         reg = <0 0x80000000 0 0x860000>;
 565                         no-map;
 566                 };
 567
 568                 cmd_db: cmd-db-region@80860000 {
 569                         compatible = "qcom,cmd-db";
 570                         reg = <0 0x80860000 0 0x20000>;
 571                         no-map;
 572                 };
 573
 574                 reserved-region@80880000 {
 575                         reg = <0 0x80880000 0 0x80000>;
 576                         no-map;
 577                 };
 578
 579                 smem_mem: smem-region@80900000 {
 580                         compatible = "qcom,smem";
 581                         reg = <0 0x80900000 0 0x200000>;
 582                         no-map;
 583                         hwlocks = <&tcsr_mutex 3>;
 584                 };
 585
 586                 reserved-region@80b00000 {
 587                         reg = <0 0x80b00000 0 0x100000>;
 588                         no-map;
 589                 };
 590
 591                 reserved-region@83b00000 {
 592                         reg = <0 0x83b00000 0 0x1700000>;
 593                         no-map;
 594                 };
 595
 596                 reserved-region@85b00000 {
 597                         reg = <0 0x85b00000 0 0xc00000>;
 598                         no-map;
 599                 };
 600
 601                 pil_adsp_mem: adsp-region@86c00000 {
 602                         reg = <0 0x86c00000 0 0x2000000>;
 603                         no-map;
 604                 };
 605
 606                 pil_nsp0_mem: cdsp0-region@8a100000 {
 607                         reg = <0 0x8a100000 0 0x1e00000>;
 608                         no-map;
 609                 };
 610
 611                 pil_nsp1_mem: cdsp1-region@8c600000 {
 612                         reg = <0 0x8c600000 0 0x1e00000>;
 613                         no-map;
 614                 };
 615
 616                 reserved-region@aeb00000 {
 617                         reg = <0 0xaeb00000 0 0x16600000>;
 618                         no-map;
 619                 };
 620         };
 621
 622         smp2p-adsp {
 623                 compatible = "qcom,smp2p";
 624                 qcom,smem = <443>, <429>;
 625                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 626                                              IPCC_MPROC_SIGNAL_SMP2P
 627                                              IRQ_TYPE_EDGE_RISING>;
 628                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 629                                 IPCC_MPROC_SIGNAL_SMP2P>;
 630
 631                 qcom,local-pid = <0>;
 632                 qcom,remote-pid = <2>;
 633
 634                 smp2p_adsp_out: master-kernel {
 635                         qcom,entry-name = "master-kernel";
 636                         #qcom,smem-state-cells = <1>;
 637                 };
 638
 639                 smp2p_adsp_in: slave-kernel {
 640                         qcom,entry-name = "slave-kernel";
 641                         interrupt-controller;
 642                         #interrupt-cells = <2>;
 643                 };
 644         };
 645
 646         smp2p-nsp0 {
 647                 compatible = "qcom,smp2p";
 648                 qcom,smem = <94>, <432>;
 649                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 650                                              IPCC_MPROC_SIGNAL_SMP2P
 651                                              IRQ_TYPE_EDGE_RISING>;
 652                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 653                                 IPCC_MPROC_SIGNAL_SMP2P>;
 654
 655                 qcom,local-pid = <0>;
 656                 qcom,remote-pid = <5>;
 657
 658                 smp2p_nsp0_out: master-kernel {
 659                         qcom,entry-name = "master-kernel";
 660                         #qcom,smem-state-cells = <1>;
 661                 };
 662
 663                 smp2p_nsp0_in: slave-kernel {
 664                         qcom,entry-name = "slave-kernel";
 665                         interrupt-controller;
 666                         #interrupt-cells = <2>;
 667                 };
 668         };
 669
 670         smp2p-nsp1 {
 671                 compatible = "qcom,smp2p";
 672                 qcom,smem = <617>, <616>;
 673                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
 674                                              IPCC_MPROC_SIGNAL_SMP2P
 675                                              IRQ_TYPE_EDGE_RISING>;
 676                 mboxes = <&ipcc IPCC_CLIENT_NSP1
 677                                 IPCC_MPROC_SIGNAL_SMP2P>;
 678
 679                 qcom,local-pid = <0>;
 680                 qcom,remote-pid = <12>;
 681
 682                 smp2p_nsp1_out: master-kernel {
 683                         qcom,entry-name = "master-kernel";
 684                         #qcom,smem-state-cells = <1>;
 685                 };
 686
 687                 smp2p_nsp1_in: slave-kernel {
 688                         qcom,entry-name = "slave-kernel";
 689                         interrupt-controller;
 690                         #interrupt-cells = <2>;
 691                 };
 692         };
 693
 694         soc: soc@0 {
 695                 compatible = "simple-bus";
 696                 #address-cells = <2>;
 697                 #size-cells = <2>;
 698                 ranges = <0 0 0 0 0x10 0>;
 699                 dma-ranges = <0 0 0 0 0x10 0>;
 700
 701                 gcc: clock-controller@100000 {
 702                         compatible = "qcom,gcc-sc8280xp";
 703                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 704                         #clock-cells = <1>;
 705                         #reset-cells = <1>;
 706                         #power-domain-cells = <1>;
 707                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 708                                  <&sleep_clk>,
 709                                  <0>,
 710                                  <0>,
 711                                  <0>,
 712                                  <0>,
 713                                  <0>,
 714                                  <0>,
 715                                  <&usb_0_ssphy>,
 716                                  <0>,
 717                                  <0>,
 718                                  <0>,
 719                                  <0>,
 720                                  <0>,
 721                                  <0>,
 722                                  <0>,
 723                                  <&usb_1_ssphy>,
 724                                  <0>,
 725                                  <0>,
 726                                  <0>,
 727                                  <0>,
 728                                  <0>,
 729                                  <0>,
 730                                  <0>,
 731                                  <0>,
 732                                  <0>,
 733                                  <0>,
 734                                  <0>,
 735                                  <0>,
 736                                  <0>,
 737                                  <0>,
 738                                  <0>,
 739                                  <0>;
 740                         power-domains = <&rpmhpd SC8280XP_CX>;
 741                 };
 742
 743                 ipcc: mailbox@408000 {
 744                         compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
 745                         reg = <0 0x00408000 0 0x1000>;
 746                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 747                         interrupt-controller;
 748                         #interrupt-cells = <3>;
 749                         #mbox-cells = <2>;
 750                 };
 751
 752                 qup2: geniqup@8c0000 {
 753                         compatible = "qcom,geni-se-qup";
 754                         reg = <0 0x008c0000 0 0x2000>;
 755                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 756                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 757                         clock-names = "m-ahb", "s-ahb";
 758                         iommus = <&apps_smmu 0xa3 0>;
 759
 760                         #address-cells = <2>;
 761                         #size-cells = <2>;
 762                         ranges;
 763
 764                         status = "disabled";
 765
 766                         qup2_uart17: serial@884000 {
 767                                 compatible = "qcom,geni-uart";
 768                                 reg = <0 0x00884000 0 0x4000>;
 769                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 770                                 clock-names = "se";
 771                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 772                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 773                                 power-domains = <&rpmhpd SC8280XP_CX>;
 774                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 775                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
 776                                 interconnect-names = "qup-core", "qup-config";
 777                                 status = "disabled";
 778                         };
 779
 780                         qup2_i2c5: i2c@894000 {
 781                                 compatible = "qcom,geni-i2c";
 782                                 reg = <0 0x00894000 0 0x4000>;
 783                                 clock-names = "se";
 784                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 785                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 786                                 #address-cells = <1>;
 787                                 #size-cells = <0>;
 788                                 power-domains = <&rpmhpd SC8280XP_CX>;
 789                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 790                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 791                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 792                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 793                                 status = "disabled";
 794                         };
 795                 };
 796
 797                 qup0: geniqup@9c0000 {
 798                         compatible = "qcom,geni-se-qup";
 799                         reg = <0 0x009c0000 0 0x6000>;
 800                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 801                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 802                         clock-names = "m-ahb", "s-ahb";
 803                         iommus = <&apps_smmu 0x563 0>;
 804
 805                         #address-cells = <2>;
 806                         #size-cells = <2>;
 807                         ranges;
 808
 809                         status = "disabled";
 810
 811                         qup0_i2c4: i2c@990000 {
 812                                 compatible = "qcom,geni-i2c";
 813                                 reg = <0 0x00990000 0 0x4000>;
 814                                 clock-names = "se";
 815                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 816                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 817                                 #address-cells = <1>;
 818                                 #size-cells = <0>;
 819                                 power-domains = <&rpmhpd SC8280XP_CX>;
 820                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 821                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 822                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 823                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 824                                 status = "disabled";
 825                         };
 826                 };
 827
 828                 qup1: geniqup@ac0000 {
 829                         compatible = "qcom,geni-se-qup";
 830                         reg = <0 0x00ac0000 0 0x6000>;
 831                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 832                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 833                         clock-names = "m-ahb", "s-ahb";
 834                         iommus = <&apps_smmu 0x83 0>;
 835
 836                         #address-cells = <2>;
 837                         #size-cells = <2>;
 838                         ranges;
 839
 840                         status = "disabled";
 841                 };
 842
 843                 ufs_mem_hc: ufs@1d84000 {
 844                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
 845                                      "jedec,ufs-2.0";
 846                         reg = <0 0x01d84000 0 0x3000>;
 847                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 848                         phys = <&ufs_mem_phy_lanes>;
 849                         phy-names = "ufsphy";
 850                         lanes-per-direction = <2>;
 851                         #reset-cells = <1>;
 852                         resets = <&gcc GCC_UFS_PHY_BCR>;
 853                         reset-names = "rst";
 854
 855                         power-domains = <&gcc UFS_PHY_GDSC>;
 856                         required-opps = <&rpmhpd_opp_nom>;
 857
 858                         iommus = <&apps_smmu 0xe0 0x0>;
 859                         dma-coherent;
 860
 861                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
 862                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 863                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
 864                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 865                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
 866                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 867                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 868                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
 869                         clock-names = "core_clk",
 870                                       "bus_aggr_clk",
 871                                       "iface_clk",
 872                                       "core_clk_unipro",
 873                                       "ref_clk",
 874                                       "tx_lane0_sync_clk",
 875                                       "rx_lane0_sync_clk",
 876                                       "rx_lane1_sync_clk";
 877                         freq-table-hz = <75000000 300000000>,
 878                                         <0 0>,
 879                                         <0 0>,
 880                                         <75000000 300000000>,
 881                                         <0 0>,
 882                                         <0 0>,
 883                                         <0 0>,
 884                                         <0 0>;
 885                         status = "disabled";
 886                 };
 887
 888                 ufs_mem_phy: phy@1d87000 {
 889                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
 890                         reg = <0 0x01d87000 0 0x1c8>;
 891                         #address-cells = <2>;
 892                         #size-cells = <2>;
 893                         ranges;
 894                         clock-names = "ref",
 895                                       "ref_aux";
 896                         clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
 897                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 898
 899                         resets = <&ufs_mem_hc 0>;
 900                         reset-names = "ufsphy";
 901                         status = "disabled";
 902
 903                         ufs_mem_phy_lanes: phy@1d87400 {
 904                                 reg = <0 0x01d87400 0 0x108>,
 905                                       <0 0x01d87600 0 0x1e0>,
 906                                       <0 0x01d87c00 0 0x1dc>,
 907                                       <0 0x01d87800 0 0x108>,
 908                                       <0 0x01d87a00 0 0x1e0>;
 909                                 #phy-cells = <0>;
 910                         };
 911                 };
 912
 913                 ufs_card_hc: ufs@1da4000 {
 914                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
 915                                      "jedec,ufs-2.0";
 916                         reg = <0 0x01da4000 0 0x3000>;
 917                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 918                         phys = <&ufs_card_phy_lanes>;
 919                         phy-names = "ufsphy";
 920                         lanes-per-direction = <2>;
 921                         #reset-cells = <1>;
 922                         resets = <&gcc GCC_UFS_CARD_BCR>;
 923                         reset-names = "rst";
 924
 925                         power-domains = <&gcc UFS_CARD_GDSC>;
 926
 927                         iommus = <&apps_smmu 0x4a0 0x0>;
 928                         dma-coherent;
 929
 930                         clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
 931                                  <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
 932                                  <&gcc GCC_UFS_CARD_AHB_CLK>,
 933                                  <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
 934                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
 935                                  <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
 936                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
 937                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
 938                         clock-names = "core_clk",
 939                                       "bus_aggr_clk",
 940                                       "iface_clk",
 941                                       "core_clk_unipro",
 942                                       "ref_clk",
 943                                       "tx_lane0_sync_clk",
 944                                       "rx_lane0_sync_clk",
 945                                       "rx_lane1_sync_clk";
 946                         freq-table-hz = <75000000 300000000>,
 947                                         <0 0>,
 948                                         <0 0>,
 949                                         <75000000 300000000>,
 950                                         <0 0>,
 951                                         <0 0>,
 952                                         <0 0>,
 953                                         <0 0>;
 954                         status = "disabled";
 955                 };
 956
 957                 ufs_card_phy: phy@1da7000 {
 958                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
 959                         reg = <0 0x01da7000 0 0x1c8>;
 960                         #address-cells = <2>;
 961                         #size-cells = <2>;
 962                         ranges;
 963                         clock-names = "ref",
 964                                       "ref_aux";
 965                         clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
 966                                  <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
 967
 968                         resets = <&ufs_card_hc 0>;
 969                         reset-names = "ufsphy";
 970
 971                         status = "disabled";
 972
 973                         ufs_card_phy_lanes: phy@1da7400 {
 974                                 reg = <0 0x01da7400 0 0x108>,
 975                                       <0 0x01da7600 0 0x1e0>,
 976                                       <0 0x01da7c00 0 0x1dc>,
 977                                       <0 0x01da7800 0 0x108>,
 978                                       <0 0x01da7a00 0 0x1e0>;
 979                                 #phy-cells = <0>;
 980                         };
 981                 };
 982
 983                 tcsr_mutex: hwlock@1f40000 {
 984                         compatible = "qcom,tcsr-mutex";
 985                         reg = <0x0 0x01f40000 0x0 0x20000>;
 986                         #hwlock-cells = <1>;
 987                 };
 988
 989                 usb_0_hsphy: phy@88e5000 {
 990                         compatible = "qcom,sc8280xp-usb-hs-phy",
 991                                      "qcom,usb-snps-hs-5nm-phy";
 992                         reg = <0 0x088e5000 0 0x400>;
 993                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 994                         clock-names = "ref";
 995                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 996
 997                         #phy-cells = <0>;
 998
 999                         status = "disabled";
1000                 };
1001
1002                 usb_2_hsphy0: phy@88e7000 {
1003                         compatible = "qcom,sc8280xp-usb-hs-phy",
1004                                      "qcom,usb-snps-hs-5nm-phy";
1005                         reg = <0 0x088e7000 0 0x400>;
1006                         clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
1007                         clock-names = "ref";
1008                         resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
1009
1010                         #phy-cells = <0>;
1011
1012                         status = "disabled";
1013                 };
1014
1015                 usb_2_hsphy1: phy@88e8000 {
1016                         compatible = "qcom,sc8280xp-usb-hs-phy",
1017                                      "qcom,usb-snps-hs-5nm-phy";
1018                         reg = <0 0x088e8000 0 0x400>;
1019                         clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
1020                         clock-names = "ref";
1021                         resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
1022
1023                         #phy-cells = <0>;
1024
1025                         status = "disabled";
1026                 };
1027
1028                 usb_2_hsphy2: phy@88e9000 {
1029                         compatible = "qcom,sc8280xp-usb-hs-phy",
1030                                      "qcom,usb-snps-hs-5nm-phy";
1031                         reg = <0 0x088e9000 0 0x400>;
1032                         clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
1033                         clock-names = "ref";
1034                         resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
1035
1036                         #phy-cells = <0>;
1037
1038                         status = "disabled";
1039                 };
1040
1041                 usb_2_hsphy3: phy@88ea000 {
1042                         compatible = "qcom,sc8280xp-usb-hs-phy",
1043                                      "qcom,usb-snps-hs-5nm-phy";
1044                         reg = <0 0x088ea000 0 0x400>;
1045                         clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
1046                         clock-names = "ref";
1047                         resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
1048
1049                         #phy-cells = <0>;
1050
1051                         status = "disabled";
1052                 };
1053
1054                 usb_2_qmpphy0: phy-wrapper@88ef000 {
1055                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1056                         reg = <0 0x088ef000 0 0x1c8>;
1057                         #address-cells = <2>;
1058                         #size-cells = <2>;
1059                         ranges;
1060
1061                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1062                                  <&rpmhcc RPMH_CXO_CLK>,
1063                                  <&gcc GCC_USB3_MP0_CLKREF_CLK>,
1064                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1065                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1066
1067                         resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
1068                                  <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
1069                         reset-names = "phy", "common";
1070
1071                         power-domains = <&gcc USB30_MP_GDSC>;
1072
1073                         status = "disabled";
1074
1075                         usb_2_ssphy0: phy@88efe00 {
1076                                 reg = <0 0x088efe00 0 0x160>,
1077                                       <0 0x088f0000 0 0x1ec>,
1078                                       <0 0x088ef200 0 0x1f0>;
1079                                 #phy-cells = <0>;
1080                                 #clock-cells = <0>;
1081                                 clocks = <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
1082                                 clock-names = "pipe0";
1083                                 clock-output-names = "usb2_phy0_pipe_clk";
1084                         };
1085                 };
1086
1087                 usb_2_qmpphy1: phy-wrapper@88f1000 {
1088                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
1089                         reg = <0 0x088f1000 0 0x1c8>;
1090                         #address-cells = <2>;
1091                         #size-cells = <2>;
1092                         ranges;
1093
1094                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
1095                                  <&rpmhcc RPMH_CXO_CLK>,
1096                                  <&gcc GCC_USB3_MP1_CLKREF_CLK>,
1097                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>;
1098                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1099
1100                         resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
1101                                  <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
1102                         reset-names = "phy", "common";
1103
1104                         power-domains = <&gcc USB30_MP_GDSC>;
1105
1106                         status = "disabled";
1107
1108                         usb_2_ssphy1: phy@88f1e00 {
1109                                 reg = <0 0x088f1e00 0 0x160>,
1110                                       <0 0x088f2000 0 0x1ec>,
1111                                       <0 0x088f1200 0 0x1f0>;
1112                                 #phy-cells = <0>;
1113                                 #clock-cells = <0>;
1114                                 clocks = <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
1115                                 clock-names = "pipe0";
1116                                 clock-output-names = "usb2_phy1_pipe_clk";
1117                         };
1118                 };
1119
1120                 remoteproc_adsp: remoteproc@3000000 {
1121                         compatible = "qcom,sc8280xp-adsp-pas";
1122                         reg = <0 0x03000000 0 0x100>;
1123
1124                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1125                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1126                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1127                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1128                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
1129                                               <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
1130                         interrupt-names = "wdog", "fatal", "ready",
1131                                           "handover", "stop-ack", "shutdown-ack";
1132
1133                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1134                         clock-names = "xo";
1135
1136                         power-domains = <&rpmhpd SC8280XP_LCX>,
1137                                         <&rpmhpd SC8280XP_LMX>;
1138                         power-domain-names = "lcx", "lmx";
1139
1140                         memory-region = <&pil_adsp_mem>;
1141
1142                         qcom,qmp = <&aoss_qmp>;
1143
1144                         qcom,smem-states = <&smp2p_adsp_out 0>;
1145                         qcom,smem-state-names = "stop";
1146
1147                         status = "disabled";
1148
1149                         remoteproc_adsp_glink: glink-edge {
1150                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1151                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1152                                                              IRQ_TYPE_EDGE_RISING>;
1153                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
1154                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1155
1156                                 label = "lpass";
1157                                 qcom,remote-pid = <2>;
1158                         };
1159                 };
1160
1161                 usb_0_qmpphy: phy-wrapper@88ec000 {
1162                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1163                         reg = <0 0x088ec000 0 0x1e4>,
1164                               <0 0x088eb000 0 0x40>,
1165                               <0 0x088ed000 0 0x1c8>;
1166                         #address-cells = <2>;
1167                         #size-cells = <2>;
1168                         ranges;
1169
1170                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1171                                  <&rpmhcc RPMH_CXO_CLK>,
1172                                  <&gcc GCC_USB4_EUD_CLKREF_CLK>,
1173                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1174                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1175
1176                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1177                                  <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
1178                         reset-names = "phy", "common";
1179
1180                         power-domains = <&gcc USB30_PRIM_GDSC>;
1181
1182                         status = "disabled";
1183
1184                         usb_0_ssphy: usb3-phy@88eb400 {
1185                                 reg = <0 0x088eb400 0 0x100>,
1186                                       <0 0x088eb600 0 0x3ec>,
1187                                       <0 0x088ec400 0 0x364>,
1188                                       <0 0x088eba00 0 0x100>,
1189                                       <0 0x088ebc00 0 0x3ec>,
1190                                       <0 0x088ec200 0 0x18>;
1191                                 #phy-cells = <0>;
1192                                 #clock-cells = <0>;
1193                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1194                                 clock-names = "pipe0";
1195                                 clock-output-names = "usb0_phy_pipe_clk_src";
1196                         };
1197                 };
1198
1199                 usb_1_hsphy: phy@8902000 {
1200                         compatible = "qcom,sc8280xp-usb-hs-phy",
1201                                      "qcom,usb-snps-hs-5nm-phy";
1202                         reg = <0 0x08902000 0 0x400>;
1203                         #phy-cells = <0>;
1204
1205                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1206                         clock-names = "ref";
1207
1208                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1209
1210                         status = "disabled";
1211                 };
1212
1213                 usb_1_qmpphy: phy-wrapper@8904000 {
1214                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
1215                         reg = <0 0x08904000 0 0x1e4>,
1216                               <0 0x08903000 0 0x40>,
1217                               <0 0x08905000 0 0x1c8>;
1218                         #address-cells = <2>;
1219                         #size-cells = <2>;
1220                         ranges;
1221
1222                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1223                                  <&rpmhcc RPMH_CXO_CLK>,
1224                                  <&gcc GCC_USB4_CLKREF_CLK>,
1225                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
1226                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
1227
1228                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1229                                  <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
1230                         reset-names = "phy", "common";
1231
1232                         power-domains = <&gcc USB30_SEC_GDSC>;
1233
1234                         status = "disabled";
1235
1236                         usb_1_ssphy: usb3-phy@8903400 {
1237                                 reg = <0 0x08903400 0 0x100>,
1238                                       <0 0x08903600 0 0x3ec>,
1239                                       <0 0x08904400 0 0x364>,
1240                                       <0 0x08903a00 0 0x100>,
1241                                       <0 0x08903c00 0 0x3ec>,
1242                                       <0 0x08904200 0 0x18>;
1243                                 #phy-cells = <0>;
1244                                 #clock-cells = <0>;
1245                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1246                                 clock-names = "pipe0";
1247                                 clock-output-names = "usb1_phy_pipe_clk_src";
1248                         };
1249                 };
1250
1251                 system-cache-controller@9200000 {
1252                         compatible = "qcom,sc8280xp-llcc";
1253                         reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
1254                         reg-names = "llcc_base", "llcc_broadcast_base";
1255                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1256                 };
1257
1258                 usb_0: usb@a6f8800 {
1259                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1260                         reg = <0 0x0a6f8800 0 0x400>;
1261                         #address-cells = <2>;
1262                         #size-cells = <2>;
1263                         ranges;
1264
1265                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1266                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1267                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1268                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1269                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1270                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1271                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1272                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1273                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1274                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1275                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1276
1277                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1278                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1279                         assigned-clock-rates = <19200000>, <200000000>;
1280
1281                         interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
1282                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
1283                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1284                                               <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
1285                         interrupt-names = "pwr_event",
1286                                           "dp_hs_phy_irq",
1287                                           "dm_hs_phy_irq",
1288                                           "ss_phy_irq";
1289
1290                         power-domains = <&gcc USB30_PRIM_GDSC>;
1291                         required-opps = <&rpmhpd_opp_nom>;
1292
1293                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1294
1295                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1296                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1297                         interconnect-names = "usb-ddr", "apps-usb";
1298
1299                         wakeup-source;
1300
1301                         status = "disabled";
1302
1303                         usb_0_dwc3: usb@a600000 {
1304                                 compatible = "snps,dwc3";
1305                                 reg = <0 0x0a600000 0 0xcd00>;
1306                                 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1307                                 iommus = <&apps_smmu 0x820 0x0>;
1308                                 phys = <&usb_0_hsphy>, <&usb_0_ssphy>;
1309                                 phy-names = "usb2-phy", "usb3-phy";
1310                         };
1311                 };
1312
1313                 usb_1: usb@a8f8800 {
1314                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
1315                         reg = <0 0x0a8f8800 0 0x400>;
1316                         #address-cells = <2>;
1317                         #size-cells = <2>;
1318                         ranges;
1319
1320                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1321                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1322                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1323                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1324                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1325                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
1326                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
1327                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
1328                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
1329                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
1330                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
1331
1332                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1333                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1334                         assigned-clock-rates = <19200000>, <200000000>;
1335
1336                         interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
1337                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
1338                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
1339                                               <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
1340                         interrupt-names = "pwr_event",
1341                                           "dp_hs_phy_irq",
1342                                           "dm_hs_phy_irq",
1343                                           "ss_phy_irq";
1344
1345                         power-domains = <&gcc USB30_SEC_GDSC>;
1346                         required-opps = <&rpmhpd_opp_nom>;
1347
1348                         resets = <&gcc GCC_USB30_SEC_BCR>;
1349
1350                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1351                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1352                         interconnect-names = "usb-ddr", "apps-usb";
1353
1354                         wakeup-source;
1355
1356                         status = "disabled";
1357
1358                         usb_1_dwc3: usb@a800000 {
1359                                 compatible = "snps,dwc3";
1360                                 reg = <0 0x0a800000 0 0xcd00>;
1361                                 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1362                                 iommus = <&apps_smmu 0x860 0x0>;
1363                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1364                                 phy-names = "usb2-phy", "usb3-phy";
1365                         };
1366                 };
1367
1368                 pdc: interrupt-controller@b220000 {
1369                         compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
1370                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1371                         qcom,pdc-ranges = <0 480 40>,
1372                                           <40 140 14>,
1373                                           <54 263 1>,
1374                                           <55 306 4>,
1375                                           <59 312 3>,
1376                                           <62 374 2>,
1377                                           <64 434 2>,
1378                                           <66 438 3>,
1379                                           <69 86 1>,
1380                                           <70 520 54>,
1381                                           <124 609 28>,
1382                                           <159 638 1>,
1383                                           <160 720 8>,
1384                                           <168 801 1>,
1385                                           <169 728 30>,
1386                                           <199 416 2>,
1387                                           <201 449 1>,
1388                                           <202 89 1>,
1389                                           <203 451 1>,
1390                                           <204 462 1>,
1391                                           <205 264 1>,
1392                                           <206 579 1>,
1393                                           <207 653 1>,
1394                                           <208 656 1>,
1395                                           <209 659 1>,
1396                                           <210 122 1>,
1397                                           <211 699 1>,
1398                                           <212 705 1>,
1399                                           <213 450 1>,
1400                                           <214 643 1>,
1401                                           <216 646 5>,
1402                                           <221 390 5>,
1403                                           <226 700 3>,
1404                                           <229 240 3>,
1405                                           <232 269 1>,
1406                                           <233 377 1>,
1407                                           <234 372 1>,
1408                                           <235 138 1>,
1409                                           <236 857 1>,
1410                                           <237 860 1>,
1411                                           <238 137 1>,
1412                                           <239 668 1>,
1413                                           <240 366 1>,
1414                                           <241 949 1>,
1415                                           <242 815 5>,
1416                                           <247 769 1>,
1417                                           <248 768 1>,
1418                                           <249 663 1>,
1419                                           <250 799 2>,
1420                                           <252 798 1>,
1421                                           <253 765 1>,
1422                                           <254 763 1>,
1423                                           <255 454 1>,
1424                                           <258 139 1>,
1425                                           <259 786 2>,
1426                                           <261 370 2>,
1427                                           <263 158 2>;
1428                         #interrupt-cells = <2>;
1429                         interrupt-parent = <&intc>;
1430                         interrupt-controller;
1431                 };
1432
1433                 tsens0: thermal-sensor@c263000 {
1434                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1435                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1436                               <0 0x0c222000 0 0x8>; /* SROT */
1437                         #qcom,sensors = <14>;
1438                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1439                                               <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1440                         interrupt-names = "uplow", "critical";
1441                         #thermal-sensor-cells = <1>;
1442                 };
1443
1444                 tsens1: thermal-sensor@c265000 {
1445                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
1446                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1447                               <0 0x0c223000 0 0x8>; /* SROT */
1448                         #qcom,sensors = <16>;
1449                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1450                                               <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1451                         interrupt-names = "uplow", "critical";
1452                         #thermal-sensor-cells = <1>;
1453                 };
1454
1455                 aoss_qmp: power-controller@c300000 {
1456                         compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
1457                         reg = <0 0x0c300000 0 0x400>;
1458                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
1459                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1460
1461                         #clock-cells = <0>;
1462                 };
1463
1464                 spmi_bus: spmi@c440000 {
1465                         compatible = "qcom,spmi-pmic-arb";
1466                         reg = <0 0x0c440000 0 0x1100>,
1467                               <0 0x0c600000 0 0x2000000>,
1468                               <0 0x0e600000 0 0x100000>,
1469                               <0 0x0e700000 0 0xa0000>,
1470                               <0 0x0c40a000 0 0x26000>;
1471                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1472                         interrupt-names = "periph_irq";
1473                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1474                         qcom,ee = <0>;
1475                         qcom,channel = <0>;
1476                         #address-cells = <2>;
1477                         #size-cells = <0>;
1478                         interrupt-controller;
1479                         #interrupt-cells = <4>;
1480                 };
1481
1482                 tlmm: pinctrl@f100000 {
1483                         compatible = "qcom,sc8280xp-tlmm";
1484                         reg = <0 0x0f100000 0 0x300000>;
1485                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1486                         gpio-controller;
1487                         #gpio-cells = <2>;
1488                         interrupt-controller;
1489                         #interrupt-cells = <2>;
1490                         gpio-ranges = <&tlmm 0 0 230>;
1491                 };
1492
1493                 apps_smmu: iommu@15000000 {
1494                         compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
1495                         reg = <0 0x15000000 0 0x100000>;
1496                         #iommu-cells = <2>;
1497                         #global-interrupts = <2>;
1498                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1499                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1500                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1501                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1502                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1503                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1504                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1505                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1506                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1507                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1508                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1509                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1510                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1512                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1513                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1514                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1515                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1516                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1517                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1518                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1519                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1520                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1521                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1522                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1523                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1524                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1525                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1526                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1527                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1528                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1529                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1530                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1531                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1532                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1533                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1534                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1535                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1536                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1537                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1538                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1539                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1540                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1541                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1542                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1543                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1544                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1545                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1546                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1547                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1548                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1549                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1550                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1551                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1552                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1553                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1554                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1555                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1556                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1557                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1558                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1559                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1560                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1561                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1562                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1563                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1564                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1565                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1566                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1567                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1568                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1569                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1570                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1571                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1572                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1573                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1574                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1575                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1576                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1577                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1578                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
1579                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1580                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1581                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1582                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
1583                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1584                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1585                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1586                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1587                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1588                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1589                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1590                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1591                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1592                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
1593                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
1594                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1595                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
1596                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
1597                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
1598                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
1599                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
1600                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
1601                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
1602                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
1603                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
1604                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
1605                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
1606                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
1607                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
1608                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
1609                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
1610                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
1611                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
1612                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
1613                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
1614                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
1615                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
1616                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
1617                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
1618                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
1619                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
1620                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
1621                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
1622                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
1623                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
1624                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
1625                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
1626                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
1627                                      <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
1628                 };
1629
1630                 intc: interrupt-controller@17a00000 {
1631                         compatible = "arm,gic-v3";
1632                         interrupt-controller;
1633                         #interrupt-cells = <3>;
1634                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1635                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1636                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1637                         #redistributor-regions = <1>;
1638                         redistributor-stride = <0 0x20000>;
1639
1640                         #address-cells = <2>;
1641                         #size-cells = <2>;
1642                         ranges;
1643
1644                         gic-its@17a40000 {
1645                                 compatible = "arm,gic-v3-its";
1646                                 reg = <0 0x17a40000 0 0x20000>;
1647                                 msi-controller;
1648                                 #msi-cells = <1>;
1649                         };
1650                 };
1651
1652                 watchdog@17c10000 {
1653                         compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
1654                         reg = <0 0x17c10000 0 0x1000>;
1655                         clocks = <&sleep_clk>;
1656                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
1657                 };
1658
1659                 timer@17c20000 {
1660                         compatible = "arm,armv7-timer-mem";
1661                         reg = <0x0 0x17c20000 0x0 0x1000>;
1662                         #address-cells = <1>;
1663                         #size-cells = <1>;
1664                         ranges = <0x0 0x0 0x0 0x20000000>;
1665
1666                         frame@17c21000 {
1667                                 frame-number = <0>;
1668                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1669                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1670                                 reg = <0x17c21000 0x1000>,
1671                                       <0x17c22000 0x1000>;
1672                         };
1673
1674                         frame@17c23000 {
1675                                 frame-number = <1>;
1676                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1677                                 reg = <0x17c23000 0x1000>;
1678                                 status = "disabled";
1679                         };
1680
1681                         frame@17c25000 {
1682                                 frame-number = <2>;
1683                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1684                                 reg = <0x17c25000 0x1000>;
1685                                 status = "disabled";
1686                         };
1687
1688                         frame@17c27000 {
1689                                 frame-number = <3>;
1690                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1691                                 reg = <0x17c26000 0x1000>;
1692                                 status = "disabled";
1693                         };
1694
1695                         frame@17c29000 {
1696                                 frame-number = <4>;
1697                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1698                                 reg = <0x17c29000 0x1000>;
1699                                 status = "disabled";
1700                         };
1701
1702                         frame@17c2b000 {
1703                                 frame-number = <5>;
1704                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1705                                 reg = <0x17c2b000 0x1000>;
1706                                 status = "disabled";
1707                         };
1708
1709                         frame@17c2d000 {
1710                                 frame-number = <6>;
1711                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1712                                 reg = <0x17c2d000 0x1000>;
1713                                 status = "disabled";
1714                         };
1715                 };
1716
1717                 apps_rsc: rsc@18200000 {
1718                         compatible = "qcom,rpmh-rsc";
1719                         reg = <0x0 0x18200000 0x0 0x10000>,
1720                                 <0x0 0x18210000 0x0 0x10000>,
1721                                 <0x0 0x18220000 0x0 0x10000>;
1722                         reg-names = "drv-0", "drv-1", "drv-2";
1723                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1724                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1725                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1726                         qcom,tcs-offset = <0xd00>;
1727                         qcom,drv-id = <2>;
1728                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
1729                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
1730                         label = "apps_rsc";
1731                         power-domains = <&CLUSTER_PD>;
1732
1733                         apps_bcm_voter: bcm-voter {
1734                                 compatible = "qcom,bcm-voter";
1735                         };
1736
1737                         rpmhcc: clock-controller {
1738                                 compatible = "qcom,sc8280xp-rpmh-clk";
1739                                 #clock-cells = <1>;
1740                                 clock-names = "xo";
1741                                 clocks = <&xo_board_clk>;
1742                         };
1743
1744                         rpmhpd: power-controller {
1745                                 compatible = "qcom,sc8280xp-rpmhpd";
1746                                 #power-domain-cells = <1>;
1747                                 operating-points-v2 = <&rpmhpd_opp_table>;
1748
1749                                 rpmhpd_opp_table: opp-table {
1750                                         compatible = "operating-points-v2";
1751
1752                                         rpmhpd_opp_ret: opp1 {
1753                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1754                                         };
1755
1756                                         rpmhpd_opp_min_svs: opp2 {
1757                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1758                                         };
1759
1760                                         rpmhpd_opp_low_svs: opp3 {
1761                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1762                                         };
1763
1764                                         rpmhpd_opp_svs: opp4 {
1765                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1766                                         };
1767
1768                                         rpmhpd_opp_svs_l1: opp5 {
1769                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1770                                         };
1771
1772                                         rpmhpd_opp_nom: opp6 {
1773                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1774                                         };
1775
1776                                         rpmhpd_opp_nom_l1: opp7 {
1777                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1778                                         };
1779
1780                                         rpmhpd_opp_nom_l2: opp8 {
1781                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1782                                         };
1783
1784                                         rpmhpd_opp_turbo: opp9 {
1785                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1786                                         };
1787
1788                                         rpmhpd_opp_turbo_l1: opp10 {
1789                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1790                                         };
1791                                 };
1792                         };
1793                 };
1794
1795                 cpufreq_hw: cpufreq@18591000 {
1796                         compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
1797                         reg = <0 0x18591000 0 0x1000>,
1798                               <0 0x18592000 0 0x1000>;
1799                         reg-names = "freq-domain0", "freq-domain1";
1800
1801                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1802                         clock-names = "xo", "alternate";
1803
1804                         #freq-domain-cells = <1>;
1805                 };
1806
1807                 remoteproc_nsp0: remoteproc@1b300000 {
1808                         compatible = "qcom,sc8280xp-nsp0-pas";
1809                         reg = <0 0x1b300000 0 0x100>;
1810
1811                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1812                                               <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
1813                                               <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
1814                                               <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
1815                                               <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
1816                         interrupt-names = "wdog", "fatal", "ready",
1817                                           "handover", "stop-ack";
1818
1819                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1820                         clock-names = "xo";
1821
1822                         power-domains = <&rpmhpd SC8280XP_NSP>;
1823                         power-domain-names = "nsp";
1824
1825                         memory-region = <&pil_nsp0_mem>;
1826
1827                         qcom,smem-states = <&smp2p_nsp0_out 0>;
1828                         qcom,smem-state-names = "stop";
1829
1830                         interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
1831
1832                         status = "disabled";
1833
1834                         glink-edge {
1835                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1836                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1837                                                              IRQ_TYPE_EDGE_RISING>;
1838                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1839                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1840
1841                                 label = "nsp0";
1842                                 qcom,remote-pid = <5>;
1843
1844                                 fastrpc {
1845                                         compatible = "qcom,fastrpc";
1846                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1847                                         label = "cdsp";
1848                                         #address-cells = <1>;
1849                                         #size-cells = <0>;
1850
1851                                         compute-cb@1 {
1852                                                 compatible = "qcom,fastrpc-compute-cb";
1853                                                 reg = <1>;
1854                                                 iommus = <&apps_smmu 0x3181 0x0420>;
1855                                         };
1856
1857                                         compute-cb@2 {
1858                                                 compatible = "qcom,fastrpc-compute-cb";
1859                                                 reg = <2>;
1860                                                 iommus = <&apps_smmu 0x3182 0x0420>;
1861                                         };
1862
1863                                         compute-cb@3 {
1864                                                 compatible = "qcom,fastrpc-compute-cb";
1865                                                 reg = <3>;
1866                                                 iommus = <&apps_smmu 0x3183 0x0420>;
1867                                         };
1868
1869                                         compute-cb@4 {
1870                                                 compatible = "qcom,fastrpc-compute-cb";
1871                                                 reg = <4>;
1872                                                 iommus = <&apps_smmu 0x3184 0x0420>;
1873                                         };
1874
1875                                         compute-cb@5 {
1876                                                 compatible = "qcom,fastrpc-compute-cb";
1877                                                 reg = <5>;
1878                                                 iommus = <&apps_smmu 0x3185 0x0420>;
1879                                         };
1880
1881                                         compute-cb@6 {
1882                                                 compatible = "qcom,fastrpc-compute-cb";
1883                                                 reg = <6>;
1884                                                 iommus = <&apps_smmu 0x3186 0x0420>;
1885                                         };
1886
1887                                         compute-cb@7 {
1888                                                 compatible = "qcom,fastrpc-compute-cb";
1889                                                 reg = <7>;
1890                                                 iommus = <&apps_smmu 0x3187 0x0420>;
1891                                         };
1892
1893                                         compute-cb@8 {
1894                                                 compatible = "qcom,fastrpc-compute-cb";
1895                                                 reg = <8>;
1896                                                 iommus = <&apps_smmu 0x3188 0x0420>;
1897                                         };
1898
1899                                         compute-cb@9 {
1900                                                 compatible = "qcom,fastrpc-compute-cb";
1901                                                 reg = <9>;
1902                                                 iommus = <&apps_smmu 0x318b 0x0420>;
1903                                         };
1904
1905                                         compute-cb@10 {
1906                                                 compatible = "qcom,fastrpc-compute-cb";
1907                                                 reg = <10>;
1908                                                 iommus = <&apps_smmu 0x318b 0x0420>;
1909                                         };
1910
1911                                         compute-cb@11 {
1912                                                 compatible = "qcom,fastrpc-compute-cb";
1913                                                 reg = <11>;
1914                                                 iommus = <&apps_smmu 0x318c 0x0420>;
1915                                         };
1916
1917                                         compute-cb@12 {
1918                                                 compatible = "qcom,fastrpc-compute-cb";
1919                                                 reg = <12>;
1920                                                 iommus = <&apps_smmu 0x318d 0x0420>;
1921                                         };
1922
1923                                         compute-cb@13 {
1924                                                 compatible = "qcom,fastrpc-compute-cb";
1925                                                 reg = <13>;
1926                                                 iommus = <&apps_smmu 0x318e 0x0420>;
1927                                         };
1928
1929                                         compute-cb@14 {
1930                                                 compatible = "qcom,fastrpc-compute-cb";
1931                                                 reg = <14>;
1932                                                 iommus = <&apps_smmu 0x318f 0x0420>;
1933                                         };
1934                                 };
1935                         };
1936                 };
1937
1938                 remoteproc_nsp1: remoteproc@21300000 {
1939                         compatible = "qcom,sc8280xp-nsp1-pas";
1940                         reg = <0 0x21300000 0 0x100>;
1941
1942                         interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
1943                                               <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
1944                                               <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
1945                                               <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
1946                                               <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
1947                         interrupt-names = "wdog", "fatal", "ready",
1948                                           "handover", "stop-ack";
1949
1950                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1951                         clock-names = "xo";
1952
1953                         power-domains = <&rpmhpd SC8280XP_NSP>;
1954                         power-domain-names = "nsp";
1955
1956                         memory-region = <&pil_nsp1_mem>;
1957
1958                         qcom,smem-states = <&smp2p_nsp1_out 0>;
1959                         qcom,smem-state-names = "stop";
1960
1961                         interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
1962
1963                         status = "disabled";
1964
1965                         glink-edge {
1966                                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
1967                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1968                                                              IRQ_TYPE_EDGE_RISING>;
1969                                 mboxes = <&ipcc IPCC_CLIENT_NSP1
1970                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1971
1972                                 label = "nsp1";
1973                                 qcom,remote-pid = <12>;
1974                         };
1975                 };
1976         };
1977
1978         thermal-zones {
1979                 cpu0-thermal {
1980                         polling-delay-passive = <250>;
1981                         polling-delay = <1000>;
1982
1983                         thermal-sensors = <&tsens0 1>;
1984
1985                         trips {
1986                                 cpu-crit {
1987                                         temperature = <110000>;
1988                                         hysteresis = <1000>;
1989                                         type = "critical";
1990                                 };
1991                         };
1992                 };
1993
1994                 cpu1-thermal {
1995                         polling-delay-passive = <250>;
1996                         polling-delay = <1000>;
1997
1998                         thermal-sensors = <&tsens0 2>;
1999
2000                         trips {
2001                                 cpu-crit {
2002                                         temperature = <110000>;
2003                                         hysteresis = <1000>;
2004                                         type = "critical";
2005                                 };
2006                         };
2007                 };
2008
2009                 cpu2-thermal {
2010                         polling-delay-passive = <250>;
2011                         polling-delay = <1000>;
2012
2013                         thermal-sensors = <&tsens0 3>;
2014
2015                         trips {
2016                                 cpu-crit {
2017                                         temperature = <110000>;
2018                                         hysteresis = <1000>;
2019                                         type = "critical";
2020                                 };
2021                         };
2022                 };
2023
2024                 cpu3-thermal {
2025                         polling-delay-passive = <250>;
2026                         polling-delay = <1000>;
2027
2028                         thermal-sensors = <&tsens0 4>;
2029
2030                         trips {
2031                                 cpu-crit {
2032                                         temperature = <110000>;
2033                                         hysteresis = <1000>;
2034                                         type = "critical";
2035                                 };
2036                         };
2037                 };
2038
2039                 cpu4-thermal {
2040                         polling-delay-passive = <250>;
2041                         polling-delay = <1000>;
2042
2043                         thermal-sensors = <&tsens0 5>;
2044
2045                         trips {
2046                                 cpu-crit {
2047                                         temperature = <110000>;
2048                                         hysteresis = <1000>;
2049                                         type = "critical";
2050                                 };
2051                         };
2052                 };
2053
2054                 cpu5-thermal {
2055                         polling-delay-passive = <250>;
2056                         polling-delay = <1000>;
2057
2058                         thermal-sensors = <&tsens0 6>;
2059
2060                         trips {
2061                                 cpu-crit {
2062                                         temperature = <110000>;
2063                                         hysteresis = <1000>;
2064                                         type = "critical";
2065                                 };
2066                         };
2067                 };
2068
2069                 cpu6-thermal {
2070                         polling-delay-passive = <250>;
2071                         polling-delay = <1000>;
2072
2073                         thermal-sensors = <&tsens0 7>;
2074
2075                         trips {
2076                                 cpu-crit {
2077                                         temperature = <110000>;
2078                                         hysteresis = <1000>;
2079                                         type = "critical";
2080                                 };
2081                         };
2082                 };
2083
2084                 cpu7-thermal {
2085                         polling-delay-passive = <250>;
2086                         polling-delay = <1000>;
2087
2088                         thermal-sensors = <&tsens0 8>;
2089
2090                         trips {
2091                                 cpu-crit {
2092                                         temperature = <110000>;
2093                                         hysteresis = <1000>;
2094                                         type = "critical";
2095                                 };
2096                         };
2097                 };
2098
2099                 cluster0-thermal {
2100                         polling-delay-passive = <250>;
2101                         polling-delay = <1000>;
2102
2103                         thermal-sensors = <&tsens0 9>;
2104
2105                         trips {
2106                                 cpu-crit {
2107                                         temperature = <110000>;
2108                                         hysteresis = <1000>;
2109                                         type = "critical";
2110                                 };
2111                         };
2112                 };
2113
2114                 mem-thermal {
2115                         polling-delay-passive = <250>;
2116                         polling-delay = <1000>;
2117
2118                         thermal-sensors = <&tsens1 15>;
2119
2120                         trips {
2121                                 trip-point0 {
2122                                         temperature = <90000>;
2123                                         hysteresis = <2000>;
2124                                         type = "hot";
2125                                 };
2126                         };
2127                 };
2128         };
2129
2130         timer {
2131                 compatible = "arm,armv8-timer";
2132                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2133                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2134                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2135                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2136         };
2137 };