1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sc7280.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/mailbox/qcom-ipcc.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/power/qcom-rpmpd.h>
24 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
25 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
26 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
27 #include <dt-bindings/sound/qcom,lpass.h>
28 #include <dt-bindings/thermal/thermal.h>
31 interrupt-parent = <&intc>;
77 compatible = "fixed-clock";
78 clock-frequency = <76800000>;
82 sleep_clk: sleep-clk {
83 compatible = "fixed-clock";
84 clock-frequency = <32000>;
94 wlan_ce_mem: memory@4cd000 {
96 reg = <0x0 0x004cd000 0x0 0x1000>;
99 hyp_mem: memory@80000000 {
100 reg = <0x0 0x80000000 0x0 0x600000>;
104 xbl_mem: memory@80600000 {
105 reg = <0x0 0x80600000 0x0 0x200000>;
109 aop_mem: memory@80800000 {
110 reg = <0x0 0x80800000 0x0 0x60000>;
114 aop_cmd_db_mem: memory@80860000 {
115 reg = <0x0 0x80860000 0x0 0x20000>;
116 compatible = "qcom,cmd-db";
120 reserved_xbl_uefi_log: memory@80880000 {
121 reg = <0x0 0x80884000 0x0 0x10000>;
125 sec_apps_mem: memory@808ff000 {
126 reg = <0x0 0x808ff000 0x0 0x1000>;
130 smem_mem: memory@80900000 {
131 reg = <0x0 0x80900000 0x0 0x200000>;
135 cpucp_mem: memory@80b00000 {
137 reg = <0x0 0x80b00000 0x0 0x100000>;
140 wlan_fw_mem: memory@80c00000 {
141 reg = <0x0 0x80c00000 0x0 0xc00000>;
145 video_mem: memory@8b200000 {
146 reg = <0x0 0x8b200000 0x0 0x500000>;
150 ipa_fw_mem: memory@8b700000 {
151 reg = <0 0x8b700000 0 0x10000>;
155 rmtfs_mem: memory@9c900000 {
156 compatible = "qcom,rmtfs-mem";
157 reg = <0x0 0x9c900000 0x0 0x280000>;
160 qcom,client-id = <1>;
161 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
166 #address-cells = <2>;
171 compatible = "qcom,kryo";
173 clocks = <&cpufreq_hw 0>;
174 enable-method = "psci";
175 power-domains = <&CPU_PD0>;
176 power-domain-names = "psci";
177 next-level-cache = <&L2_0>;
178 operating-points-v2 = <&cpu0_opp_table>;
179 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
180 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
181 qcom,freq-domain = <&cpufreq_hw 0>;
182 #cooling-cells = <2>;
184 compatible = "cache";
187 next-level-cache = <&L3_0>;
189 compatible = "cache";
198 compatible = "qcom,kryo";
200 clocks = <&cpufreq_hw 0>;
201 enable-method = "psci";
202 power-domains = <&CPU_PD1>;
203 power-domain-names = "psci";
204 next-level-cache = <&L2_100>;
205 operating-points-v2 = <&cpu0_opp_table>;
206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
208 qcom,freq-domain = <&cpufreq_hw 0>;
209 #cooling-cells = <2>;
211 compatible = "cache";
214 next-level-cache = <&L3_0>;
220 compatible = "qcom,kryo";
222 clocks = <&cpufreq_hw 0>;
223 enable-method = "psci";
224 power-domains = <&CPU_PD2>;
225 power-domain-names = "psci";
226 next-level-cache = <&L2_200>;
227 operating-points-v2 = <&cpu0_opp_table>;
228 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
229 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
230 qcom,freq-domain = <&cpufreq_hw 0>;
231 #cooling-cells = <2>;
233 compatible = "cache";
236 next-level-cache = <&L3_0>;
242 compatible = "qcom,kryo";
244 clocks = <&cpufreq_hw 0>;
245 enable-method = "psci";
246 power-domains = <&CPU_PD3>;
247 power-domain-names = "psci";
248 next-level-cache = <&L2_300>;
249 operating-points-v2 = <&cpu0_opp_table>;
250 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
251 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
252 qcom,freq-domain = <&cpufreq_hw 0>;
253 #cooling-cells = <2>;
255 compatible = "cache";
258 next-level-cache = <&L3_0>;
264 compatible = "qcom,kryo";
266 clocks = <&cpufreq_hw 1>;
267 enable-method = "psci";
268 power-domains = <&CPU_PD4>;
269 power-domain-names = "psci";
270 next-level-cache = <&L2_400>;
271 operating-points-v2 = <&cpu4_opp_table>;
272 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
273 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
274 qcom,freq-domain = <&cpufreq_hw 1>;
275 #cooling-cells = <2>;
277 compatible = "cache";
280 next-level-cache = <&L3_0>;
286 compatible = "qcom,kryo";
288 clocks = <&cpufreq_hw 1>;
289 enable-method = "psci";
290 power-domains = <&CPU_PD5>;
291 power-domain-names = "psci";
292 next-level-cache = <&L2_500>;
293 operating-points-v2 = <&cpu4_opp_table>;
294 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
295 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
296 qcom,freq-domain = <&cpufreq_hw 1>;
297 #cooling-cells = <2>;
299 compatible = "cache";
302 next-level-cache = <&L3_0>;
308 compatible = "qcom,kryo";
310 clocks = <&cpufreq_hw 1>;
311 enable-method = "psci";
312 power-domains = <&CPU_PD6>;
313 power-domain-names = "psci";
314 next-level-cache = <&L2_600>;
315 operating-points-v2 = <&cpu4_opp_table>;
316 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
317 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
318 qcom,freq-domain = <&cpufreq_hw 1>;
319 #cooling-cells = <2>;
321 compatible = "cache";
324 next-level-cache = <&L3_0>;
330 compatible = "qcom,kryo";
332 clocks = <&cpufreq_hw 2>;
333 enable-method = "psci";
334 power-domains = <&CPU_PD7>;
335 power-domain-names = "psci";
336 next-level-cache = <&L2_700>;
337 operating-points-v2 = <&cpu7_opp_table>;
338 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
339 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
340 qcom,freq-domain = <&cpufreq_hw 2>;
341 #cooling-cells = <2>;
343 compatible = "cache";
346 next-level-cache = <&L3_0>;
387 entry-method = "psci";
389 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
390 compatible = "arm,idle-state";
391 idle-state-name = "little-power-down";
392 arm,psci-suspend-param = <0x40000003>;
393 entry-latency-us = <549>;
394 exit-latency-us = <901>;
395 min-residency-us = <1774>;
399 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
400 compatible = "arm,idle-state";
401 idle-state-name = "little-rail-power-down";
402 arm,psci-suspend-param = <0x40000004>;
403 entry-latency-us = <702>;
404 exit-latency-us = <915>;
405 min-residency-us = <4001>;
409 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "big-power-down";
412 arm,psci-suspend-param = <0x40000003>;
413 entry-latency-us = <523>;
414 exit-latency-us = <1244>;
415 min-residency-us = <2207>;
419 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
420 compatible = "arm,idle-state";
421 idle-state-name = "big-rail-power-down";
422 arm,psci-suspend-param = <0x40000004>;
423 entry-latency-us = <526>;
424 exit-latency-us = <1854>;
425 min-residency-us = <5555>;
431 CLUSTER_SLEEP_0: cluster-sleep-0 {
432 compatible = "domain-idle-state";
433 idle-state-name = "cluster-power-down";
434 arm,psci-suspend-param = <0x40003444>;
435 entry-latency-us = <3263>;
436 exit-latency-us = <6562>;
437 min-residency-us = <9926>;
443 cpu0_opp_table: opp-table-cpu0 {
444 compatible = "operating-points-v2";
447 cpu0_opp_300mhz: opp-300000000 {
448 opp-hz = /bits/ 64 <300000000>;
449 opp-peak-kBps = <800000 9600000>;
452 cpu0_opp_691mhz: opp-691200000 {
453 opp-hz = /bits/ 64 <691200000>;
454 opp-peak-kBps = <800000 17817600>;
457 cpu0_opp_806mhz: opp-806400000 {
458 opp-hz = /bits/ 64 <806400000>;
459 opp-peak-kBps = <800000 20889600>;
462 cpu0_opp_941mhz: opp-940800000 {
463 opp-hz = /bits/ 64 <940800000>;
464 opp-peak-kBps = <1804000 24576000>;
467 cpu0_opp_1152mhz: opp-1152000000 {
468 opp-hz = /bits/ 64 <1152000000>;
469 opp-peak-kBps = <2188000 27033600>;
472 cpu0_opp_1325mhz: opp-1324800000 {
473 opp-hz = /bits/ 64 <1324800000>;
474 opp-peak-kBps = <2188000 33792000>;
477 cpu0_opp_1517mhz: opp-1516800000 {
478 opp-hz = /bits/ 64 <1516800000>;
479 opp-peak-kBps = <3072000 38092800>;
482 cpu0_opp_1651mhz: opp-1651200000 {
483 opp-hz = /bits/ 64 <1651200000>;
484 opp-peak-kBps = <3072000 41779200>;
487 cpu0_opp_1805mhz: opp-1804800000 {
488 opp-hz = /bits/ 64 <1804800000>;
489 opp-peak-kBps = <4068000 48537600>;
492 cpu0_opp_1958mhz: opp-1958400000 {
493 opp-hz = /bits/ 64 <1958400000>;
494 opp-peak-kBps = <4068000 48537600>;
497 cpu0_opp_2016mhz: opp-2016000000 {
498 opp-hz = /bits/ 64 <2016000000>;
499 opp-peak-kBps = <6220000 48537600>;
503 cpu4_opp_table: opp-table-cpu4 {
504 compatible = "operating-points-v2";
507 cpu4_opp_691mhz: opp-691200000 {
508 opp-hz = /bits/ 64 <691200000>;
509 opp-peak-kBps = <1804000 9600000>;
512 cpu4_opp_941mhz: opp-940800000 {
513 opp-hz = /bits/ 64 <940800000>;
514 opp-peak-kBps = <2188000 17817600>;
517 cpu4_opp_1229mhz: opp-1228800000 {
518 opp-hz = /bits/ 64 <1228800000>;
519 opp-peak-kBps = <4068000 24576000>;
522 cpu4_opp_1344mhz: opp-1344000000 {
523 opp-hz = /bits/ 64 <1344000000>;
524 opp-peak-kBps = <4068000 24576000>;
527 cpu4_opp_1517mhz: opp-1516800000 {
528 opp-hz = /bits/ 64 <1516800000>;
529 opp-peak-kBps = <4068000 24576000>;
532 cpu4_opp_1651mhz: opp-1651200000 {
533 opp-hz = /bits/ 64 <1651200000>;
534 opp-peak-kBps = <6220000 38092800>;
537 cpu4_opp_1901mhz: opp-1900800000 {
538 opp-hz = /bits/ 64 <1900800000>;
539 opp-peak-kBps = <6220000 44851200>;
542 cpu4_opp_2054mhz: opp-2054400000 {
543 opp-hz = /bits/ 64 <2054400000>;
544 opp-peak-kBps = <6220000 44851200>;
547 cpu4_opp_2112mhz: opp-2112000000 {
548 opp-hz = /bits/ 64 <2112000000>;
549 opp-peak-kBps = <6220000 44851200>;
552 cpu4_opp_2131mhz: opp-2131200000 {
553 opp-hz = /bits/ 64 <2131200000>;
554 opp-peak-kBps = <6220000 44851200>;
557 cpu4_opp_2208mhz: opp-2208000000 {
558 opp-hz = /bits/ 64 <2208000000>;
559 opp-peak-kBps = <6220000 44851200>;
562 cpu4_opp_2400mhz: opp-2400000000 {
563 opp-hz = /bits/ 64 <2400000000>;
564 opp-peak-kBps = <8532000 48537600>;
567 cpu4_opp_2611mhz: opp-2611200000 {
568 opp-hz = /bits/ 64 <2611200000>;
569 opp-peak-kBps = <8532000 48537600>;
573 cpu7_opp_table: opp-table-cpu7 {
574 compatible = "operating-points-v2";
577 cpu7_opp_806mhz: opp-806400000 {
578 opp-hz = /bits/ 64 <806400000>;
579 opp-peak-kBps = <1804000 9600000>;
582 cpu7_opp_1056mhz: opp-1056000000 {
583 opp-hz = /bits/ 64 <1056000000>;
584 opp-peak-kBps = <2188000 17817600>;
587 cpu7_opp_1325mhz: opp-1324800000 {
588 opp-hz = /bits/ 64 <1324800000>;
589 opp-peak-kBps = <4068000 24576000>;
592 cpu7_opp_1517mhz: opp-1516800000 {
593 opp-hz = /bits/ 64 <1516800000>;
594 opp-peak-kBps = <4068000 24576000>;
597 cpu7_opp_1766mhz: opp-1766400000 {
598 opp-hz = /bits/ 64 <1766400000>;
599 opp-peak-kBps = <6220000 38092800>;
602 cpu7_opp_1862mhz: opp-1862400000 {
603 opp-hz = /bits/ 64 <1862400000>;
604 opp-peak-kBps = <6220000 38092800>;
607 cpu7_opp_2035mhz: opp-2035200000 {
608 opp-hz = /bits/ 64 <2035200000>;
609 opp-peak-kBps = <6220000 38092800>;
612 cpu7_opp_2112mhz: opp-2112000000 {
613 opp-hz = /bits/ 64 <2112000000>;
614 opp-peak-kBps = <6220000 44851200>;
617 cpu7_opp_2208mhz: opp-2208000000 {
618 opp-hz = /bits/ 64 <2208000000>;
619 opp-peak-kBps = <6220000 44851200>;
622 cpu7_opp_2381mhz: opp-2380800000 {
623 opp-hz = /bits/ 64 <2380800000>;
624 opp-peak-kBps = <6832000 44851200>;
627 cpu7_opp_2400mhz: opp-2400000000 {
628 opp-hz = /bits/ 64 <2400000000>;
629 opp-peak-kBps = <8532000 48537600>;
632 cpu7_opp_2515mhz: opp-2515200000 {
633 opp-hz = /bits/ 64 <2515200000>;
634 opp-peak-kBps = <8532000 48537600>;
637 cpu7_opp_2707mhz: opp-2707200000 {
638 opp-hz = /bits/ 64 <2707200000>;
639 opp-peak-kBps = <8532000 48537600>;
642 cpu7_opp_3014mhz: opp-3014400000 {
643 opp-hz = /bits/ 64 <3014400000>;
644 opp-peak-kBps = <8532000 48537600>;
649 device_type = "memory";
650 /* We expect the bootloader to fill in the size */
651 reg = <0 0x80000000 0 0>;
656 compatible = "qcom,scm-sc7280", "qcom,scm";
660 clk_virt: interconnect {
661 compatible = "qcom,sc7280-clk-virt";
662 #interconnect-cells = <2>;
663 qcom,bcm-voters = <&apps_bcm_voter>;
667 compatible = "qcom,smem";
668 memory-region = <&smem_mem>;
669 hwlocks = <&tcsr_mutex 3>;
673 compatible = "qcom,smp2p";
674 qcom,smem = <443>, <429>;
675 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
676 IPCC_MPROC_SIGNAL_SMP2P
677 IRQ_TYPE_EDGE_RISING>;
678 mboxes = <&ipcc IPCC_CLIENT_LPASS
679 IPCC_MPROC_SIGNAL_SMP2P>;
681 qcom,local-pid = <0>;
682 qcom,remote-pid = <2>;
684 adsp_smp2p_out: master-kernel {
685 qcom,entry-name = "master-kernel";
686 #qcom,smem-state-cells = <1>;
689 adsp_smp2p_in: slave-kernel {
690 qcom,entry-name = "slave-kernel";
691 interrupt-controller;
692 #interrupt-cells = <2>;
697 compatible = "qcom,smp2p";
698 qcom,smem = <94>, <432>;
699 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
700 IPCC_MPROC_SIGNAL_SMP2P
701 IRQ_TYPE_EDGE_RISING>;
702 mboxes = <&ipcc IPCC_CLIENT_CDSP
703 IPCC_MPROC_SIGNAL_SMP2P>;
705 qcom,local-pid = <0>;
706 qcom,remote-pid = <5>;
708 cdsp_smp2p_out: master-kernel {
709 qcom,entry-name = "master-kernel";
710 #qcom,smem-state-cells = <1>;
713 cdsp_smp2p_in: slave-kernel {
714 qcom,entry-name = "slave-kernel";
715 interrupt-controller;
716 #interrupt-cells = <2>;
721 compatible = "qcom,smp2p";
722 qcom,smem = <435>, <428>;
723 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
724 IPCC_MPROC_SIGNAL_SMP2P
725 IRQ_TYPE_EDGE_RISING>;
726 mboxes = <&ipcc IPCC_CLIENT_MPSS
727 IPCC_MPROC_SIGNAL_SMP2P>;
729 qcom,local-pid = <0>;
730 qcom,remote-pid = <1>;
732 modem_smp2p_out: master-kernel {
733 qcom,entry-name = "master-kernel";
734 #qcom,smem-state-cells = <1>;
737 modem_smp2p_in: slave-kernel {
738 qcom,entry-name = "slave-kernel";
739 interrupt-controller;
740 #interrupt-cells = <2>;
743 ipa_smp2p_out: ipa-ap-to-modem {
744 qcom,entry-name = "ipa";
745 #qcom,smem-state-cells = <1>;
748 ipa_smp2p_in: ipa-modem-to-ap {
749 qcom,entry-name = "ipa";
750 interrupt-controller;
751 #interrupt-cells = <2>;
756 compatible = "qcom,smp2p";
757 qcom,smem = <617>, <616>;
758 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
759 IPCC_MPROC_SIGNAL_SMP2P
760 IRQ_TYPE_EDGE_RISING>;
761 mboxes = <&ipcc IPCC_CLIENT_WPSS
762 IPCC_MPROC_SIGNAL_SMP2P>;
764 qcom,local-pid = <0>;
765 qcom,remote-pid = <13>;
767 wpss_smp2p_out: master-kernel {
768 qcom,entry-name = "master-kernel";
769 #qcom,smem-state-cells = <1>;
772 wpss_smp2p_in: slave-kernel {
773 qcom,entry-name = "slave-kernel";
774 interrupt-controller;
775 #interrupt-cells = <2>;
778 wlan_smp2p_out: wlan-ap-to-wpss {
779 qcom,entry-name = "wlan";
780 #qcom,smem-state-cells = <1>;
783 wlan_smp2p_in: wlan-wpss-to-ap {
784 qcom,entry-name = "wlan";
785 interrupt-controller;
786 #interrupt-cells = <2>;
791 compatible = "arm,armv8-pmuv3";
792 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
796 compatible = "arm,psci-1.0";
799 CPU_PD0: power-domain-cpu0 {
800 #power-domain-cells = <0>;
801 power-domains = <&CLUSTER_PD>;
802 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
805 CPU_PD1: power-domain-cpu1 {
806 #power-domain-cells = <0>;
807 power-domains = <&CLUSTER_PD>;
808 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
811 CPU_PD2: power-domain-cpu2 {
812 #power-domain-cells = <0>;
813 power-domains = <&CLUSTER_PD>;
814 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
817 CPU_PD3: power-domain-cpu3 {
818 #power-domain-cells = <0>;
819 power-domains = <&CLUSTER_PD>;
820 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
823 CPU_PD4: power-domain-cpu4 {
824 #power-domain-cells = <0>;
825 power-domains = <&CLUSTER_PD>;
826 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
829 CPU_PD5: power-domain-cpu5 {
830 #power-domain-cells = <0>;
831 power-domains = <&CLUSTER_PD>;
832 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
835 CPU_PD6: power-domain-cpu6 {
836 #power-domain-cells = <0>;
837 power-domains = <&CLUSTER_PD>;
838 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
841 CPU_PD7: power-domain-cpu7 {
842 #power-domain-cells = <0>;
843 power-domains = <&CLUSTER_PD>;
844 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
847 CLUSTER_PD: power-domain-cluster {
848 #power-domain-cells = <0>;
849 domain-idle-states = <&CLUSTER_SLEEP_0>;
853 qspi_opp_table: opp-table-qspi {
854 compatible = "operating-points-v2";
857 opp-hz = /bits/ 64 <75000000>;
858 required-opps = <&rpmhpd_opp_low_svs>;
862 opp-hz = /bits/ 64 <150000000>;
863 required-opps = <&rpmhpd_opp_svs>;
867 opp-hz = /bits/ 64 <200000000>;
868 required-opps = <&rpmhpd_opp_svs_l1>;
872 opp-hz = /bits/ 64 <300000000>;
873 required-opps = <&rpmhpd_opp_nom>;
877 qup_opp_table: opp-table-qup {
878 compatible = "operating-points-v2";
881 opp-hz = /bits/ 64 <75000000>;
882 required-opps = <&rpmhpd_opp_low_svs>;
886 opp-hz = /bits/ 64 <100000000>;
887 required-opps = <&rpmhpd_opp_svs>;
891 opp-hz = /bits/ 64 <128000000>;
892 required-opps = <&rpmhpd_opp_nom>;
897 #address-cells = <2>;
899 ranges = <0 0 0 0 0x10 0>;
900 dma-ranges = <0 0 0 0 0x10 0>;
901 compatible = "simple-bus";
903 gcc: clock-controller@100000 {
904 compatible = "qcom,gcc-sc7280";
905 reg = <0 0x00100000 0 0x1f0000>;
906 clocks = <&rpmhcc RPMH_CXO_CLK>,
907 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
910 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
911 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
912 "pcie_0_pipe_clk", "pcie_1_pipe_clk",
913 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
914 "ufs_phy_tx_symbol_0_clk",
915 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
918 #power-domain-cells = <1>;
919 power-domains = <&rpmhpd SC7280_CX>;
922 ipcc: mailbox@408000 {
923 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
924 reg = <0 0x00408000 0 0x1000>;
925 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
926 interrupt-controller;
927 #interrupt-cells = <3>;
931 qfprom: efuse@784000 {
932 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
933 reg = <0 0x00784000 0 0xa20>,
934 <0 0x00780000 0 0xa20>,
935 <0 0x00782000 0 0x120>,
936 <0 0x00786000 0 0x1fff>;
937 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
938 clock-names = "core";
939 power-domains = <&rpmhpd SC7280_MX>;
940 #address-cells = <1>;
943 gpu_speed_bin: gpu_speed_bin@1e9 {
950 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
951 pinctrl-names = "default", "sleep";
952 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
953 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
956 reg = <0 0x007c4000 0 0x1000>,
957 <0 0x007c5000 0 0x1000>;
958 reg-names = "hc", "cqhci";
960 iommus = <&apps_smmu 0xc0 0x0>;
961 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
963 interrupt-names = "hc_irq", "pwr_irq";
965 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
966 <&gcc GCC_SDCC1_APPS_CLK>,
967 <&rpmhcc RPMH_CXO_CLK>;
968 clock-names = "iface", "core", "xo";
969 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
970 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
971 interconnect-names = "sdhc-ddr","cpu-sdhc";
972 power-domains = <&rpmhpd SC7280_CX>;
973 operating-points-v2 = <&sdhc1_opp_table>;
978 qcom,dll-config = <0x0007642c>;
979 qcom,ddr-config = <0x80040868>;
984 mmc-hs400-enhanced-strobe;
986 resets = <&gcc GCC_SDCC1_BCR>;
988 sdhc1_opp_table: opp-table {
989 compatible = "operating-points-v2";
992 opp-hz = /bits/ 64 <100000000>;
993 required-opps = <&rpmhpd_opp_low_svs>;
994 opp-peak-kBps = <1800000 400000>;
995 opp-avg-kBps = <100000 0>;
999 opp-hz = /bits/ 64 <384000000>;
1000 required-opps = <&rpmhpd_opp_nom>;
1001 opp-peak-kBps = <5400000 1600000>;
1002 opp-avg-kBps = <390000 0>;
1007 gpi_dma0: dma-controller@900000 {
1009 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1010 reg = <0 0x00900000 0 0x60000>;
1011 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1017 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1018 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1019 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1023 dma-channels = <12>;
1024 dma-channel-mask = <0x7f>;
1025 iommus = <&apps_smmu 0x0136 0x0>;
1026 status = "disabled";
1029 qupv3_id_0: geniqup@9c0000 {
1030 compatible = "qcom,geni-se-qup";
1031 reg = <0 0x009c0000 0 0x2000>;
1032 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1033 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1034 clock-names = "m-ahb", "s-ahb";
1035 #address-cells = <2>;
1038 iommus = <&apps_smmu 0x123 0x0>;
1039 status = "disabled";
1042 compatible = "qcom,geni-i2c";
1043 reg = <0 0x00980000 0 0x4000>;
1044 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1046 pinctrl-names = "default";
1047 pinctrl-0 = <&qup_i2c0_data_clk>;
1048 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1049 #address-cells = <1>;
1051 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1052 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1053 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1054 interconnect-names = "qup-core", "qup-config",
1056 power-domains = <&rpmhpd SC7280_CX>;
1057 required-opps = <&rpmhpd_opp_low_svs>;
1058 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1059 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1060 dma-names = "tx", "rx";
1061 status = "disabled";
1065 compatible = "qcom,geni-spi";
1066 reg = <0 0x00980000 0 0x4000>;
1067 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1071 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1072 #address-cells = <1>;
1074 power-domains = <&rpmhpd SC7280_CX>;
1075 operating-points-v2 = <&qup_opp_table>;
1076 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1077 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1078 interconnect-names = "qup-core", "qup-config";
1079 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1080 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1081 dma-names = "tx", "rx";
1082 status = "disabled";
1085 uart0: serial@980000 {
1086 compatible = "qcom,geni-uart";
1087 reg = <0 0x00980000 0 0x4000>;
1088 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1092 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1093 power-domains = <&rpmhpd SC7280_CX>;
1094 operating-points-v2 = <&qup_opp_table>;
1095 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1096 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1097 interconnect-names = "qup-core", "qup-config";
1098 status = "disabled";
1102 compatible = "qcom,geni-i2c";
1103 reg = <0 0x00984000 0 0x4000>;
1104 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&qup_i2c1_data_clk>;
1108 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1109 #address-cells = <1>;
1111 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1112 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1113 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1114 interconnect-names = "qup-core", "qup-config",
1116 power-domains = <&rpmhpd SC7280_CX>;
1117 required-opps = <&rpmhpd_opp_low_svs>;
1118 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1119 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1120 dma-names = "tx", "rx";
1121 status = "disabled";
1125 compatible = "qcom,geni-spi";
1126 reg = <0 0x00984000 0 0x4000>;
1127 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1131 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1132 #address-cells = <1>;
1134 power-domains = <&rpmhpd SC7280_CX>;
1135 operating-points-v2 = <&qup_opp_table>;
1136 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1137 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1138 interconnect-names = "qup-core", "qup-config";
1139 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1140 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1141 dma-names = "tx", "rx";
1142 status = "disabled";
1145 uart1: serial@984000 {
1146 compatible = "qcom,geni-uart";
1147 reg = <0 0x00984000 0 0x4000>;
1148 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1152 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1153 power-domains = <&rpmhpd SC7280_CX>;
1154 operating-points-v2 = <&qup_opp_table>;
1155 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1156 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1157 interconnect-names = "qup-core", "qup-config";
1158 status = "disabled";
1162 compatible = "qcom,geni-i2c";
1163 reg = <0 0x00988000 0 0x4000>;
1164 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&qup_i2c2_data_clk>;
1168 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1169 #address-cells = <1>;
1171 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1172 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1173 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1174 interconnect-names = "qup-core", "qup-config",
1176 power-domains = <&rpmhpd SC7280_CX>;
1177 required-opps = <&rpmhpd_opp_low_svs>;
1178 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1179 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1180 dma-names = "tx", "rx";
1181 status = "disabled";
1185 compatible = "qcom,geni-spi";
1186 reg = <0 0x00988000 0 0x4000>;
1187 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1189 pinctrl-names = "default";
1190 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1191 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1192 #address-cells = <1>;
1194 power-domains = <&rpmhpd SC7280_CX>;
1195 operating-points-v2 = <&qup_opp_table>;
1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1197 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1198 interconnect-names = "qup-core", "qup-config";
1199 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1200 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1201 dma-names = "tx", "rx";
1202 status = "disabled";
1205 uart2: serial@988000 {
1206 compatible = "qcom,geni-uart";
1207 reg = <0 0x00988000 0 0x4000>;
1208 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1212 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1213 power-domains = <&rpmhpd SC7280_CX>;
1214 operating-points-v2 = <&qup_opp_table>;
1215 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1216 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1217 interconnect-names = "qup-core", "qup-config";
1218 status = "disabled";
1222 compatible = "qcom,geni-i2c";
1223 reg = <0 0x0098c000 0 0x4000>;
1224 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1226 pinctrl-names = "default";
1227 pinctrl-0 = <&qup_i2c3_data_clk>;
1228 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1229 #address-cells = <1>;
1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1232 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1233 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1234 interconnect-names = "qup-core", "qup-config",
1236 power-domains = <&rpmhpd SC7280_CX>;
1237 required-opps = <&rpmhpd_opp_low_svs>;
1238 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1239 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1240 dma-names = "tx", "rx";
1241 status = "disabled";
1245 compatible = "qcom,geni-spi";
1246 reg = <0 0x0098c000 0 0x4000>;
1247 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1251 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1252 #address-cells = <1>;
1254 power-domains = <&rpmhpd SC7280_CX>;
1255 operating-points-v2 = <&qup_opp_table>;
1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1257 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1258 interconnect-names = "qup-core", "qup-config";
1259 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1260 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1261 dma-names = "tx", "rx";
1262 status = "disabled";
1265 uart3: serial@98c000 {
1266 compatible = "qcom,geni-uart";
1267 reg = <0 0x0098c000 0 0x4000>;
1268 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1272 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1273 power-domains = <&rpmhpd SC7280_CX>;
1274 operating-points-v2 = <&qup_opp_table>;
1275 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1276 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1277 interconnect-names = "qup-core", "qup-config";
1278 status = "disabled";
1282 compatible = "qcom,geni-i2c";
1283 reg = <0 0x00990000 0 0x4000>;
1284 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&qup_i2c4_data_clk>;
1288 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1289 #address-cells = <1>;
1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1292 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1293 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1294 interconnect-names = "qup-core", "qup-config",
1296 power-domains = <&rpmhpd SC7280_CX>;
1297 required-opps = <&rpmhpd_opp_low_svs>;
1298 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1299 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1300 dma-names = "tx", "rx";
1301 status = "disabled";
1305 compatible = "qcom,geni-spi";
1306 reg = <0 0x00990000 0 0x4000>;
1307 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1309 pinctrl-names = "default";
1310 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1311 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1312 #address-cells = <1>;
1314 power-domains = <&rpmhpd SC7280_CX>;
1315 operating-points-v2 = <&qup_opp_table>;
1316 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1317 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1318 interconnect-names = "qup-core", "qup-config";
1319 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1320 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1321 dma-names = "tx", "rx";
1322 status = "disabled";
1325 uart4: serial@990000 {
1326 compatible = "qcom,geni-uart";
1327 reg = <0 0x00990000 0 0x4000>;
1328 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1332 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1333 power-domains = <&rpmhpd SC7280_CX>;
1334 operating-points-v2 = <&qup_opp_table>;
1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1336 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1337 interconnect-names = "qup-core", "qup-config";
1338 status = "disabled";
1342 compatible = "qcom,geni-i2c";
1343 reg = <0 0x00994000 0 0x4000>;
1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1346 pinctrl-names = "default";
1347 pinctrl-0 = <&qup_i2c5_data_clk>;
1348 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1349 #address-cells = <1>;
1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1352 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1353 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1354 interconnect-names = "qup-core", "qup-config",
1356 power-domains = <&rpmhpd SC7280_CX>;
1357 required-opps = <&rpmhpd_opp_low_svs>;
1358 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1359 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1360 dma-names = "tx", "rx";
1361 status = "disabled";
1365 compatible = "qcom,geni-spi";
1366 reg = <0 0x00994000 0 0x4000>;
1367 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1369 pinctrl-names = "default";
1370 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1371 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1372 #address-cells = <1>;
1374 power-domains = <&rpmhpd SC7280_CX>;
1375 operating-points-v2 = <&qup_opp_table>;
1376 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1377 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1378 interconnect-names = "qup-core", "qup-config";
1379 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1380 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1381 dma-names = "tx", "rx";
1382 status = "disabled";
1385 uart5: serial@994000 {
1386 compatible = "qcom,geni-uart";
1387 reg = <0 0x00994000 0 0x4000>;
1388 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1390 pinctrl-names = "default";
1391 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1392 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1393 power-domains = <&rpmhpd SC7280_CX>;
1394 operating-points-v2 = <&qup_opp_table>;
1395 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1396 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1397 interconnect-names = "qup-core", "qup-config";
1398 status = "disabled";
1402 compatible = "qcom,geni-i2c";
1403 reg = <0 0x00998000 0 0x4000>;
1404 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1406 pinctrl-names = "default";
1407 pinctrl-0 = <&qup_i2c6_data_clk>;
1408 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1409 #address-cells = <1>;
1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1413 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1414 interconnect-names = "qup-core", "qup-config",
1416 power-domains = <&rpmhpd SC7280_CX>;
1417 required-opps = <&rpmhpd_opp_low_svs>;
1418 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1419 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1420 dma-names = "tx", "rx";
1421 status = "disabled";
1425 compatible = "qcom,geni-spi";
1426 reg = <0 0x00998000 0 0x4000>;
1427 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1429 pinctrl-names = "default";
1430 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1431 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1432 #address-cells = <1>;
1434 power-domains = <&rpmhpd SC7280_CX>;
1435 operating-points-v2 = <&qup_opp_table>;
1436 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1437 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1438 interconnect-names = "qup-core", "qup-config";
1439 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1440 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1441 dma-names = "tx", "rx";
1442 status = "disabled";
1445 uart6: serial@998000 {
1446 compatible = "qcom,geni-uart";
1447 reg = <0 0x00998000 0 0x4000>;
1448 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1452 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1453 power-domains = <&rpmhpd SC7280_CX>;
1454 operating-points-v2 = <&qup_opp_table>;
1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1456 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1457 interconnect-names = "qup-core", "qup-config";
1458 status = "disabled";
1462 compatible = "qcom,geni-i2c";
1463 reg = <0 0x0099c000 0 0x4000>;
1464 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_i2c7_data_clk>;
1468 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1469 #address-cells = <1>;
1471 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1472 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1473 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1474 interconnect-names = "qup-core", "qup-config",
1476 power-domains = <&rpmhpd SC7280_CX>;
1477 required-opps = <&rpmhpd_opp_low_svs>;
1478 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1479 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1480 dma-names = "tx", "rx";
1481 status = "disabled";
1485 compatible = "qcom,geni-spi";
1486 reg = <0 0x0099c000 0 0x4000>;
1487 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1489 pinctrl-names = "default";
1490 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1491 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1492 #address-cells = <1>;
1494 power-domains = <&rpmhpd SC7280_CX>;
1495 operating-points-v2 = <&qup_opp_table>;
1496 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1497 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1498 interconnect-names = "qup-core", "qup-config";
1499 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1500 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1501 dma-names = "tx", "rx";
1502 status = "disabled";
1505 uart7: serial@99c000 {
1506 compatible = "qcom,geni-uart";
1507 reg = <0 0x0099c000 0 0x4000>;
1508 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1510 pinctrl-names = "default";
1511 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1512 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1513 power-domains = <&rpmhpd SC7280_CX>;
1514 operating-points-v2 = <&qup_opp_table>;
1515 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1516 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1517 interconnect-names = "qup-core", "qup-config";
1518 status = "disabled";
1522 gpi_dma1: dma-controller@a00000 {
1524 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1525 reg = <0 0x00a00000 0 0x60000>;
1526 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1538 dma-channels = <12>;
1539 dma-channel-mask = <0x1e>;
1540 iommus = <&apps_smmu 0x56 0x0>;
1541 status = "disabled";
1544 qupv3_id_1: geniqup@ac0000 {
1545 compatible = "qcom,geni-se-qup";
1546 reg = <0 0x00ac0000 0 0x2000>;
1547 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1548 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1549 clock-names = "m-ahb", "s-ahb";
1550 #address-cells = <2>;
1553 iommus = <&apps_smmu 0x43 0x0>;
1554 status = "disabled";
1557 compatible = "qcom,geni-i2c";
1558 reg = <0 0x00a80000 0 0x4000>;
1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1561 pinctrl-names = "default";
1562 pinctrl-0 = <&qup_i2c8_data_clk>;
1563 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1564 #address-cells = <1>;
1566 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1567 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1568 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1569 interconnect-names = "qup-core", "qup-config",
1571 power-domains = <&rpmhpd SC7280_CX>;
1572 required-opps = <&rpmhpd_opp_low_svs>;
1573 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1574 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1575 dma-names = "tx", "rx";
1576 status = "disabled";
1580 compatible = "qcom,geni-spi";
1581 reg = <0 0x00a80000 0 0x4000>;
1582 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1584 pinctrl-names = "default";
1585 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1586 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1587 #address-cells = <1>;
1589 power-domains = <&rpmhpd SC7280_CX>;
1590 operating-points-v2 = <&qup_opp_table>;
1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1592 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1593 interconnect-names = "qup-core", "qup-config";
1594 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1595 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1596 dma-names = "tx", "rx";
1597 status = "disabled";
1600 uart8: serial@a80000 {
1601 compatible = "qcom,geni-uart";
1602 reg = <0 0x00a80000 0 0x4000>;
1603 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1605 pinctrl-names = "default";
1606 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1607 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1608 power-domains = <&rpmhpd SC7280_CX>;
1609 operating-points-v2 = <&qup_opp_table>;
1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1611 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1612 interconnect-names = "qup-core", "qup-config";
1613 status = "disabled";
1617 compatible = "qcom,geni-i2c";
1618 reg = <0 0x00a84000 0 0x4000>;
1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c9_data_clk>;
1623 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1624 #address-cells = <1>;
1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1627 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1628 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1629 interconnect-names = "qup-core", "qup-config",
1631 power-domains = <&rpmhpd SC7280_CX>;
1632 required-opps = <&rpmhpd_opp_low_svs>;
1633 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1634 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1635 dma-names = "tx", "rx";
1636 status = "disabled";
1640 compatible = "qcom,geni-spi";
1641 reg = <0 0x00a84000 0 0x4000>;
1642 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1644 pinctrl-names = "default";
1645 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1646 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1647 #address-cells = <1>;
1649 power-domains = <&rpmhpd SC7280_CX>;
1650 operating-points-v2 = <&qup_opp_table>;
1651 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1652 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1653 interconnect-names = "qup-core", "qup-config";
1654 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1655 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1656 dma-names = "tx", "rx";
1657 status = "disabled";
1660 uart9: serial@a84000 {
1661 compatible = "qcom,geni-uart";
1662 reg = <0 0x00a84000 0 0x4000>;
1663 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1667 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1668 power-domains = <&rpmhpd SC7280_CX>;
1669 operating-points-v2 = <&qup_opp_table>;
1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1671 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1672 interconnect-names = "qup-core", "qup-config";
1673 status = "disabled";
1677 compatible = "qcom,geni-i2c";
1678 reg = <0 0x00a88000 0 0x4000>;
1679 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1681 pinctrl-names = "default";
1682 pinctrl-0 = <&qup_i2c10_data_clk>;
1683 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1684 #address-cells = <1>;
1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1687 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1688 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1689 interconnect-names = "qup-core", "qup-config",
1691 power-domains = <&rpmhpd SC7280_CX>;
1692 required-opps = <&rpmhpd_opp_low_svs>;
1693 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1694 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1695 dma-names = "tx", "rx";
1696 status = "disabled";
1700 compatible = "qcom,geni-spi";
1701 reg = <0 0x00a88000 0 0x4000>;
1702 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1704 pinctrl-names = "default";
1705 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1706 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1707 #address-cells = <1>;
1709 power-domains = <&rpmhpd SC7280_CX>;
1710 operating-points-v2 = <&qup_opp_table>;
1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1712 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1713 interconnect-names = "qup-core", "qup-config";
1714 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1715 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1716 dma-names = "tx", "rx";
1717 status = "disabled";
1720 uart10: serial@a88000 {
1721 compatible = "qcom,geni-uart";
1722 reg = <0 0x00a88000 0 0x4000>;
1723 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1725 pinctrl-names = "default";
1726 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1727 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1728 power-domains = <&rpmhpd SC7280_CX>;
1729 operating-points-v2 = <&qup_opp_table>;
1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1731 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1732 interconnect-names = "qup-core", "qup-config";
1733 status = "disabled";
1737 compatible = "qcom,geni-i2c";
1738 reg = <0 0x00a8c000 0 0x4000>;
1739 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1741 pinctrl-names = "default";
1742 pinctrl-0 = <&qup_i2c11_data_clk>;
1743 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1744 #address-cells = <1>;
1746 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1747 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1748 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1749 interconnect-names = "qup-core", "qup-config",
1751 power-domains = <&rpmhpd SC7280_CX>;
1752 required-opps = <&rpmhpd_opp_low_svs>;
1753 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1754 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1755 dma-names = "tx", "rx";
1756 status = "disabled";
1760 compatible = "qcom,geni-spi";
1761 reg = <0 0x00a8c000 0 0x4000>;
1762 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1764 pinctrl-names = "default";
1765 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1766 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1767 #address-cells = <1>;
1769 power-domains = <&rpmhpd SC7280_CX>;
1770 operating-points-v2 = <&qup_opp_table>;
1771 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1772 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1773 interconnect-names = "qup-core", "qup-config";
1774 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1775 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1776 dma-names = "tx", "rx";
1777 status = "disabled";
1780 uart11: serial@a8c000 {
1781 compatible = "qcom,geni-uart";
1782 reg = <0 0x00a8c000 0 0x4000>;
1783 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1785 pinctrl-names = "default";
1786 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1787 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1788 power-domains = <&rpmhpd SC7280_CX>;
1789 operating-points-v2 = <&qup_opp_table>;
1790 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1791 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1792 interconnect-names = "qup-core", "qup-config";
1793 status = "disabled";
1797 compatible = "qcom,geni-i2c";
1798 reg = <0 0x00a90000 0 0x4000>;
1799 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1801 pinctrl-names = "default";
1802 pinctrl-0 = <&qup_i2c12_data_clk>;
1803 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1804 #address-cells = <1>;
1806 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1807 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1808 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1809 interconnect-names = "qup-core", "qup-config",
1811 power-domains = <&rpmhpd SC7280_CX>;
1812 required-opps = <&rpmhpd_opp_low_svs>;
1813 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1814 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1815 dma-names = "tx", "rx";
1816 status = "disabled";
1820 compatible = "qcom,geni-spi";
1821 reg = <0 0x00a90000 0 0x4000>;
1822 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1824 pinctrl-names = "default";
1825 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1826 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1827 #address-cells = <1>;
1829 power-domains = <&rpmhpd SC7280_CX>;
1830 operating-points-v2 = <&qup_opp_table>;
1831 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1832 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1833 interconnect-names = "qup-core", "qup-config";
1834 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1835 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1836 dma-names = "tx", "rx";
1837 status = "disabled";
1840 uart12: serial@a90000 {
1841 compatible = "qcom,geni-uart";
1842 reg = <0 0x00a90000 0 0x4000>;
1843 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1845 pinctrl-names = "default";
1846 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1847 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1848 power-domains = <&rpmhpd SC7280_CX>;
1849 operating-points-v2 = <&qup_opp_table>;
1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1851 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1852 interconnect-names = "qup-core", "qup-config";
1853 status = "disabled";
1857 compatible = "qcom,geni-i2c";
1858 reg = <0 0x00a94000 0 0x4000>;
1859 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1861 pinctrl-names = "default";
1862 pinctrl-0 = <&qup_i2c13_data_clk>;
1863 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1864 #address-cells = <1>;
1866 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1867 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1868 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1869 interconnect-names = "qup-core", "qup-config",
1871 power-domains = <&rpmhpd SC7280_CX>;
1872 required-opps = <&rpmhpd_opp_low_svs>;
1873 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1874 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1875 dma-names = "tx", "rx";
1876 status = "disabled";
1880 compatible = "qcom,geni-spi";
1881 reg = <0 0x00a94000 0 0x4000>;
1882 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1884 pinctrl-names = "default";
1885 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1886 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1887 #address-cells = <1>;
1889 power-domains = <&rpmhpd SC7280_CX>;
1890 operating-points-v2 = <&qup_opp_table>;
1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1892 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1893 interconnect-names = "qup-core", "qup-config";
1894 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1895 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1896 dma-names = "tx", "rx";
1897 status = "disabled";
1900 uart13: serial@a94000 {
1901 compatible = "qcom,geni-uart";
1902 reg = <0 0x00a94000 0 0x4000>;
1903 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1905 pinctrl-names = "default";
1906 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1907 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1908 power-domains = <&rpmhpd SC7280_CX>;
1909 operating-points-v2 = <&qup_opp_table>;
1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1912 interconnect-names = "qup-core", "qup-config";
1913 status = "disabled";
1917 compatible = "qcom,geni-i2c";
1918 reg = <0 0x00a98000 0 0x4000>;
1919 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1921 pinctrl-names = "default";
1922 pinctrl-0 = <&qup_i2c14_data_clk>;
1923 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1924 #address-cells = <1>;
1926 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1927 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1928 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1929 interconnect-names = "qup-core", "qup-config",
1931 power-domains = <&rpmhpd SC7280_CX>;
1932 required-opps = <&rpmhpd_opp_low_svs>;
1933 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1934 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1935 dma-names = "tx", "rx";
1936 status = "disabled";
1940 compatible = "qcom,geni-spi";
1941 reg = <0 0x00a98000 0 0x4000>;
1942 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1944 pinctrl-names = "default";
1945 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1946 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1947 #address-cells = <1>;
1949 power-domains = <&rpmhpd SC7280_CX>;
1950 operating-points-v2 = <&qup_opp_table>;
1951 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1952 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1953 interconnect-names = "qup-core", "qup-config";
1954 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1955 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1956 dma-names = "tx", "rx";
1957 status = "disabled";
1960 uart14: serial@a98000 {
1961 compatible = "qcom,geni-uart";
1962 reg = <0 0x00a98000 0 0x4000>;
1963 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1965 pinctrl-names = "default";
1966 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1967 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1968 power-domains = <&rpmhpd SC7280_CX>;
1969 operating-points-v2 = <&qup_opp_table>;
1970 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1971 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1972 interconnect-names = "qup-core", "qup-config";
1973 status = "disabled";
1977 compatible = "qcom,geni-i2c";
1978 reg = <0 0x00a9c000 0 0x4000>;
1979 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1981 pinctrl-names = "default";
1982 pinctrl-0 = <&qup_i2c15_data_clk>;
1983 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1984 #address-cells = <1>;
1986 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1987 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1988 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1989 interconnect-names = "qup-core", "qup-config",
1991 power-domains = <&rpmhpd SC7280_CX>;
1992 required-opps = <&rpmhpd_opp_low_svs>;
1993 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1994 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1995 dma-names = "tx", "rx";
1996 status = "disabled";
2000 compatible = "qcom,geni-spi";
2001 reg = <0 0x00a9c000 0 0x4000>;
2002 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2004 pinctrl-names = "default";
2005 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2006 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2007 #address-cells = <1>;
2009 power-domains = <&rpmhpd SC7280_CX>;
2010 operating-points-v2 = <&qup_opp_table>;
2011 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2012 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2013 interconnect-names = "qup-core", "qup-config";
2014 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2015 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2016 dma-names = "tx", "rx";
2017 status = "disabled";
2020 uart15: serial@a9c000 {
2021 compatible = "qcom,geni-uart";
2022 reg = <0 0x00a9c000 0 0x4000>;
2023 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2025 pinctrl-names = "default";
2026 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
2027 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
2028 power-domains = <&rpmhpd SC7280_CX>;
2029 operating-points-v2 = <&qup_opp_table>;
2030 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
2031 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2032 interconnect-names = "qup-core", "qup-config";
2033 status = "disabled";
2037 cnoc2: interconnect@1500000 {
2038 reg = <0 0x01500000 0 0x1000>;
2039 compatible = "qcom,sc7280-cnoc2";
2040 #interconnect-cells = <2>;
2041 qcom,bcm-voters = <&apps_bcm_voter>;
2044 cnoc3: interconnect@1502000 {
2045 reg = <0 0x01502000 0 0x1000>;
2046 compatible = "qcom,sc7280-cnoc3";
2047 #interconnect-cells = <2>;
2048 qcom,bcm-voters = <&apps_bcm_voter>;
2051 mc_virt: interconnect@1580000 {
2052 reg = <0 0x01580000 0 0x4>;
2053 compatible = "qcom,sc7280-mc-virt";
2054 #interconnect-cells = <2>;
2055 qcom,bcm-voters = <&apps_bcm_voter>;
2058 system_noc: interconnect@1680000 {
2059 reg = <0 0x01680000 0 0x15480>;
2060 compatible = "qcom,sc7280-system-noc";
2061 #interconnect-cells = <2>;
2062 qcom,bcm-voters = <&apps_bcm_voter>;
2065 aggre1_noc: interconnect@16e0000 {
2066 compatible = "qcom,sc7280-aggre1-noc";
2067 reg = <0 0x016e0000 0 0x1c080>;
2068 #interconnect-cells = <2>;
2069 qcom,bcm-voters = <&apps_bcm_voter>;
2072 aggre2_noc: interconnect@1700000 {
2073 reg = <0 0x01700000 0 0x2b080>;
2074 compatible = "qcom,sc7280-aggre2-noc";
2075 #interconnect-cells = <2>;
2076 qcom,bcm-voters = <&apps_bcm_voter>;
2079 mmss_noc: interconnect@1740000 {
2080 reg = <0 0x01740000 0 0x1e080>;
2081 compatible = "qcom,sc7280-mmss-noc";
2082 #interconnect-cells = <2>;
2083 qcom,bcm-voters = <&apps_bcm_voter>;
2086 wifi: wifi@17a10040 {
2087 compatible = "qcom,wcn6750-wifi";
2088 reg = <0 0x17a10040 0 0x0>;
2089 iommus = <&apps_smmu 0x1c00 0x1>;
2090 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
2091 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
2092 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
2093 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
2094 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
2095 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
2096 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
2097 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
2098 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
2099 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
2100 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
2101 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
2102 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
2103 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
2104 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
2105 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
2106 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
2107 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
2108 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
2109 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
2110 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
2111 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
2112 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
2113 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
2114 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
2115 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
2116 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
2117 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
2118 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
2119 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2120 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2121 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2122 qcom,rproc = <&remoteproc_wpss>;
2123 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2124 status = "disabled";
2125 qcom,smem-states = <&wlan_smp2p_out 0>;
2126 qcom,smem-state-names = "wlan-smp2p-out";
2129 pcie1: pci@1c08000 {
2130 compatible = "qcom,pcie-sc7280";
2131 reg = <0 0x01c08000 0 0x3000>,
2132 <0 0x40000000 0 0xf1d>,
2133 <0 0x40000f20 0 0xa8>,
2134 <0 0x40001000 0 0x1000>,
2135 <0 0x40100000 0 0x100000>;
2137 reg-names = "parf", "dbi", "elbi", "atu", "config";
2138 device_type = "pci";
2139 linux,pci-domain = <1>;
2140 bus-range = <0x00 0xff>;
2143 #address-cells = <3>;
2146 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2147 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2149 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2150 interrupt-names = "msi";
2151 #interrupt-cells = <1>;
2152 interrupt-map-mask = <0 0 0 0x7>;
2153 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2154 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2155 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2156 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2158 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2159 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2161 <&rpmhcc RPMH_CXO_CLK>,
2162 <&gcc GCC_PCIE_1_AUX_CLK>,
2163 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2164 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2165 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2166 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2167 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2168 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
2169 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2170 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
2172 clock-names = "pipe",
2186 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2187 assigned-clock-rates = <19200000>;
2189 resets = <&gcc GCC_PCIE_1_BCR>;
2190 reset-names = "pci";
2192 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2194 phys = <&pcie1_phy>;
2195 phy-names = "pciephy";
2197 pinctrl-names = "default";
2198 pinctrl-0 = <&pcie1_clkreq_n>;
2202 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2203 <0x100 &apps_smmu 0x1c81 0x1>;
2205 status = "disabled";
2208 pcie1_phy: phy@1c0e000 {
2209 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2210 reg = <0 0x01c0e000 0 0x1000>;
2211 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2212 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2213 <&gcc GCC_PCIE_CLKREF_EN>,
2214 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
2215 <&gcc GCC_PCIE_1_PIPE_CLK>;
2216 clock-names = "aux",
2222 clock-output-names = "pcie_1_pipe_clk";
2227 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2228 reset-names = "phy";
2230 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2231 assigned-clock-rates = <100000000>;
2233 status = "disabled";
2237 compatible = "qcom,sc7280-ipa";
2239 iommus = <&apps_smmu 0x480 0x0>,
2240 <&apps_smmu 0x482 0x0>;
2241 reg = <0 0x01e40000 0 0x8000>,
2242 <0 0x01e50000 0 0x4ad0>,
2243 <0 0x01e04000 0 0x23000>;
2244 reg-names = "ipa-reg",
2248 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2249 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2250 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2251 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2252 interrupt-names = "ipa",
2257 clocks = <&rpmhcc RPMH_IPA_CLK>;
2258 clock-names = "core";
2260 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2262 interconnect-names = "memory",
2265 qcom,qmp = <&aoss_qmp>;
2267 qcom,smem-states = <&ipa_smp2p_out 0>,
2269 qcom,smem-state-names = "ipa-clock-enabled-valid",
2270 "ipa-clock-enabled";
2272 status = "disabled";
2275 tcsr_mutex: hwlock@1f40000 {
2276 compatible = "qcom,tcsr-mutex";
2277 reg = <0 0x01f40000 0 0x20000>;
2278 #hwlock-cells = <1>;
2281 tcsr_1: syscon@1f60000 {
2282 compatible = "qcom,sc7280-tcsr", "syscon";
2283 reg = <0 0x01f60000 0 0x20000>;
2286 tcsr_2: syscon@1fc0000 {
2287 compatible = "qcom,sc7280-tcsr", "syscon";
2288 reg = <0 0x01fc0000 0 0x30000>;
2291 lpasscc: lpasscc@3000000 {
2292 compatible = "qcom,sc7280-lpasscc";
2293 reg = <0 0x03000000 0 0x40>,
2294 <0 0x03c04000 0 0x4>;
2295 reg-names = "qdsp6ss", "top_cc";
2296 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2297 clock-names = "iface";
2299 status = "reserved"; /* Owned by ADSP firmware */
2302 lpass_rx_macro: codec@3200000 {
2303 compatible = "qcom,sc7280-lpass-rx-macro";
2304 reg = <0 0x03200000 0 0x1000>;
2306 pinctrl-names = "default";
2307 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2309 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2310 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2312 clock-names = "mclk", "npl", "fsgen";
2314 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2315 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2316 power-domain-names = "macro", "dcodec";
2319 #sound-dai-cells = <1>;
2321 status = "disabled";
2324 swr0: soundwire@3210000 {
2325 compatible = "qcom,soundwire-v1.6.0";
2326 reg = <0 0x03210000 0 0x2000>;
2328 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2329 clocks = <&lpass_rx_macro>;
2330 clock-names = "iface";
2332 qcom,din-ports = <0>;
2333 qcom,dout-ports = <5>;
2335 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2336 reset-names = "swr_audio_cgcr";
2338 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2339 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2340 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2341 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2342 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2343 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2344 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2345 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2346 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2348 #sound-dai-cells = <1>;
2349 #address-cells = <2>;
2352 status = "disabled";
2355 lpass_tx_macro: codec@3220000 {
2356 compatible = "qcom,sc7280-lpass-tx-macro";
2357 reg = <0 0x03220000 0 0x1000>;
2359 pinctrl-names = "default";
2360 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2362 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2363 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2365 clock-names = "mclk", "npl", "fsgen";
2367 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2368 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2369 power-domain-names = "macro", "dcodec";
2372 #sound-dai-cells = <1>;
2374 status = "disabled";
2377 swr1: soundwire@3230000 {
2378 compatible = "qcom,soundwire-v1.6.0";
2379 reg = <0 0x03230000 0 0x2000>;
2381 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2382 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
2383 clocks = <&lpass_tx_macro>;
2384 clock-names = "iface";
2386 qcom,din-ports = <3>;
2387 qcom,dout-ports = <0>;
2389 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2390 reset-names = "swr_audio_cgcr";
2392 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2393 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2394 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2395 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2396 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2397 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2398 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2399 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2400 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2402 #sound-dai-cells = <1>;
2403 #address-cells = <2>;
2406 status = "disabled";
2409 lpass_audiocc: clock-controller@3300000 {
2410 compatible = "qcom,sc7280-lpassaudiocc";
2411 reg = <0 0x03300000 0 0x30000>,
2412 <0 0x032a9000 0 0x1000>;
2413 clocks = <&rpmhcc RPMH_CXO_CLK>,
2414 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2415 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2416 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2418 #power-domain-cells = <1>;
2422 lpass_va_macro: codec@3370000 {
2423 compatible = "qcom,sc7280-lpass-va-macro";
2424 reg = <0 0x03370000 0 0x1000>;
2426 pinctrl-names = "default";
2427 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2429 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
2430 clock-names = "mclk";
2432 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2433 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2434 power-domain-names = "macro", "dcodec";
2437 #sound-dai-cells = <1>;
2439 status = "disabled";
2442 lpass_aon: clock-controller@3380000 {
2443 compatible = "qcom,sc7280-lpassaoncc";
2444 reg = <0 0x03380000 0 0x30000>;
2445 clocks = <&rpmhcc RPMH_CXO_CLK>,
2446 <&rpmhcc RPMH_CXO_CLK_A>,
2447 <&lpass_core LPASS_CORE_CC_CORE_CLK>;
2448 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2450 #power-domain-cells = <1>;
2451 status = "reserved"; /* Owned by ADSP firmware */
2454 lpass_core: clock-controller@3900000 {
2455 compatible = "qcom,sc7280-lpasscorecc";
2456 reg = <0 0x03900000 0 0x50000>;
2457 clocks = <&rpmhcc RPMH_CXO_CLK>;
2458 clock-names = "bi_tcxo";
2459 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2461 #power-domain-cells = <1>;
2462 status = "reserved"; /* Owned by ADSP firmware */
2465 lpass_cpu: audio@3987000 {
2466 compatible = "qcom,sc7280-lpass-cpu";
2468 reg = <0 0x03987000 0 0x68000>,
2469 <0 0x03b00000 0 0x29000>,
2470 <0 0x03260000 0 0xc000>,
2471 <0 0x03280000 0 0x29000>,
2472 <0 0x03340000 0 0x29000>,
2473 <0 0x0336c000 0 0x3000>;
2474 reg-names = "lpass-hdmiif",
2476 "lpass-rxtx-cdc-dma-lpm",
2479 "lpass-va-cdc-dma-lpm";
2481 iommus = <&apps_smmu 0x1820 0>,
2482 <&apps_smmu 0x1821 0>,
2483 <&apps_smmu 0x1832 0>;
2485 power-domains = <&rpmhpd SC7280_LCX>;
2486 power-domain-names = "lcx";
2487 required-opps = <&rpmhpd_opp_nom>;
2489 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
2490 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
2491 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
2492 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
2493 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
2494 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2495 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2496 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2497 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
2498 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
2499 clock-names = "aon_cc_audio_hm_h",
2500 "audio_cc_ext_mclk0",
2501 "core_cc_sysnoc_mport_core",
2502 "core_cc_ext_if0_ibit",
2503 "core_cc_ext_if1_ibit",
2504 "audio_cc_codec_mem",
2505 "audio_cc_codec_mem0",
2506 "audio_cc_codec_mem1",
2507 "audio_cc_codec_mem2",
2510 #sound-dai-cells = <1>;
2511 #address-cells = <1>;
2514 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2515 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2516 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
2517 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
2518 interrupt-names = "lpass-irq-lpaif",
2523 status = "disabled";
2526 lpass_hm: clock-controller@3c00000 {
2527 compatible = "qcom,sc7280-lpasshm";
2528 reg = <0 0x03c00000 0 0x28>;
2529 clocks = <&rpmhcc RPMH_CXO_CLK>;
2530 clock-names = "bi_tcxo";
2532 #power-domain-cells = <1>;
2533 status = "reserved"; /* Owned by ADSP firmware */
2536 lpass_ag_noc: interconnect@3c40000 {
2537 reg = <0 0x03c40000 0 0xf080>;
2538 compatible = "qcom,sc7280-lpass-ag-noc";
2539 #interconnect-cells = <2>;
2540 qcom,bcm-voters = <&apps_bcm_voter>;
2543 lpass_tlmm: pinctrl@33c0000 {
2544 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2545 reg = <0 0x033c0000 0x0 0x20000>,
2546 <0 0x03550000 0x0 0x10000>;
2549 gpio-ranges = <&lpass_tlmm 0 0 15>;
2551 lpass_dmic01_clk: dmic01-clk-state {
2553 function = "dmic1_clk";
2556 lpass_dmic01_data: dmic01-data-state {
2558 function = "dmic1_data";
2561 lpass_dmic23_clk: dmic23-clk-state {
2563 function = "dmic2_clk";
2566 lpass_dmic23_data: dmic23-data-state {
2568 function = "dmic2_data";
2571 lpass_rx_swr_clk: rx-swr-clk-state {
2573 function = "swr_rx_clk";
2576 lpass_rx_swr_data: rx-swr-data-state {
2577 pins = "gpio4", "gpio5";
2578 function = "swr_rx_data";
2581 lpass_tx_swr_clk: tx-swr-clk-state {
2583 function = "swr_tx_clk";
2586 lpass_tx_swr_data: tx-swr-data-state {
2587 pins = "gpio1", "gpio2", "gpio14";
2588 function = "swr_tx_data";
2593 compatible = "qcom,adreno-635.0", "qcom,adreno";
2594 reg = <0 0x03d00000 0 0x40000>,
2595 <0 0x03d9e000 0 0x1000>,
2596 <0 0x03d61000 0 0x800>;
2597 reg-names = "kgsl_3d0_reg_memory",
2600 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2601 iommus = <&adreno_smmu 0 0x401>;
2602 operating-points-v2 = <&gpu_opp_table>;
2604 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2605 interconnect-names = "gfx-mem";
2606 #cooling-cells = <2>;
2608 nvmem-cells = <&gpu_speed_bin>;
2609 nvmem-cell-names = "speed_bin";
2611 gpu_opp_table: opp-table {
2612 compatible = "operating-points-v2";
2615 opp-hz = /bits/ 64 <315000000>;
2616 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2617 opp-peak-kBps = <1804000>;
2618 opp-supported-hw = <0x03>;
2622 opp-hz = /bits/ 64 <450000000>;
2623 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2624 opp-peak-kBps = <4068000>;
2625 opp-supported-hw = <0x03>;
2628 /* Only applicable for SKUs which has 550Mhz as Fmax */
2630 opp-hz = /bits/ 64 <550000000>;
2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2632 opp-peak-kBps = <8368000>;
2633 opp-supported-hw = <0x01>;
2637 opp-hz = /bits/ 64 <550000000>;
2638 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2639 opp-peak-kBps = <6832000>;
2640 opp-supported-hw = <0x02>;
2644 opp-hz = /bits/ 64 <608000000>;
2645 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2646 opp-peak-kBps = <8368000>;
2647 opp-supported-hw = <0x02>;
2651 opp-hz = /bits/ 64 <700000000>;
2652 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2653 opp-peak-kBps = <8532000>;
2654 opp-supported-hw = <0x02>;
2658 opp-hz = /bits/ 64 <812000000>;
2659 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2660 opp-peak-kBps = <8532000>;
2661 opp-supported-hw = <0x02>;
2665 opp-hz = /bits/ 64 <840000000>;
2666 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2667 opp-peak-kBps = <8532000>;
2668 opp-supported-hw = <0x02>;
2672 opp-hz = /bits/ 64 <900000000>;
2673 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2674 opp-peak-kBps = <8532000>;
2675 opp-supported-hw = <0x02>;
2681 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2682 reg = <0 0x03d6a000 0 0x34000>,
2683 <0 0x3de0000 0 0x10000>,
2684 <0 0x0b290000 0 0x10000>;
2685 reg-names = "gmu", "rscc", "gmu_pdc";
2686 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2687 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2688 interrupt-names = "hfi", "gmu";
2689 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2690 <&gpucc GPU_CC_CXO_CLK>,
2691 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2692 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2693 <&gpucc GPU_CC_AHB_CLK>,
2694 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2695 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2696 clock-names = "gmu",
2703 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2704 <&gpucc GPU_CC_GX_GDSC>;
2705 power-domain-names = "cx",
2707 iommus = <&adreno_smmu 5 0x400>;
2708 operating-points-v2 = <&gmu_opp_table>;
2710 gmu_opp_table: opp-table {
2711 compatible = "operating-points-v2";
2714 opp-hz = /bits/ 64 <200000000>;
2715 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2720 gpucc: clock-controller@3d90000 {
2721 compatible = "qcom,sc7280-gpucc";
2722 reg = <0 0x03d90000 0 0x9000>;
2723 clocks = <&rpmhcc RPMH_CXO_CLK>,
2724 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2725 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2726 clock-names = "bi_tcxo",
2727 "gcc_gpu_gpll0_clk_src",
2728 "gcc_gpu_gpll0_div_clk_src";
2731 #power-domain-cells = <1>;
2735 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2736 reg = <0x0 0x0117f000 0x0 0x1000>,
2737 <0x0 0x01112000 0x0 0x6000>;
2740 adreno_smmu: iommu@3da0000 {
2741 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2742 "qcom,smmu-500", "arm,mmu-500";
2743 reg = <0 0x03da0000 0 0x20000>;
2745 #global-interrupts = <2>;
2746 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2747 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2748 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2749 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2750 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2751 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2752 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2753 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2754 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2755 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2756 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2757 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2759 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2760 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2761 <&gpucc GPU_CC_AHB_CLK>,
2762 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2763 <&gpucc GPU_CC_CX_GMU_CLK>,
2764 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2765 <&gpucc GPU_CC_HUB_AON_CLK>;
2766 clock-names = "gcc_gpu_memnoc_gfx_clk",
2767 "gcc_gpu_snoc_dvm_gfx_clk",
2769 "gpu_cc_hlos1_vote_gpu_smmu_clk",
2770 "gpu_cc_cx_gmu_clk",
2771 "gpu_cc_hub_cx_int_clk",
2772 "gpu_cc_hub_aon_clk";
2774 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2777 remoteproc_mpss: remoteproc@4080000 {
2778 compatible = "qcom,sc7280-mpss-pas";
2779 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2780 reg-names = "qdsp6", "rmb";
2782 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2783 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2784 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2785 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2786 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2787 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2788 interrupt-names = "wdog", "fatal", "ready", "handover",
2789 "stop-ack", "shutdown-ack";
2791 clocks = <&rpmhcc RPMH_CXO_CLK>;
2794 power-domains = <&rpmhpd SC7280_CX>,
2795 <&rpmhpd SC7280_MSS>;
2796 power-domain-names = "cx", "mss";
2798 memory-region = <&mpss_mem>;
2800 qcom,qmp = <&aoss_qmp>;
2802 qcom,smem-states = <&modem_smp2p_out 0>;
2803 qcom,smem-state-names = "stop";
2805 status = "disabled";
2808 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2809 IPCC_MPROC_SIGNAL_GLINK_QMP
2810 IRQ_TYPE_EDGE_RISING>;
2811 mboxes = <&ipcc IPCC_CLIENT_MPSS
2812 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2814 qcom,remote-pid = <1>;
2819 compatible = "arm,coresight-stm", "arm,primecell";
2820 reg = <0 0x06002000 0 0x1000>,
2821 <0 0x16280000 0 0x180000>;
2822 reg-names = "stm-base", "stm-stimulus-base";
2824 clocks = <&aoss_qmp>;
2825 clock-names = "apb_pclk";
2830 remote-endpoint = <&funnel0_in7>;
2837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2838 reg = <0 0x06041000 0 0x1000>;
2840 clocks = <&aoss_qmp>;
2841 clock-names = "apb_pclk";
2845 funnel0_out: endpoint {
2846 remote-endpoint = <&merge_funnel_in0>;
2852 #address-cells = <1>;
2857 funnel0_in7: endpoint {
2858 remote-endpoint = <&stm_out>;
2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2866 reg = <0 0x06042000 0 0x1000>;
2868 clocks = <&aoss_qmp>;
2869 clock-names = "apb_pclk";
2873 funnel1_out: endpoint {
2874 remote-endpoint = <&merge_funnel_in1>;
2880 #address-cells = <1>;
2885 funnel1_in4: endpoint {
2886 remote-endpoint = <&apss_merge_funnel_out>;
2893 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2894 reg = <0 0x06045000 0 0x1000>;
2896 clocks = <&aoss_qmp>;
2897 clock-names = "apb_pclk";
2901 merge_funnel_out: endpoint {
2902 remote-endpoint = <&swao_funnel_in>;
2908 #address-cells = <1>;
2913 merge_funnel_in0: endpoint {
2914 remote-endpoint = <&funnel0_out>;
2920 merge_funnel_in1: endpoint {
2921 remote-endpoint = <&funnel1_out>;
2927 replicator@6046000 {
2928 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2929 reg = <0 0x06046000 0 0x1000>;
2931 clocks = <&aoss_qmp>;
2932 clock-names = "apb_pclk";
2936 replicator_out: endpoint {
2937 remote-endpoint = <&etr_in>;
2944 replicator_in: endpoint {
2945 remote-endpoint = <&swao_replicator_out>;
2952 compatible = "arm,coresight-tmc", "arm,primecell";
2953 reg = <0 0x06048000 0 0x1000>;
2954 iommus = <&apps_smmu 0x04c0 0>;
2956 clocks = <&aoss_qmp>;
2957 clock-names = "apb_pclk";
2963 remote-endpoint = <&replicator_out>;
2970 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2971 reg = <0 0x06b04000 0 0x1000>;
2973 clocks = <&aoss_qmp>;
2974 clock-names = "apb_pclk";
2978 swao_funnel_out: endpoint {
2979 remote-endpoint = <&etf_in>;
2985 #address-cells = <1>;
2990 swao_funnel_in: endpoint {
2991 remote-endpoint = <&merge_funnel_out>;
2998 compatible = "arm,coresight-tmc", "arm,primecell";
2999 reg = <0 0x06b05000 0 0x1000>;
3001 clocks = <&aoss_qmp>;
3002 clock-names = "apb_pclk";
3007 remote-endpoint = <&swao_replicator_in>;
3015 remote-endpoint = <&swao_funnel_out>;
3021 replicator@6b06000 {
3022 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3023 reg = <0 0x06b06000 0 0x1000>;
3025 clocks = <&aoss_qmp>;
3026 clock-names = "apb_pclk";
3027 qcom,replicator-loses-context;
3031 swao_replicator_out: endpoint {
3032 remote-endpoint = <&replicator_in>;
3039 swao_replicator_in: endpoint {
3040 remote-endpoint = <&etf_out>;
3047 compatible = "arm,coresight-etm4x", "arm,primecell";
3048 reg = <0 0x07040000 0 0x1000>;
3052 clocks = <&aoss_qmp>;
3053 clock-names = "apb_pclk";
3054 arm,coresight-loses-context-with-cpu;
3059 etm0_out: endpoint {
3060 remote-endpoint = <&apss_funnel_in0>;
3067 compatible = "arm,coresight-etm4x", "arm,primecell";
3068 reg = <0 0x07140000 0 0x1000>;
3072 clocks = <&aoss_qmp>;
3073 clock-names = "apb_pclk";
3074 arm,coresight-loses-context-with-cpu;
3079 etm1_out: endpoint {
3080 remote-endpoint = <&apss_funnel_in1>;
3087 compatible = "arm,coresight-etm4x", "arm,primecell";
3088 reg = <0 0x07240000 0 0x1000>;
3092 clocks = <&aoss_qmp>;
3093 clock-names = "apb_pclk";
3094 arm,coresight-loses-context-with-cpu;
3099 etm2_out: endpoint {
3100 remote-endpoint = <&apss_funnel_in2>;
3107 compatible = "arm,coresight-etm4x", "arm,primecell";
3108 reg = <0 0x07340000 0 0x1000>;
3112 clocks = <&aoss_qmp>;
3113 clock-names = "apb_pclk";
3114 arm,coresight-loses-context-with-cpu;
3119 etm3_out: endpoint {
3120 remote-endpoint = <&apss_funnel_in3>;
3127 compatible = "arm,coresight-etm4x", "arm,primecell";
3128 reg = <0 0x07440000 0 0x1000>;
3132 clocks = <&aoss_qmp>;
3133 clock-names = "apb_pclk";
3134 arm,coresight-loses-context-with-cpu;
3139 etm4_out: endpoint {
3140 remote-endpoint = <&apss_funnel_in4>;
3147 compatible = "arm,coresight-etm4x", "arm,primecell";
3148 reg = <0 0x07540000 0 0x1000>;
3152 clocks = <&aoss_qmp>;
3153 clock-names = "apb_pclk";
3154 arm,coresight-loses-context-with-cpu;
3159 etm5_out: endpoint {
3160 remote-endpoint = <&apss_funnel_in5>;
3167 compatible = "arm,coresight-etm4x", "arm,primecell";
3168 reg = <0 0x07640000 0 0x1000>;
3172 clocks = <&aoss_qmp>;
3173 clock-names = "apb_pclk";
3174 arm,coresight-loses-context-with-cpu;
3179 etm6_out: endpoint {
3180 remote-endpoint = <&apss_funnel_in6>;
3187 compatible = "arm,coresight-etm4x", "arm,primecell";
3188 reg = <0 0x07740000 0 0x1000>;
3192 clocks = <&aoss_qmp>;
3193 clock-names = "apb_pclk";
3194 arm,coresight-loses-context-with-cpu;
3199 etm7_out: endpoint {
3200 remote-endpoint = <&apss_funnel_in7>;
3206 funnel@7800000 { /* APSS Funnel */
3207 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3208 reg = <0 0x07800000 0 0x1000>;
3210 clocks = <&aoss_qmp>;
3211 clock-names = "apb_pclk";
3215 apss_funnel_out: endpoint {
3216 remote-endpoint = <&apss_merge_funnel_in>;
3222 #address-cells = <1>;
3227 apss_funnel_in0: endpoint {
3228 remote-endpoint = <&etm0_out>;
3234 apss_funnel_in1: endpoint {
3235 remote-endpoint = <&etm1_out>;
3241 apss_funnel_in2: endpoint {
3242 remote-endpoint = <&etm2_out>;
3248 apss_funnel_in3: endpoint {
3249 remote-endpoint = <&etm3_out>;
3255 apss_funnel_in4: endpoint {
3256 remote-endpoint = <&etm4_out>;
3262 apss_funnel_in5: endpoint {
3263 remote-endpoint = <&etm5_out>;
3269 apss_funnel_in6: endpoint {
3270 remote-endpoint = <&etm6_out>;
3276 apss_funnel_in7: endpoint {
3277 remote-endpoint = <&etm7_out>;
3284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3285 reg = <0 0x07810000 0 0x1000>;
3287 clocks = <&aoss_qmp>;
3288 clock-names = "apb_pclk";
3292 apss_merge_funnel_out: endpoint {
3293 remote-endpoint = <&funnel1_in4>;
3300 apss_merge_funnel_in: endpoint {
3301 remote-endpoint = <&apss_funnel_out>;
3307 sdhc_2: mmc@8804000 {
3308 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3309 pinctrl-names = "default", "sleep";
3310 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3311 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3312 status = "disabled";
3314 reg = <0 0x08804000 0 0x1000>;
3316 iommus = <&apps_smmu 0x100 0x0>;
3317 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3318 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3319 interrupt-names = "hc_irq", "pwr_irq";
3321 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3322 <&gcc GCC_SDCC2_APPS_CLK>,
3323 <&rpmhcc RPMH_CXO_CLK>;
3324 clock-names = "iface", "core", "xo";
3325 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3326 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3327 interconnect-names = "sdhc-ddr","cpu-sdhc";
3328 power-domains = <&rpmhpd SC7280_CX>;
3329 operating-points-v2 = <&sdhc2_opp_table>;
3333 qcom,dll-config = <0x0007642c>;
3335 resets = <&gcc GCC_SDCC2_BCR>;
3337 sdhc2_opp_table: opp-table {
3338 compatible = "operating-points-v2";
3341 opp-hz = /bits/ 64 <100000000>;
3342 required-opps = <&rpmhpd_opp_low_svs>;
3343 opp-peak-kBps = <1800000 400000>;
3344 opp-avg-kBps = <100000 0>;
3348 opp-hz = /bits/ 64 <202000000>;
3349 required-opps = <&rpmhpd_opp_nom>;
3350 opp-peak-kBps = <5400000 1600000>;
3351 opp-avg-kBps = <200000 0>;
3356 usb_1_hsphy: phy@88e3000 {
3357 compatible = "qcom,sc7280-usb-hs-phy",
3358 "qcom,usb-snps-hs-7nm-phy";
3359 reg = <0 0x088e3000 0 0x400>;
3360 status = "disabled";
3363 clocks = <&rpmhcc RPMH_CXO_CLK>;
3364 clock-names = "ref";
3366 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3369 usb_2_hsphy: phy@88e4000 {
3370 compatible = "qcom,sc7280-usb-hs-phy",
3371 "qcom,usb-snps-hs-7nm-phy";
3372 reg = <0 0x088e4000 0 0x400>;
3373 status = "disabled";
3376 clocks = <&rpmhcc RPMH_CXO_CLK>;
3377 clock-names = "ref";
3379 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3382 usb_1_qmpphy: phy@88e8000 {
3383 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3384 reg = <0 0x088e8000 0 0x3000>;
3385 status = "disabled";
3387 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3388 <&rpmhcc RPMH_CXO_CLK>,
3389 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3390 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3391 clock-names = "aux",
3396 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3397 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3398 reset-names = "phy", "common";
3404 usb_2: usb@8cf8800 {
3405 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3406 reg = <0 0x08cf8800 0 0x400>;
3407 status = "disabled";
3408 #address-cells = <2>;
3413 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3414 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3415 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3416 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3417 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3418 clock-names = "cfg_noc",
3424 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3425 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3426 assigned-clock-rates = <19200000>, <200000000>;
3428 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3429 <&pdc 12 IRQ_TYPE_EDGE_RISING>,
3430 <&pdc 13 IRQ_TYPE_EDGE_RISING>;
3431 interrupt-names = "hs_phy_irq",
3435 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3436 required-opps = <&rpmhpd_opp_nom>;
3438 resets = <&gcc GCC_USB30_SEC_BCR>;
3440 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3442 interconnect-names = "usb-ddr", "apps-usb";
3444 usb_2_dwc3: usb@8c00000 {
3445 compatible = "snps,dwc3";
3446 reg = <0 0x08c00000 0 0xe000>;
3447 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3448 iommus = <&apps_smmu 0xa0 0x0>;
3449 snps,dis_u2_susphy_quirk;
3450 snps,dis_enblslpm_quirk;
3451 phys = <&usb_2_hsphy>;
3452 phy-names = "usb2-phy";
3453 maximum-speed = "high-speed";
3457 usb2_role_switch: endpoint {
3458 remote-endpoint = <&eud_ep>;
3465 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3466 reg = <0 0x088dc000 0 0x1000>;
3467 iommus = <&apps_smmu 0x20 0x0>;
3468 #address-cells = <1>;
3470 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3471 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3472 <&gcc GCC_QSPI_CORE_CLK>;
3473 clock-names = "iface", "core";
3474 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3475 &cnoc2 SLAVE_QSPI_0 0>;
3476 interconnect-names = "qspi-config";
3477 power-domains = <&rpmhpd SC7280_CX>;
3478 operating-points-v2 = <&qspi_opp_table>;
3479 status = "disabled";
3482 remoteproc_wpss: remoteproc@8a00000 {
3483 compatible = "qcom,sc7280-wpss-pil";
3484 reg = <0 0x08a00000 0 0x10000>;
3486 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3487 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3488 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3489 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3490 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3491 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3492 interrupt-names = "wdog", "fatal", "ready", "handover",
3493 "stop-ack", "shutdown-ack";
3495 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
3496 <&gcc GCC_WPSS_AHB_CLK>,
3497 <&gcc GCC_WPSS_RSCP_CLK>,
3498 <&rpmhcc RPMH_CXO_CLK>;
3499 clock-names = "ahb_bdg", "ahb",
3502 power-domains = <&rpmhpd SC7280_CX>,
3503 <&rpmhpd SC7280_MX>;
3504 power-domain-names = "cx", "mx";
3506 memory-region = <&wpss_mem>;
3508 qcom,qmp = <&aoss_qmp>;
3510 qcom,smem-states = <&wpss_smp2p_out 0>;
3511 qcom,smem-state-names = "stop";
3513 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
3514 <&pdc_reset PDC_WPSS_SYNC_RESET>;
3515 reset-names = "restart", "pdc_sync";
3517 qcom,halt-regs = <&tcsr_1 0x17000>;
3519 status = "disabled";
3522 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3523 IPCC_MPROC_SIGNAL_GLINK_QMP
3524 IRQ_TYPE_EDGE_RISING>;
3525 mboxes = <&ipcc IPCC_CLIENT_WPSS
3526 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3529 qcom,remote-pid = <13>;
3534 compatible = "qcom,sc7280-llcc-bwmon";
3535 reg = <0 0x09091000 0 0x1000>;
3537 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3539 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3541 operating-points-v2 = <&llcc_bwmon_opp_table>;
3543 llcc_bwmon_opp_table: opp-table {
3544 compatible = "operating-points-v2";
3547 opp-peak-kBps = <800000>;
3550 opp-peak-kBps = <1804000>;
3553 opp-peak-kBps = <2188000>;
3556 opp-peak-kBps = <3072000>;
3559 opp-peak-kBps = <4068000>;
3562 opp-peak-kBps = <6220000>;
3565 opp-peak-kBps = <6832000>;
3568 opp-peak-kBps = <8532000>;
3574 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3575 reg = <0 0x090b6400 0 0x600>;
3577 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3579 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3580 operating-points-v2 = <&cpu_bwmon_opp_table>;
3582 cpu_bwmon_opp_table: opp-table {
3583 compatible = "operating-points-v2";
3586 opp-peak-kBps = <2400000>;
3589 opp-peak-kBps = <4800000>;
3592 opp-peak-kBps = <7456000>;
3595 opp-peak-kBps = <9600000>;
3598 opp-peak-kBps = <12896000>;
3601 opp-peak-kBps = <14928000>;
3604 opp-peak-kBps = <17056000>;
3609 dc_noc: interconnect@90e0000 {
3610 reg = <0 0x090e0000 0 0x5080>;
3611 compatible = "qcom,sc7280-dc-noc";
3612 #interconnect-cells = <2>;
3613 qcom,bcm-voters = <&apps_bcm_voter>;
3616 gem_noc: interconnect@9100000 {
3617 reg = <0 0x09100000 0 0xe2200>;
3618 compatible = "qcom,sc7280-gem-noc";
3619 #interconnect-cells = <2>;
3620 qcom,bcm-voters = <&apps_bcm_voter>;
3623 system-cache-controller@9200000 {
3624 compatible = "qcom,sc7280-llcc";
3625 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3626 <0 0x09600000 0 0x58000>;
3627 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
3628 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3632 compatible = "qcom,sc7280-eud", "qcom,eud";
3633 reg = <0 0x88e0000 0 0x2000>,
3634 <0 0x88e2000 0 0x1000>;
3635 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3637 status = "disabled";
3640 #address-cells = <1>;
3646 remote-endpoint = <&usb2_role_switch>;
3652 nsp_noc: interconnect@a0c0000 {
3653 reg = <0 0x0a0c0000 0 0x10000>;
3654 compatible = "qcom,sc7280-nsp-noc";
3655 #interconnect-cells = <2>;
3656 qcom,bcm-voters = <&apps_bcm_voter>;
3659 usb_1: usb@a6f8800 {
3660 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3661 reg = <0 0x0a6f8800 0 0x400>;
3662 status = "disabled";
3663 #address-cells = <2>;
3668 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3669 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3670 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3671 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3672 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3673 clock-names = "cfg_noc",
3679 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3680 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3681 assigned-clock-rates = <19200000>, <200000000>;
3683 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3684 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
3685 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3686 <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
3687 interrupt-names = "hs_phy_irq",
3692 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3693 required-opps = <&rpmhpd_opp_nom>;
3695 resets = <&gcc GCC_USB30_PRIM_BCR>;
3697 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3699 interconnect-names = "usb-ddr", "apps-usb";
3703 usb_1_dwc3: usb@a600000 {
3704 compatible = "snps,dwc3";
3705 reg = <0 0x0a600000 0 0xe000>;
3706 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3707 iommus = <&apps_smmu 0xe0 0x0>;
3708 snps,dis_u2_susphy_quirk;
3709 snps,dis_enblslpm_quirk;
3710 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3711 phy-names = "usb2-phy", "usb3-phy";
3712 maximum-speed = "super-speed";
3716 venus: video-codec@aa00000 {
3717 compatible = "qcom,sc7280-venus";
3718 reg = <0 0x0aa00000 0 0xd0600>;
3719 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3721 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
3722 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
3723 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3724 <&videocc VIDEO_CC_MVS0_CORE_CLK>,
3725 <&videocc VIDEO_CC_MVS0_AXI_CLK>;
3726 clock-names = "core", "bus", "iface",
3727 "vcodec_core", "vcodec_bus";
3729 power-domains = <&videocc MVSC_GDSC>,
3730 <&videocc MVS0_GDSC>,
3731 <&rpmhpd SC7280_CX>;
3732 power-domain-names = "venus", "vcodec0", "cx";
3733 operating-points-v2 = <&venus_opp_table>;
3735 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3736 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3737 interconnect-names = "cpu-cfg", "video-mem";
3739 iommus = <&apps_smmu 0x2180 0x20>,
3740 <&apps_smmu 0x2184 0x20>;
3741 memory-region = <&video_mem>;
3744 compatible = "venus-decoder";
3748 compatible = "venus-encoder";
3752 iommus = <&apps_smmu 0x21a2 0x0>;
3755 venus_opp_table: opp-table {
3756 compatible = "operating-points-v2";
3759 opp-hz = /bits/ 64 <133330000>;
3760 required-opps = <&rpmhpd_opp_low_svs>;
3764 opp-hz = /bits/ 64 <240000000>;
3765 required-opps = <&rpmhpd_opp_svs>;
3769 opp-hz = /bits/ 64 <335000000>;
3770 required-opps = <&rpmhpd_opp_svs_l1>;
3774 opp-hz = /bits/ 64 <424000000>;
3775 required-opps = <&rpmhpd_opp_nom>;
3779 opp-hz = /bits/ 64 <460000048>;
3780 required-opps = <&rpmhpd_opp_turbo>;
3785 videocc: clock-controller@aaf0000 {
3786 compatible = "qcom,sc7280-videocc";
3787 reg = <0 0x0aaf0000 0 0x10000>;
3788 clocks = <&rpmhcc RPMH_CXO_CLK>,
3789 <&rpmhcc RPMH_CXO_CLK_A>;
3790 clock-names = "bi_tcxo", "bi_tcxo_ao";
3793 #power-domain-cells = <1>;
3796 camcc: clock-controller@ad00000 {
3797 compatible = "qcom,sc7280-camcc";
3798 reg = <0 0x0ad00000 0 0x10000>;
3799 clocks = <&rpmhcc RPMH_CXO_CLK>,
3800 <&rpmhcc RPMH_CXO_CLK_A>,
3802 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3805 #power-domain-cells = <1>;
3808 dispcc: clock-controller@af00000 {
3809 compatible = "qcom,sc7280-dispcc";
3810 reg = <0 0x0af00000 0 0x20000>;
3811 clocks = <&rpmhcc RPMH_CXO_CLK>,
3812 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3815 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3816 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3819 clock-names = "bi_tcxo",
3820 "gcc_disp_gpll0_clk",
3821 "dsi0_phy_pll_out_byteclk",
3822 "dsi0_phy_pll_out_dsiclk",
3823 "dp_phy_pll_link_clk",
3824 "dp_phy_pll_vco_div_clk",
3825 "edp_phy_pll_link_clk",
3826 "edp_phy_pll_vco_div_clk";
3829 #power-domain-cells = <1>;
3832 mdss: display-subsystem@ae00000 {
3833 compatible = "qcom,sc7280-mdss";
3834 reg = <0 0x0ae00000 0 0x1000>;
3837 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3839 clocks = <&gcc GCC_DISP_AHB_CLK>,
3840 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3841 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3842 clock-names = "iface",
3846 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3847 interrupt-controller;
3848 #interrupt-cells = <1>;
3850 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3851 interconnect-names = "mdp0-mem";
3853 iommus = <&apps_smmu 0x900 0x402>;
3855 #address-cells = <2>;
3859 status = "disabled";
3861 mdss_mdp: display-controller@ae01000 {
3862 compatible = "qcom,sc7280-dpu";
3863 reg = <0 0x0ae01000 0 0x8f030>,
3864 <0 0x0aeb0000 0 0x2008>;
3865 reg-names = "mdp", "vbif";
3867 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3868 <&gcc GCC_DISP_SF_AXI_CLK>,
3869 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3870 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3871 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3872 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3873 clock-names = "bus",
3879 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3880 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3881 assigned-clock-rates = <19200000>,
3883 operating-points-v2 = <&mdp_opp_table>;
3884 power-domains = <&rpmhpd SC7280_CX>;
3886 interrupt-parent = <&mdss>;
3890 #address-cells = <1>;
3895 dpu_intf1_out: endpoint {
3896 remote-endpoint = <&mdss_dsi0_in>;
3902 dpu_intf5_out: endpoint {
3903 remote-endpoint = <&edp_in>;
3909 dpu_intf0_out: endpoint {
3910 remote-endpoint = <&dp_in>;
3915 mdp_opp_table: opp-table {
3916 compatible = "operating-points-v2";
3919 opp-hz = /bits/ 64 <200000000>;
3920 required-opps = <&rpmhpd_opp_low_svs>;
3924 opp-hz = /bits/ 64 <300000000>;
3925 required-opps = <&rpmhpd_opp_svs>;
3929 opp-hz = /bits/ 64 <380000000>;
3930 required-opps = <&rpmhpd_opp_svs_l1>;
3934 opp-hz = /bits/ 64 <506666667>;
3935 required-opps = <&rpmhpd_opp_nom>;
3940 mdss_dsi: dsi@ae94000 {
3941 compatible = "qcom,sc7280-dsi-ctrl",
3942 "qcom,mdss-dsi-ctrl";
3943 reg = <0 0x0ae94000 0 0x400>;
3944 reg-names = "dsi_ctrl";
3946 interrupt-parent = <&mdss>;
3949 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3950 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3951 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3952 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3953 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3954 <&gcc GCC_DISP_HF_AXI_CLK>;
3955 clock-names = "byte",
3962 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3963 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
3965 operating-points-v2 = <&dsi_opp_table>;
3966 power-domains = <&rpmhpd SC7280_CX>;
3968 phys = <&mdss_dsi_phy>;
3970 #address-cells = <1>;
3973 status = "disabled";
3976 #address-cells = <1>;
3981 mdss_dsi0_in: endpoint {
3982 remote-endpoint = <&dpu_intf1_out>;
3988 mdss_dsi0_out: endpoint {
3993 dsi_opp_table: opp-table {
3994 compatible = "operating-points-v2";
3997 opp-hz = /bits/ 64 <187500000>;
3998 required-opps = <&rpmhpd_opp_low_svs>;
4002 opp-hz = /bits/ 64 <300000000>;
4003 required-opps = <&rpmhpd_opp_svs>;
4007 opp-hz = /bits/ 64 <358000000>;
4008 required-opps = <&rpmhpd_opp_svs_l1>;
4013 mdss_dsi_phy: phy@ae94400 {
4014 compatible = "qcom,sc7280-dsi-phy-7nm";
4015 reg = <0 0x0ae94400 0 0x200>,
4016 <0 0x0ae94600 0 0x280>,
4017 <0 0x0ae94900 0 0x280>;
4018 reg-names = "dsi_phy",
4025 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4026 <&rpmhcc RPMH_CXO_CLK>;
4027 clock-names = "iface", "ref";
4029 status = "disabled";
4032 mdss_edp: edp@aea0000 {
4033 compatible = "qcom,sc7280-edp";
4034 pinctrl-names = "default";
4035 pinctrl-0 = <&edp_hot_plug_det>;
4037 reg = <0 0x0aea0000 0 0x200>,
4038 <0 0x0aea0200 0 0x200>,
4039 <0 0x0aea0400 0 0xc00>,
4040 <0 0x0aea1000 0 0x400>;
4042 interrupt-parent = <&mdss>;
4045 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4046 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
4047 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
4048 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
4049 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
4050 clock-names = "core_iface",
4055 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4056 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
4057 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4059 phys = <&mdss_edp_phy>;
4062 operating-points-v2 = <&edp_opp_table>;
4063 power-domains = <&rpmhpd SC7280_CX>;
4065 status = "disabled";
4068 #address-cells = <1>;
4074 remote-endpoint = <&dpu_intf5_out>;
4080 mdss_edp_out: endpoint { };
4084 edp_opp_table: opp-table {
4085 compatible = "operating-points-v2";
4088 opp-hz = /bits/ 64 <160000000>;
4089 required-opps = <&rpmhpd_opp_low_svs>;
4093 opp-hz = /bits/ 64 <270000000>;
4094 required-opps = <&rpmhpd_opp_svs>;
4098 opp-hz = /bits/ 64 <540000000>;
4099 required-opps = <&rpmhpd_opp_nom>;
4103 opp-hz = /bits/ 64 <810000000>;
4104 required-opps = <&rpmhpd_opp_nom>;
4109 mdss_edp_phy: phy@aec2a00 {
4110 compatible = "qcom,sc7280-edp-phy";
4112 reg = <0 0x0aec2a00 0 0x19c>,
4113 <0 0x0aec2200 0 0xa0>,
4114 <0 0x0aec2600 0 0xa0>,
4115 <0 0x0aec2000 0 0x1c0>;
4117 clocks = <&rpmhcc RPMH_CXO_CLK>,
4118 <&gcc GCC_EDP_CLKREF_EN>;
4119 clock-names = "aux",
4125 status = "disabled";
4128 mdss_dp: displayport-controller@ae90000 {
4129 compatible = "qcom,sc7280-dp";
4131 reg = <0 0x0ae90000 0 0x200>,
4132 <0 0x0ae90200 0 0x200>,
4133 <0 0x0ae90400 0 0xc00>,
4134 <0 0x0ae91000 0 0x400>,
4135 <0 0x0ae91400 0 0x400>;
4137 interrupt-parent = <&mdss>;
4140 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4141 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4142 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4143 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4144 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4145 clock-names = "core_iface",
4150 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4151 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4152 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4153 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4154 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4157 operating-points-v2 = <&dp_opp_table>;
4158 power-domains = <&rpmhpd SC7280_CX>;
4160 #sound-dai-cells = <0>;
4162 status = "disabled";
4165 #address-cells = <1>;
4171 remote-endpoint = <&dpu_intf0_out>;
4177 mdss_dp_out: endpoint { };
4181 dp_opp_table: opp-table {
4182 compatible = "operating-points-v2";
4185 opp-hz = /bits/ 64 <160000000>;
4186 required-opps = <&rpmhpd_opp_low_svs>;
4190 opp-hz = /bits/ 64 <270000000>;
4191 required-opps = <&rpmhpd_opp_svs>;
4195 opp-hz = /bits/ 64 <540000000>;
4196 required-opps = <&rpmhpd_opp_svs_l1>;
4200 opp-hz = /bits/ 64 <810000000>;
4201 required-opps = <&rpmhpd_opp_nom>;
4207 pdc: interrupt-controller@b220000 {
4208 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4209 reg = <0 0x0b220000 0 0x30000>;
4210 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4211 <55 306 4>, <59 312 3>, <62 374 2>,
4212 <64 434 2>, <66 438 3>, <69 86 1>,
4213 <70 520 54>, <124 609 31>, <155 63 1>,
4215 #interrupt-cells = <2>;
4216 interrupt-parent = <&intc>;
4217 interrupt-controller;
4220 pdc_reset: reset-controller@b5e0000 {
4221 compatible = "qcom,sc7280-pdc-global";
4222 reg = <0 0x0b5e0000 0 0x20000>;
4224 status = "reserved"; /* Owned by firmware */
4227 tsens0: thermal-sensor@c263000 {
4228 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4229 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4230 <0 0x0c222000 0 0x1ff>; /* SROT */
4231 #qcom,sensors = <15>;
4232 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4234 interrupt-names = "uplow","critical";
4235 #thermal-sensor-cells = <1>;
4238 tsens1: thermal-sensor@c265000 {
4239 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4240 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4241 <0 0x0c223000 0 0x1ff>; /* SROT */
4242 #qcom,sensors = <12>;
4243 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4245 interrupt-names = "uplow","critical";
4246 #thermal-sensor-cells = <1>;
4249 aoss_reset: reset-controller@c2a0000 {
4250 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4251 reg = <0 0x0c2a0000 0 0x31000>;
4255 aoss_qmp: power-management@c300000 {
4256 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4257 reg = <0 0x0c300000 0 0x400>;
4258 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4259 IPCC_MPROC_SIGNAL_GLINK_QMP
4260 IRQ_TYPE_EDGE_RISING>;
4261 mboxes = <&ipcc IPCC_CLIENT_AOP
4262 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4268 compatible = "qcom,rpmh-stats";
4269 reg = <0 0x0c3f0000 0 0x400>;
4272 spmi_bus: spmi@c440000 {
4273 compatible = "qcom,spmi-pmic-arb";
4274 reg = <0 0x0c440000 0 0x1100>,
4275 <0 0x0c600000 0 0x2000000>,
4276 <0 0x0e600000 0 0x100000>,
4277 <0 0x0e700000 0 0xa0000>,
4278 <0 0x0c40a000 0 0x26000>;
4279 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4280 interrupt-names = "periph_irq";
4281 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4284 #address-cells = <2>;
4286 interrupt-controller;
4287 #interrupt-cells = <4>;
4290 tlmm: pinctrl@f100000 {
4291 compatible = "qcom,sc7280-pinctrl";
4292 reg = <0 0x0f100000 0 0x300000>;
4293 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4296 interrupt-controller;
4297 #interrupt-cells = <2>;
4298 gpio-ranges = <&tlmm 0 0 175>;
4299 wakeup-parent = <&pdc>;
4301 dp_hot_plug_det: dp-hot-plug-det-state {
4303 function = "dp_hot";
4306 edp_hot_plug_det: edp-hot-plug-det-state {
4308 function = "edp_hot";
4311 mi2s0_data0: mi2s0-data0-state {
4313 function = "mi2s0_data0";
4316 mi2s0_data1: mi2s0-data1-state {
4318 function = "mi2s0_data1";
4321 mi2s0_mclk: mi2s0-mclk-state {
4323 function = "pri_mi2s";
4326 mi2s0_sclk: mi2s0-sclk-state {
4328 function = "mi2s0_sck";
4331 mi2s0_ws: mi2s0-ws-state {
4333 function = "mi2s0_ws";
4336 mi2s1_data0: mi2s1-data0-state {
4338 function = "mi2s1_data0";
4341 mi2s1_sclk: mi2s1-sclk-state {
4343 function = "mi2s1_sck";
4346 mi2s1_ws: mi2s1-ws-state {
4348 function = "mi2s1_ws";
4351 pcie1_clkreq_n: pcie1-clkreq-n-state {
4353 function = "pcie1_clkreqn";
4356 qspi_clk: qspi-clk-state {
4358 function = "qspi_clk";
4361 qspi_cs0: qspi-cs0-state {
4363 function = "qspi_cs";
4366 qspi_cs1: qspi-cs1-state {
4368 function = "qspi_cs";
4371 qspi_data0: qspi-data0-state {
4373 function = "qspi_data";
4376 qspi_data1: qspi-data1-state {
4378 function = "qspi_data";
4381 qspi_data23: qspi-data23-state {
4382 pins = "gpio16", "gpio17";
4383 function = "qspi_data";
4386 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4387 pins = "gpio0", "gpio1";
4391 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4392 pins = "gpio4", "gpio5";
4396 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4397 pins = "gpio8", "gpio9";
4401 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4402 pins = "gpio12", "gpio13";
4406 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4407 pins = "gpio16", "gpio17";
4411 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4412 pins = "gpio20", "gpio21";
4416 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4417 pins = "gpio24", "gpio25";
4421 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4422 pins = "gpio28", "gpio29";
4426 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4427 pins = "gpio32", "gpio33";
4431 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4432 pins = "gpio36", "gpio37";
4436 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4437 pins = "gpio40", "gpio41";
4441 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4442 pins = "gpio44", "gpio45";
4446 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4447 pins = "gpio48", "gpio49";
4451 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4452 pins = "gpio52", "gpio53";
4456 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4457 pins = "gpio56", "gpio57";
4461 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4462 pins = "gpio60", "gpio61";
4466 qup_spi0_data_clk: qup-spi0-data-clk-state {
4467 pins = "gpio0", "gpio1", "gpio2";
4471 qup_spi0_cs: qup-spi0-cs-state {
4476 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4481 qup_spi1_data_clk: qup-spi1-data-clk-state {
4482 pins = "gpio4", "gpio5", "gpio6";
4486 qup_spi1_cs: qup-spi1-cs-state {
4491 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4496 qup_spi2_data_clk: qup-spi2-data-clk-state {
4497 pins = "gpio8", "gpio9", "gpio10";
4501 qup_spi2_cs: qup-spi2-cs-state {
4506 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4511 qup_spi3_data_clk: qup-spi3-data-clk-state {
4512 pins = "gpio12", "gpio13", "gpio14";
4516 qup_spi3_cs: qup-spi3-cs-state {
4521 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
4526 qup_spi4_data_clk: qup-spi4-data-clk-state {
4527 pins = "gpio16", "gpio17", "gpio18";
4531 qup_spi4_cs: qup-spi4-cs-state {
4536 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
4541 qup_spi5_data_clk: qup-spi5-data-clk-state {
4542 pins = "gpio20", "gpio21", "gpio22";
4546 qup_spi5_cs: qup-spi5-cs-state {
4551 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
4556 qup_spi6_data_clk: qup-spi6-data-clk-state {
4557 pins = "gpio24", "gpio25", "gpio26";
4561 qup_spi6_cs: qup-spi6-cs-state {
4566 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
4571 qup_spi7_data_clk: qup-spi7-data-clk-state {
4572 pins = "gpio28", "gpio29", "gpio30";
4576 qup_spi7_cs: qup-spi7-cs-state {
4581 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
4586 qup_spi8_data_clk: qup-spi8-data-clk-state {
4587 pins = "gpio32", "gpio33", "gpio34";
4591 qup_spi8_cs: qup-spi8-cs-state {
4596 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
4601 qup_spi9_data_clk: qup-spi9-data-clk-state {
4602 pins = "gpio36", "gpio37", "gpio38";
4606 qup_spi9_cs: qup-spi9-cs-state {
4611 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
4616 qup_spi10_data_clk: qup-spi10-data-clk-state {
4617 pins = "gpio40", "gpio41", "gpio42";
4621 qup_spi10_cs: qup-spi10-cs-state {
4626 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
4631 qup_spi11_data_clk: qup-spi11-data-clk-state {
4632 pins = "gpio44", "gpio45", "gpio46";
4636 qup_spi11_cs: qup-spi11-cs-state {
4641 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
4646 qup_spi12_data_clk: qup-spi12-data-clk-state {
4647 pins = "gpio48", "gpio49", "gpio50";
4651 qup_spi12_cs: qup-spi12-cs-state {
4656 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
4661 qup_spi13_data_clk: qup-spi13-data-clk-state {
4662 pins = "gpio52", "gpio53", "gpio54";
4666 qup_spi13_cs: qup-spi13-cs-state {
4671 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
4676 qup_spi14_data_clk: qup-spi14-data-clk-state {
4677 pins = "gpio56", "gpio57", "gpio58";
4681 qup_spi14_cs: qup-spi14-cs-state {
4686 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
4691 qup_spi15_data_clk: qup-spi15-data-clk-state {
4692 pins = "gpio60", "gpio61", "gpio62";
4696 qup_spi15_cs: qup-spi15-cs-state {
4701 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
4706 qup_uart0_cts: qup-uart0-cts-state {
4711 qup_uart0_rts: qup-uart0-rts-state {
4716 qup_uart0_tx: qup-uart0-tx-state {
4721 qup_uart0_rx: qup-uart0-rx-state {
4726 qup_uart1_cts: qup-uart1-cts-state {
4731 qup_uart1_rts: qup-uart1-rts-state {
4736 qup_uart1_tx: qup-uart1-tx-state {
4741 qup_uart1_rx: qup-uart1-rx-state {
4746 qup_uart2_cts: qup-uart2-cts-state {
4751 qup_uart2_rts: qup-uart2-rts-state {
4756 qup_uart2_tx: qup-uart2-tx-state {
4761 qup_uart2_rx: qup-uart2-rx-state {
4766 qup_uart3_cts: qup-uart3-cts-state {
4771 qup_uart3_rts: qup-uart3-rts-state {
4776 qup_uart3_tx: qup-uart3-tx-state {
4781 qup_uart3_rx: qup-uart3-rx-state {
4786 qup_uart4_cts: qup-uart4-cts-state {
4791 qup_uart4_rts: qup-uart4-rts-state {
4796 qup_uart4_tx: qup-uart4-tx-state {
4801 qup_uart4_rx: qup-uart4-rx-state {
4806 qup_uart5_cts: qup-uart5-cts-state {
4811 qup_uart5_rts: qup-uart5-rts-state {
4816 qup_uart5_tx: qup-uart5-tx-state {
4821 qup_uart5_rx: qup-uart5-rx-state {
4826 qup_uart6_cts: qup-uart6-cts-state {
4831 qup_uart6_rts: qup-uart6-rts-state {
4836 qup_uart6_tx: qup-uart6-tx-state {
4841 qup_uart6_rx: qup-uart6-rx-state {
4846 qup_uart7_cts: qup-uart7-cts-state {
4851 qup_uart7_rts: qup-uart7-rts-state {
4856 qup_uart7_tx: qup-uart7-tx-state {
4861 qup_uart7_rx: qup-uart7-rx-state {
4866 qup_uart8_cts: qup-uart8-cts-state {
4871 qup_uart8_rts: qup-uart8-rts-state {
4876 qup_uart8_tx: qup-uart8-tx-state {
4881 qup_uart8_rx: qup-uart8-rx-state {
4886 qup_uart9_cts: qup-uart9-cts-state {
4891 qup_uart9_rts: qup-uart9-rts-state {
4896 qup_uart9_tx: qup-uart9-tx-state {
4901 qup_uart9_rx: qup-uart9-rx-state {
4906 qup_uart10_cts: qup-uart10-cts-state {
4911 qup_uart10_rts: qup-uart10-rts-state {
4916 qup_uart10_tx: qup-uart10-tx-state {
4921 qup_uart10_rx: qup-uart10-rx-state {
4926 qup_uart11_cts: qup-uart11-cts-state {
4931 qup_uart11_rts: qup-uart11-rts-state {
4936 qup_uart11_tx: qup-uart11-tx-state {
4941 qup_uart11_rx: qup-uart11-rx-state {
4946 qup_uart12_cts: qup-uart12-cts-state {
4951 qup_uart12_rts: qup-uart12-rts-state {
4956 qup_uart12_tx: qup-uart12-tx-state {
4961 qup_uart12_rx: qup-uart12-rx-state {
4966 qup_uart13_cts: qup-uart13-cts-state {
4971 qup_uart13_rts: qup-uart13-rts-state {
4976 qup_uart13_tx: qup-uart13-tx-state {
4981 qup_uart13_rx: qup-uart13-rx-state {
4986 qup_uart14_cts: qup-uart14-cts-state {
4991 qup_uart14_rts: qup-uart14-rts-state {
4996 qup_uart14_tx: qup-uart14-tx-state {
5001 qup_uart14_rx: qup-uart14-rx-state {
5006 qup_uart15_cts: qup-uart15-cts-state {
5011 qup_uart15_rts: qup-uart15-rts-state {
5016 qup_uart15_tx: qup-uart15-tx-state {
5021 qup_uart15_rx: qup-uart15-rx-state {
5026 sdc1_clk: sdc1-clk-state {
5030 sdc1_cmd: sdc1-cmd-state {
5034 sdc1_data: sdc1-data-state {
5038 sdc1_rclk: sdc1-rclk-state {
5042 sdc1_clk_sleep: sdc1-clk-sleep-state {
5044 drive-strength = <2>;
5048 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5050 drive-strength = <2>;
5054 sdc1_data_sleep: sdc1-data-sleep-state {
5056 drive-strength = <2>;
5060 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5062 drive-strength = <2>;
5066 sdc2_clk: sdc2-clk-state {
5070 sdc2_cmd: sdc2-cmd-state {
5074 sdc2_data: sdc2-data-state {
5078 sdc2_clk_sleep: sdc2-clk-sleep-state {
5080 drive-strength = <2>;
5084 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5086 drive-strength = <2>;
5090 sdc2_data_sleep: sdc2-data-sleep-state {
5092 drive-strength = <2>;
5098 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5099 reg = <0 0x146a5000 0 0x6000>;
5101 #address-cells = <1>;
5104 ranges = <0 0 0x146a5000 0x6000>;
5107 compatible = "qcom,pil-reloc-info";
5108 reg = <0x594c 0xc8>;
5112 apps_smmu: iommu@15000000 {
5113 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5114 reg = <0 0x15000000 0 0x100000>;
5116 #global-interrupts = <1>;
5118 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5162 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5163 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5164 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5165 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5166 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5167 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5168 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5169 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5170 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5171 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5172 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5173 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5174 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5175 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5176 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5177 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5178 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5179 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5180 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5181 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5182 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5183 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5184 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5185 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5186 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5187 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5188 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5189 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5190 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5191 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5192 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5193 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5194 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5195 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5196 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5197 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5198 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
5201 intc: interrupt-controller@17a00000 {
5202 compatible = "arm,gic-v3";
5203 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5204 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
5206 #interrupt-cells = <3>;
5207 interrupt-controller;
5208 #address-cells = <2>;
5212 msi-controller@17a40000 {
5213 compatible = "arm,gic-v3-its";
5214 reg = <0 0x17a40000 0 0x20000>;
5217 status = "disabled";
5221 watchdog: watchdog@17c10000 {
5222 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5223 reg = <0 0x17c10000 0 0x1000>;
5224 clocks = <&sleep_clk>;
5225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5226 status = "reserved"; /* Owned by Gunyah hyp */
5230 #address-cells = <1>;
5232 ranges = <0 0 0 0x20000000>;
5233 compatible = "arm,armv7-timer-mem";
5234 reg = <0 0x17c20000 0 0x1000>;
5238 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5239 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5240 reg = <0x17c21000 0x1000>,
5241 <0x17c22000 0x1000>;
5246 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5247 reg = <0x17c23000 0x1000>;
5248 status = "disabled";
5253 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5254 reg = <0x17c25000 0x1000>;
5255 status = "disabled";
5260 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5261 reg = <0x17c27000 0x1000>;
5262 status = "disabled";
5267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5268 reg = <0x17c29000 0x1000>;
5269 status = "disabled";
5274 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5275 reg = <0x17c2b000 0x1000>;
5276 status = "disabled";
5281 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5282 reg = <0x17c2d000 0x1000>;
5283 status = "disabled";
5287 apps_rsc: rsc@18200000 {
5288 compatible = "qcom,rpmh-rsc";
5289 reg = <0 0x18200000 0 0x10000>,
5290 <0 0x18210000 0 0x10000>,
5291 <0 0x18220000 0 0x10000>;
5292 reg-names = "drv-0", "drv-1", "drv-2";
5293 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5294 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5295 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5296 qcom,tcs-offset = <0xd00>;
5298 qcom,tcs-config = <ACTIVE_TCS 2>,
5302 power-domains = <&CLUSTER_PD>;
5304 apps_bcm_voter: bcm-voter {
5305 compatible = "qcom,bcm-voter";
5308 rpmhpd: power-controller {
5309 compatible = "qcom,sc7280-rpmhpd";
5310 #power-domain-cells = <1>;
5311 operating-points-v2 = <&rpmhpd_opp_table>;
5313 rpmhpd_opp_table: opp-table {
5314 compatible = "operating-points-v2";
5316 rpmhpd_opp_ret: opp1 {
5317 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5320 rpmhpd_opp_low_svs: opp2 {
5321 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5324 rpmhpd_opp_svs: opp3 {
5325 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5328 rpmhpd_opp_svs_l1: opp4 {
5329 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5332 rpmhpd_opp_svs_l2: opp5 {
5333 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5336 rpmhpd_opp_nom: opp6 {
5337 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5340 rpmhpd_opp_nom_l1: opp7 {
5341 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5344 rpmhpd_opp_turbo: opp8 {
5345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5348 rpmhpd_opp_turbo_l1: opp9 {
5349 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5354 rpmhcc: clock-controller {
5355 compatible = "qcom,sc7280-rpmh-clk";
5356 clocks = <&xo_board>;
5362 epss_l3: interconnect@18590000 {
5363 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
5364 reg = <0 0x18590000 0 0x1000>;
5365 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5366 clock-names = "xo", "alternate";
5367 #interconnect-cells = <1>;
5370 cpufreq_hw: cpufreq@18591000 {
5371 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
5372 reg = <0 0x18591000 0 0x1000>,
5373 <0 0x18592000 0 0x1000>,
5374 <0 0x18593000 0 0x1000>;
5376 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5377 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5378 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5379 interrupt-names = "dcvsh-irq-0",
5383 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5384 clock-names = "xo", "alternate";
5385 #freq-domain-cells = <1>;
5390 thermal_zones: thermal-zones {
5392 polling-delay-passive = <250>;
5393 polling-delay = <0>;
5395 thermal-sensors = <&tsens0 1>;
5398 cpu0_alert0: trip-point0 {
5399 temperature = <90000>;
5400 hysteresis = <2000>;
5404 cpu0_alert1: trip-point1 {
5405 temperature = <95000>;
5406 hysteresis = <2000>;
5410 cpu0_crit: cpu-crit {
5411 temperature = <110000>;
5419 trip = <&cpu0_alert0>;
5420 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5421 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5422 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5423 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5426 trip = <&cpu0_alert1>;
5427 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5428 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5429 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5430 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5436 polling-delay-passive = <250>;
5437 polling-delay = <0>;
5439 thermal-sensors = <&tsens0 2>;
5442 cpu1_alert0: trip-point0 {
5443 temperature = <90000>;
5444 hysteresis = <2000>;
5448 cpu1_alert1: trip-point1 {
5449 temperature = <95000>;
5450 hysteresis = <2000>;
5454 cpu1_crit: cpu-crit {
5455 temperature = <110000>;
5463 trip = <&cpu1_alert0>;
5464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5470 trip = <&cpu1_alert1>;
5471 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5472 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5473 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5474 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5480 polling-delay-passive = <250>;
5481 polling-delay = <0>;
5483 thermal-sensors = <&tsens0 3>;
5486 cpu2_alert0: trip-point0 {
5487 temperature = <90000>;
5488 hysteresis = <2000>;
5492 cpu2_alert1: trip-point1 {
5493 temperature = <95000>;
5494 hysteresis = <2000>;
5498 cpu2_crit: cpu-crit {
5499 temperature = <110000>;
5507 trip = <&cpu2_alert0>;
5508 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5509 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5510 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5511 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5514 trip = <&cpu2_alert1>;
5515 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5516 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5517 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5518 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5524 polling-delay-passive = <250>;
5525 polling-delay = <0>;
5527 thermal-sensors = <&tsens0 4>;
5530 cpu3_alert0: trip-point0 {
5531 temperature = <90000>;
5532 hysteresis = <2000>;
5536 cpu3_alert1: trip-point1 {
5537 temperature = <95000>;
5538 hysteresis = <2000>;
5542 cpu3_crit: cpu-crit {
5543 temperature = <110000>;
5551 trip = <&cpu3_alert0>;
5552 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5553 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5554 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5555 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5558 trip = <&cpu3_alert1>;
5559 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5560 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5561 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5562 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5568 polling-delay-passive = <250>;
5569 polling-delay = <0>;
5571 thermal-sensors = <&tsens0 7>;
5574 cpu4_alert0: trip-point0 {
5575 temperature = <90000>;
5576 hysteresis = <2000>;
5580 cpu4_alert1: trip-point1 {
5581 temperature = <95000>;
5582 hysteresis = <2000>;
5586 cpu4_crit: cpu-crit {
5587 temperature = <110000>;
5595 trip = <&cpu4_alert0>;
5596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5602 trip = <&cpu4_alert1>;
5603 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5604 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5605 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5606 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5612 polling-delay-passive = <250>;
5613 polling-delay = <0>;
5615 thermal-sensors = <&tsens0 8>;
5618 cpu5_alert0: trip-point0 {
5619 temperature = <90000>;
5620 hysteresis = <2000>;
5624 cpu5_alert1: trip-point1 {
5625 temperature = <95000>;
5626 hysteresis = <2000>;
5630 cpu5_crit: cpu-crit {
5631 temperature = <110000>;
5639 trip = <&cpu5_alert0>;
5640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5646 trip = <&cpu5_alert1>;
5647 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5648 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5649 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5650 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5656 polling-delay-passive = <250>;
5657 polling-delay = <0>;
5659 thermal-sensors = <&tsens0 9>;
5662 cpu6_alert0: trip-point0 {
5663 temperature = <90000>;
5664 hysteresis = <2000>;
5668 cpu6_alert1: trip-point1 {
5669 temperature = <95000>;
5670 hysteresis = <2000>;
5674 cpu6_crit: cpu-crit {
5675 temperature = <110000>;
5683 trip = <&cpu6_alert0>;
5684 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5686 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5687 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5690 trip = <&cpu6_alert1>;
5691 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5692 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5693 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5694 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5700 polling-delay-passive = <250>;
5701 polling-delay = <0>;
5703 thermal-sensors = <&tsens0 10>;
5706 cpu7_alert0: trip-point0 {
5707 temperature = <90000>;
5708 hysteresis = <2000>;
5712 cpu7_alert1: trip-point1 {
5713 temperature = <95000>;
5714 hysteresis = <2000>;
5718 cpu7_crit: cpu-crit {
5719 temperature = <110000>;
5727 trip = <&cpu7_alert0>;
5728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5734 trip = <&cpu7_alert1>;
5735 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5736 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5737 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5738 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5744 polling-delay-passive = <250>;
5745 polling-delay = <0>;
5747 thermal-sensors = <&tsens0 11>;
5750 cpu8_alert0: trip-point0 {
5751 temperature = <90000>;
5752 hysteresis = <2000>;
5756 cpu8_alert1: trip-point1 {
5757 temperature = <95000>;
5758 hysteresis = <2000>;
5762 cpu8_crit: cpu-crit {
5763 temperature = <110000>;
5771 trip = <&cpu8_alert0>;
5772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5778 trip = <&cpu8_alert1>;
5779 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5780 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5781 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5782 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5788 polling-delay-passive = <250>;
5789 polling-delay = <0>;
5791 thermal-sensors = <&tsens0 12>;
5794 cpu9_alert0: trip-point0 {
5795 temperature = <90000>;
5796 hysteresis = <2000>;
5800 cpu9_alert1: trip-point1 {
5801 temperature = <95000>;
5802 hysteresis = <2000>;
5806 cpu9_crit: cpu-crit {
5807 temperature = <110000>;
5815 trip = <&cpu9_alert0>;
5816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5822 trip = <&cpu9_alert1>;
5823 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5824 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5825 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5826 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5832 polling-delay-passive = <250>;
5833 polling-delay = <0>;
5835 thermal-sensors = <&tsens0 13>;
5838 cpu10_alert0: trip-point0 {
5839 temperature = <90000>;
5840 hysteresis = <2000>;
5844 cpu10_alert1: trip-point1 {
5845 temperature = <95000>;
5846 hysteresis = <2000>;
5850 cpu10_crit: cpu-crit {
5851 temperature = <110000>;
5859 trip = <&cpu10_alert0>;
5860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5866 trip = <&cpu10_alert1>;
5867 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5868 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5869 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5870 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5876 polling-delay-passive = <250>;
5877 polling-delay = <0>;
5879 thermal-sensors = <&tsens0 14>;
5882 cpu11_alert0: trip-point0 {
5883 temperature = <90000>;
5884 hysteresis = <2000>;
5888 cpu11_alert1: trip-point1 {
5889 temperature = <95000>;
5890 hysteresis = <2000>;
5894 cpu11_crit: cpu-crit {
5895 temperature = <110000>;
5903 trip = <&cpu11_alert0>;
5904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5910 trip = <&cpu11_alert1>;
5911 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5912 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5913 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5914 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5920 polling-delay-passive = <0>;
5921 polling-delay = <0>;
5923 thermal-sensors = <&tsens0 0>;
5926 aoss0_alert0: trip-point0 {
5927 temperature = <90000>;
5928 hysteresis = <2000>;
5932 aoss0_crit: aoss0-crit {
5933 temperature = <110000>;
5941 polling-delay-passive = <0>;
5942 polling-delay = <0>;
5944 thermal-sensors = <&tsens1 0>;
5947 aoss1_alert0: trip-point0 {
5948 temperature = <90000>;
5949 hysteresis = <2000>;
5953 aoss1_crit: aoss1-crit {
5954 temperature = <110000>;
5962 polling-delay-passive = <0>;
5963 polling-delay = <0>;
5965 thermal-sensors = <&tsens0 5>;
5968 cpuss0_alert0: trip-point0 {
5969 temperature = <90000>;
5970 hysteresis = <2000>;
5973 cpuss0_crit: cluster0-crit {
5974 temperature = <110000>;
5982 polling-delay-passive = <0>;
5983 polling-delay = <0>;
5985 thermal-sensors = <&tsens0 6>;
5988 cpuss1_alert0: trip-point0 {
5989 temperature = <90000>;
5990 hysteresis = <2000>;
5993 cpuss1_crit: cluster0-crit {
5994 temperature = <110000>;
6002 polling-delay-passive = <100>;
6003 polling-delay = <0>;
6005 thermal-sensors = <&tsens1 1>;
6008 gpuss0_alert0: trip-point0 {
6009 temperature = <95000>;
6010 hysteresis = <2000>;
6014 gpuss0_crit: gpuss0-crit {
6015 temperature = <110000>;
6023 trip = <&gpuss0_alert0>;
6024 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6030 polling-delay-passive = <100>;
6031 polling-delay = <0>;
6033 thermal-sensors = <&tsens1 2>;
6036 gpuss1_alert0: trip-point0 {
6037 temperature = <95000>;
6038 hysteresis = <2000>;
6042 gpuss1_crit: gpuss1-crit {
6043 temperature = <110000>;
6051 trip = <&gpuss1_alert0>;
6052 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6058 polling-delay-passive = <0>;
6059 polling-delay = <0>;
6061 thermal-sensors = <&tsens1 3>;
6064 nspss0_alert0: trip-point0 {
6065 temperature = <90000>;
6066 hysteresis = <2000>;
6070 nspss0_crit: nspss0-crit {
6071 temperature = <110000>;
6079 polling-delay-passive = <0>;
6080 polling-delay = <0>;
6082 thermal-sensors = <&tsens1 4>;
6085 nspss1_alert0: trip-point0 {
6086 temperature = <90000>;
6087 hysteresis = <2000>;
6091 nspss1_crit: nspss1-crit {
6092 temperature = <110000>;
6100 polling-delay-passive = <0>;
6101 polling-delay = <0>;
6103 thermal-sensors = <&tsens1 5>;
6106 video_alert0: trip-point0 {
6107 temperature = <90000>;
6108 hysteresis = <2000>;
6112 video_crit: video-crit {
6113 temperature = <110000>;
6121 polling-delay-passive = <0>;
6122 polling-delay = <0>;
6124 thermal-sensors = <&tsens1 6>;
6127 ddr_alert0: trip-point0 {
6128 temperature = <90000>;
6129 hysteresis = <2000>;
6133 ddr_crit: ddr-crit {
6134 temperature = <110000>;
6142 polling-delay-passive = <0>;
6143 polling-delay = <0>;
6145 thermal-sensors = <&tsens1 7>;
6148 mdmss0_alert0: trip-point0 {
6149 temperature = <90000>;
6150 hysteresis = <2000>;
6154 mdmss0_crit: mdmss0-crit {
6155 temperature = <110000>;
6163 polling-delay-passive = <0>;
6164 polling-delay = <0>;
6166 thermal-sensors = <&tsens1 8>;
6169 mdmss1_alert0: trip-point0 {
6170 temperature = <90000>;
6171 hysteresis = <2000>;
6175 mdmss1_crit: mdmss1-crit {
6176 temperature = <110000>;
6184 polling-delay-passive = <0>;
6185 polling-delay = <0>;
6187 thermal-sensors = <&tsens1 9>;
6190 mdmss2_alert0: trip-point0 {
6191 temperature = <90000>;
6192 hysteresis = <2000>;
6196 mdmss2_crit: mdmss2-crit {
6197 temperature = <110000>;
6205 polling-delay-passive = <0>;
6206 polling-delay = <0>;
6208 thermal-sensors = <&tsens1 10>;
6211 mdmss3_alert0: trip-point0 {
6212 temperature = <90000>;
6213 hysteresis = <2000>;
6217 mdmss3_crit: mdmss3-crit {
6218 temperature = <110000>;
6226 polling-delay-passive = <0>;
6227 polling-delay = <0>;
6229 thermal-sensors = <&tsens1 11>;
6232 camera0_alert0: trip-point0 {
6233 temperature = <90000>;
6234 hysteresis = <2000>;
6238 camera0_crit: camera0-crit {
6239 temperature = <110000>;
6248 compatible = "arm,armv8-timer";
6249 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6250 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6251 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6252 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;