arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
   8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
  11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
  12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
  15 #include <dt-bindings/dma/qcom-gpi.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  18 #include <dt-bindings/interconnect/qcom,sc7280.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/mailbox/qcom-ipcc.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/sound/qcom,lpass.h>
  26 #include <dt-bindings/thermal/thermal.h>
  27
  28 / {
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         chosen { };
  35
  36         aliases {
  37                 i2c0 = &i2c0;
  38                 i2c1 = &i2c1;
  39                 i2c2 = &i2c2;
  40                 i2c3 = &i2c3;
  41                 i2c4 = &i2c4;
  42                 i2c5 = &i2c5;
  43                 i2c6 = &i2c6;
  44                 i2c7 = &i2c7;
  45                 i2c8 = &i2c8;
  46                 i2c9 = &i2c9;
  47                 i2c10 = &i2c10;
  48                 i2c11 = &i2c11;
  49                 i2c12 = &i2c12;
  50                 i2c13 = &i2c13;
  51                 i2c14 = &i2c14;
  52                 i2c15 = &i2c15;
  53                 mmc1 = &sdhc_1;
  54                 mmc2 = &sdhc_2;
  55                 spi0 = &spi0;
  56                 spi1 = &spi1;
  57                 spi2 = &spi2;
  58                 spi3 = &spi3;
  59                 spi4 = &spi4;
  60                 spi5 = &spi5;
  61                 spi6 = &spi6;
  62                 spi7 = &spi7;
  63                 spi8 = &spi8;
  64                 spi9 = &spi9;
  65                 spi10 = &spi10;
  66                 spi11 = &spi11;
  67                 spi12 = &spi12;
  68                 spi13 = &spi13;
  69                 spi14 = &spi14;
  70                 spi15 = &spi15;
  71         };
  72
  73         clocks {
  74                 xo_board: xo-board {
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <76800000>;
  77                         #clock-cells = <0>;
  78                 };
  79
  80                 sleep_clk: sleep-clk {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32000>;
  83                         #clock-cells = <0>;
  84                 };
  85         };
  86
  87         reserved-memory {
  88                 #address-cells = <2>;
  89                 #size-cells = <2>;
  90                 ranges;
  91
  92                 wlan_ce_mem: memory@4cd000 {
  93                         no-map;
  94                         reg = <0x0 0x004cd000 0x0 0x1000>;
  95                 };
  96
  97                 hyp_mem: memory@80000000 {
  98                         reg = <0x0 0x80000000 0x0 0x600000>;
  99                         no-map;
 100                 };
 101
 102                 xbl_mem: memory@80600000 {
 103                         reg = <0x0 0x80600000 0x0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 aop_mem: memory@80800000 {
 108                         reg = <0x0 0x80800000 0x0 0x60000>;
 109                         no-map;
 110                 };
 111
 112                 aop_cmd_db_mem: memory@80860000 {
 113                         reg = <0x0 0x80860000 0x0 0x20000>;
 114                         compatible = "qcom,cmd-db";
 115                         no-map;
 116                 };
 117
 118                 reserved_xbl_uefi_log: memory@80880000 {
 119                         reg = <0x0 0x80884000 0x0 0x10000>;
 120                         no-map;
 121                 };
 122
 123                 sec_apps_mem: memory@808ff000 {
 124                         reg = <0x0 0x808ff000 0x0 0x1000>;
 125                         no-map;
 126                 };
 127
 128                 smem_mem: memory@80900000 {
 129                         reg = <0x0 0x80900000 0x0 0x200000>;
 130                         no-map;
 131                 };
 132
 133                 cpucp_mem: memory@80b00000 {
 134                         no-map;
 135                         reg = <0x0 0x80b00000 0x0 0x100000>;
 136                 };
 137
 138                 wlan_fw_mem: memory@80c00000 {
 139                         reg = <0x0 0x80c00000 0x0 0xc00000>;
 140                         no-map;
 141                 };
 142
 143                 video_mem: memory@8b200000 {
 144                         reg = <0x0 0x8b200000 0x0 0x500000>;
 145                         no-map;
 146                 };
 147
 148                 ipa_fw_mem: memory@8b700000 {
 149                         reg = <0 0x8b700000 0 0x10000>;
 150                         no-map;
 151                 };
 152
 153                 rmtfs_mem: memory@9c900000 {
 154                         compatible = "qcom,rmtfs-mem";
 155                         reg = <0x0 0x9c900000 0x0 0x280000>;
 156                         no-map;
 157
 158                         qcom,client-id = <1>;
 159                         qcom,vmid = <15>;
 160                 };
 161         };
 162
 163         cpus {
 164                 #address-cells = <2>;
 165                 #size-cells = <0>;
 166
 167                 CPU0: cpu@0 {
 168                         device_type = "cpu";
 169                         compatible = "arm,kryo";
 170                         reg = <0x0 0x0>;
 171                         enable-method = "psci";
 172                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 173                                            &LITTLE_CPU_SLEEP_1
 174                                            &CLUSTER_SLEEP_0>;
 175                         next-level-cache = <&L2_0>;
 176                         operating-points-v2 = <&cpu0_opp_table>;
 177                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 178                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 179                         qcom,freq-domain = <&cpufreq_hw 0>;
 180                         #cooling-cells = <2>;
 181                         L2_0: l2-cache {
 182                                 compatible = "cache";
 183                                 next-level-cache = <&L3_0>;
 184                                 L3_0: l3-cache {
 185                                         compatible = "cache";
 186                                 };
 187                         };
 188                 };
 189
 190                 CPU1: cpu@100 {
 191                         device_type = "cpu";
 192                         compatible = "arm,kryo";
 193                         reg = <0x0 0x100>;
 194                         enable-method = "psci";
 195                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 196                                            &LITTLE_CPU_SLEEP_1
 197                                            &CLUSTER_SLEEP_0>;
 198                         next-level-cache = <&L2_100>;
 199                         operating-points-v2 = <&cpu0_opp_table>;
 200                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 201                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 202                         qcom,freq-domain = <&cpufreq_hw 0>;
 203                         #cooling-cells = <2>;
 204                         L2_100: l2-cache {
 205                                 compatible = "cache";
 206                                 next-level-cache = <&L3_0>;
 207                         };
 208                 };
 209
 210                 CPU2: cpu@200 {
 211                         device_type = "cpu";
 212                         compatible = "arm,kryo";
 213                         reg = <0x0 0x200>;
 214                         enable-method = "psci";
 215                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 216                                            &LITTLE_CPU_SLEEP_1
 217                                            &CLUSTER_SLEEP_0>;
 218                         next-level-cache = <&L2_200>;
 219                         operating-points-v2 = <&cpu0_opp_table>;
 220                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 221                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 222                         qcom,freq-domain = <&cpufreq_hw 0>;
 223                         #cooling-cells = <2>;
 224                         L2_200: l2-cache {
 225                                 compatible = "cache";
 226                                 next-level-cache = <&L3_0>;
 227                         };
 228                 };
 229
 230                 CPU3: cpu@300 {
 231                         device_type = "cpu";
 232                         compatible = "arm,kryo";
 233                         reg = <0x0 0x300>;
 234                         enable-method = "psci";
 235                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 236                                            &LITTLE_CPU_SLEEP_1
 237                                            &CLUSTER_SLEEP_0>;
 238                         next-level-cache = <&L2_300>;
 239                         operating-points-v2 = <&cpu0_opp_table>;
 240                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 241                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 242                         qcom,freq-domain = <&cpufreq_hw 0>;
 243                         #cooling-cells = <2>;
 244                         L2_300: l2-cache {
 245                                 compatible = "cache";
 246                                 next-level-cache = <&L3_0>;
 247                         };
 248                 };
 249
 250                 CPU4: cpu@400 {
 251                         device_type = "cpu";
 252                         compatible = "arm,kryo";
 253                         reg = <0x0 0x400>;
 254                         enable-method = "psci";
 255                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 256                                            &BIG_CPU_SLEEP_1
 257                                            &CLUSTER_SLEEP_0>;
 258                         next-level-cache = <&L2_400>;
 259                         operating-points-v2 = <&cpu4_opp_table>;
 260                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 261                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 262                         qcom,freq-domain = <&cpufreq_hw 1>;
 263                         #cooling-cells = <2>;
 264                         L2_400: l2-cache {
 265                                 compatible = "cache";
 266                                 next-level-cache = <&L3_0>;
 267                         };
 268                 };
 269
 270                 CPU5: cpu@500 {
 271                         device_type = "cpu";
 272                         compatible = "arm,kryo";
 273                         reg = <0x0 0x500>;
 274                         enable-method = "psci";
 275                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 276                                            &BIG_CPU_SLEEP_1
 277                                            &CLUSTER_SLEEP_0>;
 278                         next-level-cache = <&L2_500>;
 279                         operating-points-v2 = <&cpu4_opp_table>;
 280                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 281                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 282                         qcom,freq-domain = <&cpufreq_hw 1>;
 283                         #cooling-cells = <2>;
 284                         L2_500: l2-cache {
 285                                 compatible = "cache";
 286                                 next-level-cache = <&L3_0>;
 287                         };
 288                 };
 289
 290                 CPU6: cpu@600 {
 291                         device_type = "cpu";
 292                         compatible = "arm,kryo";
 293                         reg = <0x0 0x600>;
 294                         enable-method = "psci";
 295                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 296                                            &BIG_CPU_SLEEP_1
 297                                            &CLUSTER_SLEEP_0>;
 298                         next-level-cache = <&L2_600>;
 299                         operating-points-v2 = <&cpu4_opp_table>;
 300                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 301                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 302                         qcom,freq-domain = <&cpufreq_hw 1>;
 303                         #cooling-cells = <2>;
 304                         L2_600: l2-cache {
 305                                 compatible = "cache";
 306                                 next-level-cache = <&L3_0>;
 307                         };
 308                 };
 309
 310                 CPU7: cpu@700 {
 311                         device_type = "cpu";
 312                         compatible = "arm,kryo";
 313                         reg = <0x0 0x700>;
 314                         enable-method = "psci";
 315                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 316                                            &BIG_CPU_SLEEP_1
 317                                            &CLUSTER_SLEEP_0>;
 318                         next-level-cache = <&L2_700>;
 319                         operating-points-v2 = <&cpu7_opp_table>;
 320                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 321                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 322                         qcom,freq-domain = <&cpufreq_hw 2>;
 323                         #cooling-cells = <2>;
 324                         L2_700: l2-cache {
 325                                 compatible = "cache";
 326                                 next-level-cache = <&L3_0>;
 327                         };
 328                 };
 329
 330                 cpu-map {
 331                         cluster0 {
 332                                 core0 {
 333                                         cpu = <&CPU0>;
 334                                 };
 335
 336                                 core1 {
 337                                         cpu = <&CPU1>;
 338                                 };
 339
 340                                 core2 {
 341                                         cpu = <&CPU2>;
 342                                 };
 343
 344                                 core3 {
 345                                         cpu = <&CPU3>;
 346                                 };
 347
 348                                 core4 {
 349                                         cpu = <&CPU4>;
 350                                 };
 351
 352                                 core5 {
 353                                         cpu = <&CPU5>;
 354                                 };
 355
 356                                 core6 {
 357                                         cpu = <&CPU6>;
 358                                 };
 359
 360                                 core7 {
 361                                         cpu = <&CPU7>;
 362                                 };
 363                         };
 364                 };
 365
 366                 idle-states {
 367                         entry-method = "psci";
 368
 369                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 370                                 compatible = "arm,idle-state";
 371                                 idle-state-name = "little-power-down";
 372                                 arm,psci-suspend-param = <0x40000003>;
 373                                 entry-latency-us = <549>;
 374                                 exit-latency-us = <901>;
 375                                 min-residency-us = <1774>;
 376                                 local-timer-stop;
 377                         };
 378
 379                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 380                                 compatible = "arm,idle-state";
 381                                 idle-state-name = "little-rail-power-down";
 382                                 arm,psci-suspend-param = <0x40000004>;
 383                                 entry-latency-us = <702>;
 384                                 exit-latency-us = <915>;
 385                                 min-residency-us = <4001>;
 386                                 local-timer-stop;
 387                         };
 388
 389                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 390                                 compatible = "arm,idle-state";
 391                                 idle-state-name = "big-power-down";
 392                                 arm,psci-suspend-param = <0x40000003>;
 393                                 entry-latency-us = <523>;
 394                                 exit-latency-us = <1244>;
 395                                 min-residency-us = <2207>;
 396                                 local-timer-stop;
 397                         };
 398
 399                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 400                                 compatible = "arm,idle-state";
 401                                 idle-state-name = "big-rail-power-down";
 402                                 arm,psci-suspend-param = <0x40000004>;
 403                                 entry-latency-us = <526>;
 404                                 exit-latency-us = <1854>;
 405                                 min-residency-us = <5555>;
 406                                 local-timer-stop;
 407                         };
 408
 409                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 410                                 compatible = "arm,idle-state";
 411                                 idle-state-name = "cluster-power-down";
 412                                 arm,psci-suspend-param = <0x40003444>;
 413                                 entry-latency-us = <3263>;
 414                                 exit-latency-us = <6562>;
 415                                 min-residency-us = <9926>;
 416                                 local-timer-stop;
 417                         };
 418                 };
 419         };
 420
 421         cpu0_opp_table: opp-table-cpu0 {
 422                 compatible = "operating-points-v2";
 423                 opp-shared;
 424
 425                 cpu0_opp_300mhz: opp-300000000 {
 426                         opp-hz = /bits/ 64 <300000000>;
 427                         opp-peak-kBps = <800000 9600000>;
 428                 };
 429
 430                 cpu0_opp_691mhz: opp-691200000 {
 431                         opp-hz = /bits/ 64 <691200000>;
 432                         opp-peak-kBps = <800000 17817600>;
 433                 };
 434
 435                 cpu0_opp_806mhz: opp-806400000 {
 436                         opp-hz = /bits/ 64 <806400000>;
 437                         opp-peak-kBps = <800000 20889600>;
 438                 };
 439
 440                 cpu0_opp_941mhz: opp-940800000 {
 441                         opp-hz = /bits/ 64 <940800000>;
 442                         opp-peak-kBps = <1804000 24576000>;
 443                 };
 444
 445                 cpu0_opp_1152mhz: opp-1152000000 {
 446                         opp-hz = /bits/ 64 <1152000000>;
 447                         opp-peak-kBps = <2188000 27033600>;
 448                 };
 449
 450                 cpu0_opp_1325mhz: opp-1324800000 {
 451                         opp-hz = /bits/ 64 <1324800000>;
 452                         opp-peak-kBps = <2188000 33792000>;
 453                 };
 454
 455                 cpu0_opp_1517mhz: opp-1516800000 {
 456                         opp-hz = /bits/ 64 <1516800000>;
 457                         opp-peak-kBps = <3072000 38092800>;
 458                 };
 459
 460                 cpu0_opp_1651mhz: opp-1651200000 {
 461                         opp-hz = /bits/ 64 <1651200000>;
 462                         opp-peak-kBps = <3072000 41779200>;
 463                 };
 464
 465                 cpu0_opp_1805mhz: opp-1804800000 {
 466                         opp-hz = /bits/ 64 <1804800000>;
 467                         opp-peak-kBps = <4068000 48537600>;
 468                 };
 469
 470                 cpu0_opp_1958mhz: opp-1958400000 {
 471                         opp-hz = /bits/ 64 <1958400000>;
 472                         opp-peak-kBps = <4068000 48537600>;
 473                 };
 474
 475                 cpu0_opp_2016mhz: opp-2016000000 {
 476                         opp-hz = /bits/ 64 <2016000000>;
 477                         opp-peak-kBps = <6220000 48537600>;
 478                 };
 479         };
 480
 481         cpu4_opp_table: opp-table-cpu4 {
 482                 compatible = "operating-points-v2";
 483                 opp-shared;
 484
 485                 cpu4_opp_691mhz: opp-691200000 {
 486                         opp-hz = /bits/ 64 <691200000>;
 487                         opp-peak-kBps = <1804000 9600000>;
 488                 };
 489
 490                 cpu4_opp_941mhz: opp-940800000 {
 491                         opp-hz = /bits/ 64 <940800000>;
 492                         opp-peak-kBps = <2188000 17817600>;
 493                 };
 494
 495                 cpu4_opp_1229mhz: opp-1228800000 {
 496                         opp-hz = /bits/ 64 <1228800000>;
 497                         opp-peak-kBps = <4068000 24576000>;
 498                 };
 499
 500                 cpu4_opp_1344mhz: opp-1344000000 {
 501                         opp-hz = /bits/ 64 <1344000000>;
 502                         opp-peak-kBps = <4068000 24576000>;
 503                 };
 504
 505                 cpu4_opp_1517mhz: opp-1516800000 {
 506                         opp-hz = /bits/ 64 <1516800000>;
 507                         opp-peak-kBps = <4068000 24576000>;
 508                 };
 509
 510                 cpu4_opp_1651mhz: opp-1651200000 {
 511                         opp-hz = /bits/ 64 <1651200000>;
 512                         opp-peak-kBps = <6220000 38092800>;
 513                 };
 514
 515                 cpu4_opp_1901mhz: opp-1900800000 {
 516                         opp-hz = /bits/ 64 <1900800000>;
 517                         opp-peak-kBps = <6220000 44851200>;
 518                 };
 519
 520                 cpu4_opp_2054mhz: opp-2054400000 {
 521                         opp-hz = /bits/ 64 <2054400000>;
 522                         opp-peak-kBps = <6220000 44851200>;
 523                 };
 524
 525                 cpu4_opp_2112mhz: opp-2112000000 {
 526                         opp-hz = /bits/ 64 <2112000000>;
 527                         opp-peak-kBps = <6220000 44851200>;
 528                 };
 529
 530                 cpu4_opp_2131mhz: opp-2131200000 {
 531                         opp-hz = /bits/ 64 <2131200000>;
 532                         opp-peak-kBps = <6220000 44851200>;
 533                 };
 534
 535                 cpu4_opp_2208mhz: opp-2208000000 {
 536                         opp-hz = /bits/ 64 <2208000000>;
 537                         opp-peak-kBps = <6220000 44851200>;
 538                 };
 539
 540                 cpu4_opp_2400mhz: opp-2400000000 {
 541                         opp-hz = /bits/ 64 <2400000000>;
 542                         opp-peak-kBps = <8532000 48537600>;
 543                 };
 544
 545                 cpu4_opp_2611mhz: opp-2611200000 {
 546                         opp-hz = /bits/ 64 <2611200000>;
 547                         opp-peak-kBps = <8532000 48537600>;
 548                 };
 549         };
 550
 551         cpu7_opp_table: opp-table-cpu7 {
 552                 compatible = "operating-points-v2";
 553                 opp-shared;
 554
 555                 cpu7_opp_806mhz: opp-806400000 {
 556                         opp-hz = /bits/ 64 <806400000>;
 557                         opp-peak-kBps = <1804000 9600000>;
 558                 };
 559
 560                 cpu7_opp_1056mhz: opp-1056000000 {
 561                         opp-hz = /bits/ 64 <1056000000>;
 562                         opp-peak-kBps = <2188000 17817600>;
 563                 };
 564
 565                 cpu7_opp_1325mhz: opp-1324800000 {
 566                         opp-hz = /bits/ 64 <1324800000>;
 567                         opp-peak-kBps = <4068000 24576000>;
 568                 };
 569
 570                 cpu7_opp_1517mhz: opp-1516800000 {
 571                         opp-hz = /bits/ 64 <1516800000>;
 572                         opp-peak-kBps = <4068000 24576000>;
 573                 };
 574
 575                 cpu7_opp_1766mhz: opp-1766400000 {
 576                         opp-hz = /bits/ 64 <1766400000>;
 577                         opp-peak-kBps = <6220000 38092800>;
 578                 };
 579
 580                 cpu7_opp_1862mhz: opp-1862400000 {
 581                         opp-hz = /bits/ 64 <1862400000>;
 582                         opp-peak-kBps = <6220000 38092800>;
 583                 };
 584
 585                 cpu7_opp_2035mhz: opp-2035200000 {
 586                         opp-hz = /bits/ 64 <2035200000>;
 587                         opp-peak-kBps = <6220000 38092800>;
 588                 };
 589
 590                 cpu7_opp_2112mhz: opp-2112000000 {
 591                         opp-hz = /bits/ 64 <2112000000>;
 592                         opp-peak-kBps = <6220000 44851200>;
 593                 };
 594
 595                 cpu7_opp_2208mhz: opp-2208000000 {
 596                         opp-hz = /bits/ 64 <2208000000>;
 597                         opp-peak-kBps = <6220000 44851200>;
 598                 };
 599
 600                 cpu7_opp_2381mhz: opp-2380800000 {
 601                         opp-hz = /bits/ 64 <2380800000>;
 602                         opp-peak-kBps = <6832000 44851200>;
 603                 };
 604
 605                 cpu7_opp_2400mhz: opp-2400000000 {
 606                         opp-hz = /bits/ 64 <2400000000>;
 607                         opp-peak-kBps = <8532000 48537600>;
 608                 };
 609
 610                 cpu7_opp_2515mhz: opp-2515200000 {
 611                         opp-hz = /bits/ 64 <2515200000>;
 612                         opp-peak-kBps = <8532000 48537600>;
 613                 };
 614
 615                 cpu7_opp_2707mhz: opp-2707200000 {
 616                         opp-hz = /bits/ 64 <2707200000>;
 617                         opp-peak-kBps = <8532000 48537600>;
 618                 };
 619
 620                 cpu7_opp_3014mhz: opp-3014400000 {
 621                         opp-hz = /bits/ 64 <3014400000>;
 622                         opp-peak-kBps = <8532000 48537600>;
 623                 };
 624         };
 625
 626         memory@80000000 {
 627                 device_type = "memory";
 628                 /* We expect the bootloader to fill in the size */
 629                 reg = <0 0x80000000 0 0>;
 630         };
 631
 632         firmware {
 633                 scm {
 634                         compatible = "qcom,scm-sc7280", "qcom,scm";
 635                 };
 636         };
 637
 638         clk_virt: interconnect {
 639                 compatible = "qcom,sc7280-clk-virt";
 640                 #interconnect-cells = <2>;
 641                 qcom,bcm-voters = <&apps_bcm_voter>;
 642         };
 643
 644         smem {
 645                 compatible = "qcom,smem";
 646                 memory-region = <&smem_mem>;
 647                 hwlocks = <&tcsr_mutex 3>;
 648         };
 649
 650         smp2p-adsp {
 651                 compatible = "qcom,smp2p";
 652                 qcom,smem = <443>, <429>;
 653                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 654                                              IPCC_MPROC_SIGNAL_SMP2P
 655                                              IRQ_TYPE_EDGE_RISING>;
 656                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 657                                 IPCC_MPROC_SIGNAL_SMP2P>;
 658
 659                 qcom,local-pid = <0>;
 660                 qcom,remote-pid = <2>;
 661
 662                 adsp_smp2p_out: master-kernel {
 663                         qcom,entry-name = "master-kernel";
 664                         #qcom,smem-state-cells = <1>;
 665                 };
 666
 667                 adsp_smp2p_in: slave-kernel {
 668                         qcom,entry-name = "slave-kernel";
 669                         interrupt-controller;
 670                         #interrupt-cells = <2>;
 671                 };
 672         };
 673
 674         smp2p-cdsp {
 675                 compatible = "qcom,smp2p";
 676                 qcom,smem = <94>, <432>;
 677                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 678                                              IPCC_MPROC_SIGNAL_SMP2P
 679                                              IRQ_TYPE_EDGE_RISING>;
 680                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 681                                 IPCC_MPROC_SIGNAL_SMP2P>;
 682
 683                 qcom,local-pid = <0>;
 684                 qcom,remote-pid = <5>;
 685
 686                 cdsp_smp2p_out: master-kernel {
 687                         qcom,entry-name = "master-kernel";
 688                         #qcom,smem-state-cells = <1>;
 689                 };
 690
 691                 cdsp_smp2p_in: slave-kernel {
 692                         qcom,entry-name = "slave-kernel";
 693                         interrupt-controller;
 694                         #interrupt-cells = <2>;
 695                 };
 696         };
 697
 698         smp2p-mpss {
 699                 compatible = "qcom,smp2p";
 700                 qcom,smem = <435>, <428>;
 701                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 702                                              IPCC_MPROC_SIGNAL_SMP2P
 703                                              IRQ_TYPE_EDGE_RISING>;
 704                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 705                                 IPCC_MPROC_SIGNAL_SMP2P>;
 706
 707                 qcom,local-pid = <0>;
 708                 qcom,remote-pid = <1>;
 709
 710                 modem_smp2p_out: master-kernel {
 711                         qcom,entry-name = "master-kernel";
 712                         #qcom,smem-state-cells = <1>;
 713                 };
 714
 715                 modem_smp2p_in: slave-kernel {
 716                         qcom,entry-name = "slave-kernel";
 717                         interrupt-controller;
 718                         #interrupt-cells = <2>;
 719                 };
 720
 721                 ipa_smp2p_out: ipa-ap-to-modem {
 722                         qcom,entry-name = "ipa";
 723                         #qcom,smem-state-cells = <1>;
 724                 };
 725
 726                 ipa_smp2p_in: ipa-modem-to-ap {
 727                         qcom,entry-name = "ipa";
 728                         interrupt-controller;
 729                         #interrupt-cells = <2>;
 730                 };
 731         };
 732
 733         smp2p-wpss {
 734                 compatible = "qcom,smp2p";
 735                 qcom,smem = <617>, <616>;
 736                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 737                                              IPCC_MPROC_SIGNAL_SMP2P
 738                                              IRQ_TYPE_EDGE_RISING>;
 739                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 740                                 IPCC_MPROC_SIGNAL_SMP2P>;
 741
 742                 qcom,local-pid = <0>;
 743                 qcom,remote-pid = <13>;
 744
 745                 wpss_smp2p_out: master-kernel {
 746                         qcom,entry-name = "master-kernel";
 747                         #qcom,smem-state-cells = <1>;
 748                 };
 749
 750                 wpss_smp2p_in: slave-kernel {
 751                         qcom,entry-name = "slave-kernel";
 752                         interrupt-controller;
 753                         #interrupt-cells = <2>;
 754                 };
 755         };
 756
 757         pmu {
 758                 compatible = "arm,armv8-pmuv3";
 759                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 760         };
 761
 762         psci {
 763                 compatible = "arm,psci-1.0";
 764                 method = "smc";
 765         };
 766
 767         qspi_opp_table: opp-table-qspi {
 768                 compatible = "operating-points-v2";
 769
 770                 opp-75000000 {
 771                         opp-hz = /bits/ 64 <75000000>;
 772                         required-opps = <&rpmhpd_opp_low_svs>;
 773                 };
 774
 775                 opp-150000000 {
 776                         opp-hz = /bits/ 64 <150000000>;
 777                         required-opps = <&rpmhpd_opp_svs>;
 778                 };
 779
 780                 opp-200000000 {
 781                         opp-hz = /bits/ 64 <200000000>;
 782                         required-opps = <&rpmhpd_opp_svs_l1>;
 783                 };
 784
 785                 opp-300000000 {
 786                         opp-hz = /bits/ 64 <300000000>;
 787                         required-opps = <&rpmhpd_opp_nom>;
 788                 };
 789         };
 790
 791         qup_opp_table: opp-table-qup {
 792                 compatible = "operating-points-v2";
 793
 794                 opp-75000000 {
 795                         opp-hz = /bits/ 64 <75000000>;
 796                         required-opps = <&rpmhpd_opp_low_svs>;
 797                 };
 798
 799                 opp-100000000 {
 800                         opp-hz = /bits/ 64 <100000000>;
 801                         required-opps = <&rpmhpd_opp_svs>;
 802                 };
 803
 804                 opp-128000000 {
 805                         opp-hz = /bits/ 64 <128000000>;
 806                         required-opps = <&rpmhpd_opp_nom>;
 807                 };
 808         };
 809
 810         soc: soc@0 {
 811                 #address-cells = <2>;
 812                 #size-cells = <2>;
 813                 ranges = <0 0 0 0 0x10 0>;
 814                 dma-ranges = <0 0 0 0 0x10 0>;
 815                 compatible = "simple-bus";
 816
 817                 gcc: clock-controller@100000 {
 818                         compatible = "qcom,gcc-sc7280";
 819                         reg = <0 0x00100000 0 0x1f0000>;
 820                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 821                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 822                                  <0>, <&pcie1_lane>,
 823                                  <0>, <0>, <0>,
 824                                  <&usb_1_ssphy>;
 825                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 826                                       "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 827                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 828                                       "ufs_phy_tx_symbol_0_clk",
 829                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 830                         #clock-cells = <1>;
 831                         #reset-cells = <1>;
 832                         #power-domain-cells = <1>;
 833                         power-domains = <&rpmhpd SC7280_CX>;
 834                 };
 835
 836                 ipcc: mailbox@408000 {
 837                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 838                         reg = <0 0x00408000 0 0x1000>;
 839                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 840                         interrupt-controller;
 841                         #interrupt-cells = <3>;
 842                         #mbox-cells = <2>;
 843                 };
 844
 845                 qfprom: efuse@784000 {
 846                         compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
 847                         reg = <0 0x00784000 0 0xa20>,
 848                               <0 0x00780000 0 0xa20>,
 849                               <0 0x00782000 0 0x120>,
 850                               <0 0x00786000 0 0x1fff>;
 851                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 852                         clock-names = "core";
 853                         power-domains = <&rpmhpd SC7280_MX>;
 854                         #address-cells = <1>;
 855                         #size-cells = <1>;
 856
 857                         gpu_speed_bin: gpu_speed_bin@1e9 {
 858                                 reg = <0x1e9 0x2>;
 859                                 bits = <5 8>;
 860                         };
 861                 };
 862
 863                 sdhc_1: mmc@7c4000 {
 864                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 865                         pinctrl-names = "default", "sleep";
 866                         pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
 867                         pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
 868                         status = "disabled";
 869
 870                         reg = <0 0x007c4000 0 0x1000>,
 871                               <0 0x007c5000 0 0x1000>;
 872                         reg-names = "hc", "cqhci";
 873
 874                         iommus = <&apps_smmu 0xc0 0x0>;
 875                         interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
 876                                      <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 877                         interrupt-names = "hc_irq", "pwr_irq";
 878
 879                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 880                                  <&gcc GCC_SDCC1_APPS_CLK>,
 881                                  <&rpmhcc RPMH_CXO_CLK>;
 882                         clock-names = "iface", "core", "xo";
 883                         interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
 884                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
 885                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 886                         power-domains = <&rpmhpd SC7280_CX>;
 887                         operating-points-v2 = <&sdhc1_opp_table>;
 888
 889                         bus-width = <8>;
 890                         supports-cqe;
 891                         dma-coherent;
 892
 893                         qcom,dll-config = <0x0007642c>;
 894                         qcom,ddr-config = <0x80040868>;
 895
 896                         mmc-ddr-1_8v;
 897                         mmc-hs200-1_8v;
 898                         mmc-hs400-1_8v;
 899                         mmc-hs400-enhanced-strobe;
 900
 901                         resets = <&gcc GCC_SDCC1_BCR>;
 902
 903                         sdhc1_opp_table: opp-table {
 904                                 compatible = "operating-points-v2";
 905
 906                                 opp-100000000 {
 907                                         opp-hz = /bits/ 64 <100000000>;
 908                                         required-opps = <&rpmhpd_opp_low_svs>;
 909                                         opp-peak-kBps = <1800000 400000>;
 910                                         opp-avg-kBps = <100000 0>;
 911                                 };
 912
 913                                 opp-384000000 {
 914                                         opp-hz = /bits/ 64 <384000000>;
 915                                         required-opps = <&rpmhpd_opp_nom>;
 916                                         opp-peak-kBps = <5400000 1600000>;
 917                                         opp-avg-kBps = <390000 0>;
 918                                 };
 919                         };
 920
 921                 };
 922
 923                 gpi_dma0: dma-controller@900000 {
 924                         #dma-cells = <3>;
 925                         compatible = "qcom,sc7280-gpi-dma";
 926                         reg = <0 0x00900000 0 0x60000>;
 927                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 933                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 934                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 936                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 937                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 938                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 939                         dma-channels = <12>;
 940                         dma-channel-mask = <0x7f>;
 941                         iommus = <&apps_smmu 0x0136 0x0>;
 942                         status = "disabled";
 943                 };
 944
 945                 qupv3_id_0: geniqup@9c0000 {
 946                         compatible = "qcom,geni-se-qup";
 947                         reg = <0 0x009c0000 0 0x2000>;
 948                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 949                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 950                         clock-names = "m-ahb", "s-ahb";
 951                         #address-cells = <2>;
 952                         #size-cells = <2>;
 953                         ranges;
 954                         iommus = <&apps_smmu 0x123 0x0>;
 955                         status = "disabled";
 956
 957                         i2c0: i2c@980000 {
 958                                 compatible = "qcom,geni-i2c";
 959                                 reg = <0 0x00980000 0 0x4000>;
 960                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 961                                 clock-names = "se";
 962                                 pinctrl-names = "default";
 963                                 pinctrl-0 = <&qup_i2c0_data_clk>;
 964                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 965                                 #address-cells = <1>;
 966                                 #size-cells = <0>;
 967                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 968                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 969                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 970                                 interconnect-names = "qup-core", "qup-config",
 971                                                         "qup-memory";
 972                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 973                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 974                                 dma-names = "tx", "rx";
 975                                 status = "disabled";
 976                         };
 977
 978                         spi0: spi@980000 {
 979                                 compatible = "qcom,geni-spi";
 980                                 reg = <0 0x00980000 0 0x4000>;
 981                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 982                                 clock-names = "se";
 983                                 pinctrl-names = "default";
 984                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
 985                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 986                                 #address-cells = <1>;
 987                                 #size-cells = <0>;
 988                                 power-domains = <&rpmhpd SC7280_CX>;
 989                                 operating-points-v2 = <&qup_opp_table>;
 990                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 991                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 992                                 interconnect-names = "qup-core", "qup-config";
 993                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 994                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 995                                 dma-names = "tx", "rx";
 996                                 status = "disabled";
 997                         };
 998
 999                         uart0: serial@980000 {
1000                                 compatible = "qcom,geni-uart";
1001                                 reg = <0 0x00980000 0 0x4000>;
1002                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1003                                 clock-names = "se";
1004                                 pinctrl-names = "default";
1005                                 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1006                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1007                                 power-domains = <&rpmhpd SC7280_CX>;
1008                                 operating-points-v2 = <&qup_opp_table>;
1009                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1010                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1011                                 interconnect-names = "qup-core", "qup-config";
1012                                 status = "disabled";
1013                         };
1014
1015                         i2c1: i2c@984000 {
1016                                 compatible = "qcom,geni-i2c";
1017                                 reg = <0 0x00984000 0 0x4000>;
1018                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1019                                 clock-names = "se";
1020                                 pinctrl-names = "default";
1021                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1022                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1023                                 #address-cells = <1>;
1024                                 #size-cells = <0>;
1025                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1026                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1027                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1028                                 interconnect-names = "qup-core", "qup-config",
1029                                                         "qup-memory";
1030                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1031                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1032                                 dma-names = "tx", "rx";
1033                                 status = "disabled";
1034                         };
1035
1036                         spi1: spi@984000 {
1037                                 compatible = "qcom,geni-spi";
1038                                 reg = <0 0x00984000 0 0x4000>;
1039                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1040                                 clock-names = "se";
1041                                 pinctrl-names = "default";
1042                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1043                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1044                                 #address-cells = <1>;
1045                                 #size-cells = <0>;
1046                                 power-domains = <&rpmhpd SC7280_CX>;
1047                                 operating-points-v2 = <&qup_opp_table>;
1048                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1049                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1050                                 interconnect-names = "qup-core", "qup-config";
1051                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1052                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1053                                 dma-names = "tx", "rx";
1054                                 status = "disabled";
1055                         };
1056
1057                         uart1: serial@984000 {
1058                                 compatible = "qcom,geni-uart";
1059                                 reg = <0 0x00984000 0 0x4000>;
1060                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1061                                 clock-names = "se";
1062                                 pinctrl-names = "default";
1063                                 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1064                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1065                                 power-domains = <&rpmhpd SC7280_CX>;
1066                                 operating-points-v2 = <&qup_opp_table>;
1067                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1068                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1069                                 interconnect-names = "qup-core", "qup-config";
1070                                 status = "disabled";
1071                         };
1072
1073                         i2c2: i2c@988000 {
1074                                 compatible = "qcom,geni-i2c";
1075                                 reg = <0 0x00988000 0 0x4000>;
1076                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1077                                 clock-names = "se";
1078                                 pinctrl-names = "default";
1079                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1080                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1081                                 #address-cells = <1>;
1082                                 #size-cells = <0>;
1083                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1084                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1085                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1086                                 interconnect-names = "qup-core", "qup-config",
1087                                                         "qup-memory";
1088                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1089                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1090                                 dma-names = "tx", "rx";
1091                                 status = "disabled";
1092                         };
1093
1094                         spi2: spi@988000 {
1095                                 compatible = "qcom,geni-spi";
1096                                 reg = <0 0x00988000 0 0x4000>;
1097                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1098                                 clock-names = "se";
1099                                 pinctrl-names = "default";
1100                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1101                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1102                                 #address-cells = <1>;
1103                                 #size-cells = <0>;
1104                                 power-domains = <&rpmhpd SC7280_CX>;
1105                                 operating-points-v2 = <&qup_opp_table>;
1106                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1107                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1108                                 interconnect-names = "qup-core", "qup-config";
1109                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1110                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1111                                 dma-names = "tx", "rx";
1112                                 status = "disabled";
1113                         };
1114
1115                         uart2: serial@988000 {
1116                                 compatible = "qcom,geni-uart";
1117                                 reg = <0 0x00988000 0 0x4000>;
1118                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1119                                 clock-names = "se";
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1122                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1123                                 power-domains = <&rpmhpd SC7280_CX>;
1124                                 operating-points-v2 = <&qup_opp_table>;
1125                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1126                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1127                                 interconnect-names = "qup-core", "qup-config";
1128                                 status = "disabled";
1129                         };
1130
1131                         i2c3: i2c@98c000 {
1132                                 compatible = "qcom,geni-i2c";
1133                                 reg = <0 0x0098c000 0 0x4000>;
1134                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1135                                 clock-names = "se";
1136                                 pinctrl-names = "default";
1137                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1138                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1142                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1143                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1144                                 interconnect-names = "qup-core", "qup-config",
1145                                                         "qup-memory";
1146                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1147                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1148                                 dma-names = "tx", "rx";
1149                                 status = "disabled";
1150                         };
1151
1152                         spi3: spi@98c000 {
1153                                 compatible = "qcom,geni-spi";
1154                                 reg = <0 0x0098c000 0 0x4000>;
1155                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1156                                 clock-names = "se";
1157                                 pinctrl-names = "default";
1158                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1159                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1160                                 #address-cells = <1>;
1161                                 #size-cells = <0>;
1162                                 power-domains = <&rpmhpd SC7280_CX>;
1163                                 operating-points-v2 = <&qup_opp_table>;
1164                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1165                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1166                                 interconnect-names = "qup-core", "qup-config";
1167                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1168                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1169                                 dma-names = "tx", "rx";
1170                                 status = "disabled";
1171                         };
1172
1173                         uart3: serial@98c000 {
1174                                 compatible = "qcom,geni-uart";
1175                                 reg = <0 0x0098c000 0 0x4000>;
1176                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1177                                 clock-names = "se";
1178                                 pinctrl-names = "default";
1179                                 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1180                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1181                                 power-domains = <&rpmhpd SC7280_CX>;
1182                                 operating-points-v2 = <&qup_opp_table>;
1183                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1184                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1185                                 interconnect-names = "qup-core", "qup-config";
1186                                 status = "disabled";
1187                         };
1188
1189                         i2c4: i2c@990000 {
1190                                 compatible = "qcom,geni-i2c";
1191                                 reg = <0 0x00990000 0 0x4000>;
1192                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1193                                 clock-names = "se";
1194                                 pinctrl-names = "default";
1195                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1196                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1197                                 #address-cells = <1>;
1198                                 #size-cells = <0>;
1199                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1200                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1201                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1202                                 interconnect-names = "qup-core", "qup-config",
1203                                                         "qup-memory";
1204                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1205                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1206                                 dma-names = "tx", "rx";
1207                                 status = "disabled";
1208                         };
1209
1210                         spi4: spi@990000 {
1211                                 compatible = "qcom,geni-spi";
1212                                 reg = <0 0x00990000 0 0x4000>;
1213                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1214                                 clock-names = "se";
1215                                 pinctrl-names = "default";
1216                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1217                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 power-domains = <&rpmhpd SC7280_CX>;
1221                                 operating-points-v2 = <&qup_opp_table>;
1222                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1223                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1224                                 interconnect-names = "qup-core", "qup-config";
1225                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1226                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1227                                 dma-names = "tx", "rx";
1228                                 status = "disabled";
1229                         };
1230
1231                         uart4: serial@990000 {
1232                                 compatible = "qcom,geni-uart";
1233                                 reg = <0 0x00990000 0 0x4000>;
1234                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1235                                 clock-names = "se";
1236                                 pinctrl-names = "default";
1237                                 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1238                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1239                                 power-domains = <&rpmhpd SC7280_CX>;
1240                                 operating-points-v2 = <&qup_opp_table>;
1241                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1242                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1243                                 interconnect-names = "qup-core", "qup-config";
1244                                 status = "disabled";
1245                         };
1246
1247                         i2c5: i2c@994000 {
1248                                 compatible = "qcom,geni-i2c";
1249                                 reg = <0 0x00994000 0 0x4000>;
1250                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1251                                 clock-names = "se";
1252                                 pinctrl-names = "default";
1253                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1254                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1255                                 #address-cells = <1>;
1256                                 #size-cells = <0>;
1257                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1258                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1259                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1260                                 interconnect-names = "qup-core", "qup-config",
1261                                                         "qup-memory";
1262                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1263                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1264                                 dma-names = "tx", "rx";
1265                                 status = "disabled";
1266                         };
1267
1268                         spi5: spi@994000 {
1269                                 compatible = "qcom,geni-spi";
1270                                 reg = <0 0x00994000 0 0x4000>;
1271                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1272                                 clock-names = "se";
1273                                 pinctrl-names = "default";
1274                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1275                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1276                                 #address-cells = <1>;
1277                                 #size-cells = <0>;
1278                                 power-domains = <&rpmhpd SC7280_CX>;
1279                                 operating-points-v2 = <&qup_opp_table>;
1280                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1281                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1282                                 interconnect-names = "qup-core", "qup-config";
1283                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1284                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1285                                 dma-names = "tx", "rx";
1286                                 status = "disabled";
1287                         };
1288
1289                         uart5: serial@994000 {
1290                                 compatible = "qcom,geni-uart";
1291                                 reg = <0 0x00994000 0 0x4000>;
1292                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1293                                 clock-names = "se";
1294                                 pinctrl-names = "default";
1295                                 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1296                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1297                                 power-domains = <&rpmhpd SC7280_CX>;
1298                                 operating-points-v2 = <&qup_opp_table>;
1299                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1301                                 interconnect-names = "qup-core", "qup-config";
1302                                 status = "disabled";
1303                         };
1304
1305                         i2c6: i2c@998000 {
1306                                 compatible = "qcom,geni-i2c";
1307                                 reg = <0 0x00998000 0 0x4000>;
1308                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1309                                 clock-names = "se";
1310                                 pinctrl-names = "default";
1311                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1312                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1313                                 #address-cells = <1>;
1314                                 #size-cells = <0>;
1315                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1316                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1317                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1318                                 interconnect-names = "qup-core", "qup-config",
1319                                                         "qup-memory";
1320                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1321                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1322                                 dma-names = "tx", "rx";
1323                                 status = "disabled";
1324                         };
1325
1326                         spi6: spi@998000 {
1327                                 compatible = "qcom,geni-spi";
1328                                 reg = <0 0x00998000 0 0x4000>;
1329                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1330                                 clock-names = "se";
1331                                 pinctrl-names = "default";
1332                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1333                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1334                                 #address-cells = <1>;
1335                                 #size-cells = <0>;
1336                                 power-domains = <&rpmhpd SC7280_CX>;
1337                                 operating-points-v2 = <&qup_opp_table>;
1338                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1339                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1340                                 interconnect-names = "qup-core", "qup-config";
1341                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1342                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1343                                 dma-names = "tx", "rx";
1344                                 status = "disabled";
1345                         };
1346
1347                         uart6: serial@998000 {
1348                                 compatible = "qcom,geni-uart";
1349                                 reg = <0 0x00998000 0 0x4000>;
1350                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1351                                 clock-names = "se";
1352                                 pinctrl-names = "default";
1353                                 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1354                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1355                                 power-domains = <&rpmhpd SC7280_CX>;
1356                                 operating-points-v2 = <&qup_opp_table>;
1357                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1358                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1359                                 interconnect-names = "qup-core", "qup-config";
1360                                 status = "disabled";
1361                         };
1362
1363                         i2c7: i2c@99c000 {
1364                                 compatible = "qcom,geni-i2c";
1365                                 reg = <0 0x0099c000 0 0x4000>;
1366                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1367                                 clock-names = "se";
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_i2c7_data_clk>;
1370                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1371                                 #address-cells = <1>;
1372                                 #size-cells = <0>;
1373                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1374                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1375                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1376                                 interconnect-names = "qup-core", "qup-config",
1377                                                         "qup-memory";
1378                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1379                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1380                                 dma-names = "tx", "rx";
1381                                 status = "disabled";
1382                         };
1383
1384                         spi7: spi@99c000 {
1385                                 compatible = "qcom,geni-spi";
1386                                 reg = <0 0x0099c000 0 0x4000>;
1387                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1388                                 clock-names = "se";
1389                                 pinctrl-names = "default";
1390                                 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1391                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1392                                 #address-cells = <1>;
1393                                 #size-cells = <0>;
1394                                 power-domains = <&rpmhpd SC7280_CX>;
1395                                 operating-points-v2 = <&qup_opp_table>;
1396                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1397                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1398                                 interconnect-names = "qup-core", "qup-config";
1399                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1400                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1401                                 dma-names = "tx", "rx";
1402                                 status = "disabled";
1403                         };
1404
1405                         uart7: serial@99c000 {
1406                                 compatible = "qcom,geni-uart";
1407                                 reg = <0 0x0099c000 0 0x4000>;
1408                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1409                                 clock-names = "se";
1410                                 pinctrl-names = "default";
1411                                 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1412                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1413                                 power-domains = <&rpmhpd SC7280_CX>;
1414                                 operating-points-v2 = <&qup_opp_table>;
1415                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1416                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1417                                 interconnect-names = "qup-core", "qup-config";
1418                                 status = "disabled";
1419                         };
1420                 };
1421
1422                 gpi_dma1: dma-controller@a00000 {
1423                         #dma-cells = <3>;
1424                         compatible = "qcom,sc7280-gpi-dma";
1425                         reg = <0 0x00a00000 0 0x60000>;
1426                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1427                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1428                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1429                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1430                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1431                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1432                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1433                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1434                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1435                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1436                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1437                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1438                         dma-channels = <12>;
1439                         dma-channel-mask = <0x1e>;
1440                         iommus = <&apps_smmu 0x56 0x0>;
1441                         status = "disabled";
1442                 };
1443
1444                 qupv3_id_1: geniqup@ac0000 {
1445                         compatible = "qcom,geni-se-qup";
1446                         reg = <0 0x00ac0000 0 0x2000>;
1447                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1448                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1449                         clock-names = "m-ahb", "s-ahb";
1450                         #address-cells = <2>;
1451                         #size-cells = <2>;
1452                         ranges;
1453                         iommus = <&apps_smmu 0x43 0x0>;
1454                         status = "disabled";
1455
1456                         i2c8: i2c@a80000 {
1457                                 compatible = "qcom,geni-i2c";
1458                                 reg = <0 0x00a80000 0 0x4000>;
1459                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1460                                 clock-names = "se";
1461                                 pinctrl-names = "default";
1462                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1463                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1464                                 #address-cells = <1>;
1465                                 #size-cells = <0>;
1466                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1467                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1468                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1469                                 interconnect-names = "qup-core", "qup-config",
1470                                                         "qup-memory";
1471                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1472                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1473                                 dma-names = "tx", "rx";
1474                                 status = "disabled";
1475                         };
1476
1477                         spi8: spi@a80000 {
1478                                 compatible = "qcom,geni-spi";
1479                                 reg = <0 0x00a80000 0 0x4000>;
1480                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1481                                 clock-names = "se";
1482                                 pinctrl-names = "default";
1483                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1484                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1485                                 #address-cells = <1>;
1486                                 #size-cells = <0>;
1487                                 power-domains = <&rpmhpd SC7280_CX>;
1488                                 operating-points-v2 = <&qup_opp_table>;
1489                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1490                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1491                                 interconnect-names = "qup-core", "qup-config";
1492                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1493                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1494                                 dma-names = "tx", "rx";
1495                                 status = "disabled";
1496                         };
1497
1498                         uart8: serial@a80000 {
1499                                 compatible = "qcom,geni-uart";
1500                                 reg = <0 0x00a80000 0 0x4000>;
1501                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1502                                 clock-names = "se";
1503                                 pinctrl-names = "default";
1504                                 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1505                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1506                                 power-domains = <&rpmhpd SC7280_CX>;
1507                                 operating-points-v2 = <&qup_opp_table>;
1508                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1509                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1510                                 interconnect-names = "qup-core", "qup-config";
1511                                 status = "disabled";
1512                         };
1513
1514                         i2c9: i2c@a84000 {
1515                                 compatible = "qcom,geni-i2c";
1516                                 reg = <0 0x00a84000 0 0x4000>;
1517                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1518                                 clock-names = "se";
1519                                 pinctrl-names = "default";
1520                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1521                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1522                                 #address-cells = <1>;
1523                                 #size-cells = <0>;
1524                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1525                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1526                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1527                                 interconnect-names = "qup-core", "qup-config",
1528                                                         "qup-memory";
1529                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1531                                 dma-names = "tx", "rx";
1532                                 status = "disabled";
1533                         };
1534
1535                         spi9: spi@a84000 {
1536                                 compatible = "qcom,geni-spi";
1537                                 reg = <0 0x00a84000 0 0x4000>;
1538                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1539                                 clock-names = "se";
1540                                 pinctrl-names = "default";
1541                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1542                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1543                                 #address-cells = <1>;
1544                                 #size-cells = <0>;
1545                                 power-domains = <&rpmhpd SC7280_CX>;
1546                                 operating-points-v2 = <&qup_opp_table>;
1547                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1548                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1549                                 interconnect-names = "qup-core", "qup-config";
1550                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1551                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1552                                 dma-names = "tx", "rx";
1553                                 status = "disabled";
1554                         };
1555
1556                         uart9: serial@a84000 {
1557                                 compatible = "qcom,geni-uart";
1558                                 reg = <0 0x00a84000 0 0x4000>;
1559                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1560                                 clock-names = "se";
1561                                 pinctrl-names = "default";
1562                                 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1563                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1564                                 power-domains = <&rpmhpd SC7280_CX>;
1565                                 operating-points-v2 = <&qup_opp_table>;
1566                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1567                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1568                                 interconnect-names = "qup-core", "qup-config";
1569                                 status = "disabled";
1570                         };
1571
1572                         i2c10: i2c@a88000 {
1573                                 compatible = "qcom,geni-i2c";
1574                                 reg = <0 0x00a88000 0 0x4000>;
1575                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1576                                 clock-names = "se";
1577                                 pinctrl-names = "default";
1578                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1579                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1583                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1584                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1585                                 interconnect-names = "qup-core", "qup-config",
1586                                                         "qup-memory";
1587                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1588                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1589                                 dma-names = "tx", "rx";
1590                                 status = "disabled";
1591                         };
1592
1593                         spi10: spi@a88000 {
1594                                 compatible = "qcom,geni-spi";
1595                                 reg = <0 0x00a88000 0 0x4000>;
1596                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1597                                 clock-names = "se";
1598                                 pinctrl-names = "default";
1599                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1600                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1601                                 #address-cells = <1>;
1602                                 #size-cells = <0>;
1603                                 power-domains = <&rpmhpd SC7280_CX>;
1604                                 operating-points-v2 = <&qup_opp_table>;
1605                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1606                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1607                                 interconnect-names = "qup-core", "qup-config";
1608                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1609                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1610                                 dma-names = "tx", "rx";
1611                                 status = "disabled";
1612                         };
1613
1614                         uart10: serial@a88000 {
1615                                 compatible = "qcom,geni-uart";
1616                                 reg = <0 0x00a88000 0 0x4000>;
1617                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1618                                 clock-names = "se";
1619                                 pinctrl-names = "default";
1620                                 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1621                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1622                                 power-domains = <&rpmhpd SC7280_CX>;
1623                                 operating-points-v2 = <&qup_opp_table>;
1624                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1625                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1626                                 interconnect-names = "qup-core", "qup-config";
1627                                 status = "disabled";
1628                         };
1629
1630                         i2c11: i2c@a8c000 {
1631                                 compatible = "qcom,geni-i2c";
1632                                 reg = <0 0x00a8c000 0 0x4000>;
1633                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1634                                 clock-names = "se";
1635                                 pinctrl-names = "default";
1636                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1637                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1638                                 #address-cells = <1>;
1639                                 #size-cells = <0>;
1640                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1641                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1642                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1643                                 interconnect-names = "qup-core", "qup-config",
1644                                                         "qup-memory";
1645                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1646                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1647                                 dma-names = "tx", "rx";
1648                                 status = "disabled";
1649                         };
1650
1651                         spi11: spi@a8c000 {
1652                                 compatible = "qcom,geni-spi";
1653                                 reg = <0 0x00a8c000 0 0x4000>;
1654                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1655                                 clock-names = "se";
1656                                 pinctrl-names = "default";
1657                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1658                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1659                                 #address-cells = <1>;
1660                                 #size-cells = <0>;
1661                                 power-domains = <&rpmhpd SC7280_CX>;
1662                                 operating-points-v2 = <&qup_opp_table>;
1663                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1664                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1665                                 interconnect-names = "qup-core", "qup-config";
1666                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1667                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1668                                 dma-names = "tx", "rx";
1669                                 status = "disabled";
1670                         };
1671
1672                         uart11: serial@a8c000 {
1673                                 compatible = "qcom,geni-uart";
1674                                 reg = <0 0x00a8c000 0 0x4000>;
1675                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1676                                 clock-names = "se";
1677                                 pinctrl-names = "default";
1678                                 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1679                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1680                                 power-domains = <&rpmhpd SC7280_CX>;
1681                                 operating-points-v2 = <&qup_opp_table>;
1682                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1683                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1684                                 interconnect-names = "qup-core", "qup-config";
1685                                 status = "disabled";
1686                         };
1687
1688                         i2c12: i2c@a90000 {
1689                                 compatible = "qcom,geni-i2c";
1690                                 reg = <0 0x00a90000 0 0x4000>;
1691                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1692                                 clock-names = "se";
1693                                 pinctrl-names = "default";
1694                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1695                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1696                                 #address-cells = <1>;
1697                                 #size-cells = <0>;
1698                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1699                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1700                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1701                                 interconnect-names = "qup-core", "qup-config",
1702                                                         "qup-memory";
1703                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1704                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1705                                 dma-names = "tx", "rx";
1706                                 status = "disabled";
1707                         };
1708
1709                         spi12: spi@a90000 {
1710                                 compatible = "qcom,geni-spi";
1711                                 reg = <0 0x00a90000 0 0x4000>;
1712                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1713                                 clock-names = "se";
1714                                 pinctrl-names = "default";
1715                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1716                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1717                                 #address-cells = <1>;
1718                                 #size-cells = <0>;
1719                                 power-domains = <&rpmhpd SC7280_CX>;
1720                                 operating-points-v2 = <&qup_opp_table>;
1721                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1722                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1723                                 interconnect-names = "qup-core", "qup-config";
1724                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1725                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1726                                 dma-names = "tx", "rx";
1727                                 status = "disabled";
1728                         };
1729
1730                         uart12: serial@a90000 {
1731                                 compatible = "qcom,geni-uart";
1732                                 reg = <0 0x00a90000 0 0x4000>;
1733                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1734                                 clock-names = "se";
1735                                 pinctrl-names = "default";
1736                                 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1737                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1738                                 power-domains = <&rpmhpd SC7280_CX>;
1739                                 operating-points-v2 = <&qup_opp_table>;
1740                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1741                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1742                                 interconnect-names = "qup-core", "qup-config";
1743                                 status = "disabled";
1744                         };
1745
1746                         i2c13: i2c@a94000 {
1747                                 compatible = "qcom,geni-i2c";
1748                                 reg = <0 0x00a94000 0 0x4000>;
1749                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1750                                 clock-names = "se";
1751                                 pinctrl-names = "default";
1752                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1753                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1754                                 #address-cells = <1>;
1755                                 #size-cells = <0>;
1756                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1757                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1758                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1759                                 interconnect-names = "qup-core", "qup-config",
1760                                                         "qup-memory";
1761                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1762                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1763                                 dma-names = "tx", "rx";
1764                                 status = "disabled";
1765                         };
1766
1767                         spi13: spi@a94000 {
1768                                 compatible = "qcom,geni-spi";
1769                                 reg = <0 0x00a94000 0 0x4000>;
1770                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1771                                 clock-names = "se";
1772                                 pinctrl-names = "default";
1773                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1774                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1775                                 #address-cells = <1>;
1776                                 #size-cells = <0>;
1777                                 power-domains = <&rpmhpd SC7280_CX>;
1778                                 operating-points-v2 = <&qup_opp_table>;
1779                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1780                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1781                                 interconnect-names = "qup-core", "qup-config";
1782                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1783                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1784                                 dma-names = "tx", "rx";
1785                                 status = "disabled";
1786                         };
1787
1788                         uart13: serial@a94000 {
1789                                 compatible = "qcom,geni-uart";
1790                                 reg = <0 0x00a94000 0 0x4000>;
1791                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1792                                 clock-names = "se";
1793                                 pinctrl-names = "default";
1794                                 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1795                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1796                                 power-domains = <&rpmhpd SC7280_CX>;
1797                                 operating-points-v2 = <&qup_opp_table>;
1798                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1799                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1800                                 interconnect-names = "qup-core", "qup-config";
1801                                 status = "disabled";
1802                         };
1803
1804                         i2c14: i2c@a98000 {
1805                                 compatible = "qcom,geni-i2c";
1806                                 reg = <0 0x00a98000 0 0x4000>;
1807                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1808                                 clock-names = "se";
1809                                 pinctrl-names = "default";
1810                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1811                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1812                                 #address-cells = <1>;
1813                                 #size-cells = <0>;
1814                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1815                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1816                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1817                                 interconnect-names = "qup-core", "qup-config",
1818                                                         "qup-memory";
1819                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1820                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1821                                 dma-names = "tx", "rx";
1822                                 status = "disabled";
1823                         };
1824
1825                         spi14: spi@a98000 {
1826                                 compatible = "qcom,geni-spi";
1827                                 reg = <0 0x00a98000 0 0x4000>;
1828                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1829                                 clock-names = "se";
1830                                 pinctrl-names = "default";
1831                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1832                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1833                                 #address-cells = <1>;
1834                                 #size-cells = <0>;
1835                                 power-domains = <&rpmhpd SC7280_CX>;
1836                                 operating-points-v2 = <&qup_opp_table>;
1837                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1838                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1839                                 interconnect-names = "qup-core", "qup-config";
1840                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1841                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1842                                 dma-names = "tx", "rx";
1843                                 status = "disabled";
1844                         };
1845
1846                         uart14: serial@a98000 {
1847                                 compatible = "qcom,geni-uart";
1848                                 reg = <0 0x00a98000 0 0x4000>;
1849                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1850                                 clock-names = "se";
1851                                 pinctrl-names = "default";
1852                                 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1853                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1854                                 power-domains = <&rpmhpd SC7280_CX>;
1855                                 operating-points-v2 = <&qup_opp_table>;
1856                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1857                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1858                                 interconnect-names = "qup-core", "qup-config";
1859                                 status = "disabled";
1860                         };
1861
1862                         i2c15: i2c@a9c000 {
1863                                 compatible = "qcom,geni-i2c";
1864                                 reg = <0 0x00a9c000 0 0x4000>;
1865                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1866                                 clock-names = "se";
1867                                 pinctrl-names = "default";
1868                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1869                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1870                                 #address-cells = <1>;
1871                                 #size-cells = <0>;
1872                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1873                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1874                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1875                                 interconnect-names = "qup-core", "qup-config",
1876                                                         "qup-memory";
1877                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1878                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1879                                 dma-names = "tx", "rx";
1880                                 status = "disabled";
1881                         };
1882
1883                         spi15: spi@a9c000 {
1884                                 compatible = "qcom,geni-spi";
1885                                 reg = <0 0x00a9c000 0 0x4000>;
1886                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1887                                 clock-names = "se";
1888                                 pinctrl-names = "default";
1889                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1890                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1891                                 #address-cells = <1>;
1892                                 #size-cells = <0>;
1893                                 power-domains = <&rpmhpd SC7280_CX>;
1894                                 operating-points-v2 = <&qup_opp_table>;
1895                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1896                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1897                                 interconnect-names = "qup-core", "qup-config";
1898                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1899                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1900                                 dma-names = "tx", "rx";
1901                                 status = "disabled";
1902                         };
1903
1904                         uart15: serial@a9c000 {
1905                                 compatible = "qcom,geni-uart";
1906                                 reg = <0 0x00a9c000 0 0x4000>;
1907                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1908                                 clock-names = "se";
1909                                 pinctrl-names = "default";
1910                                 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1911                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1912                                 power-domains = <&rpmhpd SC7280_CX>;
1913                                 operating-points-v2 = <&qup_opp_table>;
1914                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1915                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1916                                 interconnect-names = "qup-core", "qup-config";
1917                                 status = "disabled";
1918                         };
1919                 };
1920
1921                 cnoc2: interconnect@1500000 {
1922                         reg = <0 0x01500000 0 0x1000>;
1923                         compatible = "qcom,sc7280-cnoc2";
1924                         #interconnect-cells = <2>;
1925                         qcom,bcm-voters = <&apps_bcm_voter>;
1926                 };
1927
1928                 cnoc3: interconnect@1502000 {
1929                         reg = <0 0x01502000 0 0x1000>;
1930                         compatible = "qcom,sc7280-cnoc3";
1931                         #interconnect-cells = <2>;
1932                         qcom,bcm-voters = <&apps_bcm_voter>;
1933                 };
1934
1935                 mc_virt: interconnect@1580000 {
1936                         reg = <0 0x01580000 0 0x4>;
1937                         compatible = "qcom,sc7280-mc-virt";
1938                         #interconnect-cells = <2>;
1939                         qcom,bcm-voters = <&apps_bcm_voter>;
1940                 };
1941
1942                 system_noc: interconnect@1680000 {
1943                         reg = <0 0x01680000 0 0x15480>;
1944                         compatible = "qcom,sc7280-system-noc";
1945                         #interconnect-cells = <2>;
1946                         qcom,bcm-voters = <&apps_bcm_voter>;
1947                 };
1948
1949                 aggre1_noc: interconnect@16e0000 {
1950                         compatible = "qcom,sc7280-aggre1-noc";
1951                         reg = <0 0x016e0000 0 0x1c080>;
1952                         #interconnect-cells = <2>;
1953                         qcom,bcm-voters = <&apps_bcm_voter>;
1954                 };
1955
1956                 aggre2_noc: interconnect@1700000 {
1957                         reg = <0 0x01700000 0 0x2b080>;
1958                         compatible = "qcom,sc7280-aggre2-noc";
1959                         #interconnect-cells = <2>;
1960                         qcom,bcm-voters = <&apps_bcm_voter>;
1961                 };
1962
1963                 mmss_noc: interconnect@1740000 {
1964                         reg = <0 0x01740000 0 0x1e080>;
1965                         compatible = "qcom,sc7280-mmss-noc";
1966                         #interconnect-cells = <2>;
1967                         qcom,bcm-voters = <&apps_bcm_voter>;
1968                 };
1969
1970                 wifi: wifi@17a10040 {
1971                         compatible = "qcom,wcn6750-wifi";
1972                         reg = <0 0x17a10040 0 0x0>;
1973                         iommus = <&apps_smmu 0x1c00 0x1>;
1974                         interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
1975                                      <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
1976                                      <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
1977                                      <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
1978                                      <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
1979                                      <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
1980                                      <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
1981                                      <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
1982                                      <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
1983                                      <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
1984                                      <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
1985                                      <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
1986                                      <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
1987                                      <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
1988                                      <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
1989                                      <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
1990                                      <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
1991                                      <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
1992                                      <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
1993                                      <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
1994                                      <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
1995                                      <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
1996                                      <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
1997                                      <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
1998                                      <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
1999                                      <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
2000                                      <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
2001                                      <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
2002                                      <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
2003                                      <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2004                                      <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2005                                      <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2006                         qcom,rproc = <&remoteproc_wpss>;
2007                         memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2008                         status = "disabled";
2009                 };
2010
2011                 pcie1: pci@1c08000 {
2012                         compatible = "qcom,pcie-sc7280";
2013                         reg = <0 0x01c08000 0 0x3000>,
2014                               <0 0x40000000 0 0xf1d>,
2015                               <0 0x40000f20 0 0xa8>,
2016                               <0 0x40001000 0 0x1000>,
2017                               <0 0x40100000 0 0x100000>;
2018
2019                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2020                         device_type = "pci";
2021                         linux,pci-domain = <1>;
2022                         bus-range = <0x00 0xff>;
2023                         num-lanes = <2>;
2024
2025                         #address-cells = <3>;
2026                         #size-cells = <2>;
2027
2028                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2029                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2030
2031                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2032                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2033                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2034                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2035                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2036                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2037                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2038                                      <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2039                         interrupt-names = "msi0", "msi1", "msi2", "msi3",
2040                                           "msi4", "msi5", "msi6", "msi7";
2041                         #interrupt-cells = <1>;
2042                         interrupt-map-mask = <0 0 0 0x7>;
2043                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2044                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2045                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2046                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2047
2048                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2049                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2050                                  <&pcie1_lane>,
2051                                  <&rpmhcc RPMH_CXO_CLK>,
2052                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2053                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2054                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2055                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2056                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2057                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2058                                  <&gcc GCC_DDRSS_PCIE_SF_CLK>,
2059                                  <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2060                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
2061
2062                         clock-names = "pipe",
2063                                       "pipe_mux",
2064                                       "phy_pipe",
2065                                       "ref",
2066                                       "aux",
2067                                       "cfg",
2068                                       "bus_master",
2069                                       "bus_slave",
2070                                       "slave_q2a",
2071                                       "tbu",
2072                                       "ddrss_sf_tbu",
2073                                       "aggre0",
2074                                       "aggre1";
2075
2076                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2077                         assigned-clock-rates = <19200000>;
2078
2079                         resets = <&gcc GCC_PCIE_1_BCR>;
2080                         reset-names = "pci";
2081
2082                         power-domains = <&gcc GCC_PCIE_1_GDSC>;
2083
2084                         phys = <&pcie1_lane>;
2085                         phy-names = "pciephy";
2086
2087                         pinctrl-names = "default";
2088                         pinctrl-0 = <&pcie1_clkreq_n>;
2089
2090                         dma-coherent;
2091
2092                         iommus = <&apps_smmu 0x1c80 0x1>;
2093
2094                         iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2095                                     <0x100 &apps_smmu 0x1c81 0x1>;
2096
2097                         status = "disabled";
2098                 };
2099
2100                 pcie1_phy: phy@1c0e000 {
2101                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2102                         reg = <0 0x01c0e000 0 0x1c0>;
2103                         #address-cells = <2>;
2104                         #size-cells = <2>;
2105                         ranges;
2106                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2107                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2108                                  <&gcc GCC_PCIE_CLKREF_EN>,
2109                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2110                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2111
2112                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2113                         reset-names = "phy";
2114
2115                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2116                         assigned-clock-rates = <100000000>;
2117
2118                         status = "disabled";
2119
2120                         pcie1_lane: phy@1c0e200 {
2121                                 reg = <0 0x01c0e200 0 0x170>,
2122                                       <0 0x01c0e400 0 0x200>,
2123                                       <0 0x01c0ea00 0 0x1f0>,
2124                                       <0 0x01c0e600 0 0x170>,
2125                                       <0 0x01c0e800 0 0x200>,
2126                                       <0 0x01c0ee00 0 0xf4>;
2127                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2128                                 clock-names = "pipe0";
2129
2130                                 #phy-cells = <0>;
2131                                 #clock-cells = <0>;
2132                                 clock-output-names = "pcie_1_pipe_clk";
2133                         };
2134                 };
2135
2136                 ipa: ipa@1e40000 {
2137                         compatible = "qcom,sc7280-ipa";
2138
2139                         iommus = <&apps_smmu 0x480 0x0>,
2140                                  <&apps_smmu 0x482 0x0>;
2141                         reg = <0 0x1e40000 0 0x8000>,
2142                               <0 0x1e50000 0 0x4ad0>,
2143                               <0 0x1e04000 0 0x23000>;
2144                         reg-names = "ipa-reg",
2145                                     "ipa-shared",
2146                                     "gsi";
2147
2148                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2149                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2150                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2151                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2152                         interrupt-names = "ipa",
2153                                           "gsi",
2154                                           "ipa-clock-query",
2155                                           "ipa-setup-ready";
2156
2157                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2158                         clock-names = "core";
2159
2160                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2161                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2162                         interconnect-names = "memory",
2163                                              "config";
2164
2165                         qcom,qmp = <&aoss_qmp>;
2166
2167                         qcom,smem-states = <&ipa_smp2p_out 0>,
2168                                            <&ipa_smp2p_out 1>;
2169                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2170                                                 "ipa-clock-enabled";
2171
2172                         status = "disabled";
2173                 };
2174
2175                 tcsr_mutex: hwlock@1f40000 {
2176                         compatible = "qcom,tcsr-mutex";
2177                         reg = <0 0x01f40000 0 0x20000>;
2178                         #hwlock-cells = <1>;
2179                 };
2180
2181                 tcsr_1: syscon@1f60000 {
2182                         compatible = "qcom,sc7280-tcsr", "syscon";
2183                         reg = <0 0x01f60000 0 0x20000>;
2184                 };
2185
2186                 tcsr_2: syscon@1fc0000 {
2187                         compatible = "qcom,sc7280-tcsr", "syscon";
2188                         reg = <0 0x01fc0000 0 0x30000>;
2189                 };
2190
2191                 lpasscc: lpasscc@3000000 {
2192                         compatible = "qcom,sc7280-lpasscc";
2193                         reg = <0 0x03000000 0 0x40>,
2194                               <0 0x03c04000 0 0x4>;
2195                         reg-names = "qdsp6ss", "top_cc";
2196                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2197                         clock-names = "iface";
2198                         #clock-cells = <1>;
2199                         status = "reserved"; /* Owned by ADSP firmware */
2200                 };
2201
2202                 lpass_rx_macro: codec@3200000 {
2203                         compatible = "qcom,sc7280-lpass-rx-macro";
2204                         reg = <0 0x03200000 0 0x1000>;
2205
2206                         pinctrl-names = "default";
2207                         pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2208
2209                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2210                                  <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2211                                  <&lpass_va_macro>;
2212                         clock-names = "mclk", "npl", "fsgen";
2213
2214                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2215                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2216                         power-domain-names = "macro", "dcodec";
2217
2218                         #clock-cells = <0>;
2219                         #sound-dai-cells = <1>;
2220
2221                         status = "disabled";
2222                 };
2223
2224                 swr0: soundwire@3210000 {
2225                         compatible = "qcom,soundwire-v1.6.0";
2226                         reg = <0 0x03210000 0 0x2000>;
2227
2228                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2229                         clocks = <&lpass_rx_macro>;
2230                         clock-names = "iface";
2231
2232                         qcom,din-ports = <0>;
2233                         qcom,dout-ports = <5>;
2234
2235                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2236                         reset-names = "swr_audio_cgcr";
2237
2238                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2239                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2240                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2241                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2242                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2243                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2244                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2245                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2246                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2247
2248                         #sound-dai-cells = <1>;
2249                         #address-cells = <2>;
2250                         #size-cells = <0>;
2251
2252                         status = "disabled";
2253                 };
2254
2255                 lpass_tx_macro: codec@3220000 {
2256                         compatible = "qcom,sc7280-lpass-tx-macro";
2257                         reg = <0 0x03220000 0 0x1000>;
2258
2259                         pinctrl-names = "default";
2260                         pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2261
2262                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2263                                  <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2264                                  <&lpass_va_macro>;
2265                         clock-names = "mclk", "npl", "fsgen";
2266
2267                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2268                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2269                         power-domain-names = "macro", "dcodec";
2270
2271                         #clock-cells = <0>;
2272                         #sound-dai-cells = <1>;
2273
2274                         status = "disabled";
2275                 };
2276
2277                 swr1: soundwire@3230000 {
2278                         compatible = "qcom,soundwire-v1.6.0";
2279                         reg = <0 0x03230000 0 0x2000>;
2280
2281                         interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2282                                               <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
2283                         clocks = <&lpass_tx_macro>;
2284                         clock-names = "iface";
2285
2286                         qcom,din-ports = <3>;
2287                         qcom,dout-ports = <0>;
2288
2289                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2290                         reset-names = "swr_audio_cgcr";
2291
2292                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x03 0x03>;
2293                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02>;
2294                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00>;
2295                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff>;
2296                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff>;
2297                         qcom,ports-word-length =        /bits/ 8 <0xff 0x00 0xff>;
2298                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff>;
2299                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff>;
2300                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00>;
2301                         qcom,port-offset = <1>;
2302
2303                         #sound-dai-cells = <1>;
2304                         #address-cells = <2>;
2305                         #size-cells = <0>;
2306
2307                         status = "disabled";
2308                 };
2309
2310                 lpass_audiocc: clock-controller@3300000 {
2311                         compatible = "qcom,sc7280-lpassaudiocc";
2312                         reg = <0 0x03300000 0 0x30000>,
2313                               <0 0x032a9000 0 0x1000>;
2314                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2315                                <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2316                         clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2317                         power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2318                         #clock-cells = <1>;
2319                         #power-domain-cells = <1>;
2320                         #reset-cells = <1>;
2321                 };
2322
2323                 lpass_va_macro: codec@3370000 {
2324                         compatible = "qcom,sc7280-lpass-va-macro";
2325                         reg = <0 0x03370000 0 0x1000>;
2326
2327                         pinctrl-names = "default";
2328                         pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2329
2330                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
2331                         clock-names = "mclk";
2332
2333                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2334                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2335                         power-domain-names = "macro", "dcodec";
2336
2337                         #clock-cells = <0>;
2338                         #sound-dai-cells = <1>;
2339
2340                         status = "disabled";
2341                 };
2342
2343                 lpass_aon: clock-controller@3380000 {
2344                         compatible = "qcom,sc7280-lpassaoncc";
2345                         reg = <0 0x03380000 0 0x30000>;
2346                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2347                                <&rpmhcc RPMH_CXO_CLK_A>,
2348                                <&lpass_core LPASS_CORE_CC_CORE_CLK>;
2349                         clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2350                         #clock-cells = <1>;
2351                         #power-domain-cells = <1>;
2352                         status = "reserved"; /* Owned by ADSP firmware */
2353                 };
2354
2355                 lpass_core: clock-controller@3900000 {
2356                         compatible = "qcom,sc7280-lpasscorecc";
2357                         reg = <0 0x03900000 0 0x50000>;
2358                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2359                         clock-names = "bi_tcxo";
2360                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2361                         #clock-cells = <1>;
2362                         #power-domain-cells = <1>;
2363                         status = "reserved"; /* Owned by ADSP firmware */
2364                 };
2365
2366                 lpass_cpu: audio@3987000 {
2367                         compatible = "qcom,sc7280-lpass-cpu";
2368
2369                         reg = <0 0x03987000 0 0x68000>,
2370                               <0 0x03b00000 0 0x29000>,
2371                               <0 0x03260000 0 0xc000>,
2372                               <0 0x03280000 0 0x29000>,
2373                               <0 0x03340000 0 0x29000>,
2374                               <0 0x0336c000 0 0x3000>;
2375                         reg-names = "lpass-hdmiif",
2376                                     "lpass-lpaif",
2377                                     "lpass-rxtx-cdc-dma-lpm",
2378                                     "lpass-rxtx-lpaif",
2379                                     "lpass-va-lpaif",
2380                                     "lpass-va-cdc-dma-lpm";
2381
2382                         iommus = <&apps_smmu 0x1820 0>,
2383                                  <&apps_smmu 0x1821 0>,
2384                                  <&apps_smmu 0x1832 0>;
2385
2386                         power-domains = <&rpmhpd SC7280_LCX>;
2387                         power-domain-names = "lcx";
2388                         required-opps = <&rpmhpd_opp_nom>;
2389
2390                         clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
2391                                  <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
2392                                  <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
2393                                  <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
2394                                  <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
2395                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2396                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2397                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2398                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
2399                                  <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
2400                         clock-names = "aon_cc_audio_hm_h",
2401                                       "audio_cc_ext_mclk0",
2402                                       "core_cc_sysnoc_mport_core",
2403                                       "core_cc_ext_if0_ibit",
2404                                       "core_cc_ext_if1_ibit",
2405                                       "audio_cc_codec_mem",
2406                                       "audio_cc_codec_mem0",
2407                                       "audio_cc_codec_mem1",
2408                                       "audio_cc_codec_mem2",
2409                                       "aon_cc_va_mem0";
2410
2411                         #sound-dai-cells = <1>;
2412                         #address-cells = <1>;
2413                         #size-cells = <0>;
2414
2415                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2416                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2417                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
2418                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
2419                         interrupt-names = "lpass-irq-lpaif",
2420                                           "lpass-irq-hdmi",
2421                                           "lpass-irq-vaif",
2422                                           "lpass-irq-rxtxif";
2423
2424                         status = "disabled";
2425                 };
2426
2427                 lpass_hm: clock-controller@3c00000 {
2428                         compatible = "qcom,sc7280-lpasshm";
2429                         reg = <0 0x3c00000 0 0x28>;
2430                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2431                         clock-names = "bi_tcxo";
2432                         #clock-cells = <1>;
2433                         #power-domain-cells = <1>;
2434                         status = "reserved"; /* Owned by ADSP firmware */
2435                 };
2436
2437                 lpass_ag_noc: interconnect@3c40000 {
2438                         reg = <0 0x03c40000 0 0xf080>;
2439                         compatible = "qcom,sc7280-lpass-ag-noc";
2440                         #interconnect-cells = <2>;
2441                         qcom,bcm-voters = <&apps_bcm_voter>;
2442                 };
2443
2444                 lpass_tlmm: pinctrl@33c0000 {
2445                         compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2446                         reg = <0 0x033c0000 0x0 0x20000>,
2447                                 <0 0x03550000 0x0 0x10000>;
2448                         qcom,adsp-bypass-mode;
2449                         gpio-controller;
2450                         #gpio-cells = <2>;
2451                         gpio-ranges = <&lpass_tlmm 0 0 15>;
2452
2453                         #clock-cells = <1>;
2454
2455                         lpass_dmic01_clk: dmic01-clk {
2456                                 pins = "gpio6";
2457                                 function = "dmic1_clk";
2458                         };
2459
2460                         lpass_dmic01_clk_sleep: dmic01-clk-sleep {
2461                                 pins = "gpio6";
2462                                 function = "dmic1_clk";
2463                         };
2464
2465                         lpass_dmic01_data: dmic01-data {
2466                                 pins = "gpio7";
2467                                 function = "dmic1_data";
2468                         };
2469
2470                         lpass_dmic01_data_sleep: dmic01-data-sleep {
2471                                 pins = "gpio7";
2472                                 function = "dmic1_data";
2473                         };
2474
2475                         lpass_dmic23_clk: dmic23-clk {
2476                                 pins = "gpio8";
2477                                 function = "dmic2_clk";
2478                         };
2479
2480                         lpass_dmic23_clk_sleep: dmic23-clk-sleep {
2481                                 pins = "gpio8";
2482                                 function = "dmic2_clk";
2483                         };
2484
2485                         lpass_dmic23_data: dmic23-data {
2486                                 pins = "gpio9";
2487                                 function = "dmic2_data";
2488                         };
2489
2490                         lpass_dmic23_data_sleep: dmic23-data-sleep {
2491                                 pins = "gpio9";
2492                                 function = "dmic2_data";
2493                         };
2494
2495                         lpass_rx_swr_clk: rx-swr-clk {
2496                                 pins = "gpio3";
2497                                 function = "swr_rx_clk";
2498                         };
2499
2500                         lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
2501                                 pins = "gpio3";
2502                                 function = "swr_rx_clk";
2503                         };
2504
2505                         lpass_rx_swr_data: rx-swr-data {
2506                                 pins = "gpio4", "gpio5";
2507                                 function = "swr_rx_data";
2508                         };
2509
2510                         lpass_rx_swr_data_sleep: rx-swr-data-sleep {
2511                                 pins = "gpio4", "gpio5";
2512                                 function = "swr_rx_data";
2513                         };
2514
2515                         lpass_tx_swr_clk: tx-swr-clk {
2516                                 pins = "gpio0";
2517                                 function = "swr_tx_clk";
2518                         };
2519
2520                         lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
2521                                 pins = "gpio0";
2522                                 function = "swr_tx_clk";
2523                         };
2524
2525                         lpass_tx_swr_data: tx-swr-data {
2526                                 pins = "gpio1", "gpio2", "gpio14";
2527                                 function = "swr_tx_data";
2528                         };
2529
2530                         lpass_tx_swr_data_sleep: tx-swr-data-sleep {
2531                                 pins = "gpio1", "gpio2", "gpio14";
2532                                 function = "swr_tx_data";
2533                         };
2534                 };
2535
2536                 gpu: gpu@3d00000 {
2537                         compatible = "qcom,adreno-635.0", "qcom,adreno";
2538                         reg = <0 0x03d00000 0 0x40000>,
2539                               <0 0x03d9e000 0 0x1000>,
2540                               <0 0x03d61000 0 0x800>;
2541                         reg-names = "kgsl_3d0_reg_memory",
2542                                     "cx_mem",
2543                                     "cx_dbgc";
2544                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2545                         iommus = <&adreno_smmu 0 0x400>,
2546                                  <&adreno_smmu 1 0x400>;
2547                         operating-points-v2 = <&gpu_opp_table>;
2548                         qcom,gmu = <&gmu>;
2549                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2550                         interconnect-names = "gfx-mem";
2551                         #cooling-cells = <2>;
2552
2553                         nvmem-cells = <&gpu_speed_bin>;
2554                         nvmem-cell-names = "speed_bin";
2555
2556                         gpu_opp_table: opp-table {
2557                                 compatible = "operating-points-v2";
2558
2559                                 opp-315000000 {
2560                                         opp-hz = /bits/ 64 <315000000>;
2561                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2562                                         opp-peak-kBps = <1804000>;
2563                                         opp-supported-hw = <0x03>;
2564                                 };
2565
2566                                 opp-450000000 {
2567                                         opp-hz = /bits/ 64 <450000000>;
2568                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2569                                         opp-peak-kBps = <4068000>;
2570                                         opp-supported-hw = <0x03>;
2571                                 };
2572
2573                                 /* Only applicable for SKUs which has 550Mhz as Fmax */
2574                                 opp-550000000-0 {
2575                                         opp-hz = /bits/ 64 <550000000>;
2576                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2577                                         opp-peak-kBps = <8368000>;
2578                                         opp-supported-hw = <0x01>;
2579                                 };
2580
2581                                 opp-550000000-1 {
2582                                         opp-hz = /bits/ 64 <550000000>;
2583                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2584                                         opp-peak-kBps = <6832000>;
2585                                         opp-supported-hw = <0x02>;
2586                                 };
2587
2588                                 opp-608000000 {
2589                                         opp-hz = /bits/ 64 <608000000>;
2590                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2591                                         opp-peak-kBps = <8368000>;
2592                                         opp-supported-hw = <0x02>;
2593                                 };
2594
2595                                 opp-700000000 {
2596                                         opp-hz = /bits/ 64 <700000000>;
2597                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2598                                         opp-peak-kBps = <8532000>;
2599                                         opp-supported-hw = <0x02>;
2600                                 };
2601
2602                                 opp-812000000 {
2603                                         opp-hz = /bits/ 64 <812000000>;
2604                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2605                                         opp-peak-kBps = <8532000>;
2606                                         opp-supported-hw = <0x02>;
2607                                 };
2608
2609                                 opp-840000000 {
2610                                         opp-hz = /bits/ 64 <840000000>;
2611                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2612                                         opp-peak-kBps = <8532000>;
2613                                         opp-supported-hw = <0x02>;
2614                                 };
2615
2616                                 opp-900000000 {
2617                                         opp-hz = /bits/ 64 <900000000>;
2618                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2619                                         opp-peak-kBps = <8532000>;
2620                                         opp-supported-hw = <0x02>;
2621                                 };
2622                         };
2623                 };
2624
2625                 gmu: gmu@3d6a000 {
2626                         compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2627                         reg = <0 0x03d6a000 0 0x34000>,
2628                                 <0 0x3de0000 0 0x10000>,
2629                                 <0 0x0b290000 0 0x10000>;
2630                         reg-names = "gmu", "rscc", "gmu_pdc";
2631                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2632                                         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2633                         interrupt-names = "hfi", "gmu";
2634                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2635                                  <&gpucc GPU_CC_CXO_CLK>,
2636                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2637                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2638                                  <&gpucc GPU_CC_AHB_CLK>,
2639                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2640                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2641                         clock-names = "gmu",
2642                                       "cxo",
2643                                       "axi",
2644                                       "memnoc",
2645                                       "ahb",
2646                                       "hub",
2647                                       "smmu_vote";
2648                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2649                                         <&gpucc GPU_CC_GX_GDSC>;
2650                         power-domain-names = "cx",
2651                                              "gx";
2652                         iommus = <&adreno_smmu 5 0x400>;
2653                         operating-points-v2 = <&gmu_opp_table>;
2654
2655                         gmu_opp_table: opp-table {
2656                                 compatible = "operating-points-v2";
2657
2658                                 opp-200000000 {
2659                                         opp-hz = /bits/ 64 <200000000>;
2660                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2661                                 };
2662                         };
2663                 };
2664
2665                 gpucc: clock-controller@3d90000 {
2666                         compatible = "qcom,sc7280-gpucc";
2667                         reg = <0 0x03d90000 0 0x9000>;
2668                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2669                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2670                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2671                         clock-names = "bi_tcxo",
2672                                       "gcc_gpu_gpll0_clk_src",
2673                                       "gcc_gpu_gpll0_div_clk_src";
2674                         #clock-cells = <1>;
2675                         #reset-cells = <1>;
2676                         #power-domain-cells = <1>;
2677                 };
2678
2679                 adreno_smmu: iommu@3da0000 {
2680                         compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2681                         reg = <0 0x03da0000 0 0x20000>;
2682                         #iommu-cells = <2>;
2683                         #global-interrupts = <2>;
2684                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2685                                         <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2686                                         <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2687                                         <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2688                                         <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2689                                         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2690                                         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2691                                         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2692                                         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2693                                         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2694                                         <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2695                                         <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2696
2697                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2698                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2699                                  <&gpucc GPU_CC_AHB_CLK>,
2700                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2701                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2702                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2703                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2704                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2705                                         "gcc_gpu_snoc_dvm_gfx_clk",
2706                                         "gpu_cc_ahb_clk",
2707                                         "gpu_cc_hlos1_vote_gpu_smmu_clk",
2708                                         "gpu_cc_cx_gmu_clk",
2709                                         "gpu_cc_hub_cx_int_clk",
2710                                         "gpu_cc_hub_aon_clk";
2711
2712                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2713                         dma-coherent;
2714                 };
2715
2716                 remoteproc_mpss: remoteproc@4080000 {
2717                         compatible = "qcom,sc7280-mpss-pas";
2718                         reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2719                         reg-names = "qdsp6", "rmb";
2720
2721                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2722                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2723                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2724                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2725                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2726                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2727                         interrupt-names = "wdog", "fatal", "ready", "handover",
2728                                           "stop-ack", "shutdown-ack";
2729
2730                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2731                                  <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
2732                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2733                                  <&rpmhcc RPMH_PKA_CLK>,
2734                                  <&rpmhcc RPMH_CXO_CLK>;
2735                         clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
2736
2737                         power-domains = <&rpmhpd SC7280_CX>,
2738                                         <&rpmhpd SC7280_MSS>;
2739                         power-domain-names = "cx", "mss";
2740
2741                         memory-region = <&mpss_mem>;
2742
2743                         qcom,qmp = <&aoss_qmp>;
2744
2745                         qcom,smem-states = <&modem_smp2p_out 0>;
2746                         qcom,smem-state-names = "stop";
2747
2748                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2749                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2750                         reset-names = "mss_restart", "pdc_reset";
2751
2752                         qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
2753                         qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
2754                         qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
2755
2756                         status = "disabled";
2757
2758                         glink-edge {
2759                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2760                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2761                                                              IRQ_TYPE_EDGE_RISING>;
2762                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2763                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2764                                 label = "modem";
2765                                 qcom,remote-pid = <1>;
2766                         };
2767                 };
2768
2769                 stm@6002000 {
2770                         compatible = "arm,coresight-stm", "arm,primecell";
2771                         reg = <0 0x06002000 0 0x1000>,
2772                               <0 0x16280000 0 0x180000>;
2773                         reg-names = "stm-base", "stm-stimulus-base";
2774
2775                         clocks = <&aoss_qmp>;
2776                         clock-names = "apb_pclk";
2777
2778                         out-ports {
2779                                 port {
2780                                         stm_out: endpoint {
2781                                                 remote-endpoint = <&funnel0_in7>;
2782                                         };
2783                                 };
2784                         };
2785                 };
2786
2787                 funnel@6041000 {
2788                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2789                         reg = <0 0x06041000 0 0x1000>;
2790
2791                         clocks = <&aoss_qmp>;
2792                         clock-names = "apb_pclk";
2793
2794                         out-ports {
2795                                 port {
2796                                         funnel0_out: endpoint {
2797                                                 remote-endpoint = <&merge_funnel_in0>;
2798                                         };
2799                                 };
2800                         };
2801
2802                         in-ports {
2803                                 #address-cells = <1>;
2804                                 #size-cells = <0>;
2805
2806                                 port@7 {
2807                                         reg = <7>;
2808                                         funnel0_in7: endpoint {
2809                                                 remote-endpoint = <&stm_out>;
2810                                         };
2811                                 };
2812                         };
2813                 };
2814
2815                 funnel@6042000 {
2816                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2817                         reg = <0 0x06042000 0 0x1000>;
2818
2819                         clocks = <&aoss_qmp>;
2820                         clock-names = "apb_pclk";
2821
2822                         out-ports {
2823                                 port {
2824                                         funnel1_out: endpoint {
2825                                                 remote-endpoint = <&merge_funnel_in1>;
2826                                         };
2827                                 };
2828                         };
2829
2830                         in-ports {
2831                                 #address-cells = <1>;
2832                                 #size-cells = <0>;
2833
2834                                 port@4 {
2835                                         reg = <4>;
2836                                         funnel1_in4: endpoint {
2837                                                 remote-endpoint = <&apss_merge_funnel_out>;
2838                                         };
2839                                 };
2840                         };
2841                 };
2842
2843                 funnel@6045000 {
2844                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2845                         reg = <0 0x06045000 0 0x1000>;
2846
2847                         clocks = <&aoss_qmp>;
2848                         clock-names = "apb_pclk";
2849
2850                         out-ports {
2851                                 port {
2852                                         merge_funnel_out: endpoint {
2853                                                 remote-endpoint = <&swao_funnel_in>;
2854                                         };
2855                                 };
2856                         };
2857
2858                         in-ports {
2859                                 #address-cells = <1>;
2860                                 #size-cells = <0>;
2861
2862                                 port@0 {
2863                                         reg = <0>;
2864                                         merge_funnel_in0: endpoint {
2865                                                 remote-endpoint = <&funnel0_out>;
2866                                         };
2867                                 };
2868
2869                                 port@1 {
2870                                         reg = <1>;
2871                                         merge_funnel_in1: endpoint {
2872                                                 remote-endpoint = <&funnel1_out>;
2873                                         };
2874                                 };
2875                         };
2876                 };
2877
2878                 replicator@6046000 {
2879                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2880                         reg = <0 0x06046000 0 0x1000>;
2881
2882                         clocks = <&aoss_qmp>;
2883                         clock-names = "apb_pclk";
2884
2885                         out-ports {
2886                                 port {
2887                                         replicator_out: endpoint {
2888                                                 remote-endpoint = <&etr_in>;
2889                                         };
2890                                 };
2891                         };
2892
2893                         in-ports {
2894                                 port {
2895                                         replicator_in: endpoint {
2896                                                 remote-endpoint = <&swao_replicator_out>;
2897                                         };
2898                                 };
2899                         };
2900                 };
2901
2902                 etr@6048000 {
2903                         compatible = "arm,coresight-tmc", "arm,primecell";
2904                         reg = <0 0x06048000 0 0x1000>;
2905                         iommus = <&apps_smmu 0x04c0 0>;
2906
2907                         clocks = <&aoss_qmp>;
2908                         clock-names = "apb_pclk";
2909                         arm,scatter-gather;
2910
2911                         in-ports {
2912                                 port {
2913                                         etr_in: endpoint {
2914                                                 remote-endpoint = <&replicator_out>;
2915                                         };
2916                                 };
2917                         };
2918                 };
2919
2920                 funnel@6b04000 {
2921                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2922                         reg = <0 0x06b04000 0 0x1000>;
2923
2924                         clocks = <&aoss_qmp>;
2925                         clock-names = "apb_pclk";
2926
2927                         out-ports {
2928                                 port {
2929                                         swao_funnel_out: endpoint {
2930                                                 remote-endpoint = <&etf_in>;
2931                                         };
2932                                 };
2933                         };
2934
2935                         in-ports {
2936                                 #address-cells = <1>;
2937                                 #size-cells = <0>;
2938
2939                                 port@7 {
2940                                         reg = <7>;
2941                                         swao_funnel_in: endpoint {
2942                                                 remote-endpoint = <&merge_funnel_out>;
2943                                         };
2944                                 };
2945                         };
2946                 };
2947
2948                 etf@6b05000 {
2949                         compatible = "arm,coresight-tmc", "arm,primecell";
2950                         reg = <0 0x06b05000 0 0x1000>;
2951
2952                         clocks = <&aoss_qmp>;
2953                         clock-names = "apb_pclk";
2954
2955                         out-ports {
2956                                 port {
2957                                         etf_out: endpoint {
2958                                                 remote-endpoint = <&swao_replicator_in>;
2959                                         };
2960                                 };
2961                         };
2962
2963                         in-ports {
2964                                 port {
2965                                         etf_in: endpoint {
2966                                                 remote-endpoint = <&swao_funnel_out>;
2967                                         };
2968                                 };
2969                         };
2970                 };
2971
2972                 replicator@6b06000 {
2973                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2974                         reg = <0 0x06b06000 0 0x1000>;
2975
2976                         clocks = <&aoss_qmp>;
2977                         clock-names = "apb_pclk";
2978                         qcom,replicator-loses-context;
2979
2980                         out-ports {
2981                                 port {
2982                                         swao_replicator_out: endpoint {
2983                                                 remote-endpoint = <&replicator_in>;
2984                                         };
2985                                 };
2986                         };
2987
2988                         in-ports {
2989                                 port {
2990                                         swao_replicator_in: endpoint {
2991                                                 remote-endpoint = <&etf_out>;
2992                                         };
2993                                 };
2994                         };
2995                 };
2996
2997                 etm@7040000 {
2998                         compatible = "arm,coresight-etm4x", "arm,primecell";
2999                         reg = <0 0x07040000 0 0x1000>;
3000
3001                         cpu = <&CPU0>;
3002
3003                         clocks = <&aoss_qmp>;
3004                         clock-names = "apb_pclk";
3005                         arm,coresight-loses-context-with-cpu;
3006                         qcom,skip-power-up;
3007
3008                         out-ports {
3009                                 port {
3010                                         etm0_out: endpoint {
3011                                                 remote-endpoint = <&apss_funnel_in0>;
3012                                         };
3013                                 };
3014                         };
3015                 };
3016
3017                 etm@7140000 {
3018                         compatible = "arm,coresight-etm4x", "arm,primecell";
3019                         reg = <0 0x07140000 0 0x1000>;
3020
3021                         cpu = <&CPU1>;
3022
3023                         clocks = <&aoss_qmp>;
3024                         clock-names = "apb_pclk";
3025                         arm,coresight-loses-context-with-cpu;
3026                         qcom,skip-power-up;
3027
3028                         out-ports {
3029                                 port {
3030                                         etm1_out: endpoint {
3031                                                 remote-endpoint = <&apss_funnel_in1>;
3032                                         };
3033                                 };
3034                         };
3035                 };
3036
3037                 etm@7240000 {
3038                         compatible = "arm,coresight-etm4x", "arm,primecell";
3039                         reg = <0 0x07240000 0 0x1000>;
3040
3041                         cpu = <&CPU2>;
3042
3043                         clocks = <&aoss_qmp>;
3044                         clock-names = "apb_pclk";
3045                         arm,coresight-loses-context-with-cpu;
3046                         qcom,skip-power-up;
3047
3048                         out-ports {
3049                                 port {
3050                                         etm2_out: endpoint {
3051                                                 remote-endpoint = <&apss_funnel_in2>;
3052                                         };
3053                                 };
3054                         };
3055                 };
3056
3057                 etm@7340000 {
3058                         compatible = "arm,coresight-etm4x", "arm,primecell";
3059                         reg = <0 0x07340000 0 0x1000>;
3060
3061                         cpu = <&CPU3>;
3062
3063                         clocks = <&aoss_qmp>;
3064                         clock-names = "apb_pclk";
3065                         arm,coresight-loses-context-with-cpu;
3066                         qcom,skip-power-up;
3067
3068                         out-ports {
3069                                 port {
3070                                         etm3_out: endpoint {
3071                                                 remote-endpoint = <&apss_funnel_in3>;
3072                                         };
3073                                 };
3074                         };
3075                 };
3076
3077                 etm@7440000 {
3078                         compatible = "arm,coresight-etm4x", "arm,primecell";
3079                         reg = <0 0x07440000 0 0x1000>;
3080
3081                         cpu = <&CPU4>;
3082
3083                         clocks = <&aoss_qmp>;
3084                         clock-names = "apb_pclk";
3085                         arm,coresight-loses-context-with-cpu;
3086                         qcom,skip-power-up;
3087
3088                         out-ports {
3089                                 port {
3090                                         etm4_out: endpoint {
3091                                                 remote-endpoint = <&apss_funnel_in4>;
3092                                         };
3093                                 };
3094                         };
3095                 };
3096
3097                 etm@7540000 {
3098                         compatible = "arm,coresight-etm4x", "arm,primecell";
3099                         reg = <0 0x07540000 0 0x1000>;
3100
3101                         cpu = <&CPU5>;
3102
3103                         clocks = <&aoss_qmp>;
3104                         clock-names = "apb_pclk";
3105                         arm,coresight-loses-context-with-cpu;
3106                         qcom,skip-power-up;
3107
3108                         out-ports {
3109                                 port {
3110                                         etm5_out: endpoint {
3111                                                 remote-endpoint = <&apss_funnel_in5>;
3112                                         };
3113                                 };
3114                         };
3115                 };
3116
3117                 etm@7640000 {
3118                         compatible = "arm,coresight-etm4x", "arm,primecell";
3119                         reg = <0 0x07640000 0 0x1000>;
3120
3121                         cpu = <&CPU6>;
3122
3123                         clocks = <&aoss_qmp>;
3124                         clock-names = "apb_pclk";
3125                         arm,coresight-loses-context-with-cpu;
3126                         qcom,skip-power-up;
3127
3128                         out-ports {
3129                                 port {
3130                                         etm6_out: endpoint {
3131                                                 remote-endpoint = <&apss_funnel_in6>;
3132                                         };
3133                                 };
3134                         };
3135                 };
3136
3137                 etm@7740000 {
3138                         compatible = "arm,coresight-etm4x", "arm,primecell";
3139                         reg = <0 0x07740000 0 0x1000>;
3140
3141                         cpu = <&CPU7>;
3142
3143                         clocks = <&aoss_qmp>;
3144                         clock-names = "apb_pclk";
3145                         arm,coresight-loses-context-with-cpu;
3146                         qcom,skip-power-up;
3147
3148                         out-ports {
3149                                 port {
3150                                         etm7_out: endpoint {
3151                                                 remote-endpoint = <&apss_funnel_in7>;
3152                                         };
3153                                 };
3154                         };
3155                 };
3156
3157                 funnel@7800000 { /* APSS Funnel */
3158                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3159                         reg = <0 0x07800000 0 0x1000>;
3160
3161                         clocks = <&aoss_qmp>;
3162                         clock-names = "apb_pclk";
3163
3164                         out-ports {
3165                                 port {
3166                                         apss_funnel_out: endpoint {
3167                                                 remote-endpoint = <&apss_merge_funnel_in>;
3168                                         };
3169                                 };
3170                         };
3171
3172                         in-ports {
3173                                 #address-cells = <1>;
3174                                 #size-cells = <0>;
3175
3176                                 port@0 {
3177                                         reg = <0>;
3178                                         apss_funnel_in0: endpoint {
3179                                                 remote-endpoint = <&etm0_out>;
3180                                         };
3181                                 };
3182
3183                                 port@1 {
3184                                         reg = <1>;
3185                                         apss_funnel_in1: endpoint {
3186                                                 remote-endpoint = <&etm1_out>;
3187                                         };
3188                                 };
3189
3190                                 port@2 {
3191                                         reg = <2>;
3192                                         apss_funnel_in2: endpoint {
3193                                                 remote-endpoint = <&etm2_out>;
3194                                         };
3195                                 };
3196
3197                                 port@3 {
3198                                         reg = <3>;
3199                                         apss_funnel_in3: endpoint {
3200                                                 remote-endpoint = <&etm3_out>;
3201                                         };
3202                                 };
3203
3204                                 port@4 {
3205                                         reg = <4>;
3206                                         apss_funnel_in4: endpoint {
3207                                                 remote-endpoint = <&etm4_out>;
3208                                         };
3209                                 };
3210
3211                                 port@5 {
3212                                         reg = <5>;
3213                                         apss_funnel_in5: endpoint {
3214                                                 remote-endpoint = <&etm5_out>;
3215                                         };
3216                                 };
3217
3218                                 port@6 {
3219                                         reg = <6>;
3220                                         apss_funnel_in6: endpoint {
3221                                                 remote-endpoint = <&etm6_out>;
3222                                         };
3223                                 };
3224
3225                                 port@7 {
3226                                         reg = <7>;
3227                                         apss_funnel_in7: endpoint {
3228                                                 remote-endpoint = <&etm7_out>;
3229                                         };
3230                                 };
3231                         };
3232                 };
3233
3234                 funnel@7810000 {
3235                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3236                         reg = <0 0x07810000 0 0x1000>;
3237
3238                         clocks = <&aoss_qmp>;
3239                         clock-names = "apb_pclk";
3240
3241                         out-ports {
3242                                 port {
3243                                         apss_merge_funnel_out: endpoint {
3244                                                 remote-endpoint = <&funnel1_in4>;
3245                                         };
3246                                 };
3247                         };
3248
3249                         in-ports {
3250                                 port {
3251                                         apss_merge_funnel_in: endpoint {
3252                                                 remote-endpoint = <&apss_funnel_out>;
3253                                         };
3254                                 };
3255                         };
3256                 };
3257
3258                 sdhc_2: mmc@8804000 {
3259                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3260                         pinctrl-names = "default", "sleep";
3261                         pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3262                         pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3263                         status = "disabled";
3264
3265                         reg = <0 0x08804000 0 0x1000>;
3266
3267                         iommus = <&apps_smmu 0x100 0x0>;
3268                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3270                         interrupt-names = "hc_irq", "pwr_irq";
3271
3272                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3273                                  <&gcc GCC_SDCC2_APPS_CLK>,
3274                                  <&rpmhcc RPMH_CXO_CLK>;
3275                         clock-names = "iface", "core", "xo";
3276                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3277                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3278                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3279                         power-domains = <&rpmhpd SC7280_CX>;
3280                         operating-points-v2 = <&sdhc2_opp_table>;
3281
3282                         bus-width = <4>;
3283                         dma-coherent;
3284
3285                         qcom,dll-config = <0x0007642c>;
3286
3287                         resets = <&gcc GCC_SDCC2_BCR>;
3288
3289                         sdhc2_opp_table: opp-table {
3290                                 compatible = "operating-points-v2";
3291
3292                                 opp-100000000 {
3293                                         opp-hz = /bits/ 64 <100000000>;
3294                                         required-opps = <&rpmhpd_opp_low_svs>;
3295                                         opp-peak-kBps = <1800000 400000>;
3296                                         opp-avg-kBps = <100000 0>;
3297                                 };
3298
3299                                 opp-202000000 {
3300                                         opp-hz = /bits/ 64 <202000000>;
3301                                         required-opps = <&rpmhpd_opp_nom>;
3302                                         opp-peak-kBps = <5400000 1600000>;
3303                                         opp-avg-kBps = <200000 0>;
3304                                 };
3305                         };
3306
3307                 };
3308
3309                 usb_1_hsphy: phy@88e3000 {
3310                         compatible = "qcom,sc7280-usb-hs-phy",
3311                                      "qcom,usb-snps-hs-7nm-phy";
3312                         reg = <0 0x088e3000 0 0x400>;
3313                         status = "disabled";
3314                         #phy-cells = <0>;
3315
3316                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3317                         clock-names = "ref";
3318
3319                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3320                 };
3321
3322                 usb_2_hsphy: phy@88e4000 {
3323                         compatible = "qcom,sc7280-usb-hs-phy",
3324                                      "qcom,usb-snps-hs-7nm-phy";
3325                         reg = <0 0x088e4000 0 0x400>;
3326                         status = "disabled";
3327                         #phy-cells = <0>;
3328
3329                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3330                         clock-names = "ref";
3331
3332                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3333                 };
3334
3335                 usb_1_qmpphy: phy-wrapper@88e9000 {
3336                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3337                                      "qcom,sm8250-qmp-usb3-dp-phy";
3338                         reg = <0 0x088e9000 0 0x200>,
3339                               <0 0x088e8000 0 0x40>,
3340                               <0 0x088ea000 0 0x200>;
3341                         status = "disabled";
3342                         #address-cells = <2>;
3343                         #size-cells = <2>;
3344                         ranges;
3345
3346                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3347                                  <&rpmhcc RPMH_CXO_CLK>,
3348                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3349                         clock-names = "aux", "ref_clk_src", "com_aux";
3350
3351                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3352                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3353                         reset-names = "phy", "common";
3354
3355                         usb_1_ssphy: usb3-phy@88e9200 {
3356                                 reg = <0 0x088e9200 0 0x200>,
3357                                       <0 0x088e9400 0 0x200>,
3358                                       <0 0x088e9c00 0 0x400>,
3359                                       <0 0x088e9600 0 0x200>,
3360                                       <0 0x088e9800 0 0x200>,
3361                                       <0 0x088e9a00 0 0x100>;
3362                                 #clock-cells = <0>;
3363                                 #phy-cells = <0>;
3364                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3365                                 clock-names = "pipe0";
3366                                 clock-output-names = "usb3_phy_pipe_clk_src";
3367                         };
3368
3369                         dp_phy: dp-phy@88ea200 {
3370                                 reg = <0 0x088ea200 0 0x200>,
3371                                       <0 0x088ea400 0 0x200>,
3372                                       <0 0x088eaa00 0 0x200>,
3373                                       <0 0x088ea600 0 0x200>,
3374                                       <0 0x088ea800 0 0x200>;
3375                                 #phy-cells = <0>;
3376                                 #clock-cells = <1>;
3377                         };
3378                 };
3379
3380                 usb_2: usb@8cf8800 {
3381                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3382                         reg = <0 0x08cf8800 0 0x400>;
3383                         status = "disabled";
3384                         #address-cells = <2>;
3385                         #size-cells = <2>;
3386                         ranges;
3387                         dma-ranges;
3388
3389                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3390                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3391                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3392                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3393                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3394                         clock-names = "cfg_noc",
3395                                       "core",
3396                                       "iface",
3397                                       "sleep",
3398                                       "mock_utmi";
3399
3400                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3401                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3402                         assigned-clock-rates = <19200000>, <200000000>;
3403
3404                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3405                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3406                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>;
3407                         interrupt-names = "hs_phy_irq",
3408                                           "dp_hs_phy_irq",
3409                                           "dm_hs_phy_irq";
3410
3411                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3412                         required-opps = <&rpmhpd_opp_nom>;
3413
3414                         resets = <&gcc GCC_USB30_SEC_BCR>;
3415
3416                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3417                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3418                         interconnect-names = "usb-ddr", "apps-usb";
3419
3420                         usb_2_dwc3: usb@8c00000 {
3421                                 compatible = "snps,dwc3";
3422                                 reg = <0 0x08c00000 0 0xe000>;
3423                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3424                                 iommus = <&apps_smmu 0xa0 0x0>;
3425                                 snps,dis_u2_susphy_quirk;
3426                                 snps,dis_enblslpm_quirk;
3427                                 phys = <&usb_2_hsphy>;
3428                                 phy-names = "usb2-phy";
3429                                 maximum-speed = "high-speed";
3430                                 usb-role-switch;
3431                                 port {
3432                                         usb2_role_switch: endpoint {
3433                                                 remote-endpoint = <&eud_ep>;
3434                                         };
3435                                 };
3436                         };
3437                 };
3438
3439                 qspi: spi@88dc000 {
3440                         compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3441                         reg = <0 0x088dc000 0 0x1000>;
3442                         #address-cells = <1>;
3443                         #size-cells = <0>;
3444                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3445                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3446                                  <&gcc GCC_QSPI_CORE_CLK>;
3447                         clock-names = "iface", "core";
3448                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
3449                                         &cnoc2 SLAVE_QSPI_0 0>;
3450                         interconnect-names = "qspi-config";
3451                         power-domains = <&rpmhpd SC7280_CX>;
3452                         operating-points-v2 = <&qspi_opp_table>;
3453                         status = "disabled";
3454                 };
3455
3456                 remoteproc_wpss: remoteproc@8a00000 {
3457                         compatible = "qcom,sc7280-wpss-pil";
3458                         reg = <0 0x08a00000 0 0x10000>;
3459
3460                         interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3461                                               <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3462                                               <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3463                                               <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3464                                               <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3465                                               <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3466                         interrupt-names = "wdog", "fatal", "ready", "handover",
3467                                           "stop-ack", "shutdown-ack";
3468
3469                         clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
3470                                  <&gcc GCC_WPSS_AHB_CLK>,
3471                                  <&gcc GCC_WPSS_RSCP_CLK>,
3472                                  <&rpmhcc RPMH_CXO_CLK>;
3473                         clock-names = "ahb_bdg", "ahb",
3474                                       "rscp", "xo";
3475
3476                         power-domains = <&rpmhpd SC7280_CX>,
3477                                         <&rpmhpd SC7280_MX>;
3478                         power-domain-names = "cx", "mx";
3479
3480                         memory-region = <&wpss_mem>;
3481
3482                         qcom,qmp = <&aoss_qmp>;
3483
3484                         qcom,smem-states = <&wpss_smp2p_out 0>;
3485                         qcom,smem-state-names = "stop";
3486
3487                         resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
3488                                  <&pdc_reset PDC_WPSS_SYNC_RESET>;
3489                         reset-names = "restart", "pdc_sync";
3490
3491                         qcom,halt-regs = <&tcsr_1 0x17000>;
3492
3493                         status = "disabled";
3494
3495                         glink-edge {
3496                                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3497                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3498                                                              IRQ_TYPE_EDGE_RISING>;
3499                                 mboxes = <&ipcc IPCC_CLIENT_WPSS
3500                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3501
3502                                 label = "wpss";
3503                                 qcom,remote-pid = <13>;
3504                         };
3505                 };
3506
3507                 pmu@9091000 {
3508                         compatible = "qcom,sc7280-llcc-bwmon";
3509                         reg = <0 0x9091000 0 0x1000>;
3510
3511                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3512
3513                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3514
3515                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3516
3517                         llcc_bwmon_opp_table: opp-table {
3518                                 compatible = "operating-points-v2";
3519
3520                                 opp-0 {
3521                                         opp-peak-kBps = <800000>;
3522                                 };
3523                                 opp-1 {
3524                                         opp-peak-kBps = <1804000>;
3525                                 };
3526                                 opp-2 {
3527                                         opp-peak-kBps = <2188000>;
3528                                 };
3529                                 opp-3 {
3530                                         opp-peak-kBps = <3072000>;
3531                                 };
3532                                 opp-4 {
3533                                         opp-peak-kBps = <4068000>;
3534                                 };
3535                                 opp-5 {
3536                                         opp-peak-kBps = <6220000>;
3537                                 };
3538                                 opp-6 {
3539                                         opp-peak-kBps = <6832000>;
3540                                 };
3541                                 opp-7 {
3542                                         opp-peak-kBps = <8532000>;
3543                                 };
3544                         };
3545                 };
3546
3547                 pmu@90b6400 {
3548                         compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
3549                         reg = <0 0x090b6400 0 0x600>;
3550
3551                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3552
3553                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3554                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3555
3556                         cpu_bwmon_opp_table: opp-table {
3557                                 compatible = "operating-points-v2";
3558
3559                                 opp-0 {
3560                                         opp-peak-kBps = <2400000>;
3561                                 };
3562                                 opp-1 {
3563                                         opp-peak-kBps = <4800000>;
3564                                 };
3565                                 opp-2 {
3566                                         opp-peak-kBps = <7456000>;
3567                                 };
3568                                 opp-3 {
3569                                         opp-peak-kBps = <9600000>;
3570                                 };
3571                                 opp-4 {
3572                                         opp-peak-kBps = <12896000>;
3573                                 };
3574                                 opp-5 {
3575                                         opp-peak-kBps = <14928000>;
3576                                 };
3577                                 opp-6 {
3578                                         opp-peak-kBps = <17056000>;
3579                                 };
3580                         };
3581                 };
3582
3583                 dc_noc: interconnect@90e0000 {
3584                         reg = <0 0x090e0000 0 0x5080>;
3585                         compatible = "qcom,sc7280-dc-noc";
3586                         #interconnect-cells = <2>;
3587                         qcom,bcm-voters = <&apps_bcm_voter>;
3588                 };
3589
3590                 gem_noc: interconnect@9100000 {
3591                         reg = <0 0x9100000 0 0xe2200>;
3592                         compatible = "qcom,sc7280-gem-noc";
3593                         #interconnect-cells = <2>;
3594                         qcom,bcm-voters = <&apps_bcm_voter>;
3595                 };
3596
3597                 system-cache-controller@9200000 {
3598                         compatible = "qcom,sc7280-llcc";
3599                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3600                         reg-names = "llcc_base", "llcc_broadcast_base";
3601                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3602                 };
3603
3604                 eud: eud@88e0000 {
3605                         compatible = "qcom,sc7280-eud","qcom,eud";
3606                         reg = <0 0x88e0000 0 0x2000>,
3607                               <0 0x88e2000 0 0x1000>;
3608                         interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3609                         ports {
3610                                 #address-cells = <1>;
3611                                 #size-cells = <0>;
3612
3613                                 port@0 {
3614                                         reg = <0>;
3615                                         eud_ep: endpoint {
3616                                                 remote-endpoint = <&usb2_role_switch>;
3617                                         };
3618                                 };
3619                                 port@1 {
3620                                         reg = <1>;
3621                                         eud_con: endpoint {
3622                                                 remote-endpoint = <&con_eud>;
3623                                         };
3624                                 };
3625                         };
3626                 };
3627
3628                 eud_typec: connector {
3629                         compatible = "usb-c-connector";
3630                         ports {
3631                                 #address-cells = <1>;
3632                                 #size-cells = <0>;
3633
3634                                 port@0 {
3635                                         reg = <0>;
3636                                         con_eud: endpoint {
3637                                                 remote-endpoint = <&eud_con>;
3638                                         };
3639                                 };
3640                         };
3641                 };
3642
3643                 nsp_noc: interconnect@a0c0000 {
3644                         reg = <0 0x0a0c0000 0 0x10000>;
3645                         compatible = "qcom,sc7280-nsp-noc";
3646                         #interconnect-cells = <2>;
3647                         qcom,bcm-voters = <&apps_bcm_voter>;
3648                 };
3649
3650                 usb_1: usb@a6f8800 {
3651                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3652                         reg = <0 0x0a6f8800 0 0x400>;
3653                         status = "disabled";
3654                         #address-cells = <2>;
3655                         #size-cells = <2>;
3656                         ranges;
3657                         dma-ranges;
3658
3659                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3660                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3661                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3662                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3663                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3664                         clock-names = "cfg_noc",
3665                                       "core",
3666                                       "iface",
3667                                       "sleep",
3668                                       "mock_utmi";
3669
3670                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3671                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3672                         assigned-clock-rates = <19200000>, <200000000>;
3673
3674                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3675                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3676                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3677                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
3678                         interrupt-names = "hs_phy_irq",
3679                                           "dp_hs_phy_irq",
3680                                           "dm_hs_phy_irq",
3681                                           "ss_phy_irq";
3682
3683                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3684                         required-opps = <&rpmhpd_opp_nom>;
3685
3686                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3687
3688                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3689                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3690                         interconnect-names = "usb-ddr", "apps-usb";
3691
3692                         wakeup-source;
3693
3694                         usb_1_dwc3: usb@a600000 {
3695                                 compatible = "snps,dwc3";
3696                                 reg = <0 0x0a600000 0 0xe000>;
3697                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3698                                 iommus = <&apps_smmu 0xe0 0x0>;
3699                                 snps,dis_u2_susphy_quirk;
3700                                 snps,dis_enblslpm_quirk;
3701                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3702                                 phy-names = "usb2-phy", "usb3-phy";
3703                                 maximum-speed = "super-speed";
3704                         };
3705                 };
3706
3707                 venus: video-codec@aa00000 {
3708                         compatible = "qcom,sc7280-venus";
3709                         reg = <0 0x0aa00000 0 0xd0600>;
3710                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3711
3712                         clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
3713                                  <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
3714                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3715                                  <&videocc VIDEO_CC_MVS0_CORE_CLK>,
3716                                  <&videocc VIDEO_CC_MVS0_AXI_CLK>;
3717                         clock-names = "core", "bus", "iface",
3718                                       "vcodec_core", "vcodec_bus";
3719
3720                         power-domains = <&videocc MVSC_GDSC>,
3721                                         <&videocc MVS0_GDSC>,
3722                                         <&rpmhpd SC7280_CX>;
3723                         power-domain-names = "venus", "vcodec0", "cx";
3724                         operating-points-v2 = <&venus_opp_table>;
3725
3726                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3727                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3728                         interconnect-names = "cpu-cfg", "video-mem";
3729
3730                         iommus = <&apps_smmu 0x2180 0x20>,
3731                                  <&apps_smmu 0x2184 0x20>;
3732                         memory-region = <&video_mem>;
3733
3734                         video-decoder {
3735                                 compatible = "venus-decoder";
3736                         };
3737
3738                         video-encoder {
3739                                 compatible = "venus-encoder";
3740                         };
3741
3742                         video-firmware {
3743                                 iommus = <&apps_smmu 0x21a2 0x0>;
3744                         };
3745
3746                         venus_opp_table: opp-table {
3747                                 compatible = "operating-points-v2";
3748
3749                                 opp-133330000 {
3750                                         opp-hz = /bits/ 64 <133330000>;
3751                                         required-opps = <&rpmhpd_opp_low_svs>;
3752                                 };
3753
3754                                 opp-240000000 {
3755                                         opp-hz = /bits/ 64 <240000000>;
3756                                         required-opps = <&rpmhpd_opp_svs>;
3757                                 };
3758
3759                                 opp-335000000 {
3760                                         opp-hz = /bits/ 64 <335000000>;
3761                                         required-opps = <&rpmhpd_opp_svs_l1>;
3762                                 };
3763
3764                                 opp-424000000 {
3765                                         opp-hz = /bits/ 64 <424000000>;
3766                                         required-opps = <&rpmhpd_opp_nom>;
3767                                 };
3768
3769                                 opp-460000048 {
3770                                         opp-hz = /bits/ 64 <460000048>;
3771                                         required-opps = <&rpmhpd_opp_turbo>;
3772                                 };
3773                         };
3774
3775                 };
3776
3777                 videocc: clock-controller@aaf0000 {
3778                         compatible = "qcom,sc7280-videocc";
3779                         reg = <0 0xaaf0000 0 0x10000>;
3780                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3781                                 <&rpmhcc RPMH_CXO_CLK_A>;
3782                         clock-names = "bi_tcxo", "bi_tcxo_ao";
3783                         #clock-cells = <1>;
3784                         #reset-cells = <1>;
3785                         #power-domain-cells = <1>;
3786                 };
3787
3788                 camcc: clock-controller@ad00000 {
3789                         compatible = "qcom,sc7280-camcc";
3790                         reg = <0 0x0ad00000 0 0x10000>;
3791                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3792                                 <&rpmhcc RPMH_CXO_CLK_A>,
3793                                 <&sleep_clk>;
3794                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3795                         #clock-cells = <1>;
3796                         #reset-cells = <1>;
3797                         #power-domain-cells = <1>;
3798                 };
3799
3800                 dispcc: clock-controller@af00000 {
3801                         compatible = "qcom,sc7280-dispcc";
3802                         reg = <0 0xaf00000 0 0x20000>;
3803                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3804                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3805                                  <&mdss_dsi_phy 0>,
3806                                  <&mdss_dsi_phy 1>,
3807                                  <&dp_phy 0>,
3808                                  <&dp_phy 1>,
3809                                  <&mdss_edp_phy 0>,
3810                                  <&mdss_edp_phy 1>;
3811                         clock-names = "bi_tcxo",
3812                                       "gcc_disp_gpll0_clk",
3813                                       "dsi0_phy_pll_out_byteclk",
3814                                       "dsi0_phy_pll_out_dsiclk",
3815                                       "dp_phy_pll_link_clk",
3816                                       "dp_phy_pll_vco_div_clk",
3817                                       "edp_phy_pll_link_clk",
3818                                       "edp_phy_pll_vco_div_clk";
3819                         #clock-cells = <1>;
3820                         #reset-cells = <1>;
3821                         #power-domain-cells = <1>;
3822                 };
3823
3824                 mdss: display-subsystem@ae00000 {
3825                         compatible = "qcom,sc7280-mdss";
3826                         reg = <0 0x0ae00000 0 0x1000>;
3827                         reg-names = "mdss";
3828
3829                         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3830
3831                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3832                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
3833                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3834                         clock-names = "iface",
3835                                       "ahb",
3836                                       "core";
3837
3838                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3839                         interrupt-controller;
3840                         #interrupt-cells = <1>;
3841
3842                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3843                         interconnect-names = "mdp0-mem";
3844
3845                         iommus = <&apps_smmu 0x900 0x402>;
3846
3847                         #address-cells = <2>;
3848                         #size-cells = <2>;
3849                         ranges;
3850
3851                         status = "disabled";
3852
3853                         mdss_mdp: display-controller@ae01000 {
3854                                 compatible = "qcom,sc7280-dpu";
3855                                 reg = <0 0x0ae01000 0 0x8f030>,
3856                                         <0 0x0aeb0000 0 0x2008>;
3857                                 reg-names = "mdp", "vbif";
3858
3859                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3860                                         <&gcc GCC_DISP_SF_AXI_CLK>,
3861                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
3862                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3863                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
3864                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3865                                 clock-names = "bus",
3866                                               "nrt_bus",
3867                                               "iface",
3868                                               "lut",
3869                                               "core",
3870                                               "vsync";
3871                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3872                                                 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3873                                 assigned-clock-rates = <19200000>,
3874                                                         <19200000>;
3875                                 operating-points-v2 = <&mdp_opp_table>;
3876                                 power-domains = <&rpmhpd SC7280_CX>;
3877
3878                                 interrupt-parent = <&mdss>;
3879                                 interrupts = <0>;
3880
3881                                 status = "disabled";
3882
3883                                 ports {
3884                                         #address-cells = <1>;
3885                                         #size-cells = <0>;
3886
3887                                         port@0 {
3888                                                 reg = <0>;
3889                                                 dpu_intf1_out: endpoint {
3890                                                         remote-endpoint = <&dsi0_in>;
3891                                                 };
3892                                         };
3893
3894                                         port@1 {
3895                                                 reg = <1>;
3896                                                 dpu_intf5_out: endpoint {
3897                                                         remote-endpoint = <&edp_in>;
3898                                                 };
3899                                         };
3900
3901                                         port@2 {
3902                                                 reg = <2>;
3903                                                 dpu_intf0_out: endpoint {
3904                                                         remote-endpoint = <&dp_in>;
3905                                                 };
3906                                         };
3907                                 };
3908
3909                                 mdp_opp_table: opp-table {
3910                                         compatible = "operating-points-v2";
3911
3912                                         opp-200000000 {
3913                                                 opp-hz = /bits/ 64 <200000000>;
3914                                                 required-opps = <&rpmhpd_opp_low_svs>;
3915                                         };
3916
3917                                         opp-300000000 {
3918                                                 opp-hz = /bits/ 64 <300000000>;
3919                                                 required-opps = <&rpmhpd_opp_svs>;
3920                                         };
3921
3922                                         opp-380000000 {
3923                                                 opp-hz = /bits/ 64 <380000000>;
3924                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3925                                         };
3926
3927                                         opp-506666667 {
3928                                                 opp-hz = /bits/ 64 <506666667>;
3929                                                 required-opps = <&rpmhpd_opp_nom>;
3930                                         };
3931                                 };
3932                         };
3933
3934                         mdss_dsi: dsi@ae94000 {
3935                                 compatible = "qcom,mdss-dsi-ctrl";
3936                                 reg = <0 0x0ae94000 0 0x400>;
3937                                 reg-names = "dsi_ctrl";
3938
3939                                 interrupt-parent = <&mdss>;
3940                                 interrupts = <4>;
3941
3942                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3943                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3944                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3945                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3946                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3947                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3948                                 clock-names = "byte",
3949                                               "byte_intf",
3950                                               "pixel",
3951                                               "core",
3952                                               "iface",
3953                                               "bus";
3954
3955                                 operating-points-v2 = <&dsi_opp_table>;
3956                                 power-domains = <&rpmhpd SC7280_CX>;
3957
3958                                 phys = <&mdss_dsi_phy>;
3959                                 phy-names = "dsi";
3960
3961                                 #address-cells = <1>;
3962                                 #size-cells = <0>;
3963
3964                                 status = "disabled";
3965
3966                                 ports {
3967                                         #address-cells = <1>;
3968                                         #size-cells = <0>;
3969
3970                                         port@0 {
3971                                                 reg = <0>;
3972                                                 dsi0_in: endpoint {
3973                                                         remote-endpoint = <&dpu_intf1_out>;
3974                                                 };
3975                                         };
3976
3977                                         port@1 {
3978                                                 reg = <1>;
3979                                                 dsi0_out: endpoint {
3980                                                 };
3981                                         };
3982                                 };
3983
3984                                 dsi_opp_table: opp-table {
3985                                         compatible = "operating-points-v2";
3986
3987                                         opp-187500000 {
3988                                                 opp-hz = /bits/ 64 <187500000>;
3989                                                 required-opps = <&rpmhpd_opp_low_svs>;
3990                                         };
3991
3992                                         opp-300000000 {
3993                                                 opp-hz = /bits/ 64 <300000000>;
3994                                                 required-opps = <&rpmhpd_opp_svs>;
3995                                         };
3996
3997                                         opp-358000000 {
3998                                                 opp-hz = /bits/ 64 <358000000>;
3999                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4000                                         };
4001                                 };
4002                         };
4003
4004                         mdss_dsi_phy: phy@ae94400 {
4005                                 compatible = "qcom,sc7280-dsi-phy-7nm";
4006                                 reg = <0 0x0ae94400 0 0x200>,
4007                                       <0 0x0ae94600 0 0x280>,
4008                                       <0 0x0ae94900 0 0x280>;
4009                                 reg-names = "dsi_phy",
4010                                             "dsi_phy_lane",
4011                                             "dsi_pll";
4012
4013                                 #clock-cells = <1>;
4014                                 #phy-cells = <0>;
4015
4016                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4017                                          <&rpmhcc RPMH_CXO_CLK>;
4018                                 clock-names = "iface", "ref";
4019
4020                                 status = "disabled";
4021                         };
4022
4023                         mdss_edp: edp@aea0000 {
4024                                 compatible = "qcom,sc7280-edp";
4025                                 pinctrl-names = "default";
4026                                 pinctrl-0 = <&edp_hot_plug_det>;
4027
4028                                 reg = <0 0xaea0000 0 0x200>,
4029                                       <0 0xaea0200 0 0x200>,
4030                                       <0 0xaea0400 0 0xc00>,
4031                                       <0 0xaea1000 0 0x400>;
4032
4033                                 interrupt-parent = <&mdss>;
4034                                 interrupts = <14>;
4035
4036                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4037                                          <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
4038                                          <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
4039                                          <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
4040                                          <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
4041                                 clock-names = "core_iface",
4042                                               "core_aux",
4043                                               "ctrl_link",
4044                                               "ctrl_link_iface",
4045                                               "stream_pixel";
4046                                 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4047                                                   <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
4048                                 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4049
4050                                 phys = <&mdss_edp_phy>;
4051                                 phy-names = "dp";
4052
4053                                 operating-points-v2 = <&edp_opp_table>;
4054                                 power-domains = <&rpmhpd SC7280_CX>;
4055
4056                                 status = "disabled";
4057
4058                                 ports {
4059                                         #address-cells = <1>;
4060                                         #size-cells = <0>;
4061
4062                                         port@0 {
4063                                                 reg = <0>;
4064                                                 edp_in: endpoint {
4065                                                         remote-endpoint = <&dpu_intf5_out>;
4066                                                 };
4067                                         };
4068
4069                                         port@1 {
4070                                                 reg = <1>;
4071                                                 mdss_edp_out: endpoint { };
4072                                         };
4073                                 };
4074
4075                                 edp_opp_table: opp-table {
4076                                         compatible = "operating-points-v2";
4077
4078                                         opp-160000000 {
4079                                                 opp-hz = /bits/ 64 <160000000>;
4080                                                 required-opps = <&rpmhpd_opp_low_svs>;
4081                                         };
4082
4083                                         opp-270000000 {
4084                                                 opp-hz = /bits/ 64 <270000000>;
4085                                                 required-opps = <&rpmhpd_opp_svs>;
4086                                         };
4087
4088                                         opp-540000000 {
4089                                                 opp-hz = /bits/ 64 <540000000>;
4090                                                 required-opps = <&rpmhpd_opp_nom>;
4091                                         };
4092
4093                                         opp-810000000 {
4094                                                 opp-hz = /bits/ 64 <810000000>;
4095                                                 required-opps = <&rpmhpd_opp_nom>;
4096                                         };
4097                                 };
4098                         };
4099
4100                         mdss_edp_phy: phy@aec2a00 {
4101                                 compatible = "qcom,sc7280-edp-phy";
4102
4103                                 reg = <0 0xaec2a00 0 0x19c>,
4104                                       <0 0xaec2200 0 0xa0>,
4105                                       <0 0xaec2600 0 0xa0>,
4106                                       <0 0xaec2000 0 0x1c0>;
4107
4108                                 clocks = <&rpmhcc RPMH_CXO_CLK>,
4109                                          <&gcc GCC_EDP_CLKREF_EN>;
4110                                 clock-names = "aux",
4111                                               "cfg_ahb";
4112
4113                                 #clock-cells = <1>;
4114                                 #phy-cells = <0>;
4115
4116                                 status = "disabled";
4117                         };
4118
4119                         mdss_dp: displayport-controller@ae90000 {
4120                                 compatible = "qcom,sc7280-dp";
4121
4122                                 reg = <0 0xae90000 0 0x200>,
4123                                       <0 0xae90200 0 0x200>,
4124                                       <0 0xae90400 0 0xc00>,
4125                                       <0 0xae91000 0 0x400>,
4126                                       <0 0xae91400 0 0x400>;
4127
4128                                 interrupt-parent = <&mdss>;
4129                                 interrupts = <12>;
4130
4131                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4132                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4133                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4134                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4135                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4136                                 clock-names = "core_iface",
4137                                                 "core_aux",
4138                                                 "ctrl_link",
4139                                                 "ctrl_link_iface",
4140                                                 "stream_pixel";
4141                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4142                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4143                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4144                                 phys = <&dp_phy>;
4145                                 phy-names = "dp";
4146
4147                                 operating-points-v2 = <&dp_opp_table>;
4148                                 power-domains = <&rpmhpd SC7280_CX>;
4149
4150                                 #sound-dai-cells = <0>;
4151
4152                                 status = "disabled";
4153
4154                                 ports {
4155                                         #address-cells = <1>;
4156                                         #size-cells = <0>;
4157
4158                                         port@0 {
4159                                                 reg = <0>;
4160                                                 dp_in: endpoint {
4161                                                         remote-endpoint = <&dpu_intf0_out>;
4162                                                 };
4163                                         };
4164
4165                                         port@1 {
4166                                                 reg = <1>;
4167                                                 dp_out: endpoint { };
4168                                         };
4169                                 };
4170
4171                                 dp_opp_table: opp-table {
4172                                         compatible = "operating-points-v2";
4173
4174                                         opp-160000000 {
4175                                                 opp-hz = /bits/ 64 <160000000>;
4176                                                 required-opps = <&rpmhpd_opp_low_svs>;
4177                                         };
4178
4179                                         opp-270000000 {
4180                                                 opp-hz = /bits/ 64 <270000000>;
4181                                                 required-opps = <&rpmhpd_opp_svs>;
4182                                         };
4183
4184                                         opp-540000000 {
4185                                                 opp-hz = /bits/ 64 <540000000>;
4186                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4187                                         };
4188
4189                                         opp-810000000 {
4190                                                 opp-hz = /bits/ 64 <810000000>;
4191                                                 required-opps = <&rpmhpd_opp_nom>;
4192                                         };
4193                                 };
4194                         };
4195                 };
4196
4197                 pdc: interrupt-controller@b220000 {
4198                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
4199                         reg = <0 0x0b220000 0 0x30000>;
4200                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4201                                           <55 306 4>, <59 312 3>, <62 374 2>,
4202                                           <64 434 2>, <66 438 3>, <69 86 1>,
4203                                           <70 520 54>, <124 609 31>, <155 63 1>,
4204                                           <156 716 12>;
4205                         #interrupt-cells = <2>;
4206                         interrupt-parent = <&intc>;
4207                         interrupt-controller;
4208                 };
4209
4210                 pdc_reset: reset-controller@b5e0000 {
4211                         compatible = "qcom,sc7280-pdc-global";
4212                         reg = <0 0x0b5e0000 0 0x20000>;
4213                         #reset-cells = <1>;
4214                         status = "reserved"; /* Owned by firmware */
4215                 };
4216
4217                 tsens0: thermal-sensor@c263000 {
4218                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4219                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4220                                 <0 0x0c222000 0 0x1ff>; /* SROT */
4221                         #qcom,sensors = <15>;
4222                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4223                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4224                         interrupt-names = "uplow","critical";
4225                         #thermal-sensor-cells = <1>;
4226                 };
4227
4228                 tsens1: thermal-sensor@c265000 {
4229                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4230                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4231                                 <0 0x0c223000 0 0x1ff>; /* SROT */
4232                         #qcom,sensors = <12>;
4233                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4234                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4235                         interrupt-names = "uplow","critical";
4236                         #thermal-sensor-cells = <1>;
4237                 };
4238
4239                 aoss_reset: reset-controller@c2a0000 {
4240                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4241                         reg = <0 0x0c2a0000 0 0x31000>;
4242                         #reset-cells = <1>;
4243                 };
4244
4245                 aoss_qmp: power-controller@c300000 {
4246                         compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4247                         reg = <0 0x0c300000 0 0x400>;
4248                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4249                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
4250                                                      IRQ_TYPE_EDGE_RISING>;
4251                         mboxes = <&ipcc IPCC_CLIENT_AOP
4252                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
4253
4254                         #clock-cells = <0>;
4255                 };
4256
4257                 sram@c3f0000 {
4258                         compatible = "qcom,rpmh-stats";
4259                         reg = <0 0x0c3f0000 0 0x400>;
4260                 };
4261
4262                 spmi_bus: spmi@c440000 {
4263                         compatible = "qcom,spmi-pmic-arb";
4264                         reg = <0 0x0c440000 0 0x1100>,
4265                               <0 0x0c600000 0 0x2000000>,
4266                               <0 0x0e600000 0 0x100000>,
4267                               <0 0x0e700000 0 0xa0000>,
4268                               <0 0x0c40a000 0 0x26000>;
4269                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4270                         interrupt-names = "periph_irq";
4271                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4272                         qcom,ee = <0>;
4273                         qcom,channel = <0>;
4274                         #address-cells = <2>;
4275                         #size-cells = <0>;
4276                         interrupt-controller;
4277                         #interrupt-cells = <4>;
4278                 };
4279
4280                 tlmm: pinctrl@f100000 {
4281                         compatible = "qcom,sc7280-pinctrl";
4282                         reg = <0 0x0f100000 0 0x300000>;
4283                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4284                         gpio-controller;
4285                         #gpio-cells = <2>;
4286                         interrupt-controller;
4287                         #interrupt-cells = <2>;
4288                         gpio-ranges = <&tlmm 0 0 175>;
4289                         wakeup-parent = <&pdc>;
4290
4291                         dp_hot_plug_det: dp-hot-plug-det-pins {
4292                                 pins = "gpio47";
4293                                 function = "dp_hot";
4294                         };
4295
4296                         edp_hot_plug_det: edp-hot-plug-det-pins {
4297                                 pins = "gpio60";
4298                                 function = "edp_hot";
4299                         };
4300
4301                         mi2s0_data0: mi2s0-data0-pins {
4302                                 pins = "gpio98";
4303                                 function = "mi2s0_data0";
4304                         };
4305
4306                         mi2s0_data1: mi2s0-data1-pins {
4307                                 pins = "gpio99";
4308                                 function = "mi2s0_data1";
4309                         };
4310
4311                         mi2s0_mclk: mi2s0-mclk-pins {
4312                                 pins = "gpio96";
4313                                 function = "pri_mi2s";
4314                         };
4315
4316                         mi2s0_sclk: mi2s0-sclk-pins {
4317                                 pins = "gpio97";
4318                                 function = "mi2s0_sck";
4319                         };
4320
4321                         mi2s0_ws: mi2s0-ws-pins {
4322                                 pins = "gpio100";
4323                                 function = "mi2s0_ws";
4324                         };
4325
4326                         mi2s1_data0: mi2s1-data0-pins {
4327                                 pins = "gpio107";
4328                                 function = "mi2s1_data0";
4329                         };
4330
4331                         mi2s1_sclk: mi2s1-sclk-pins {
4332                                 pins = "gpio106";
4333                                 function = "mi2s1_sck";
4334                         };
4335
4336                         mi2s1_ws: mi2s1-ws-pins {
4337                                 pins = "gpio108";
4338                                 function = "mi2s1_ws";
4339                         };
4340
4341                         pcie1_clkreq_n: pcie1-clkreq-n-pins {
4342                                 pins = "gpio79";
4343                                 function = "pcie1_clkreqn";
4344                         };
4345
4346                         qspi_clk: qspi-clk-pins {
4347                                 pins = "gpio14";
4348                                 function = "qspi_clk";
4349                         };
4350
4351                         qspi_cs0: qspi-cs0-pins {
4352                                 pins = "gpio15";
4353                                 function = "qspi_cs";
4354                         };
4355
4356                         qspi_cs1: qspi-cs1-pins {
4357                                 pins = "gpio19";
4358                                 function = "qspi_cs";
4359                         };
4360
4361                         qspi_data01: qspi-data01-pins {
4362                                 pins = "gpio12", "gpio13";
4363                                 function = "qspi_data";
4364                         };
4365
4366                         qspi_data23: qspi-data23-pins {
4367                                 pins = "gpio16", "gpio17";
4368                                 function = "qspi_data";
4369                         };
4370
4371                         qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
4372                                 pins = "gpio0", "gpio1";
4373                                 function = "qup00";
4374                         };
4375
4376                         qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
4377                                 pins = "gpio4", "gpio5";
4378                                 function = "qup01";
4379                         };
4380
4381                         qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
4382                                 pins = "gpio8", "gpio9";
4383                                 function = "qup02";
4384                         };
4385
4386                         qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
4387                                 pins = "gpio12", "gpio13";
4388                                 function = "qup03";
4389                         };
4390
4391                         qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
4392                                 pins = "gpio16", "gpio17";
4393                                 function = "qup04";
4394                         };
4395
4396                         qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
4397                                 pins = "gpio20", "gpio21";
4398                                 function = "qup05";
4399                         };
4400
4401                         qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
4402                                 pins = "gpio24", "gpio25";
4403                                 function = "qup06";
4404                         };
4405
4406                         qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
4407                                 pins = "gpio28", "gpio29";
4408                                 function = "qup07";
4409                         };
4410
4411                         qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
4412                                 pins = "gpio32", "gpio33";
4413                                 function = "qup10";
4414                         };
4415
4416                         qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
4417                                 pins = "gpio36", "gpio37";
4418                                 function = "qup11";
4419                         };
4420
4421                         qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
4422                                 pins = "gpio40", "gpio41";
4423                                 function = "qup12";
4424                         };
4425
4426                         qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
4427                                 pins = "gpio44", "gpio45";
4428                                 function = "qup13";
4429                         };
4430
4431                         qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
4432                                 pins = "gpio48", "gpio49";
4433                                 function = "qup14";
4434                         };
4435
4436                         qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
4437                                 pins = "gpio52", "gpio53";
4438                                 function = "qup15";
4439                         };
4440
4441                         qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
4442                                 pins = "gpio56", "gpio57";
4443                                 function = "qup16";
4444                         };
4445
4446                         qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
4447                                 pins = "gpio60", "gpio61";
4448                                 function = "qup17";
4449                         };
4450
4451                         qup_spi0_data_clk: qup-spi0-data-clk-pins {
4452                                 pins = "gpio0", "gpio1", "gpio2";
4453                                 function = "qup00";
4454                         };
4455
4456                         qup_spi0_cs: qup-spi0-cs-pins {
4457                                 pins = "gpio3";
4458                                 function = "qup00";
4459                         };
4460
4461                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
4462                                 pins = "gpio3";
4463                                 function = "gpio";
4464                         };
4465
4466                         qup_spi1_data_clk: qup-spi1-data-clk-pins {
4467                                 pins = "gpio4", "gpio5", "gpio6";
4468                                 function = "qup01";
4469                         };
4470
4471                         qup_spi1_cs: qup-spi1-cs-pins {
4472                                 pins = "gpio7";
4473                                 function = "qup01";
4474                         };
4475
4476                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
4477                                 pins = "gpio7";
4478                                 function = "gpio";
4479                         };
4480
4481                         qup_spi2_data_clk: qup-spi2-data-clk-pins {
4482                                 pins = "gpio8", "gpio9", "gpio10";
4483                                 function = "qup02";
4484                         };
4485
4486                         qup_spi2_cs: qup-spi2-cs-pins {
4487                                 pins = "gpio11";
4488                                 function = "qup02";
4489                         };
4490
4491                         qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
4492                                 pins = "gpio11";
4493                                 function = "gpio";
4494                         };
4495
4496                         qup_spi3_data_clk: qup-spi3-data-clk-pins {
4497                                 pins = "gpio12", "gpio13", "gpio14";
4498                                 function = "qup03";
4499                         };
4500
4501                         qup_spi3_cs: qup-spi3-cs-pins {
4502                                 pins = "gpio15";
4503                                 function = "qup03";
4504                         };
4505
4506                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
4507                                 pins = "gpio15";
4508                                 function = "gpio";
4509                         };
4510
4511                         qup_spi4_data_clk: qup-spi4-data-clk-pins {
4512                                 pins = "gpio16", "gpio17", "gpio18";
4513                                 function = "qup04";
4514                         };
4515
4516                         qup_spi4_cs: qup-spi4-cs-pins {
4517                                 pins = "gpio19";
4518                                 function = "qup04";
4519                         };
4520
4521                         qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
4522                                 pins = "gpio19";
4523                                 function = "gpio";
4524                         };
4525
4526                         qup_spi5_data_clk: qup-spi5-data-clk-pins {
4527                                 pins = "gpio20", "gpio21", "gpio22";
4528                                 function = "qup05";
4529                         };
4530
4531                         qup_spi5_cs: qup-spi5-cs-pins {
4532                                 pins = "gpio23";
4533                                 function = "qup05";
4534                         };
4535
4536                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
4537                                 pins = "gpio23";
4538                                 function = "gpio";
4539                         };
4540
4541                         qup_spi6_data_clk: qup-spi6-data-clk-pins {
4542                                 pins = "gpio24", "gpio25", "gpio26";
4543                                 function = "qup06";
4544                         };
4545
4546                         qup_spi6_cs: qup-spi6-cs-pins {
4547                                 pins = "gpio27";
4548                                 function = "qup06";
4549                         };
4550
4551                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
4552                                 pins = "gpio27";
4553                                 function = "gpio";
4554                         };
4555
4556                         qup_spi7_data_clk: qup-spi7-data-clk-pins {
4557                                 pins = "gpio28", "gpio29", "gpio30";
4558                                 function = "qup07";
4559                         };
4560
4561                         qup_spi7_cs: qup-spi7-cs-pins {
4562                                 pins = "gpio31";
4563                                 function = "qup07";
4564                         };
4565
4566                         qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
4567                                 pins = "gpio31";
4568                                 function = "gpio";
4569                         };
4570
4571                         qup_spi8_data_clk: qup-spi8-data-clk-pins {
4572                                 pins = "gpio32", "gpio33", "gpio34";
4573                                 function = "qup10";
4574                         };
4575
4576                         qup_spi8_cs: qup-spi8-cs-pins {
4577                                 pins = "gpio35";
4578                                 function = "qup10";
4579                         };
4580
4581                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
4582                                 pins = "gpio35";
4583                                 function = "gpio";
4584                         };
4585
4586                         qup_spi9_data_clk: qup-spi9-data-clk-pins {
4587                                 pins = "gpio36", "gpio37", "gpio38";
4588                                 function = "qup11";
4589                         };
4590
4591                         qup_spi9_cs: qup-spi9-cs-pins {
4592                                 pins = "gpio39";
4593                                 function = "qup11";
4594                         };
4595
4596                         qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
4597                                 pins = "gpio39";
4598                                 function = "gpio";
4599                         };
4600
4601                         qup_spi10_data_clk: qup-spi10-data-clk-pins {
4602                                 pins = "gpio40", "gpio41", "gpio42";
4603                                 function = "qup12";
4604                         };
4605
4606                         qup_spi10_cs: qup-spi10-cs-pins {
4607                                 pins = "gpio43";
4608                                 function = "qup12";
4609                         };
4610
4611                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
4612                                 pins = "gpio43";
4613                                 function = "gpio";
4614                         };
4615
4616                         qup_spi11_data_clk: qup-spi11-data-clk-pins {
4617                                 pins = "gpio44", "gpio45", "gpio46";
4618                                 function = "qup13";
4619                         };
4620
4621                         qup_spi11_cs: qup-spi11-cs-pins {
4622                                 pins = "gpio47";
4623                                 function = "qup13";
4624                         };
4625
4626                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
4627                                 pins = "gpio47";
4628                                 function = "gpio";
4629                         };
4630
4631                         qup_spi12_data_clk: qup-spi12-data-clk-pins {
4632                                 pins = "gpio48", "gpio49", "gpio50";
4633                                 function = "qup14";
4634                         };
4635
4636                         qup_spi12_cs: qup-spi12-cs-pins {
4637                                 pins = "gpio51";
4638                                 function = "qup14";
4639                         };
4640
4641                         qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
4642                                 pins = "gpio51";
4643                                 function = "gpio";
4644                         };
4645
4646                         qup_spi13_data_clk: qup-spi13-data-clk-pins {
4647                                 pins = "gpio52", "gpio53", "gpio54";
4648                                 function = "qup15";
4649                         };
4650
4651                         qup_spi13_cs: qup-spi13-cs-pins {
4652                                 pins = "gpio55";
4653                                 function = "qup15";
4654                         };
4655
4656                         qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
4657                                 pins = "gpio55";
4658                                 function = "gpio";
4659                         };
4660
4661                         qup_spi14_data_clk: qup-spi14-data-clk-pins {
4662                                 pins = "gpio56", "gpio57", "gpio58";
4663                                 function = "qup16";
4664                         };
4665
4666                         qup_spi14_cs: qup-spi14-cs-pins {
4667                                 pins = "gpio59";
4668                                 function = "qup16";
4669                         };
4670
4671                         qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
4672                                 pins = "gpio59";
4673                                 function = "gpio";
4674                         };
4675
4676                         qup_spi15_data_clk: qup-spi15-data-clk-pins {
4677                                 pins = "gpio60", "gpio61", "gpio62";
4678                                 function = "qup17";
4679                         };
4680
4681                         qup_spi15_cs: qup-spi15-cs-pins {
4682                                 pins = "gpio63";
4683                                 function = "qup17";
4684                         };
4685
4686                         qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
4687                                 pins = "gpio63";
4688                                 function = "gpio";
4689                         };
4690
4691                         qup_uart0_cts: qup-uart0-cts-pins {
4692                                 pins = "gpio0";
4693                                 function = "qup00";
4694                         };
4695
4696                         qup_uart0_rts: qup-uart0-rts-pins {
4697                                 pins = "gpio1";
4698                                 function = "qup00";
4699                         };
4700
4701                         qup_uart0_tx: qup-uart0-tx-pins {
4702                                 pins = "gpio2";
4703                                 function = "qup00";
4704                         };
4705
4706                         qup_uart0_rx: qup-uart0-rx-pins {
4707                                 pins = "gpio3";
4708                                 function = "qup00";
4709                         };
4710
4711                         qup_uart1_cts: qup-uart1-cts-pins {
4712                                 pins = "gpio4";
4713                                 function = "qup01";
4714                         };
4715
4716                         qup_uart1_rts: qup-uart1-rts-pins {
4717                                 pins = "gpio5";
4718                                 function = "qup01";
4719                         };
4720
4721                         qup_uart1_tx: qup-uart1-tx-pins {
4722                                 pins = "gpio6";
4723                                 function = "qup01";
4724                         };
4725
4726                         qup_uart1_rx: qup-uart1-rx-pins {
4727                                 pins = "gpio7";
4728                                 function = "qup01";
4729                         };
4730
4731                         qup_uart2_cts: qup-uart2-cts-pins {
4732                                 pins = "gpio8";
4733                                 function = "qup02";
4734                         };
4735
4736                         qup_uart2_rts: qup-uart2-rts-pins {
4737                                 pins = "gpio9";
4738                                 function = "qup02";
4739                         };
4740
4741                         qup_uart2_tx: qup-uart2-tx-pins {
4742                                 pins = "gpio10";
4743                                 function = "qup02";
4744                         };
4745
4746                         qup_uart2_rx: qup-uart2-rx-pins {
4747                                 pins = "gpio11";
4748                                 function = "qup02";
4749                         };
4750
4751                         qup_uart3_cts: qup-uart3-cts-pins {
4752                                 pins = "gpio12";
4753                                 function = "qup03";
4754                         };
4755
4756                         qup_uart3_rts: qup-uart3-rts-pins {
4757                                 pins = "gpio13";
4758                                 function = "qup03";
4759                         };
4760
4761                         qup_uart3_tx: qup-uart3-tx-pins {
4762                                 pins = "gpio14";
4763                                 function = "qup03";
4764                         };
4765
4766                         qup_uart3_rx: qup-uart3-rx-pins {
4767                                 pins = "gpio15";
4768                                 function = "qup03";
4769                         };
4770
4771                         qup_uart4_cts: qup-uart4-cts-pins {
4772                                 pins = "gpio16";
4773                                 function = "qup04";
4774                         };
4775
4776                         qup_uart4_rts: qup-uart4-rts-pins {
4777                                 pins = "gpio17";
4778                                 function = "qup04";
4779                         };
4780
4781                         qup_uart4_tx: qup-uart4-tx-pins {
4782                                 pins = "gpio18";
4783                                 function = "qup04";
4784                         };
4785
4786                         qup_uart4_rx: qup-uart4-rx-pins {
4787                                 pins = "gpio19";
4788                                 function = "qup04";
4789                         };
4790
4791                         qup_uart5_cts: qup-uart5-cts-pins {
4792                                 pins = "gpio20";
4793                                 function = "qup05";
4794                         };
4795
4796                         qup_uart5_rts: qup-uart5-rts-pins {
4797                                 pins = "gpio21";
4798                                 function = "qup05";
4799                         };
4800
4801                         qup_uart5_tx: qup-uart5-tx-pins {
4802                                 pins = "gpio22";
4803                                 function = "qup05";
4804                         };
4805
4806                         qup_uart5_rx: qup-uart5-rx-pins {
4807                                 pins = "gpio23";
4808                                 function = "qup05";
4809                         };
4810
4811                         qup_uart6_cts: qup-uart6-cts-pins {
4812                                 pins = "gpio24";
4813                                 function = "qup06";
4814                         };
4815
4816                         qup_uart6_rts: qup-uart6-rts-pins {
4817                                 pins = "gpio25";
4818                                 function = "qup06";
4819                         };
4820
4821                         qup_uart6_tx: qup-uart6-tx-pins {
4822                                 pins = "gpio26";
4823                                 function = "qup06";
4824                         };
4825
4826                         qup_uart6_rx: qup-uart6-rx-pins {
4827                                 pins = "gpio27";
4828                                 function = "qup06";
4829                         };
4830
4831                         qup_uart7_cts: qup-uart7-cts-pins {
4832                                 pins = "gpio28";
4833                                 function = "qup07";
4834                         };
4835
4836                         qup_uart7_rts: qup-uart7-rts-pins {
4837                                 pins = "gpio29";
4838                                 function = "qup07";
4839                         };
4840
4841                         qup_uart7_tx: qup-uart7-tx-pins {
4842                                 pins = "gpio30";
4843                                 function = "qup07";
4844                         };
4845
4846                         qup_uart7_rx: qup-uart7-rx-pins {
4847                                 pins = "gpio31";
4848                                 function = "qup07";
4849                         };
4850
4851                         qup_uart8_cts: qup-uart8-cts-pins {
4852                                 pins = "gpio32";
4853                                 function = "qup10";
4854                         };
4855
4856                         qup_uart8_rts: qup-uart8-rts-pins {
4857                                 pins = "gpio33";
4858                                 function = "qup10";
4859                         };
4860
4861                         qup_uart8_tx: qup-uart8-tx-pins {
4862                                 pins = "gpio34";
4863                                 function = "qup10";
4864                         };
4865
4866                         qup_uart8_rx: qup-uart8-rx-pins {
4867                                 pins = "gpio35";
4868                                 function = "qup10";
4869                         };
4870
4871                         qup_uart9_cts: qup-uart9-cts-pins {
4872                                 pins = "gpio36";
4873                                 function = "qup11";
4874                         };
4875
4876                         qup_uart9_rts: qup-uart9-rts-pins {
4877                                 pins = "gpio37";
4878                                 function = "qup11";
4879                         };
4880
4881                         qup_uart9_tx: qup-uart9-tx-pins {
4882                                 pins = "gpio38";
4883                                 function = "qup11";
4884                         };
4885
4886                         qup_uart9_rx: qup-uart9-rx-pins {
4887                                 pins = "gpio39";
4888                                 function = "qup11";
4889                         };
4890
4891                         qup_uart10_cts: qup-uart10-cts-pins {
4892                                 pins = "gpio40";
4893                                 function = "qup12";
4894                         };
4895
4896                         qup_uart10_rts: qup-uart10-rts-pins {
4897                                 pins = "gpio41";
4898                                 function = "qup12";
4899                         };
4900
4901                         qup_uart10_tx: qup-uart10-tx-pins {
4902                                 pins = "gpio42";
4903                                 function = "qup12";
4904                         };
4905
4906                         qup_uart10_rx: qup-uart10-rx-pins {
4907                                 pins = "gpio43";
4908                                 function = "qup12";
4909                         };
4910
4911                         qup_uart11_cts: qup-uart11-cts-pins {
4912                                 pins = "gpio44";
4913                                 function = "qup13";
4914                         };
4915
4916                         qup_uart11_rts: qup-uart11-rts-pins {
4917                                 pins = "gpio45";
4918                                 function = "qup13";
4919                         };
4920
4921                         qup_uart11_tx: qup-uart11-tx-pins {
4922                                 pins = "gpio46";
4923                                 function = "qup13";
4924                         };
4925
4926                         qup_uart11_rx: qup-uart11-rx-pins {
4927                                 pins = "gpio47";
4928                                 function = "qup13";
4929                         };
4930
4931                         qup_uart12_cts: qup-uart12-cts-pins {
4932                                 pins = "gpio48";
4933                                 function = "qup14";
4934                         };
4935
4936                         qup_uart12_rts: qup-uart12-rts-pins {
4937                                 pins = "gpio49";
4938                                 function = "qup14";
4939                         };
4940
4941                         qup_uart12_tx: qup-uart12-tx-pins {
4942                                 pins = "gpio50";
4943                                 function = "qup14";
4944                         };
4945
4946                         qup_uart12_rx: qup-uart12-rx-pins {
4947                                 pins = "gpio51";
4948                                 function = "qup14";
4949                         };
4950
4951                         qup_uart13_cts: qup-uart13-cts-pins {
4952                                 pins = "gpio52";
4953                                 function = "qup15";
4954                         };
4955
4956                         qup_uart13_rts: qup-uart13-rts-pins {
4957                                 pins = "gpio53";
4958                                 function = "qup15";
4959                         };
4960
4961                         qup_uart13_tx: qup-uart13-tx-pins {
4962                                 pins = "gpio54";
4963                                 function = "qup15";
4964                         };
4965
4966                         qup_uart13_rx: qup-uart13-rx-pins {
4967                                 pins = "gpio55";
4968                                 function = "qup15";
4969                         };
4970
4971                         qup_uart14_cts: qup-uart14-cts-pins {
4972                                 pins = "gpio56";
4973                                 function = "qup16";
4974                         };
4975
4976                         qup_uart14_rts: qup-uart14-rts-pins {
4977                                 pins = "gpio57";
4978                                 function = "qup16";
4979                         };
4980
4981                         qup_uart14_tx: qup-uart14-tx-pins {
4982                                 pins = "gpio58";
4983                                 function = "qup16";
4984                         };
4985
4986                         qup_uart14_rx: qup-uart14-rx-pins {
4987                                 pins = "gpio59";
4988                                 function = "qup16";
4989                         };
4990
4991                         qup_uart15_cts: qup-uart15-cts-pins {
4992                                 pins = "gpio60";
4993                                 function = "qup17";
4994                         };
4995
4996                         qup_uart15_rts: qup-uart15-rts-pins {
4997                                 pins = "gpio61";
4998                                 function = "qup17";
4999                         };
5000
5001                         qup_uart15_tx: qup-uart15-tx-pins {
5002                                 pins = "gpio62";
5003                                 function = "qup17";
5004                         };
5005
5006                         qup_uart15_rx: qup-uart15-rx-pins {
5007                                 pins = "gpio63";
5008                                 function = "qup17";
5009                         };
5010
5011                         sdc1_clk: sdc1-clk-pins {
5012                                 pins = "sdc1_clk";
5013                         };
5014
5015                         sdc1_cmd: sdc1-cmd-pins {
5016                                 pins = "sdc1_cmd";
5017                         };
5018
5019                         sdc1_data: sdc1-data-pins {
5020                                 pins = "sdc1_data";
5021                         };
5022
5023                         sdc1_rclk: sdc1-rclk-pins {
5024                                 pins = "sdc1_rclk";
5025                         };
5026
5027                         sdc1_clk_sleep: sdc1-clk-sleep-pins {
5028                                 pins = "sdc1_clk";
5029                                 drive-strength = <2>;
5030                                 bias-bus-hold;
5031                         };
5032
5033                         sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
5034                                 pins = "sdc1_cmd";
5035                                 drive-strength = <2>;
5036                                 bias-bus-hold;
5037                         };
5038
5039                         sdc1_data_sleep: sdc1-data-sleep-pins {
5040                                 pins = "sdc1_data";
5041                                 drive-strength = <2>;
5042                                 bias-bus-hold;
5043                         };
5044
5045                         sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
5046                                 pins = "sdc1_rclk";
5047                                 drive-strength = <2>;
5048                                 bias-bus-hold;
5049                         };
5050
5051                         sdc2_clk: sdc2-clk-pins {
5052                                 pins = "sdc2_clk";
5053                         };
5054
5055                         sdc2_cmd: sdc2-cmd-pins {
5056                                 pins = "sdc2_cmd";
5057                         };
5058
5059                         sdc2_data: sdc2-data-pins {
5060                                 pins = "sdc2_data";
5061                         };
5062
5063                         sdc2_clk_sleep: sdc2-clk-sleep-pins {
5064                                 pins = "sdc2_clk";
5065                                 drive-strength = <2>;
5066                                 bias-bus-hold;
5067                         };
5068
5069                         sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
5070                                 pins = "sdc2_cmd";
5071                                 drive-strength = <2>;
5072                                 bias-bus-hold;
5073                         };
5074
5075                         sdc2_data_sleep: sdc2-data-sleep-pins {
5076                                 pins = "sdc2_data";
5077                                 drive-strength = <2>;
5078                                 bias-bus-hold;
5079                         };
5080                 };
5081
5082                 sram@146a5000 {
5083                         compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5084                         reg = <0 0x146a5000 0 0x6000>;
5085
5086                         #address-cells = <1>;
5087                         #size-cells = <1>;
5088
5089                         ranges = <0 0 0x146a5000 0x6000>;
5090
5091                         pil-reloc@594c {
5092                                 compatible = "qcom,pil-reloc-info";
5093                                 reg = <0x594c 0xc8>;
5094                         };
5095                 };
5096
5097                 apps_smmu: iommu@15000000 {
5098                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5099                         reg = <0 0x15000000 0 0x100000>;
5100                         #iommu-cells = <2>;
5101                         #global-interrupts = <1>;
5102                         dma-coherent;
5103                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5104                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5105                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5106                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5107                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5108                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5109                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5110                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5111                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5112                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5113                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5114                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5115                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5116                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5117                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5118                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5119                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5120                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5121                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5122                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5123                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5124                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5125                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5126                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5127                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5128                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5129                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5130                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5131                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5132                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5133                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5134                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5135                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5136                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5137                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5138                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5139                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5140                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5141                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5142                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5143                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5144                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5145                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5146                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5147                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5148                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5149                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5150                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5151                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5152                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5153                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5154                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5155                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5156                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5157                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5158                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5159                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5160                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5161                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5162                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5163                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5164                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5165                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5166                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5167                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5168                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5169                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5170                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5171                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5172                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5173                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5174                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5175                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5176                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5177                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5178                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5179                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5180                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5181                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5182                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5183                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
5184                 };
5185
5186                 intc: interrupt-controller@17a00000 {
5187                         compatible = "arm,gic-v3";
5188                         #address-cells = <2>;
5189                         #size-cells = <2>;
5190                         ranges;
5191                         #interrupt-cells = <3>;
5192                         interrupt-controller;
5193                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
5194                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
5195                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
5196
5197                         gic-its@17a40000 {
5198                                 compatible = "arm,gic-v3-its";
5199                                 msi-controller;
5200                                 #msi-cells = <1>;
5201                                 reg = <0 0x17a40000 0 0x20000>;
5202                                 status = "disabled";
5203                         };
5204                 };
5205
5206                 watchdog: watchdog@17c10000 {
5207                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5208                         reg = <0 0x17c10000 0 0x1000>;
5209                         clocks = <&sleep_clk>;
5210                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5211                         status = "reserved"; /* Owned by Gunyah hyp */
5212                 };
5213
5214                 timer@17c20000 {
5215                         #address-cells = <1>;
5216                         #size-cells = <1>;
5217                         ranges = <0 0 0 0x20000000>;
5218                         compatible = "arm,armv7-timer-mem";
5219                         reg = <0 0x17c20000 0 0x1000>;
5220
5221                         frame@17c21000 {
5222                                 frame-number = <0>;
5223                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5224                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5225                                 reg = <0x17c21000 0x1000>,
5226                                       <0x17c22000 0x1000>;
5227                         };
5228
5229                         frame@17c23000 {
5230                                 frame-number = <1>;
5231                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5232                                 reg = <0x17c23000 0x1000>;
5233                                 status = "disabled";
5234                         };
5235
5236                         frame@17c25000 {
5237                                 frame-number = <2>;
5238                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5239                                 reg = <0x17c25000 0x1000>;
5240                                 status = "disabled";
5241                         };
5242
5243                         frame@17c27000 {
5244                                 frame-number = <3>;
5245                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5246                                 reg = <0x17c27000 0x1000>;
5247                                 status = "disabled";
5248                         };
5249
5250                         frame@17c29000 {
5251                                 frame-number = <4>;
5252                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5253                                 reg = <0x17c29000 0x1000>;
5254                                 status = "disabled";
5255                         };
5256
5257                         frame@17c2b000 {
5258                                 frame-number = <5>;
5259                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5260                                 reg = <0x17c2b000 0x1000>;
5261                                 status = "disabled";
5262                         };
5263
5264                         frame@17c2d000 {
5265                                 frame-number = <6>;
5266                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5267                                 reg = <0x17c2d000 0x1000>;
5268                                 status = "disabled";
5269                         };
5270                 };
5271
5272                 apps_rsc: rsc@18200000 {
5273                         compatible = "qcom,rpmh-rsc";
5274                         reg = <0 0x18200000 0 0x10000>,
5275                               <0 0x18210000 0 0x10000>,
5276                               <0 0x18220000 0 0x10000>;
5277                         reg-names = "drv-0", "drv-1", "drv-2";
5278                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5279                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5280                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5281                         qcom,tcs-offset = <0xd00>;
5282                         qcom,drv-id = <2>;
5283                         qcom,tcs-config = <ACTIVE_TCS  2>,
5284                                           <SLEEP_TCS   3>,
5285                                           <WAKE_TCS    3>,
5286                                           <CONTROL_TCS 1>;
5287
5288                         apps_bcm_voter: bcm-voter {
5289                                 compatible = "qcom,bcm-voter";
5290                         };
5291
5292                         rpmhpd: power-controller {
5293                                 compatible = "qcom,sc7280-rpmhpd";
5294                                 #power-domain-cells = <1>;
5295                                 operating-points-v2 = <&rpmhpd_opp_table>;
5296
5297                                 rpmhpd_opp_table: opp-table {
5298                                         compatible = "operating-points-v2";
5299
5300                                         rpmhpd_opp_ret: opp1 {
5301                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5302                                         };
5303
5304                                         rpmhpd_opp_low_svs: opp2 {
5305                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5306                                         };
5307
5308                                         rpmhpd_opp_svs: opp3 {
5309                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5310                                         };
5311
5312                                         rpmhpd_opp_svs_l1: opp4 {
5313                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5314                                         };
5315
5316                                         rpmhpd_opp_svs_l2: opp5 {
5317                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5318                                         };
5319
5320                                         rpmhpd_opp_nom: opp6 {
5321                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5322                                         };
5323
5324                                         rpmhpd_opp_nom_l1: opp7 {
5325                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5326                                         };
5327
5328                                         rpmhpd_opp_turbo: opp8 {
5329                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5330                                         };
5331
5332                                         rpmhpd_opp_turbo_l1: opp9 {
5333                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5334                                         };
5335                                 };
5336                         };
5337
5338                         rpmhcc: clock-controller {
5339                                 compatible = "qcom,sc7280-rpmh-clk";
5340                                 clocks = <&xo_board>;
5341                                 clock-names = "xo";
5342                                 #clock-cells = <1>;
5343                         };
5344                 };
5345
5346                 epss_l3: interconnect@18590000 {
5347                         compatible = "qcom,sc7280-epss-l3";
5348                         reg = <0 0x18590000 0 0x1000>;
5349                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5350                         clock-names = "xo", "alternate";
5351                         #interconnect-cells = <1>;
5352                 };
5353
5354                 cpufreq_hw: cpufreq@18591000 {
5355                         compatible = "qcom,cpufreq-epss";
5356                         reg = <0 0x18591000 0 0x1000>,
5357                               <0 0x18592000 0 0x1000>,
5358                               <0 0x18593000 0 0x1000>;
5359
5360                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5361                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5362                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5363                         interrupt-names = "dcvsh-irq-0",
5364                                           "dcvsh-irq-1",
5365                                           "dcvsh-irq-2";
5366
5367                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5368                         clock-names = "xo", "alternate";
5369                         #freq-domain-cells = <1>;
5370                 };
5371         };
5372
5373         thermal_zones: thermal-zones {
5374                 cpu0-thermal {
5375                         polling-delay-passive = <250>;
5376                         polling-delay = <0>;
5377
5378                         thermal-sensors = <&tsens0 1>;
5379
5380                         trips {
5381                                 cpu0_alert0: trip-point0 {
5382                                         temperature = <90000>;
5383                                         hysteresis = <2000>;
5384                                         type = "passive";
5385                                 };
5386
5387                                 cpu0_alert1: trip-point1 {
5388                                         temperature = <95000>;
5389                                         hysteresis = <2000>;
5390                                         type = "passive";
5391                                 };
5392
5393                                 cpu0_crit: cpu-crit {
5394                                         temperature = <110000>;
5395                                         hysteresis = <0>;
5396                                         type = "critical";
5397                                 };
5398                         };
5399
5400                         cooling-maps {
5401                                 map0 {
5402                                         trip = <&cpu0_alert0>;
5403                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5404                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5405                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5406                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5407                                 };
5408                                 map1 {
5409                                         trip = <&cpu0_alert1>;
5410                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5411                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5412                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5413                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5414                                 };
5415                         };
5416                 };
5417
5418                 cpu1-thermal {
5419                         polling-delay-passive = <250>;
5420                         polling-delay = <0>;
5421
5422                         thermal-sensors = <&tsens0 2>;
5423
5424                         trips {
5425                                 cpu1_alert0: trip-point0 {
5426                                         temperature = <90000>;
5427                                         hysteresis = <2000>;
5428                                         type = "passive";
5429                                 };
5430
5431                                 cpu1_alert1: trip-point1 {
5432                                         temperature = <95000>;
5433                                         hysteresis = <2000>;
5434                                         type = "passive";
5435                                 };
5436
5437                                 cpu1_crit: cpu-crit {
5438                                         temperature = <110000>;
5439                                         hysteresis = <0>;
5440                                         type = "critical";
5441                                 };
5442                         };
5443
5444                         cooling-maps {
5445                                 map0 {
5446                                         trip = <&cpu1_alert0>;
5447                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5448                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5449                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5450                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5451                                 };
5452                                 map1 {
5453                                         trip = <&cpu1_alert1>;
5454                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5455                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5456                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5457                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5458                                 };
5459                         };
5460                 };
5461
5462                 cpu2-thermal {
5463                         polling-delay-passive = <250>;
5464                         polling-delay = <0>;
5465
5466                         thermal-sensors = <&tsens0 3>;
5467
5468                         trips {
5469                                 cpu2_alert0: trip-point0 {
5470                                         temperature = <90000>;
5471                                         hysteresis = <2000>;
5472                                         type = "passive";
5473                                 };
5474
5475                                 cpu2_alert1: trip-point1 {
5476                                         temperature = <95000>;
5477                                         hysteresis = <2000>;
5478                                         type = "passive";
5479                                 };
5480
5481                                 cpu2_crit: cpu-crit {
5482                                         temperature = <110000>;
5483                                         hysteresis = <0>;
5484                                         type = "critical";
5485                                 };
5486                         };
5487
5488                         cooling-maps {
5489                                 map0 {
5490                                         trip = <&cpu2_alert0>;
5491                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5492                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5493                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5494                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5495                                 };
5496                                 map1 {
5497                                         trip = <&cpu2_alert1>;
5498                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5499                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5500                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5501                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5502                                 };
5503                         };
5504                 };
5505
5506                 cpu3-thermal {
5507                         polling-delay-passive = <250>;
5508                         polling-delay = <0>;
5509
5510                         thermal-sensors = <&tsens0 4>;
5511
5512                         trips {
5513                                 cpu3_alert0: trip-point0 {
5514                                         temperature = <90000>;
5515                                         hysteresis = <2000>;
5516                                         type = "passive";
5517                                 };
5518
5519                                 cpu3_alert1: trip-point1 {
5520                                         temperature = <95000>;
5521                                         hysteresis = <2000>;
5522                                         type = "passive";
5523                                 };
5524
5525                                 cpu3_crit: cpu-crit {
5526                                         temperature = <110000>;
5527                                         hysteresis = <0>;
5528                                         type = "critical";
5529                                 };
5530                         };
5531
5532                         cooling-maps {
5533                                 map0 {
5534                                         trip = <&cpu3_alert0>;
5535                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5536                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5537                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5538                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5539                                 };
5540                                 map1 {
5541                                         trip = <&cpu3_alert1>;
5542                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5543                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5544                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5545                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5546                                 };
5547                         };
5548                 };
5549
5550                 cpu4-thermal {
5551                         polling-delay-passive = <250>;
5552                         polling-delay = <0>;
5553
5554                         thermal-sensors = <&tsens0 7>;
5555
5556                         trips {
5557                                 cpu4_alert0: trip-point0 {
5558                                         temperature = <90000>;
5559                                         hysteresis = <2000>;
5560                                         type = "passive";
5561                                 };
5562
5563                                 cpu4_alert1: trip-point1 {
5564                                         temperature = <95000>;
5565                                         hysteresis = <2000>;
5566                                         type = "passive";
5567                                 };
5568
5569                                 cpu4_crit: cpu-crit {
5570                                         temperature = <110000>;
5571                                         hysteresis = <0>;
5572                                         type = "critical";
5573                                 };
5574                         };
5575
5576                         cooling-maps {
5577                                 map0 {
5578                                         trip = <&cpu4_alert0>;
5579                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5580                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5581                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5582                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5583                                 };
5584                                 map1 {
5585                                         trip = <&cpu4_alert1>;
5586                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5587                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5588                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5589                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5590                                 };
5591                         };
5592                 };
5593
5594                 cpu5-thermal {
5595                         polling-delay-passive = <250>;
5596                         polling-delay = <0>;
5597
5598                         thermal-sensors = <&tsens0 8>;
5599
5600                         trips {
5601                                 cpu5_alert0: trip-point0 {
5602                                         temperature = <90000>;
5603                                         hysteresis = <2000>;
5604                                         type = "passive";
5605                                 };
5606
5607                                 cpu5_alert1: trip-point1 {
5608                                         temperature = <95000>;
5609                                         hysteresis = <2000>;
5610                                         type = "passive";
5611                                 };
5612
5613                                 cpu5_crit: cpu-crit {
5614                                         temperature = <110000>;
5615                                         hysteresis = <0>;
5616                                         type = "critical";
5617                                 };
5618                         };
5619
5620                         cooling-maps {
5621                                 map0 {
5622                                         trip = <&cpu5_alert0>;
5623                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5624                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5625                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5626                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5627                                 };
5628                                 map1 {
5629                                         trip = <&cpu5_alert1>;
5630                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5631                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5632                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5633                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5634                                 };
5635                         };
5636                 };
5637
5638                 cpu6-thermal {
5639                         polling-delay-passive = <250>;
5640                         polling-delay = <0>;
5641
5642                         thermal-sensors = <&tsens0 9>;
5643
5644                         trips {
5645                                 cpu6_alert0: trip-point0 {
5646                                         temperature = <90000>;
5647                                         hysteresis = <2000>;
5648                                         type = "passive";
5649                                 };
5650
5651                                 cpu6_alert1: trip-point1 {
5652                                         temperature = <95000>;
5653                                         hysteresis = <2000>;
5654                                         type = "passive";
5655                                 };
5656
5657                                 cpu6_crit: cpu-crit {
5658                                         temperature = <110000>;
5659                                         hysteresis = <0>;
5660                                         type = "critical";
5661                                 };
5662                         };
5663
5664                         cooling-maps {
5665                                 map0 {
5666                                         trip = <&cpu6_alert0>;
5667                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5668                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5669                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5670                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5671                                 };
5672                                 map1 {
5673                                         trip = <&cpu6_alert1>;
5674                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5675                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5676                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5677                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5678                                 };
5679                         };
5680                 };
5681
5682                 cpu7-thermal {
5683                         polling-delay-passive = <250>;
5684                         polling-delay = <0>;
5685
5686                         thermal-sensors = <&tsens0 10>;
5687
5688                         trips {
5689                                 cpu7_alert0: trip-point0 {
5690                                         temperature = <90000>;
5691                                         hysteresis = <2000>;
5692                                         type = "passive";
5693                                 };
5694
5695                                 cpu7_alert1: trip-point1 {
5696                                         temperature = <95000>;
5697                                         hysteresis = <2000>;
5698                                         type = "passive";
5699                                 };
5700
5701                                 cpu7_crit: cpu-crit {
5702                                         temperature = <110000>;
5703                                         hysteresis = <0>;
5704                                         type = "critical";
5705                                 };
5706                         };
5707
5708                         cooling-maps {
5709                                 map0 {
5710                                         trip = <&cpu7_alert0>;
5711                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5712                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5713                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5714                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5715                                 };
5716                                 map1 {
5717                                         trip = <&cpu7_alert1>;
5718                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5719                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5720                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5721                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5722                                 };
5723                         };
5724                 };
5725
5726                 cpu8-thermal {
5727                         polling-delay-passive = <250>;
5728                         polling-delay = <0>;
5729
5730                         thermal-sensors = <&tsens0 11>;
5731
5732                         trips {
5733                                 cpu8_alert0: trip-point0 {
5734                                         temperature = <90000>;
5735                                         hysteresis = <2000>;
5736                                         type = "passive";
5737                                 };
5738
5739                                 cpu8_alert1: trip-point1 {
5740                                         temperature = <95000>;
5741                                         hysteresis = <2000>;
5742                                         type = "passive";
5743                                 };
5744
5745                                 cpu8_crit: cpu-crit {
5746                                         temperature = <110000>;
5747                                         hysteresis = <0>;
5748                                         type = "critical";
5749                                 };
5750                         };
5751
5752                         cooling-maps {
5753                                 map0 {
5754                                         trip = <&cpu8_alert0>;
5755                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5756                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5757                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5758                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5759                                 };
5760                                 map1 {
5761                                         trip = <&cpu8_alert1>;
5762                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5763                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5764                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5765                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5766                                 };
5767                         };
5768                 };
5769
5770                 cpu9-thermal {
5771                         polling-delay-passive = <250>;
5772                         polling-delay = <0>;
5773
5774                         thermal-sensors = <&tsens0 12>;
5775
5776                         trips {
5777                                 cpu9_alert0: trip-point0 {
5778                                         temperature = <90000>;
5779                                         hysteresis = <2000>;
5780                                         type = "passive";
5781                                 };
5782
5783                                 cpu9_alert1: trip-point1 {
5784                                         temperature = <95000>;
5785                                         hysteresis = <2000>;
5786                                         type = "passive";
5787                                 };
5788
5789                                 cpu9_crit: cpu-crit {
5790                                         temperature = <110000>;
5791                                         hysteresis = <0>;
5792                                         type = "critical";
5793                                 };
5794                         };
5795
5796                         cooling-maps {
5797                                 map0 {
5798                                         trip = <&cpu9_alert0>;
5799                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5800                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5801                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5802                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5803                                 };
5804                                 map1 {
5805                                         trip = <&cpu9_alert1>;
5806                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5807                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5808                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5809                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5810                                 };
5811                         };
5812                 };
5813
5814                 cpu10-thermal {
5815                         polling-delay-passive = <250>;
5816                         polling-delay = <0>;
5817
5818                         thermal-sensors = <&tsens0 13>;
5819
5820                         trips {
5821                                 cpu10_alert0: trip-point0 {
5822                                         temperature = <90000>;
5823                                         hysteresis = <2000>;
5824                                         type = "passive";
5825                                 };
5826
5827                                 cpu10_alert1: trip-point1 {
5828                                         temperature = <95000>;
5829                                         hysteresis = <2000>;
5830                                         type = "passive";
5831                                 };
5832
5833                                 cpu10_crit: cpu-crit {
5834                                         temperature = <110000>;
5835                                         hysteresis = <0>;
5836                                         type = "critical";
5837                                 };
5838                         };
5839
5840                         cooling-maps {
5841                                 map0 {
5842                                         trip = <&cpu10_alert0>;
5843                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5844                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5845                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5846                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5847                                 };
5848                                 map1 {
5849                                         trip = <&cpu10_alert1>;
5850                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5851                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5852                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5853                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5854                                 };
5855                         };
5856                 };
5857
5858                 cpu11-thermal {
5859                         polling-delay-passive = <250>;
5860                         polling-delay = <0>;
5861
5862                         thermal-sensors = <&tsens0 14>;
5863
5864                         trips {
5865                                 cpu11_alert0: trip-point0 {
5866                                         temperature = <90000>;
5867                                         hysteresis = <2000>;
5868                                         type = "passive";
5869                                 };
5870
5871                                 cpu11_alert1: trip-point1 {
5872                                         temperature = <95000>;
5873                                         hysteresis = <2000>;
5874                                         type = "passive";
5875                                 };
5876
5877                                 cpu11_crit: cpu-crit {
5878                                         temperature = <110000>;
5879                                         hysteresis = <0>;
5880                                         type = "critical";
5881                                 };
5882                         };
5883
5884                         cooling-maps {
5885                                 map0 {
5886                                         trip = <&cpu11_alert0>;
5887                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5888                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5889                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5890                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5891                                 };
5892                                 map1 {
5893                                         trip = <&cpu11_alert1>;
5894                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5895                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5896                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5897                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5898                                 };
5899                         };
5900                 };
5901
5902                 aoss0-thermal {
5903                         polling-delay-passive = <0>;
5904                         polling-delay = <0>;
5905
5906                         thermal-sensors = <&tsens0 0>;
5907
5908                         trips {
5909                                 aoss0_alert0: trip-point0 {
5910                                         temperature = <90000>;
5911                                         hysteresis = <2000>;
5912                                         type = "hot";
5913                                 };
5914
5915                                 aoss0_crit: aoss0-crit {
5916                                         temperature = <110000>;
5917                                         hysteresis = <0>;
5918                                         type = "critical";
5919                                 };
5920                         };
5921                 };
5922
5923                 aoss1-thermal {
5924                         polling-delay-passive = <0>;
5925                         polling-delay = <0>;
5926
5927                         thermal-sensors = <&tsens1 0>;
5928
5929                         trips {
5930                                 aoss1_alert0: trip-point0 {
5931                                         temperature = <90000>;
5932                                         hysteresis = <2000>;
5933                                         type = "hot";
5934                                 };
5935
5936                                 aoss1_crit: aoss1-crit {
5937                                         temperature = <110000>;
5938                                         hysteresis = <0>;
5939                                         type = "critical";
5940                                 };
5941                         };
5942                 };
5943
5944                 cpuss0-thermal {
5945                         polling-delay-passive = <0>;
5946                         polling-delay = <0>;
5947
5948                         thermal-sensors = <&tsens0 5>;
5949
5950                         trips {
5951                                 cpuss0_alert0: trip-point0 {
5952                                         temperature = <90000>;
5953                                         hysteresis = <2000>;
5954                                         type = "hot";
5955                                 };
5956                                 cpuss0_crit: cluster0-crit {
5957                                         temperature = <110000>;
5958                                         hysteresis = <0>;
5959                                         type = "critical";
5960                                 };
5961                         };
5962                 };
5963
5964                 cpuss1-thermal {
5965                         polling-delay-passive = <0>;
5966                         polling-delay = <0>;
5967
5968                         thermal-sensors = <&tsens0 6>;
5969
5970                         trips {
5971                                 cpuss1_alert0: trip-point0 {
5972                                         temperature = <90000>;
5973                                         hysteresis = <2000>;
5974                                         type = "hot";
5975                                 };
5976                                 cpuss1_crit: cluster0-crit {
5977                                         temperature = <110000>;
5978                                         hysteresis = <0>;
5979                                         type = "critical";
5980                                 };
5981                         };
5982                 };
5983
5984                 gpuss0-thermal {
5985                         polling-delay-passive = <100>;
5986                         polling-delay = <0>;
5987
5988                         thermal-sensors = <&tsens1 1>;
5989
5990                         trips {
5991                                 gpuss0_alert0: trip-point0 {
5992                                         temperature = <95000>;
5993                                         hysteresis = <2000>;
5994                                         type = "passive";
5995                                 };
5996
5997                                 gpuss0_crit: gpuss0-crit {
5998                                         temperature = <110000>;
5999                                         hysteresis = <0>;
6000                                         type = "critical";
6001                                 };
6002                         };
6003
6004                         cooling-maps {
6005                                 map0 {
6006                                         trip = <&gpuss0_alert0>;
6007                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6008                                 };
6009                         };
6010                 };
6011
6012                 gpuss1-thermal {
6013                         polling-delay-passive = <100>;
6014                         polling-delay = <0>;
6015
6016                         thermal-sensors = <&tsens1 2>;
6017
6018                         trips {
6019                                 gpuss1_alert0: trip-point0 {
6020                                         temperature = <95000>;
6021                                         hysteresis = <2000>;
6022                                         type = "passive";
6023                                 };
6024
6025                                 gpuss1_crit: gpuss1-crit {
6026                                         temperature = <110000>;
6027                                         hysteresis = <0>;
6028                                         type = "critical";
6029                                 };
6030                         };
6031
6032                         cooling-maps {
6033                                 map0 {
6034                                         trip = <&gpuss1_alert0>;
6035                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6036                                 };
6037                         };
6038                 };
6039
6040                 nspss0-thermal {
6041                         polling-delay-passive = <0>;
6042                         polling-delay = <0>;
6043
6044                         thermal-sensors = <&tsens1 3>;
6045
6046                         trips {
6047                                 nspss0_alert0: trip-point0 {
6048                                         temperature = <90000>;
6049                                         hysteresis = <2000>;
6050                                         type = "hot";
6051                                 };
6052
6053                                 nspss0_crit: nspss0-crit {
6054                                         temperature = <110000>;
6055                                         hysteresis = <0>;
6056                                         type = "critical";
6057                                 };
6058                         };
6059                 };
6060
6061                 nspss1-thermal {
6062                         polling-delay-passive = <0>;
6063                         polling-delay = <0>;
6064
6065                         thermal-sensors = <&tsens1 4>;
6066
6067                         trips {
6068                                 nspss1_alert0: trip-point0 {
6069                                         temperature = <90000>;
6070                                         hysteresis = <2000>;
6071                                         type = "hot";
6072                                 };
6073
6074                                 nspss1_crit: nspss1-crit {
6075                                         temperature = <110000>;
6076                                         hysteresis = <0>;
6077                                         type = "critical";
6078                                 };
6079                         };
6080                 };
6081
6082                 video-thermal {
6083                         polling-delay-passive = <0>;
6084                         polling-delay = <0>;
6085
6086                         thermal-sensors = <&tsens1 5>;
6087
6088                         trips {
6089                                 video_alert0: trip-point0 {
6090                                         temperature = <90000>;
6091                                         hysteresis = <2000>;
6092                                         type = "hot";
6093                                 };
6094
6095                                 video_crit: video-crit {
6096                                         temperature = <110000>;
6097                                         hysteresis = <0>;
6098                                         type = "critical";
6099                                 };
6100                         };
6101                 };
6102
6103                 ddr-thermal {
6104                         polling-delay-passive = <0>;
6105                         polling-delay = <0>;
6106
6107                         thermal-sensors = <&tsens1 6>;
6108
6109                         trips {
6110                                 ddr_alert0: trip-point0 {
6111                                         temperature = <90000>;
6112                                         hysteresis = <2000>;
6113                                         type = "hot";
6114                                 };
6115
6116                                 ddr_crit: ddr-crit {
6117                                         temperature = <110000>;
6118                                         hysteresis = <0>;
6119                                         type = "critical";
6120                                 };
6121                         };
6122                 };
6123
6124                 mdmss0-thermal {
6125                         polling-delay-passive = <0>;
6126                         polling-delay = <0>;
6127
6128                         thermal-sensors = <&tsens1 7>;
6129
6130                         trips {
6131                                 mdmss0_alert0: trip-point0 {
6132                                         temperature = <90000>;
6133                                         hysteresis = <2000>;
6134                                         type = "hot";
6135                                 };
6136
6137                                 mdmss0_crit: mdmss0-crit {
6138                                         temperature = <110000>;
6139                                         hysteresis = <0>;
6140                                         type = "critical";
6141                                 };
6142                         };
6143                 };
6144
6145                 mdmss1-thermal {
6146                         polling-delay-passive = <0>;
6147                         polling-delay = <0>;
6148
6149                         thermal-sensors = <&tsens1 8>;
6150
6151                         trips {
6152                                 mdmss1_alert0: trip-point0 {
6153                                         temperature = <90000>;
6154                                         hysteresis = <2000>;
6155                                         type = "hot";
6156                                 };
6157
6158                                 mdmss1_crit: mdmss1-crit {
6159                                         temperature = <110000>;
6160                                         hysteresis = <0>;
6161                                         type = "critical";
6162                                 };
6163                         };
6164                 };
6165
6166                 mdmss2-thermal {
6167                         polling-delay-passive = <0>;
6168                         polling-delay = <0>;
6169
6170                         thermal-sensors = <&tsens1 9>;
6171
6172                         trips {
6173                                 mdmss2_alert0: trip-point0 {
6174                                         temperature = <90000>;
6175                                         hysteresis = <2000>;
6176                                         type = "hot";
6177                                 };
6178
6179                                 mdmss2_crit: mdmss2-crit {
6180                                         temperature = <110000>;
6181                                         hysteresis = <0>;
6182                                         type = "critical";
6183                                 };
6184                         };
6185                 };
6186
6187                 mdmss3-thermal {
6188                         polling-delay-passive = <0>;
6189                         polling-delay = <0>;
6190
6191                         thermal-sensors = <&tsens1 10>;
6192
6193                         trips {
6194                                 mdmss3_alert0: trip-point0 {
6195                                         temperature = <90000>;
6196                                         hysteresis = <2000>;
6197                                         type = "hot";
6198                                 };
6199
6200                                 mdmss3_crit: mdmss3-crit {
6201                                         temperature = <110000>;
6202                                         hysteresis = <0>;
6203                                         type = "critical";
6204                                 };
6205                         };
6206                 };
6207
6208                 camera0-thermal {
6209                         polling-delay-passive = <0>;
6210                         polling-delay = <0>;
6211
6212                         thermal-sensors = <&tsens1 11>;
6213
6214                         trips {
6215                                 camera0_alert0: trip-point0 {
6216                                         temperature = <90000>;
6217                                         hysteresis = <2000>;
6218                                         type = "hot";
6219                                 };
6220
6221                                 camera0_crit: camera0-crit {
6222                                         temperature = <110000>;
6223                                         hysteresis = <0>;
6224                                         type = "critical";
6225                                 };
6226                         };
6227                 };
6228         };
6229
6230         timer {
6231                 compatible = "arm,armv8-timer";
6232                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6233                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6234                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6235                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6236         };
6237 };