1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Zombie board device tree source
5 * Copyright 2022 Google LLC.
8 #include "sc7280-herobrine.dtsi"
9 #include "sc7280-herobrine-audio-rt5682.dtsi"
12 * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES
14 * Sort order matches the order in the parent files (parents before children).
21 /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
24 clock-frequency = <400000>;
27 trackpad: trackpad@15 {
28 compatible = "hid-over-i2c";
30 pinctrl-names = "default";
31 pinctrl-0 = <&tp_int_odl>;
33 interrupt-parent = <&tlmm>;
34 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
36 hid-descr-addr = <0x01>;
37 vdd-supply = <&pp3300_z1>;
63 &pm8350c_pwm_backlight {
64 /* Set the PWM period to 320 microseconds (3.125kHz frequency) */
65 pwms = <&pm8350c_pwm 3 320000>;
77 /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
83 /* PINCTRL - BOARD-SPECIFIC */
86 * Methodology for gpio-line-names:
87 * - If a pin goes to herobrine board and is named it gets that name.
88 * - If a pin goes to herobrine board and is not named, it gets no name.
89 * - If a pin is totally internal to Qcard then it gets Qcard name.
90 * - If a pin is not hooked up on Qcard, it gets no name.
94 gpio-line-names = "FLASH_STROBE_1", /* 1 */
106 gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
117 "GNSS_L1_EN", /* 10 */
124 * AP_FLASH_WP is crossystem ABI. Schematics
125 * call it BIOS_FLASH_WP_OD.
132 "UF_CAM_RST_L", /* 20 */
143 "MOS_BT_UART_TX", /* 30 */
154 "AP_EC_SPI_MISO", /* 40 */
165 "IO_BRD_MLB_ID2", /* 50 */
176 "EDP_HOT_PLUG_DET_N", /* 60 */
187 "UF_CAM_SCL", /* 70 */
198 "EN_PP3300_DX_EDP", /* 80 */
206 "MOS_PCIE0_CLKREQ_N",
209 "MOS_LAA_AS_EN", /* 90 */
213 "MOS_BT_WLAN_SLIMBUS_CLK",
214 "MOS_BT_WLAN_SLIMBUS_DAT0",
220 "HP_LRCLK", /* 100 */
229 "UIM1_DATA_GPIO_109",
231 "UIM1_CLK_GPIO_110", /* 110 */
232 "UIM1_RESET_GPIO_111",
242 "FASTBOOT_SEL_0", /* 120 */
247 "SM_RFFE4_CLK_GRFC_8",
248 "SM_RFFE4_DATA_GRFC_9",
249 "WLAN_COEX_UART1_RX",
250 "WLAN_COEX_UART1_TX",
258 "QLINK0_WMSS_RESET_N",
261 "SMR526_QLINK1_WMSS_RESET_N",
264 "SAR1_IRQ_ODL", /* 140 */
275 "DMIC01_CLK", /* 150 */