1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * This file defines the common audio settings for the child boards
7 * Copyright 2022 Google LLC.
11 /* BOARD-SPECIFIC TOP LEVEL NODES */
13 compatible = "google,sc7280-herobrine";
14 model = "sc7280-rt5682-max98360a-1mic";
16 audio-routing = "Headphone Jack", "HPOL",
17 "Headphone Jack", "HPOR";
23 link-name = "MAX98360";
27 sound-dai = <&lpass_cpu MI2S_SECONDARY>;
31 sound-dai = <&max98360a>;
36 link-name = "DisplayPort";
40 sound-dai = <&lpass_cpu LPASS_DP_RX>;
44 sound-dai = <&mdss_dp>;
49 link-name = "ALC5682";
53 sound-dai = <&lpass_cpu MI2S_PRIMARY>;
57 sound-dai = <&alc5682 0 /* aif1 */>;
64 clock-frequency = <400000>;
68 compatible = "realtek,rt5682s";
70 pinctrl-names = "default";
71 pinctrl-0 = <&hp_irq>;
73 #sound-dai-cells = <1>;
75 interrupt-parent = <&tlmm>;
76 interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
78 AVDD-supply = <&pp1800_alc5682>;
79 DBVDD-supply = <&pp1800_alc5682>;
80 LDO1-IN-supply = <&pp1800_alc5682>;
81 MICVDD-supply = <&pp3300_codec>;
83 realtek,dmic1-data-pin = <1>;
84 realtek,dmic1-clk-pin = <2>;
86 realtek,dmic-clk-rate-hz = <2048000>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&mi2s0_data0>, <&mi2s0_data1>, <&mi2s0_mclk>, <&mi2s0_sclk>, <&mi2s0_ws>,
93 <&mi2s1_data0>, <&mi2s1_sclk>, <&mi2s1_ws>;
101 reg = <MI2S_PRIMARY>;
102 qcom,playback-sd-lines = <1>;
103 qcom,capture-sd-lines = <0>;
107 reg = <MI2S_SECONDARY>;
108 qcom,playback-sd-lines = <0>;
116 /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */
119 drive-strength = <6>;
124 drive-strength = <6>;
129 drive-strength = <6>;
134 drive-strength = <6>;
139 drive-strength = <6>;