1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sc7280 fragment for devices with Chrome bootloader
5 * This file mainly tries to abstract out the memory protections put into
6 * place by the Chrome bootloader which are different than what's put into
7 * place by Qualcomm's typical bootloader. It also has a smattering of other
8 * things that will hold true for any conceivable Chrome design
10 * Copyright 2022 Google LLC.
14 * Reserved memory changes
16 * Delete all unused memory nodes and define the peripheral memory regions
17 * required by the setup for Chrome boards.
20 /delete-node/ &hyp_mem;
21 /delete-node/ &xbl_mem;
22 /delete-node/ &reserved_xbl_uefi_log;
23 /delete-node/ &sec_apps_mem;
27 adsp_mem: memory@86700000 {
28 reg = <0x0 0x86700000 0x0 0x2800000>;
32 camera_mem: memory@8ad00000 {
33 reg = <0x0 0x8ad00000 0x0 0x500000>;
37 venus_mem: memory@8b200000 {
38 reg = <0x0 0x8b200000 0x0 0x500000>;
42 wpss_mem: memory@9ae00000 {
43 reg = <0x0 0x9ae00000 0x0 0x1900000>;
69 /* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
75 * Chrome designs always boot from SPI flash hooked up to the qspi.
77 * It's expected that all boards will support "dual SPI" at 37.5 MHz.
78 * If some boards need a different speed or have a package that allows
79 * Quad SPI together with WP then those boards can easily override.
83 pinctrl-names = "default", "sleep";
84 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>;
85 pinctrl-1 = <&qspi_sleep>;
88 compatible = "jedec,spi-nor";
91 spi-max-frequency = <37500000>;
92 spi-tx-bus-width = <2>;
93 spi-rx-bus-width = <2>;
99 firmware-name = "/*(DEBLOBBED)*/";
103 /* TF-A firmware maps memory cached so mark dma-coherent to match. */
115 iommus = <&apps_smmu 0x1c02 0x1>;
119 /* PINCTRL - chrome-common pinctrl */
122 qspi_sleep: qspi-sleep-state {
123 pins = "gpio12", "gpio13", "gpio14", "gpio15";
126 * When we're not actively transferring we want pins as GPIOs
127 * with output disabled so that the quad SPI IP block stops
128 * driving them. We rely on the normal pulls configured in
129 * the active state and don't redefine them here. Also note
130 * that we don't need the reverse (output-enable) in the
131 * normal mode since the "output-enable" only matters for