1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
59 compatible = "fixed-clock";
60 clock-frequency = <38400000>;
64 sleep_clk: sleep-clk {
65 compatible = "fixed-clock";
66 clock-frequency = <32764>;
71 reserved_memory: reserved-memory {
76 hyp_mem: memory@80000000 {
77 reg = <0x0 0x80000000 0x0 0x600000>;
81 xbl_mem: memory@80600000 {
82 reg = <0x0 0x80600000 0x0 0x200000>;
86 aop_mem: memory@80800000 {
87 reg = <0x0 0x80800000 0x0 0x20000>;
91 aop_cmd_db_mem: memory@80820000 {
92 reg = <0x0 0x80820000 0x0 0x20000>;
93 compatible = "qcom,cmd-db";
97 sec_apps_mem: memory@808ff000 {
98 reg = <0x0 0x808ff000 0x0 0x1000>;
102 smem_mem: memory@80900000 {
103 reg = <0x0 0x80900000 0x0 0x200000>;
107 tz_mem: memory@80b00000 {
108 reg = <0x0 0x80b00000 0x0 0x3900000>;
112 ipa_fw_mem: memory@8b700000 {
113 reg = <0 0x8b700000 0 0x10000>;
117 rmtfs_mem: memory@94600000 {
118 compatible = "qcom,rmtfs-mem";
119 reg = <0x0 0x94600000 0x0 0x200000>;
122 qcom,client-id = <1>;
128 #address-cells = <2>;
133 compatible = "qcom,kryo468";
135 enable-method = "psci";
136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
139 capacity-dmips-mhz = <415>;
140 dynamic-power-coefficient = <137>;
141 operating-points-v2 = <&cpu0_opp_table>;
142 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
143 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
144 next-level-cache = <&L2_0>;
145 #cooling-cells = <2>;
146 qcom,freq-domain = <&cpufreq_hw 0>;
148 compatible = "cache";
149 next-level-cache = <&L3_0>;
151 compatible = "cache";
158 compatible = "qcom,kryo468";
160 enable-method = "psci";
161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 capacity-dmips-mhz = <415>;
165 dynamic-power-coefficient = <137>;
166 next-level-cache = <&L2_100>;
167 operating-points-v2 = <&cpu0_opp_table>;
168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
170 #cooling-cells = <2>;
171 qcom,freq-domain = <&cpufreq_hw 0>;
173 compatible = "cache";
174 next-level-cache = <&L3_0>;
180 compatible = "qcom,kryo468";
182 enable-method = "psci";
183 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
186 capacity-dmips-mhz = <415>;
187 dynamic-power-coefficient = <137>;
188 next-level-cache = <&L2_200>;
189 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>;
193 qcom,freq-domain = <&cpufreq_hw 0>;
195 compatible = "cache";
196 next-level-cache = <&L3_0>;
202 compatible = "qcom,kryo468";
204 enable-method = "psci";
205 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
208 capacity-dmips-mhz = <415>;
209 dynamic-power-coefficient = <137>;
210 next-level-cache = <&L2_300>;
211 operating-points-v2 = <&cpu0_opp_table>;
212 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
214 #cooling-cells = <2>;
215 qcom,freq-domain = <&cpufreq_hw 0>;
217 compatible = "cache";
218 next-level-cache = <&L3_0>;
224 compatible = "qcom,kryo468";
226 enable-method = "psci";
227 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
230 capacity-dmips-mhz = <415>;
231 dynamic-power-coefficient = <137>;
232 next-level-cache = <&L2_400>;
233 operating-points-v2 = <&cpu0_opp_table>;
234 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
236 #cooling-cells = <2>;
237 qcom,freq-domain = <&cpufreq_hw 0>;
239 compatible = "cache";
240 next-level-cache = <&L3_0>;
246 compatible = "qcom,kryo468";
248 enable-method = "psci";
249 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
252 capacity-dmips-mhz = <415>;
253 dynamic-power-coefficient = <137>;
254 next-level-cache = <&L2_500>;
255 operating-points-v2 = <&cpu0_opp_table>;
256 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
257 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
258 #cooling-cells = <2>;
259 qcom,freq-domain = <&cpufreq_hw 0>;
261 compatible = "cache";
262 next-level-cache = <&L3_0>;
268 compatible = "qcom,kryo468";
270 enable-method = "psci";
271 cpu-idle-states = <&BIG_CPU_SLEEP_0
274 capacity-dmips-mhz = <1024>;
275 dynamic-power-coefficient = <480>;
276 next-level-cache = <&L2_600>;
277 operating-points-v2 = <&cpu6_opp_table>;
278 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
279 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
280 #cooling-cells = <2>;
281 qcom,freq-domain = <&cpufreq_hw 1>;
283 compatible = "cache";
284 next-level-cache = <&L3_0>;
290 compatible = "qcom,kryo468";
292 enable-method = "psci";
293 cpu-idle-states = <&BIG_CPU_SLEEP_0
296 capacity-dmips-mhz = <1024>;
297 dynamic-power-coefficient = <480>;
298 next-level-cache = <&L2_700>;
299 operating-points-v2 = <&cpu6_opp_table>;
300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
301 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
302 #cooling-cells = <2>;
303 qcom,freq-domain = <&cpufreq_hw 1>;
305 compatible = "cache";
306 next-level-cache = <&L3_0>;
347 entry-method = "psci";
349 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
350 compatible = "arm,idle-state";
351 idle-state-name = "little-power-down";
352 arm,psci-suspend-param = <0x40000003>;
353 entry-latency-us = <549>;
354 exit-latency-us = <901>;
355 min-residency-us = <1774>;
359 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
360 compatible = "arm,idle-state";
361 idle-state-name = "little-rail-power-down";
362 arm,psci-suspend-param = <0x40000004>;
363 entry-latency-us = <702>;
364 exit-latency-us = <915>;
365 min-residency-us = <4001>;
369 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
370 compatible = "arm,idle-state";
371 idle-state-name = "big-power-down";
372 arm,psci-suspend-param = <0x40000003>;
373 entry-latency-us = <523>;
374 exit-latency-us = <1244>;
375 min-residency-us = <2207>;
379 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
380 compatible = "arm,idle-state";
381 idle-state-name = "big-rail-power-down";
382 arm,psci-suspend-param = <0x40000004>;
383 entry-latency-us = <526>;
384 exit-latency-us = <1854>;
385 min-residency-us = <5555>;
389 CLUSTER_SLEEP_0: cluster-sleep-0 {
390 compatible = "arm,idle-state";
391 idle-state-name = "cluster-power-down";
392 arm,psci-suspend-param = <0x40003444>;
393 entry-latency-us = <3263>;
394 exit-latency-us = <6562>;
395 min-residency-us = <9926>;
401 cpu0_opp_table: opp-table-cpu0 {
402 compatible = "operating-points-v2";
405 cpu0_opp1: opp-300000000 {
406 opp-hz = /bits/ 64 <300000000>;
407 opp-peak-kBps = <1200000 4800000>;
410 cpu0_opp2: opp-576000000 {
411 opp-hz = /bits/ 64 <576000000>;
412 opp-peak-kBps = <1200000 4800000>;
415 cpu0_opp3: opp-768000000 {
416 opp-hz = /bits/ 64 <768000000>;
417 opp-peak-kBps = <1200000 4800000>;
420 cpu0_opp4: opp-1017600000 {
421 opp-hz = /bits/ 64 <1017600000>;
422 opp-peak-kBps = <1804000 8908800>;
425 cpu0_opp5: opp-1248000000 {
426 opp-hz = /bits/ 64 <1248000000>;
427 opp-peak-kBps = <2188000 12902400>;
430 cpu0_opp6: opp-1324800000 {
431 opp-hz = /bits/ 64 <1324800000>;
432 opp-peak-kBps = <2188000 12902400>;
435 cpu0_opp7: opp-1516800000 {
436 opp-hz = /bits/ 64 <1516800000>;
437 opp-peak-kBps = <3072000 15052800>;
440 cpu0_opp8: opp-1612800000 {
441 opp-hz = /bits/ 64 <1612800000>;
442 opp-peak-kBps = <3072000 15052800>;
445 cpu0_opp9: opp-1708800000 {
446 opp-hz = /bits/ 64 <1708800000>;
447 opp-peak-kBps = <3072000 15052800>;
450 cpu0_opp10: opp-1804800000 {
451 opp-hz = /bits/ 64 <1804800000>;
452 opp-peak-kBps = <4068000 22425600>;
456 cpu6_opp_table: opp-table-cpu6 {
457 compatible = "operating-points-v2";
460 cpu6_opp1: opp-300000000 {
461 opp-hz = /bits/ 64 <300000000>;
462 opp-peak-kBps = <2188000 8908800>;
465 cpu6_opp2: opp-652800000 {
466 opp-hz = /bits/ 64 <652800000>;
467 opp-peak-kBps = <2188000 8908800>;
470 cpu6_opp3: opp-825600000 {
471 opp-hz = /bits/ 64 <825600000>;
472 opp-peak-kBps = <2188000 8908800>;
475 cpu6_opp4: opp-979200000 {
476 opp-hz = /bits/ 64 <979200000>;
477 opp-peak-kBps = <2188000 8908800>;
480 cpu6_opp5: opp-1113600000 {
481 opp-hz = /bits/ 64 <1113600000>;
482 opp-peak-kBps = <2188000 8908800>;
485 cpu6_opp6: opp-1267200000 {
486 opp-hz = /bits/ 64 <1267200000>;
487 opp-peak-kBps = <4068000 12902400>;
490 cpu6_opp7: opp-1555200000 {
491 opp-hz = /bits/ 64 <1555200000>;
492 opp-peak-kBps = <4068000 15052800>;
495 cpu6_opp8: opp-1708800000 {
496 opp-hz = /bits/ 64 <1708800000>;
497 opp-peak-kBps = <6220000 19353600>;
500 cpu6_opp9: opp-1843200000 {
501 opp-hz = /bits/ 64 <1843200000>;
502 opp-peak-kBps = <6220000 19353600>;
505 cpu6_opp10: opp-1900800000 {
506 opp-hz = /bits/ 64 <1900800000>;
507 opp-peak-kBps = <6220000 22425600>;
510 cpu6_opp11: opp-1996800000 {
511 opp-hz = /bits/ 64 <1996800000>;
512 opp-peak-kBps = <6220000 22425600>;
515 cpu6_opp12: opp-2112000000 {
516 opp-hz = /bits/ 64 <2112000000>;
517 opp-peak-kBps = <6220000 22425600>;
520 cpu6_opp13: opp-2208000000 {
521 opp-hz = /bits/ 64 <2208000000>;
522 opp-peak-kBps = <7216000 22425600>;
525 cpu6_opp14: opp-2323200000 {
526 opp-hz = /bits/ 64 <2323200000>;
527 opp-peak-kBps = <7216000 22425600>;
530 cpu6_opp15: opp-2400000000 {
531 opp-hz = /bits/ 64 <2400000000>;
532 opp-peak-kBps = <8532000 23347200>;
535 cpu6_opp16: opp-2553600000 {
536 opp-hz = /bits/ 64 <2553600000>;
537 opp-peak-kBps = <8532000 23347200>;
542 device_type = "memory";
543 /* We expect the bootloader to fill in the size */
544 reg = <0 0x80000000 0 0>;
548 compatible = "arm,armv8-pmuv3";
549 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
554 compatible = "qcom,scm-sc7180", "qcom,scm";
559 compatible = "qcom,smem";
560 memory-region = <&smem_mem>;
561 hwlocks = <&tcsr_mutex 3>;
565 compatible = "qcom,smp2p";
566 qcom,smem = <94>, <432>;
568 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
570 mboxes = <&apss_shared 6>;
572 qcom,local-pid = <0>;
573 qcom,remote-pid = <5>;
575 cdsp_smp2p_out: master-kernel {
576 qcom,entry-name = "master-kernel";
577 #qcom,smem-state-cells = <1>;
580 cdsp_smp2p_in: slave-kernel {
581 qcom,entry-name = "slave-kernel";
583 interrupt-controller;
584 #interrupt-cells = <2>;
589 compatible = "qcom,smp2p";
590 qcom,smem = <443>, <429>;
592 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
594 mboxes = <&apss_shared 10>;
596 qcom,local-pid = <0>;
597 qcom,remote-pid = <2>;
599 adsp_smp2p_out: master-kernel {
600 qcom,entry-name = "master-kernel";
601 #qcom,smem-state-cells = <1>;
604 adsp_smp2p_in: slave-kernel {
605 qcom,entry-name = "slave-kernel";
607 interrupt-controller;
608 #interrupt-cells = <2>;
613 compatible = "qcom,smp2p";
614 qcom,smem = <435>, <428>;
615 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
616 mboxes = <&apss_shared 14>;
617 qcom,local-pid = <0>;
618 qcom,remote-pid = <1>;
620 modem_smp2p_out: master-kernel {
621 qcom,entry-name = "master-kernel";
622 #qcom,smem-state-cells = <1>;
625 modem_smp2p_in: slave-kernel {
626 qcom,entry-name = "slave-kernel";
627 interrupt-controller;
628 #interrupt-cells = <2>;
631 ipa_smp2p_out: ipa-ap-to-modem {
632 qcom,entry-name = "ipa";
633 #qcom,smem-state-cells = <1>;
636 ipa_smp2p_in: ipa-modem-to-ap {
637 qcom,entry-name = "ipa";
638 interrupt-controller;
639 #interrupt-cells = <2>;
644 compatible = "arm,psci-1.0";
649 #address-cells = <2>;
651 ranges = <0 0 0 0 0x10 0>;
652 dma-ranges = <0 0 0 0 0x10 0>;
653 compatible = "simple-bus";
655 gcc: clock-controller@100000 {
656 compatible = "qcom,gcc-sc7180";
657 reg = <0 0x00100000 0 0x1f0000>;
658 clocks = <&rpmhcc RPMH_CXO_CLK>,
659 <&rpmhcc RPMH_CXO_CLK_A>,
661 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
664 #power-domain-cells = <1>;
667 qfprom: efuse@784000 {
668 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
669 reg = <0 0x00784000 0 0x7a0>,
670 <0 0x00780000 0 0x7a0>,
671 <0 0x00782000 0 0x100>,
672 <0 0x00786000 0 0x1fff>;
674 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
675 clock-names = "core";
676 #address-cells = <1>;
679 qusb2p_hstx_trim: hstx-trim-primary@25b {
684 gpu_speed_bin: gpu_speed_bin@1d2 {
691 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
692 reg = <0 0x7c4000 0 0x1000>,
693 <0 0x07c5000 0 0x1000>;
694 reg-names = "hc", "cqhci";
696 iommus = <&apps_smmu 0x60 0x0>;
697 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
699 interrupt-names = "hc_irq", "pwr_irq";
701 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
702 <&gcc GCC_SDCC1_APPS_CLK>,
703 <&rpmhcc RPMH_CXO_CLK>;
704 clock-names = "iface", "core", "xo";
705 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
706 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
707 interconnect-names = "sdhc-ddr","cpu-sdhc";
708 power-domains = <&rpmhpd SC7180_CX>;
709 operating-points-v2 = <&sdhc1_opp_table>;
718 mmc-hs400-enhanced-strobe;
722 sdhc1_opp_table: opp-table {
723 compatible = "operating-points-v2";
726 opp-hz = /bits/ 64 <100000000>;
727 required-opps = <&rpmhpd_opp_low_svs>;
728 opp-peak-kBps = <1800000 600000>;
729 opp-avg-kBps = <100000 0>;
733 opp-hz = /bits/ 64 <384000000>;
734 required-opps = <&rpmhpd_opp_nom>;
735 opp-peak-kBps = <5400000 1600000>;
736 opp-avg-kBps = <390000 0>;
741 qup_opp_table: opp-table-qup {
742 compatible = "operating-points-v2";
745 opp-hz = /bits/ 64 <75000000>;
746 required-opps = <&rpmhpd_opp_low_svs>;
750 opp-hz = /bits/ 64 <100000000>;
751 required-opps = <&rpmhpd_opp_svs>;
755 opp-hz = /bits/ 64 <128000000>;
756 required-opps = <&rpmhpd_opp_nom>;
760 qupv3_id_0: geniqup@8c0000 {
761 compatible = "qcom,geni-se-qup";
762 reg = <0 0x008c0000 0 0x6000>;
763 clock-names = "m-ahb", "s-ahb";
764 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
765 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
766 #address-cells = <2>;
769 iommus = <&apps_smmu 0x43 0x0>;
773 compatible = "qcom,geni-i2c";
774 reg = <0 0x00880000 0 0x4000>;
776 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
777 pinctrl-names = "default";
778 pinctrl-0 = <&qup_i2c0_default>;
779 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
780 #address-cells = <1>;
782 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
783 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
784 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
785 interconnect-names = "qup-core", "qup-config",
787 power-domains = <&rpmhpd SC7180_CX>;
788 required-opps = <&rpmhpd_opp_low_svs>;
793 compatible = "qcom,geni-spi";
794 reg = <0 0x00880000 0 0x4000>;
796 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&qup_spi0_default>;
799 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
800 #address-cells = <1>;
802 power-domains = <&rpmhpd SC7180_CX>;
803 operating-points-v2 = <&qup_opp_table>;
804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
805 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
806 interconnect-names = "qup-core", "qup-config";
810 uart0: serial@880000 {
811 compatible = "qcom,geni-uart";
812 reg = <0 0x00880000 0 0x4000>;
814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
815 pinctrl-names = "default";
816 pinctrl-0 = <&qup_uart0_default>;
817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
818 power-domains = <&rpmhpd SC7180_CX>;
819 operating-points-v2 = <&qup_opp_table>;
820 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
821 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
822 interconnect-names = "qup-core", "qup-config";
827 compatible = "qcom,geni-i2c";
828 reg = <0 0x00884000 0 0x4000>;
830 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_i2c1_default>;
833 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
834 #address-cells = <1>;
836 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
837 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
838 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
839 interconnect-names = "qup-core", "qup-config",
841 power-domains = <&rpmhpd SC7180_CX>;
842 required-opps = <&rpmhpd_opp_low_svs>;
847 compatible = "qcom,geni-spi";
848 reg = <0 0x00884000 0 0x4000>;
850 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
851 pinctrl-names = "default";
852 pinctrl-0 = <&qup_spi1_default>;
853 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
854 #address-cells = <1>;
856 power-domains = <&rpmhpd SC7180_CX>;
857 operating-points-v2 = <&qup_opp_table>;
858 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
859 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
860 interconnect-names = "qup-core", "qup-config";
864 uart1: serial@884000 {
865 compatible = "qcom,geni-uart";
866 reg = <0 0x00884000 0 0x4000>;
868 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&qup_uart1_default>;
871 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
872 power-domains = <&rpmhpd SC7180_CX>;
873 operating-points-v2 = <&qup_opp_table>;
874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
875 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
876 interconnect-names = "qup-core", "qup-config";
881 compatible = "qcom,geni-i2c";
882 reg = <0 0x00888000 0 0x4000>;
884 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
885 pinctrl-names = "default";
886 pinctrl-0 = <&qup_i2c2_default>;
887 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
888 #address-cells = <1>;
890 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
891 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
892 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
893 interconnect-names = "qup-core", "qup-config",
895 power-domains = <&rpmhpd SC7180_CX>;
896 required-opps = <&rpmhpd_opp_low_svs>;
900 uart2: serial@888000 {
901 compatible = "qcom,geni-uart";
902 reg = <0 0x00888000 0 0x4000>;
904 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
905 pinctrl-names = "default";
906 pinctrl-0 = <&qup_uart2_default>;
907 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
908 power-domains = <&rpmhpd SC7180_CX>;
909 operating-points-v2 = <&qup_opp_table>;
910 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
911 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
912 interconnect-names = "qup-core", "qup-config";
917 compatible = "qcom,geni-i2c";
918 reg = <0 0x0088c000 0 0x4000>;
920 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&qup_i2c3_default>;
923 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
924 #address-cells = <1>;
926 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
927 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
928 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
929 interconnect-names = "qup-core", "qup-config",
931 power-domains = <&rpmhpd SC7180_CX>;
932 required-opps = <&rpmhpd_opp_low_svs>;
937 compatible = "qcom,geni-spi";
938 reg = <0 0x0088c000 0 0x4000>;
940 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
941 pinctrl-names = "default";
942 pinctrl-0 = <&qup_spi3_default>;
943 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
944 #address-cells = <1>;
946 power-domains = <&rpmhpd SC7180_CX>;
947 operating-points-v2 = <&qup_opp_table>;
948 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
949 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
950 interconnect-names = "qup-core", "qup-config";
954 uart3: serial@88c000 {
955 compatible = "qcom,geni-uart";
956 reg = <0 0x0088c000 0 0x4000>;
958 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&qup_uart3_default>;
961 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
962 power-domains = <&rpmhpd SC7180_CX>;
963 operating-points-v2 = <&qup_opp_table>;
964 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
965 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
966 interconnect-names = "qup-core", "qup-config";
971 compatible = "qcom,geni-i2c";
972 reg = <0 0x00890000 0 0x4000>;
974 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
975 pinctrl-names = "default";
976 pinctrl-0 = <&qup_i2c4_default>;
977 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
978 #address-cells = <1>;
980 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
982 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
983 interconnect-names = "qup-core", "qup-config",
985 power-domains = <&rpmhpd SC7180_CX>;
986 required-opps = <&rpmhpd_opp_low_svs>;
990 uart4: serial@890000 {
991 compatible = "qcom,geni-uart";
992 reg = <0 0x00890000 0 0x4000>;
994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
995 pinctrl-names = "default";
996 pinctrl-0 = <&qup_uart4_default>;
997 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
998 power-domains = <&rpmhpd SC7180_CX>;
999 operating-points-v2 = <&qup_opp_table>;
1000 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1001 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1002 interconnect-names = "qup-core", "qup-config";
1003 status = "disabled";
1007 compatible = "qcom,geni-i2c";
1008 reg = <0 0x00894000 0 0x4000>;
1010 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1011 pinctrl-names = "default";
1012 pinctrl-0 = <&qup_i2c5_default>;
1013 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1014 #address-cells = <1>;
1016 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1017 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1018 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1019 interconnect-names = "qup-core", "qup-config",
1021 power-domains = <&rpmhpd SC7180_CX>;
1022 required-opps = <&rpmhpd_opp_low_svs>;
1023 status = "disabled";
1027 compatible = "qcom,geni-spi";
1028 reg = <0 0x00894000 0 0x4000>;
1030 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&qup_spi5_default>;
1033 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1034 #address-cells = <1>;
1036 power-domains = <&rpmhpd SC7180_CX>;
1037 operating-points-v2 = <&qup_opp_table>;
1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1039 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1040 interconnect-names = "qup-core", "qup-config";
1041 status = "disabled";
1044 uart5: serial@894000 {
1045 compatible = "qcom,geni-uart";
1046 reg = <0 0x00894000 0 0x4000>;
1048 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&qup_uart5_default>;
1051 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1052 power-domains = <&rpmhpd SC7180_CX>;
1053 operating-points-v2 = <&qup_opp_table>;
1054 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1055 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1056 interconnect-names = "qup-core", "qup-config";
1057 status = "disabled";
1061 qupv3_id_1: geniqup@ac0000 {
1062 compatible = "qcom,geni-se-qup";
1063 reg = <0 0x00ac0000 0 0x6000>;
1064 clock-names = "m-ahb", "s-ahb";
1065 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1066 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1067 #address-cells = <2>;
1070 iommus = <&apps_smmu 0x4c3 0x0>;
1071 status = "disabled";
1074 compatible = "qcom,geni-i2c";
1075 reg = <0 0x00a80000 0 0x4000>;
1077 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1078 pinctrl-names = "default";
1079 pinctrl-0 = <&qup_i2c6_default>;
1080 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1081 #address-cells = <1>;
1083 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1085 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1086 interconnect-names = "qup-core", "qup-config",
1088 power-domains = <&rpmhpd SC7180_CX>;
1089 required-opps = <&rpmhpd_opp_low_svs>;
1090 status = "disabled";
1094 compatible = "qcom,geni-spi";
1095 reg = <0 0x00a80000 0 0x4000>;
1097 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_spi6_default>;
1100 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1101 #address-cells = <1>;
1103 power-domains = <&rpmhpd SC7180_CX>;
1104 operating-points-v2 = <&qup_opp_table>;
1105 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1106 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1107 interconnect-names = "qup-core", "qup-config";
1108 status = "disabled";
1111 uart6: serial@a80000 {
1112 compatible = "qcom,geni-uart";
1113 reg = <0 0x00a80000 0 0x4000>;
1115 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_uart6_default>;
1118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1119 power-domains = <&rpmhpd SC7180_CX>;
1120 operating-points-v2 = <&qup_opp_table>;
1121 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1122 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1123 interconnect-names = "qup-core", "qup-config";
1124 status = "disabled";
1128 compatible = "qcom,geni-i2c";
1129 reg = <0 0x00a84000 0 0x4000>;
1131 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c7_default>;
1134 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1135 #address-cells = <1>;
1137 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1138 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1139 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1140 interconnect-names = "qup-core", "qup-config",
1142 power-domains = <&rpmhpd SC7180_CX>;
1143 required-opps = <&rpmhpd_opp_low_svs>;
1144 status = "disabled";
1147 uart7: serial@a84000 {
1148 compatible = "qcom,geni-uart";
1149 reg = <0 0x00a84000 0 0x4000>;
1151 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&qup_uart7_default>;
1154 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1155 power-domains = <&rpmhpd SC7180_CX>;
1156 operating-points-v2 = <&qup_opp_table>;
1157 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1159 interconnect-names = "qup-core", "qup-config";
1160 status = "disabled";
1164 compatible = "qcom,geni-i2c";
1165 reg = <0 0x00a88000 0 0x4000>;
1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_i2c8_default>;
1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cells = <1>;
1173 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1175 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1176 interconnect-names = "qup-core", "qup-config",
1178 power-domains = <&rpmhpd SC7180_CX>;
1179 required-opps = <&rpmhpd_opp_low_svs>;
1180 status = "disabled";
1184 compatible = "qcom,geni-spi";
1185 reg = <0 0x00a88000 0 0x4000>;
1187 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&qup_spi8_default>;
1190 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1191 #address-cells = <1>;
1193 power-domains = <&rpmhpd SC7180_CX>;
1194 operating-points-v2 = <&qup_opp_table>;
1195 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1196 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1197 interconnect-names = "qup-core", "qup-config";
1198 status = "disabled";
1201 uart8: serial@a88000 {
1202 compatible = "qcom,geni-debug-uart";
1203 reg = <0 0x00a88000 0 0x4000>;
1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_uart8_default>;
1208 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains = <&rpmhpd SC7180_CX>;
1210 operating-points-v2 = <&qup_opp_table>;
1211 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1212 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1213 interconnect-names = "qup-core", "qup-config";
1214 status = "disabled";
1218 compatible = "qcom,geni-i2c";
1219 reg = <0 0x00a8c000 0 0x4000>;
1221 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&qup_i2c9_default>;
1224 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1225 #address-cells = <1>;
1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1230 interconnect-names = "qup-core", "qup-config",
1232 power-domains = <&rpmhpd SC7180_CX>;
1233 required-opps = <&rpmhpd_opp_low_svs>;
1234 status = "disabled";
1237 uart9: serial@a8c000 {
1238 compatible = "qcom,geni-uart";
1239 reg = <0 0x00a8c000 0 0x4000>;
1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1242 pinctrl-names = "default";
1243 pinctrl-0 = <&qup_uart9_default>;
1244 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1245 power-domains = <&rpmhpd SC7180_CX>;
1246 operating-points-v2 = <&qup_opp_table>;
1247 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1248 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1249 interconnect-names = "qup-core", "qup-config";
1250 status = "disabled";
1254 compatible = "qcom,geni-i2c";
1255 reg = <0 0x00a90000 0 0x4000>;
1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&qup_i2c10_default>;
1260 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1261 #address-cells = <1>;
1263 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1264 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1265 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1266 interconnect-names = "qup-core", "qup-config",
1268 power-domains = <&rpmhpd SC7180_CX>;
1269 required-opps = <&rpmhpd_opp_low_svs>;
1270 status = "disabled";
1274 compatible = "qcom,geni-spi";
1275 reg = <0 0x00a90000 0 0x4000>;
1277 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1278 pinctrl-names = "default";
1279 pinctrl-0 = <&qup_spi10_default>;
1280 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1281 #address-cells = <1>;
1283 power-domains = <&rpmhpd SC7180_CX>;
1284 operating-points-v2 = <&qup_opp_table>;
1285 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1286 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1287 interconnect-names = "qup-core", "qup-config";
1288 status = "disabled";
1291 uart10: serial@a90000 {
1292 compatible = "qcom,geni-uart";
1293 reg = <0 0x00a90000 0 0x4000>;
1295 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1296 pinctrl-names = "default";
1297 pinctrl-0 = <&qup_uart10_default>;
1298 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1299 power-domains = <&rpmhpd SC7180_CX>;
1300 operating-points-v2 = <&qup_opp_table>;
1301 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1302 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1303 interconnect-names = "qup-core", "qup-config";
1304 status = "disabled";
1308 compatible = "qcom,geni-i2c";
1309 reg = <0 0x00a94000 0 0x4000>;
1311 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1312 pinctrl-names = "default";
1313 pinctrl-0 = <&qup_i2c11_default>;
1314 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1315 #address-cells = <1>;
1317 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1318 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1319 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1320 interconnect-names = "qup-core", "qup-config",
1322 power-domains = <&rpmhpd SC7180_CX>;
1323 required-opps = <&rpmhpd_opp_low_svs>;
1324 status = "disabled";
1328 compatible = "qcom,geni-spi";
1329 reg = <0 0x00a94000 0 0x4000>;
1331 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1332 pinctrl-names = "default";
1333 pinctrl-0 = <&qup_spi11_default>;
1334 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1335 #address-cells = <1>;
1337 power-domains = <&rpmhpd SC7180_CX>;
1338 operating-points-v2 = <&qup_opp_table>;
1339 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1340 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1341 interconnect-names = "qup-core", "qup-config";
1342 status = "disabled";
1345 uart11: serial@a94000 {
1346 compatible = "qcom,geni-uart";
1347 reg = <0 0x00a94000 0 0x4000>;
1349 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1350 pinctrl-names = "default";
1351 pinctrl-0 = <&qup_uart11_default>;
1352 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1353 power-domains = <&rpmhpd SC7180_CX>;
1354 operating-points-v2 = <&qup_opp_table>;
1355 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1356 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1357 interconnect-names = "qup-core", "qup-config";
1358 status = "disabled";
1362 config_noc: interconnect@1500000 {
1363 compatible = "qcom,sc7180-config-noc";
1364 reg = <0 0x01500000 0 0x28000>;
1365 #interconnect-cells = <2>;
1366 qcom,bcm-voters = <&apps_bcm_voter>;
1369 system_noc: interconnect@1620000 {
1370 compatible = "qcom,sc7180-system-noc";
1371 reg = <0 0x01620000 0 0x17080>;
1372 #interconnect-cells = <2>;
1373 qcom,bcm-voters = <&apps_bcm_voter>;
1376 mc_virt: interconnect@1638000 {
1377 compatible = "qcom,sc7180-mc-virt";
1378 reg = <0 0x01638000 0 0x1000>;
1379 #interconnect-cells = <2>;
1380 qcom,bcm-voters = <&apps_bcm_voter>;
1383 qup_virt: interconnect@1650000 {
1384 compatible = "qcom,sc7180-qup-virt";
1385 reg = <0 0x01650000 0 0x1000>;
1386 #interconnect-cells = <2>;
1387 qcom,bcm-voters = <&apps_bcm_voter>;
1390 aggre1_noc: interconnect@16e0000 {
1391 compatible = "qcom,sc7180-aggre1-noc";
1392 reg = <0 0x016e0000 0 0x15080>;
1393 #interconnect-cells = <2>;
1394 qcom,bcm-voters = <&apps_bcm_voter>;
1397 aggre2_noc: interconnect@1705000 {
1398 compatible = "qcom,sc7180-aggre2-noc";
1399 reg = <0 0x01705000 0 0x9000>;
1400 #interconnect-cells = <2>;
1401 qcom,bcm-voters = <&apps_bcm_voter>;
1404 compute_noc: interconnect@170e000 {
1405 compatible = "qcom,sc7180-compute-noc";
1406 reg = <0 0x0170e000 0 0x6000>;
1407 #interconnect-cells = <2>;
1408 qcom,bcm-voters = <&apps_bcm_voter>;
1411 mmss_noc: interconnect@1740000 {
1412 compatible = "qcom,sc7180-mmss-noc";
1413 reg = <0 0x01740000 0 0x1c100>;
1414 #interconnect-cells = <2>;
1415 qcom,bcm-voters = <&apps_bcm_voter>;
1419 compatible = "qcom,sc7180-ipa";
1421 iommus = <&apps_smmu 0x440 0x0>,
1422 <&apps_smmu 0x442 0x0>;
1423 reg = <0 0x1e40000 0 0x7000>,
1424 <0 0x1e47000 0 0x2000>,
1425 <0 0x1e04000 0 0x2c000>;
1426 reg-names = "ipa-reg",
1430 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1431 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1432 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1433 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1434 interrupt-names = "ipa",
1439 clocks = <&rpmhcc RPMH_IPA_CLK>;
1440 clock-names = "core";
1442 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1443 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1444 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1445 interconnect-names = "memory",
1449 qcom,qmp = <&aoss_qmp>;
1451 qcom,smem-states = <&ipa_smp2p_out 0>,
1453 qcom,smem-state-names = "ipa-clock-enabled-valid",
1454 "ipa-clock-enabled";
1456 status = "disabled";
1459 tcsr_mutex: hwlock@1f40000 {
1460 compatible = "qcom,tcsr-mutex";
1461 reg = <0 0x01f40000 0 0x20000>;
1462 #hwlock-cells = <1>;
1465 tcsr_regs_1: syscon@1f60000 {
1466 compatible = "qcom,sc7180-tcsr", "syscon";
1467 reg = <0 0x01f60000 0 0x20000>;
1470 tcsr_regs_2: syscon@1fc0000 {
1471 compatible = "qcom,sc7180-tcsr", "syscon";
1472 reg = <0 0x01fc0000 0 0x40000>;
1475 tlmm: pinctrl@3500000 {
1476 compatible = "qcom,sc7180-pinctrl";
1477 reg = <0 0x03500000 0 0x300000>,
1478 <0 0x03900000 0 0x300000>,
1479 <0 0x03d00000 0 0x300000>;
1480 reg-names = "west", "north", "south";
1481 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1484 interrupt-controller;
1485 #interrupt-cells = <2>;
1486 gpio-ranges = <&tlmm 0 0 120>;
1487 wakeup-parent = <&pdc>;
1489 dp_hot_plug_det: dp-hot-plug-det {
1492 function = "dp_hot";
1496 qspi_clk: qspi-clk {
1499 function = "qspi_clk";
1503 qspi_cs0: qspi-cs0 {
1506 function = "qspi_cs";
1510 qspi_cs1: qspi-cs1 {
1513 function = "qspi_cs";
1517 qspi_data01: qspi-data01 {
1519 pins = "gpio64", "gpio65";
1520 function = "qspi_data";
1524 qspi_data23: qspi-data23 {
1526 pins = "gpio66", "gpio67";
1527 function = "qspi_data";
1531 qup_i2c0_default: qup-i2c0-default {
1533 pins = "gpio34", "gpio35";
1538 qup_i2c1_default: qup-i2c1-default {
1540 pins = "gpio0", "gpio1";
1545 qup_i2c2_default: qup-i2c2-default {
1547 pins = "gpio15", "gpio16";
1548 function = "qup02_i2c";
1552 qup_i2c3_default: qup-i2c3-default {
1554 pins = "gpio38", "gpio39";
1559 qup_i2c4_default: qup-i2c4-default {
1561 pins = "gpio115", "gpio116";
1562 function = "qup04_i2c";
1566 qup_i2c5_default: qup-i2c5-default {
1568 pins = "gpio25", "gpio26";
1573 qup_i2c6_default: qup-i2c6-default {
1575 pins = "gpio59", "gpio60";
1580 qup_i2c7_default: qup-i2c7-default {
1582 pins = "gpio6", "gpio7";
1583 function = "qup11_i2c";
1587 qup_i2c8_default: qup-i2c8-default {
1589 pins = "gpio42", "gpio43";
1594 qup_i2c9_default: qup-i2c9-default {
1596 pins = "gpio46", "gpio47";
1597 function = "qup13_i2c";
1601 qup_i2c10_default: qup-i2c10-default {
1603 pins = "gpio86", "gpio87";
1608 qup_i2c11_default: qup-i2c11-default {
1610 pins = "gpio53", "gpio54";
1615 qup_spi0_default: qup-spi0-default {
1617 pins = "gpio34", "gpio35",
1623 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1625 pins = "gpio34", "gpio35",
1636 qup_spi1_default: qup-spi1-default {
1638 pins = "gpio0", "gpio1",
1644 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1646 pins = "gpio0", "gpio1",
1657 qup_spi3_default: qup-spi3-default {
1659 pins = "gpio38", "gpio39",
1665 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1667 pins = "gpio38", "gpio39",
1678 qup_spi5_default: qup-spi5-default {
1680 pins = "gpio25", "gpio26",
1686 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1688 pins = "gpio25", "gpio26",
1699 qup_spi6_default: qup-spi6-default {
1701 pins = "gpio59", "gpio60",
1707 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1709 pins = "gpio59", "gpio60",
1720 qup_spi8_default: qup-spi8-default {
1722 pins = "gpio42", "gpio43",
1728 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1730 pins = "gpio42", "gpio43",
1741 qup_spi10_default: qup-spi10-default {
1743 pins = "gpio86", "gpio87",
1749 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1751 pins = "gpio86", "gpio87",
1762 qup_spi11_default: qup-spi11-default {
1764 pins = "gpio53", "gpio54",
1770 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1772 pins = "gpio53", "gpio54",
1783 qup_uart0_default: qup-uart0-default {
1785 pins = "gpio34", "gpio35",
1791 qup_uart1_default: qup-uart1-default {
1793 pins = "gpio0", "gpio1",
1799 qup_uart2_default: qup-uart2-default {
1801 pins = "gpio15", "gpio16";
1802 function = "qup02_uart";
1806 qup_uart3_default: qup-uart3-default {
1808 pins = "gpio38", "gpio39",
1814 qup_uart4_default: qup-uart4-default {
1816 pins = "gpio115", "gpio116";
1817 function = "qup04_uart";
1821 qup_uart5_default: qup-uart5-default {
1823 pins = "gpio25", "gpio26",
1829 qup_uart6_default: qup-uart6-default {
1831 pins = "gpio59", "gpio60",
1837 qup_uart7_default: qup-uart7-default {
1839 pins = "gpio6", "gpio7";
1840 function = "qup11_uart";
1844 qup_uart8_default: qup-uart8-default {
1846 pins = "gpio44", "gpio45";
1851 qup_uart9_default: qup-uart9-default {
1853 pins = "gpio46", "gpio47";
1854 function = "qup13_uart";
1858 qup_uart10_default: qup-uart10-default {
1860 pins = "gpio86", "gpio87",
1866 qup_uart11_default: qup-uart11-default {
1868 pins = "gpio53", "gpio54",
1874 sec_mi2s_active: sec-mi2s-active {
1876 pins = "gpio49", "gpio50", "gpio51";
1877 function = "mi2s_1";
1881 pri_mi2s_active: pri-mi2s-active {
1883 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1884 function = "mi2s_0";
1888 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1891 function = "lpass_ext";
1896 remoteproc_mpss: remoteproc@4080000 {
1897 compatible = "qcom,sc7180-mpss-pas";
1898 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1899 reg-names = "qdsp6", "rmb";
1901 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1902 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1903 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1904 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1905 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1906 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1907 interrupt-names = "wdog", "fatal", "ready", "handover",
1908 "stop-ack", "shutdown-ack";
1910 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1911 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1912 <&gcc GCC_MSS_NAV_AXI_CLK>,
1913 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1914 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1915 <&rpmhcc RPMH_CXO_CLK>;
1916 clock-names = "iface", "bus", "nav", "snoc_axi",
1919 power-domains = <&rpmhpd SC7180_CX>,
1920 <&rpmhpd SC7180_MX>,
1921 <&rpmhpd SC7180_MSS>;
1922 power-domain-names = "cx", "mx", "mss";
1924 memory-region = <&mpss_mem>;
1926 qcom,qmp = <&aoss_qmp>;
1928 qcom,smem-states = <&modem_smp2p_out 0>;
1929 qcom,smem-state-names = "stop";
1931 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1932 <&pdc_reset PDC_MODEM_SYNC_RESET>;
1933 reset-names = "mss_restart", "pdc_reset";
1935 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1936 qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
1938 status = "disabled";
1941 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1943 qcom,remote-pid = <1>;
1944 mboxes = <&apss_shared 12>;
1949 compatible = "qcom,adreno-618.0", "qcom,adreno";
1950 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1951 <0 0x05061000 0 0x800>;
1952 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1953 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1954 iommus = <&adreno_smmu 0>;
1955 operating-points-v2 = <&gpu_opp_table>;
1958 #cooling-cells = <2>;
1960 nvmem-cells = <&gpu_speed_bin>;
1961 nvmem-cell-names = "speed_bin";
1963 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1964 interconnect-names = "gfx-mem";
1966 gpu_opp_table: opp-table {
1967 compatible = "operating-points-v2";
1970 opp-hz = /bits/ 64 <825000000>;
1971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1972 opp-peak-kBps = <8532000>;
1973 opp-supported-hw = <0x04>;
1977 opp-hz = /bits/ 64 <800000000>;
1978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1979 opp-peak-kBps = <8532000>;
1980 opp-supported-hw = <0x07>;
1984 opp-hz = /bits/ 64 <650000000>;
1985 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1986 opp-peak-kBps = <7216000>;
1987 opp-supported-hw = <0x07>;
1991 opp-hz = /bits/ 64 <565000000>;
1992 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1993 opp-peak-kBps = <5412000>;
1994 opp-supported-hw = <0x07>;
1998 opp-hz = /bits/ 64 <430000000>;
1999 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2000 opp-peak-kBps = <5412000>;
2001 opp-supported-hw = <0x07>;
2005 opp-hz = /bits/ 64 <355000000>;
2006 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2007 opp-peak-kBps = <3072000>;
2008 opp-supported-hw = <0x07>;
2012 opp-hz = /bits/ 64 <267000000>;
2013 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2014 opp-peak-kBps = <3072000>;
2015 opp-supported-hw = <0x07>;
2019 opp-hz = /bits/ 64 <180000000>;
2020 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2021 opp-peak-kBps = <1804000>;
2022 opp-supported-hw = <0x07>;
2027 adreno_smmu: iommu@5040000 {
2028 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2029 reg = <0 0x05040000 0 0x10000>;
2031 #global-interrupts = <2>;
2032 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2034 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2035 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2036 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2037 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2038 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2039 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2040 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2041 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2043 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2044 <&gcc GCC_GPU_CFG_AHB_CLK>;
2045 clock-names = "bus", "iface";
2047 power-domains = <&gpucc CX_GDSC>;
2051 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2052 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2053 <0 0x0b490000 0 0x10000>;
2054 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2055 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2056 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2057 interrupt-names = "hfi", "gmu";
2058 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2059 <&gpucc GPU_CC_CXO_CLK>,
2060 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2061 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2062 clock-names = "gmu", "cxo", "axi", "memnoc";
2063 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2064 power-domain-names = "cx", "gx";
2065 iommus = <&adreno_smmu 5>;
2066 operating-points-v2 = <&gmu_opp_table>;
2068 gmu_opp_table: opp-table {
2069 compatible = "operating-points-v2";
2072 opp-hz = /bits/ 64 <200000000>;
2073 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2078 gpucc: clock-controller@5090000 {
2079 compatible = "qcom,sc7180-gpucc";
2080 reg = <0 0x05090000 0 0x9000>;
2081 clocks = <&rpmhcc RPMH_CXO_CLK>,
2082 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2083 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2084 clock-names = "bi_tcxo",
2085 "gcc_gpu_gpll0_clk_src",
2086 "gcc_gpu_gpll0_div_clk_src";
2089 #power-domain-cells = <1>;
2093 compatible = "arm,coresight-stm", "arm,primecell";
2094 reg = <0 0x06002000 0 0x1000>,
2095 <0 0x16280000 0 0x180000>;
2096 reg-names = "stm-base", "stm-stimulus-base";
2098 clocks = <&aoss_qmp>;
2099 clock-names = "apb_pclk";
2104 remote-endpoint = <&funnel0_in7>;
2111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2112 reg = <0 0x06041000 0 0x1000>;
2114 clocks = <&aoss_qmp>;
2115 clock-names = "apb_pclk";
2119 funnel0_out: endpoint {
2120 remote-endpoint = <&merge_funnel_in0>;
2126 #address-cells = <1>;
2131 funnel0_in7: endpoint {
2132 remote-endpoint = <&stm_out>;
2139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2140 reg = <0 0x06042000 0 0x1000>;
2142 clocks = <&aoss_qmp>;
2143 clock-names = "apb_pclk";
2147 funnel1_out: endpoint {
2148 remote-endpoint = <&merge_funnel_in1>;
2154 #address-cells = <1>;
2159 funnel1_in4: endpoint {
2160 remote-endpoint = <&apss_merge_funnel_out>;
2167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2168 reg = <0 0x06045000 0 0x1000>;
2170 clocks = <&aoss_qmp>;
2171 clock-names = "apb_pclk";
2175 merge_funnel_out: endpoint {
2176 remote-endpoint = <&swao_funnel_in>;
2182 #address-cells = <1>;
2187 merge_funnel_in0: endpoint {
2188 remote-endpoint = <&funnel0_out>;
2194 merge_funnel_in1: endpoint {
2195 remote-endpoint = <&funnel1_out>;
2201 replicator@6046000 {
2202 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2203 reg = <0 0x06046000 0 0x1000>;
2205 clocks = <&aoss_qmp>;
2206 clock-names = "apb_pclk";
2210 replicator_out: endpoint {
2211 remote-endpoint = <&etr_in>;
2218 replicator_in: endpoint {
2219 remote-endpoint = <&swao_replicator_out>;
2226 compatible = "arm,coresight-tmc", "arm,primecell";
2227 reg = <0 0x06048000 0 0x1000>;
2228 iommus = <&apps_smmu 0x04a0 0x20>;
2230 clocks = <&aoss_qmp>;
2231 clock-names = "apb_pclk";
2237 remote-endpoint = <&replicator_out>;
2244 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2245 reg = <0 0x06b04000 0 0x1000>;
2247 clocks = <&aoss_qmp>;
2248 clock-names = "apb_pclk";
2252 swao_funnel_out: endpoint {
2253 remote-endpoint = <&etf_in>;
2259 #address-cells = <1>;
2264 swao_funnel_in: endpoint {
2265 remote-endpoint = <&merge_funnel_out>;
2272 compatible = "arm,coresight-tmc", "arm,primecell";
2273 reg = <0 0x06b05000 0 0x1000>;
2275 clocks = <&aoss_qmp>;
2276 clock-names = "apb_pclk";
2281 remote-endpoint = <&swao_replicator_in>;
2289 remote-endpoint = <&swao_funnel_out>;
2295 replicator@6b06000 {
2296 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2297 reg = <0 0x06b06000 0 0x1000>;
2299 clocks = <&aoss_qmp>;
2300 clock-names = "apb_pclk";
2301 qcom,replicator-loses-context;
2305 swao_replicator_out: endpoint {
2306 remote-endpoint = <&replicator_in>;
2313 swao_replicator_in: endpoint {
2314 remote-endpoint = <&etf_out>;
2321 compatible = "arm,coresight-etm4x", "arm,primecell";
2322 reg = <0 0x07040000 0 0x1000>;
2326 clocks = <&aoss_qmp>;
2327 clock-names = "apb_pclk";
2328 arm,coresight-loses-context-with-cpu;
2333 etm0_out: endpoint {
2334 remote-endpoint = <&apss_funnel_in0>;
2341 compatible = "arm,coresight-etm4x", "arm,primecell";
2342 reg = <0 0x07140000 0 0x1000>;
2346 clocks = <&aoss_qmp>;
2347 clock-names = "apb_pclk";
2348 arm,coresight-loses-context-with-cpu;
2353 etm1_out: endpoint {
2354 remote-endpoint = <&apss_funnel_in1>;
2361 compatible = "arm,coresight-etm4x", "arm,primecell";
2362 reg = <0 0x07240000 0 0x1000>;
2366 clocks = <&aoss_qmp>;
2367 clock-names = "apb_pclk";
2368 arm,coresight-loses-context-with-cpu;
2373 etm2_out: endpoint {
2374 remote-endpoint = <&apss_funnel_in2>;
2381 compatible = "arm,coresight-etm4x", "arm,primecell";
2382 reg = <0 0x07340000 0 0x1000>;
2386 clocks = <&aoss_qmp>;
2387 clock-names = "apb_pclk";
2388 arm,coresight-loses-context-with-cpu;
2393 etm3_out: endpoint {
2394 remote-endpoint = <&apss_funnel_in3>;
2401 compatible = "arm,coresight-etm4x", "arm,primecell";
2402 reg = <0 0x07440000 0 0x1000>;
2406 clocks = <&aoss_qmp>;
2407 clock-names = "apb_pclk";
2408 arm,coresight-loses-context-with-cpu;
2413 etm4_out: endpoint {
2414 remote-endpoint = <&apss_funnel_in4>;
2421 compatible = "arm,coresight-etm4x", "arm,primecell";
2422 reg = <0 0x07540000 0 0x1000>;
2426 clocks = <&aoss_qmp>;
2427 clock-names = "apb_pclk";
2428 arm,coresight-loses-context-with-cpu;
2433 etm5_out: endpoint {
2434 remote-endpoint = <&apss_funnel_in5>;
2441 compatible = "arm,coresight-etm4x", "arm,primecell";
2442 reg = <0 0x07640000 0 0x1000>;
2446 clocks = <&aoss_qmp>;
2447 clock-names = "apb_pclk";
2448 arm,coresight-loses-context-with-cpu;
2453 etm6_out: endpoint {
2454 remote-endpoint = <&apss_funnel_in6>;
2461 compatible = "arm,coresight-etm4x", "arm,primecell";
2462 reg = <0 0x07740000 0 0x1000>;
2466 clocks = <&aoss_qmp>;
2467 clock-names = "apb_pclk";
2468 arm,coresight-loses-context-with-cpu;
2473 etm7_out: endpoint {
2474 remote-endpoint = <&apss_funnel_in7>;
2480 funnel@7800000 { /* APSS Funnel */
2481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2482 reg = <0 0x07800000 0 0x1000>;
2484 clocks = <&aoss_qmp>;
2485 clock-names = "apb_pclk";
2489 apss_funnel_out: endpoint {
2490 remote-endpoint = <&apss_merge_funnel_in>;
2496 #address-cells = <1>;
2501 apss_funnel_in0: endpoint {
2502 remote-endpoint = <&etm0_out>;
2508 apss_funnel_in1: endpoint {
2509 remote-endpoint = <&etm1_out>;
2515 apss_funnel_in2: endpoint {
2516 remote-endpoint = <&etm2_out>;
2522 apss_funnel_in3: endpoint {
2523 remote-endpoint = <&etm3_out>;
2529 apss_funnel_in4: endpoint {
2530 remote-endpoint = <&etm4_out>;
2536 apss_funnel_in5: endpoint {
2537 remote-endpoint = <&etm5_out>;
2543 apss_funnel_in6: endpoint {
2544 remote-endpoint = <&etm6_out>;
2550 apss_funnel_in7: endpoint {
2551 remote-endpoint = <&etm7_out>;
2558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2559 reg = <0 0x07810000 0 0x1000>;
2561 clocks = <&aoss_qmp>;
2562 clock-names = "apb_pclk";
2566 apss_merge_funnel_out: endpoint {
2567 remote-endpoint = <&funnel1_in4>;
2574 apss_merge_funnel_in: endpoint {
2575 remote-endpoint = <&apss_funnel_out>;
2581 sdhc_2: mmc@8804000 {
2582 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2583 reg = <0 0x08804000 0 0x1000>;
2585 iommus = <&apps_smmu 0x80 0>;
2586 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2587 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2588 interrupt-names = "hc_irq", "pwr_irq";
2590 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2591 <&gcc GCC_SDCC2_APPS_CLK>,
2592 <&rpmhcc RPMH_CXO_CLK>;
2593 clock-names = "iface", "core", "xo";
2595 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2596 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2597 interconnect-names = "sdhc-ddr","cpu-sdhc";
2598 power-domains = <&rpmhpd SC7180_CX>;
2599 operating-points-v2 = <&sdhc2_opp_table>;
2603 status = "disabled";
2605 sdhc2_opp_table: opp-table {
2606 compatible = "operating-points-v2";
2609 opp-hz = /bits/ 64 <100000000>;
2610 required-opps = <&rpmhpd_opp_low_svs>;
2611 opp-peak-kBps = <1800000 600000>;
2612 opp-avg-kBps = <100000 0>;
2616 opp-hz = /bits/ 64 <202000000>;
2617 required-opps = <&rpmhpd_opp_nom>;
2618 opp-peak-kBps = <5400000 1600000>;
2619 opp-avg-kBps = <200000 0>;
2624 qspi_opp_table: opp-table-qspi {
2625 compatible = "operating-points-v2";
2628 opp-hz = /bits/ 64 <75000000>;
2629 required-opps = <&rpmhpd_opp_low_svs>;
2633 opp-hz = /bits/ 64 <150000000>;
2634 required-opps = <&rpmhpd_opp_svs>;
2638 opp-hz = /bits/ 64 <300000000>;
2639 required-opps = <&rpmhpd_opp_nom>;
2644 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2645 reg = <0 0x088dc000 0 0x600>;
2646 #address-cells = <1>;
2648 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2649 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2650 <&gcc GCC_QSPI_CORE_CLK>;
2651 clock-names = "iface", "core";
2652 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2653 &config_noc SLAVE_QSPI_0 0>;
2654 interconnect-names = "qspi-config";
2655 power-domains = <&rpmhpd SC7180_CX>;
2656 operating-points-v2 = <&qspi_opp_table>;
2657 status = "disabled";
2660 usb_1_hsphy: phy@88e3000 {
2661 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2662 reg = <0 0x088e3000 0 0x400>;
2663 status = "disabled";
2665 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2666 <&rpmhcc RPMH_CXO_CLK>;
2667 clock-names = "cfg_ahb", "ref";
2668 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2670 nvmem-cells = <&qusb2p_hstx_trim>;
2673 usb_1_qmpphy: phy-wrapper@88e9000 {
2674 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2675 reg = <0 0x088e9000 0 0x18c>,
2676 <0 0x088e8000 0 0x3c>,
2677 <0 0x088ea000 0 0x18c>;
2678 status = "disabled";
2679 #address-cells = <2>;
2683 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2684 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2685 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2686 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2687 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2689 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2690 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2691 reset-names = "phy", "common";
2693 usb_1_ssphy: usb3-phy@88e9200 {
2694 reg = <0 0x088e9200 0 0x128>,
2695 <0 0x088e9400 0 0x200>,
2696 <0 0x088e9c00 0 0x218>,
2697 <0 0x088e9600 0 0x128>,
2698 <0 0x088e9800 0 0x200>,
2699 <0 0x088e9a00 0 0x18>;
2702 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2703 clock-names = "pipe0";
2704 clock-output-names = "usb3_phy_pipe_clk_src";
2707 dp_phy: dp-phy@88ea200 {
2708 reg = <0 0x088ea200 0 0x200>,
2709 <0 0x088ea400 0 0x200>,
2710 <0 0x088eaa00 0 0x200>,
2711 <0 0x088ea600 0 0x200>,
2712 <0 0x088ea800 0 0x200>;
2718 dc_noc: interconnect@9160000 {
2719 compatible = "qcom,sc7180-dc-noc";
2720 reg = <0 0x09160000 0 0x03200>;
2721 #interconnect-cells = <2>;
2722 qcom,bcm-voters = <&apps_bcm_voter>;
2725 system-cache-controller@9200000 {
2726 compatible = "qcom,sc7180-llcc";
2727 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2728 reg-names = "llcc_base", "llcc_broadcast_base";
2729 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2732 gem_noc: interconnect@9680000 {
2733 compatible = "qcom,sc7180-gem-noc";
2734 reg = <0 0x09680000 0 0x3e200>;
2735 #interconnect-cells = <2>;
2736 qcom,bcm-voters = <&apps_bcm_voter>;
2739 npu_noc: interconnect@9990000 {
2740 compatible = "qcom,sc7180-npu-noc";
2741 reg = <0 0x09990000 0 0x1600>;
2742 #interconnect-cells = <2>;
2743 qcom,bcm-voters = <&apps_bcm_voter>;
2746 usb_1: usb@a6f8800 {
2747 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2748 reg = <0 0x0a6f8800 0 0x400>;
2749 status = "disabled";
2750 #address-cells = <2>;
2755 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2756 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2757 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2758 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2759 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2760 clock-names = "cfg_noc",
2766 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2767 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2768 assigned-clock-rates = <19200000>, <150000000>;
2770 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2771 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2772 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2773 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
2774 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2775 "dm_hs_phy_irq", "dp_hs_phy_irq";
2777 power-domains = <&gcc USB30_PRIM_GDSC>;
2779 resets = <&gcc GCC_USB30_PRIM_BCR>;
2781 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2782 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2783 interconnect-names = "usb-ddr", "apps-usb";
2785 usb_1_dwc3: usb@a600000 {
2786 compatible = "snps,dwc3";
2787 reg = <0 0x0a600000 0 0xe000>;
2788 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2789 iommus = <&apps_smmu 0x540 0>;
2790 snps,dis_u2_susphy_quirk;
2791 snps,dis_enblslpm_quirk;
2792 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2793 phy-names = "usb2-phy", "usb3-phy";
2794 maximum-speed = "super-speed";
2798 venus: video-codec@aa00000 {
2799 compatible = "qcom,sc7180-venus";
2800 reg = <0 0x0aa00000 0 0xff000>;
2801 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2802 power-domains = <&videocc VENUS_GDSC>,
2803 <&videocc VCODEC0_GDSC>,
2804 <&rpmhpd SC7180_CX>;
2805 power-domain-names = "venus", "vcodec0", "cx";
2806 operating-points-v2 = <&venus_opp_table>;
2807 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2808 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2809 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2810 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2811 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2812 clock-names = "core", "iface", "bus",
2813 "vcodec0_core", "vcodec0_bus";
2814 iommus = <&apps_smmu 0x0c00 0x60>;
2815 memory-region = <&venus_mem>;
2816 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2818 interconnect-names = "video-mem", "cpu-cfg";
2821 compatible = "venus-decoder";
2825 compatible = "venus-encoder";
2828 venus_opp_table: opp-table {
2829 compatible = "operating-points-v2";
2832 opp-hz = /bits/ 64 <150000000>;
2833 required-opps = <&rpmhpd_opp_low_svs>;
2837 opp-hz = /bits/ 64 <270000000>;
2838 required-opps = <&rpmhpd_opp_svs>;
2842 opp-hz = /bits/ 64 <340000000>;
2843 required-opps = <&rpmhpd_opp_svs_l1>;
2847 opp-hz = /bits/ 64 <434000000>;
2848 required-opps = <&rpmhpd_opp_nom>;
2852 opp-hz = /bits/ 64 <500000097>;
2853 required-opps = <&rpmhpd_opp_turbo>;
2858 videocc: clock-controller@ab00000 {
2859 compatible = "qcom,sc7180-videocc";
2860 reg = <0 0x0ab00000 0 0x10000>;
2861 clocks = <&rpmhcc RPMH_CXO_CLK>;
2862 clock-names = "bi_tcxo";
2865 #power-domain-cells = <1>;
2868 camnoc_virt: interconnect@ac00000 {
2869 compatible = "qcom,sc7180-camnoc-virt";
2870 reg = <0 0x0ac00000 0 0x1000>;
2871 #interconnect-cells = <2>;
2872 qcom,bcm-voters = <&apps_bcm_voter>;
2875 camcc: clock-controller@ad00000 {
2876 compatible = "qcom,sc7180-camcc";
2877 reg = <0 0x0ad00000 0 0x10000>;
2878 clocks = <&rpmhcc RPMH_CXO_CLK>,
2879 <&gcc GCC_CAMERA_AHB_CLK>,
2880 <&gcc GCC_CAMERA_XO_CLK>;
2881 clock-names = "bi_tcxo", "iface", "xo";
2884 #power-domain-cells = <1>;
2887 mdss: mdss@ae00000 {
2888 compatible = "qcom,sc7180-mdss";
2889 reg = <0 0x0ae00000 0 0x1000>;
2892 power-domains = <&dispcc MDSS_GDSC>;
2894 clocks = <&gcc GCC_DISP_AHB_CLK>,
2895 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2896 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2897 clock-names = "iface", "ahb", "core";
2899 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2900 interrupt-controller;
2901 #interrupt-cells = <1>;
2903 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2904 interconnect-names = "mdp0-mem";
2906 iommus = <&apps_smmu 0x800 0x2>;
2908 #address-cells = <2>;
2912 status = "disabled";
2914 mdp: display-controller@ae01000 {
2915 compatible = "qcom,sc7180-dpu";
2916 reg = <0 0x0ae01000 0 0x8f000>,
2917 <0 0x0aeb0000 0 0x2008>;
2918 reg-names = "mdp", "vbif";
2920 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2921 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2922 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2923 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2924 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2925 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2926 clock-names = "bus", "iface", "rot", "lut", "core",
2928 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2929 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2930 <&dispcc DISP_CC_MDSS_AHB_CLK>;
2931 assigned-clock-rates = <19200000>,
2934 operating-points-v2 = <&mdp_opp_table>;
2935 power-domains = <&rpmhpd SC7180_CX>;
2937 interrupt-parent = <&mdss>;
2940 status = "disabled";
2943 #address-cells = <1>;
2948 dpu_intf1_out: endpoint {
2949 remote-endpoint = <&dsi0_in>;
2955 dpu_intf0_out: endpoint {
2956 remote-endpoint = <&dp_in>;
2961 mdp_opp_table: opp-table {
2962 compatible = "operating-points-v2";
2965 opp-hz = /bits/ 64 <200000000>;
2966 required-opps = <&rpmhpd_opp_low_svs>;
2970 opp-hz = /bits/ 64 <300000000>;
2971 required-opps = <&rpmhpd_opp_svs>;
2975 opp-hz = /bits/ 64 <345000000>;
2976 required-opps = <&rpmhpd_opp_svs_l1>;
2980 opp-hz = /bits/ 64 <460000000>;
2981 required-opps = <&rpmhpd_opp_nom>;
2988 compatible = "qcom,mdss-dsi-ctrl";
2989 reg = <0 0x0ae94000 0 0x400>;
2990 reg-names = "dsi_ctrl";
2992 interrupt-parent = <&mdss>;
2995 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2996 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2997 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2998 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2999 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3000 <&gcc GCC_DISP_HF_AXI_CLK>;
3001 clock-names = "byte",
3008 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3009 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3011 operating-points-v2 = <&dsi_opp_table>;
3012 power-domains = <&rpmhpd SC7180_CX>;
3017 #address-cells = <1>;
3020 status = "disabled";
3023 #address-cells = <1>;
3029 remote-endpoint = <&dpu_intf1_out>;
3035 dsi0_out: endpoint {
3040 dsi_opp_table: opp-table {
3041 compatible = "operating-points-v2";
3044 opp-hz = /bits/ 64 <187500000>;
3045 required-opps = <&rpmhpd_opp_low_svs>;
3049 opp-hz = /bits/ 64 <300000000>;
3050 required-opps = <&rpmhpd_opp_svs>;
3054 opp-hz = /bits/ 64 <358000000>;
3055 required-opps = <&rpmhpd_opp_svs_l1>;
3060 dsi_phy: dsi-phy@ae94400 {
3061 compatible = "qcom,dsi-phy-10nm";
3062 reg = <0 0x0ae94400 0 0x200>,
3063 <0 0x0ae94600 0 0x280>,
3064 <0 0x0ae94a00 0 0x1e0>;
3065 reg-names = "dsi_phy",
3072 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3073 <&rpmhcc RPMH_CXO_CLK>;
3074 clock-names = "iface", "ref";
3076 status = "disabled";
3079 mdss_dp: displayport-controller@ae90000 {
3080 compatible = "qcom,sc7180-dp";
3081 status = "disabled";
3083 reg = <0 0xae90000 0 0x200>,
3084 <0 0xae90200 0 0x200>,
3085 <0 0xae90400 0 0xc00>,
3086 <0 0xae91000 0 0x400>,
3087 <0 0xae91400 0 0x400>;
3089 interrupt-parent = <&mdss>;
3092 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3093 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3094 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3095 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3096 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3097 clock-names = "core_iface", "core_aux", "ctrl_link",
3098 "ctrl_link_iface", "stream_pixel";
3099 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3100 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3101 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3105 operating-points-v2 = <&dp_opp_table>;
3106 power-domains = <&rpmhpd SC7180_CX>;
3108 #sound-dai-cells = <0>;
3111 #address-cells = <1>;
3116 remote-endpoint = <&dpu_intf0_out>;
3122 dp_out: endpoint { };
3126 dp_opp_table: opp-table {
3127 compatible = "operating-points-v2";
3130 opp-hz = /bits/ 64 <160000000>;
3131 required-opps = <&rpmhpd_opp_low_svs>;
3135 opp-hz = /bits/ 64 <270000000>;
3136 required-opps = <&rpmhpd_opp_svs>;
3140 opp-hz = /bits/ 64 <540000000>;
3141 required-opps = <&rpmhpd_opp_svs_l1>;
3145 opp-hz = /bits/ 64 <810000000>;
3146 required-opps = <&rpmhpd_opp_nom>;
3152 dispcc: clock-controller@af00000 {
3153 compatible = "qcom,sc7180-dispcc";
3154 reg = <0 0x0af00000 0 0x200000>;
3155 clocks = <&rpmhcc RPMH_CXO_CLK>,
3156 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3161 clock-names = "bi_tcxo",
3162 "gcc_disp_gpll0_clk_src",
3163 "dsi0_phy_pll_out_byteclk",
3164 "dsi0_phy_pll_out_dsiclk",
3165 "dp_phy_pll_link_clk",
3166 "dp_phy_pll_vco_div_clk";
3169 #power-domain-cells = <1>;
3172 pdc: interrupt-controller@b220000 {
3173 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3174 reg = <0 0x0b220000 0 0x30000>;
3175 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3176 #interrupt-cells = <2>;
3177 interrupt-parent = <&intc>;
3178 interrupt-controller;
3181 pdc_reset: reset-controller@b2e0000 {
3182 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3183 reg = <0 0x0b2e0000 0 0x20000>;
3187 tsens0: thermal-sensor@c263000 {
3188 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3189 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3190 <0 0x0c222000 0 0x1ff>; /* SROT */
3191 #qcom,sensors = <15>;
3192 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3193 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3194 interrupt-names = "uplow","critical";
3195 #thermal-sensor-cells = <1>;
3198 tsens1: thermal-sensor@c265000 {
3199 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3200 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3201 <0 0x0c223000 0 0x1ff>; /* SROT */
3202 #qcom,sensors = <10>;
3203 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3204 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3205 interrupt-names = "uplow","critical";
3206 #thermal-sensor-cells = <1>;
3209 aoss_reset: reset-controller@c2a0000 {
3210 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3211 reg = <0 0x0c2a0000 0 0x31000>;
3215 aoss_qmp: power-controller@c300000 {
3216 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3217 reg = <0 0x0c300000 0 0x400>;
3218 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3219 mboxes = <&apss_shared 0>;
3225 compatible = "qcom,rpmh-stats";
3226 reg = <0 0x0c3f0000 0 0x400>;
3229 spmi_bus: spmi@c440000 {
3230 compatible = "qcom,spmi-pmic-arb";
3231 reg = <0 0x0c440000 0 0x1100>,
3232 <0 0x0c600000 0 0x2000000>,
3233 <0 0x0e600000 0 0x100000>,
3234 <0 0x0e700000 0 0xa0000>,
3235 <0 0x0c40a000 0 0x26000>;
3236 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3237 interrupt-names = "periph_irq";
3238 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3241 #address-cells = <2>;
3243 interrupt-controller;
3244 #interrupt-cells = <4>;
3249 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3250 reg = <0 0x146aa000 0 0x2000>;
3252 #address-cells = <1>;
3255 ranges = <0 0 0x146aa000 0x2000>;
3258 compatible = "qcom,pil-reloc-info";
3263 apps_smmu: iommu@15000000 {
3264 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3265 reg = <0 0x15000000 0 0x100000>;
3267 #global-interrupts = <1>;
3268 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3270 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3271 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3282 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3283 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3284 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3285 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3286 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3287 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3288 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3289 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3290 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3291 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3292 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3293 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3294 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3295 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3297 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3298 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3299 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3300 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3301 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3302 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3303 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3304 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3305 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3306 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3307 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3308 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3309 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3310 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3311 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3312 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3313 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3314 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3315 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3316 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3317 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3318 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3319 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3320 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3321 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3322 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3323 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3324 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3325 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3326 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3327 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3328 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3329 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3330 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3332 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3333 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3334 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3335 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3336 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3337 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3338 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3339 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3340 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3341 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3342 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3343 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3344 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3345 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3346 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3347 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3348 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3351 intc: interrupt-controller@17a00000 {
3352 compatible = "arm,gic-v3";
3353 #address-cells = <2>;
3356 #interrupt-cells = <3>;
3357 interrupt-controller;
3358 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3359 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3362 msi-controller@17a40000 {
3363 compatible = "arm,gic-v3-its";
3366 reg = <0 0x17a40000 0 0x20000>;
3367 status = "disabled";
3371 apss_shared: mailbox@17c00000 {
3372 compatible = "qcom,sc7180-apss-shared";
3373 reg = <0 0x17c00000 0 0x10000>;
3378 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3379 reg = <0 0x17c10000 0 0x1000>;
3380 clocks = <&sleep_clk>;
3381 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3385 #address-cells = <1>;
3387 ranges = <0 0 0 0x20000000>;
3388 compatible = "arm,armv7-timer-mem";
3389 reg = <0 0x17c20000 0 0x1000>;
3393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3394 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3395 reg = <0x17c21000 0x1000>,
3396 <0x17c22000 0x1000>;
3401 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3402 reg = <0x17c23000 0x1000>;
3403 status = "disabled";
3408 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3409 reg = <0x17c25000 0x1000>;
3410 status = "disabled";
3415 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3416 reg = <0x17c27000 0x1000>;
3417 status = "disabled";
3422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3423 reg = <0x17c29000 0x1000>;
3424 status = "disabled";
3429 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3430 reg = <0x17c2b000 0x1000>;
3431 status = "disabled";
3436 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3437 reg = <0x17c2d000 0x1000>;
3438 status = "disabled";
3442 apps_rsc: rsc@18200000 {
3443 compatible = "qcom,rpmh-rsc";
3444 reg = <0 0x18200000 0 0x10000>,
3445 <0 0x18210000 0 0x10000>,
3446 <0 0x18220000 0 0x10000>;
3447 reg-names = "drv-0", "drv-1", "drv-2";
3448 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3449 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3450 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3451 qcom,tcs-offset = <0xd00>;
3453 qcom,tcs-config = <ACTIVE_TCS 2>,
3458 rpmhcc: clock-controller {
3459 compatible = "qcom,sc7180-rpmh-clk";
3460 clocks = <&xo_board>;
3465 rpmhpd: power-controller {
3466 compatible = "qcom,sc7180-rpmhpd";
3467 #power-domain-cells = <1>;
3468 operating-points-v2 = <&rpmhpd_opp_table>;
3470 rpmhpd_opp_table: opp-table {
3471 compatible = "operating-points-v2";
3473 rpmhpd_opp_ret: opp1 {
3474 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3477 rpmhpd_opp_min_svs: opp2 {
3478 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3481 rpmhpd_opp_low_svs: opp3 {
3482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3485 rpmhpd_opp_svs: opp4 {
3486 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3489 rpmhpd_opp_svs_l1: opp5 {
3490 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3493 rpmhpd_opp_svs_l2: opp6 {
3497 rpmhpd_opp_nom: opp7 {
3498 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3501 rpmhpd_opp_nom_l1: opp8 {
3502 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3505 rpmhpd_opp_nom_l2: opp9 {
3506 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3509 rpmhpd_opp_turbo: opp10 {
3510 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3513 rpmhpd_opp_turbo_l1: opp11 {
3514 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3519 apps_bcm_voter: bcm-voter {
3520 compatible = "qcom,bcm-voter";
3524 osm_l3: interconnect@18321000 {
3525 compatible = "qcom,sc7180-osm-l3";
3526 reg = <0 0x18321000 0 0x1400>;
3528 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3529 clock-names = "xo", "alternate";
3531 #interconnect-cells = <1>;
3534 cpufreq_hw: cpufreq@18323000 {
3535 compatible = "qcom,cpufreq-hw";
3536 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3537 reg-names = "freq-domain0", "freq-domain1";
3539 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3540 clock-names = "xo", "alternate";
3542 #freq-domain-cells = <1>;
3545 wifi: wifi@18800000 {
3546 compatible = "qcom,wcn3990-wifi";
3547 reg = <0 0x18800000 0 0x800000>;
3548 reg-names = "membase";
3549 iommus = <&apps_smmu 0xc0 0x1>;
3551 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3552 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3553 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3554 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3555 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3556 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3557 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3558 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3559 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3560 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3561 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3562 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3563 memory-region = <&wlan_mem>;
3564 qcom,msa-fixed-perm;
3565 status = "disabled";
3568 lpasscc: clock-controller@62d00000 {
3569 compatible = "qcom,sc7180-lpasscorecc";
3570 reg = <0 0x62d00000 0 0x50000>,
3571 <0 0x62780000 0 0x30000>;
3572 reg-names = "lpass_core_cc", "lpass_audio_cc";
3573 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3574 <&rpmhcc RPMH_CXO_CLK>;
3575 clock-names = "iface", "bi_tcxo";
3576 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3578 #power-domain-cells = <1>;
3581 lpass_cpu: lpass@62d87000 {
3582 compatible = "qcom,sc7180-lpass-cpu";
3584 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3585 reg-names = "lpass-hdmiif", "lpass-lpaif";
3587 iommus = <&apps_smmu 0x1020 0>,
3588 <&apps_smmu 0x1021 0>,
3589 <&apps_smmu 0x1032 0>;
3591 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3593 status = "disabled";
3595 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3596 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3597 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3598 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3599 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3600 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3602 clock-names = "pcnoc-sway-clk", "audio-core",
3603 "mclk0", "pcnoc-mport-clk",
3604 "mi2s-bit-clk0", "mi2s-bit-clk1";
3607 #sound-dai-cells = <1>;
3608 #address-cells = <1>;
3611 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3613 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3616 lpass_hm: clock-controller@63000000 {
3617 compatible = "qcom,sc7180-lpasshm";
3618 reg = <0 0x63000000 0 0x28>;
3619 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3620 <&rpmhcc RPMH_CXO_CLK>;
3621 clock-names = "iface", "bi_tcxo";
3623 #power-domain-cells = <1>;
3628 cpu0_thermal: cpu0-thermal {
3629 polling-delay-passive = <250>;
3630 polling-delay = <0>;
3632 thermal-sensors = <&tsens0 1>;
3633 sustainable-power = <1052>;
3636 cpu0_alert0: trip-point0 {
3637 temperature = <90000>;
3638 hysteresis = <2000>;
3642 cpu0_alert1: trip-point1 {
3643 temperature = <95000>;
3644 hysteresis = <2000>;
3648 cpu0_crit: cpu_crit {
3649 temperature = <110000>;
3650 hysteresis = <1000>;
3657 trip = <&cpu0_alert0>;
3658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3660 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3661 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3662 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3663 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3666 trip = <&cpu0_alert1>;
3667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3668 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3669 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3670 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3671 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3672 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3677 cpu1_thermal: cpu1-thermal {
3678 polling-delay-passive = <250>;
3679 polling-delay = <0>;
3681 thermal-sensors = <&tsens0 2>;
3682 sustainable-power = <1052>;
3685 cpu1_alert0: trip-point0 {
3686 temperature = <90000>;
3687 hysteresis = <2000>;
3691 cpu1_alert1: trip-point1 {
3692 temperature = <95000>;
3693 hysteresis = <2000>;
3697 cpu1_crit: cpu_crit {
3698 temperature = <110000>;
3699 hysteresis = <1000>;
3706 trip = <&cpu1_alert0>;
3707 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3708 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3709 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3710 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3711 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3712 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3715 trip = <&cpu1_alert1>;
3716 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3717 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3718 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3719 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3720 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3721 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3726 cpu2_thermal: cpu2-thermal {
3727 polling-delay-passive = <250>;
3728 polling-delay = <0>;
3730 thermal-sensors = <&tsens0 3>;
3731 sustainable-power = <1052>;
3734 cpu2_alert0: trip-point0 {
3735 temperature = <90000>;
3736 hysteresis = <2000>;
3740 cpu2_alert1: trip-point1 {
3741 temperature = <95000>;
3742 hysteresis = <2000>;
3746 cpu2_crit: cpu_crit {
3747 temperature = <110000>;
3748 hysteresis = <1000>;
3755 trip = <&cpu2_alert0>;
3756 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3757 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3758 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3759 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3760 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3764 trip = <&cpu2_alert1>;
3765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3769 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3775 cpu3_thermal: cpu3-thermal {
3776 polling-delay-passive = <250>;
3777 polling-delay = <0>;
3779 thermal-sensors = <&tsens0 4>;
3780 sustainable-power = <1052>;
3783 cpu3_alert0: trip-point0 {
3784 temperature = <90000>;
3785 hysteresis = <2000>;
3789 cpu3_alert1: trip-point1 {
3790 temperature = <95000>;
3791 hysteresis = <2000>;
3795 cpu3_crit: cpu_crit {
3796 temperature = <110000>;
3797 hysteresis = <1000>;
3804 trip = <&cpu3_alert0>;
3805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3806 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3807 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3813 trip = <&cpu3_alert1>;
3814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3816 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3817 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3819 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3824 cpu4_thermal: cpu4-thermal {
3825 polling-delay-passive = <250>;
3826 polling-delay = <0>;
3828 thermal-sensors = <&tsens0 5>;
3829 sustainable-power = <1052>;
3832 cpu4_alert0: trip-point0 {
3833 temperature = <90000>;
3834 hysteresis = <2000>;
3838 cpu4_alert1: trip-point1 {
3839 temperature = <95000>;
3840 hysteresis = <2000>;
3844 cpu4_crit: cpu_crit {
3845 temperature = <110000>;
3846 hysteresis = <1000>;
3853 trip = <&cpu4_alert0>;
3854 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3855 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3856 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3857 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3858 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3862 trip = <&cpu4_alert1>;
3863 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3864 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3865 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3866 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3868 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3873 cpu5_thermal: cpu5-thermal {
3874 polling-delay-passive = <250>;
3875 polling-delay = <0>;
3877 thermal-sensors = <&tsens0 6>;
3878 sustainable-power = <1052>;
3881 cpu5_alert0: trip-point0 {
3882 temperature = <90000>;
3883 hysteresis = <2000>;
3887 cpu5_alert1: trip-point1 {
3888 temperature = <95000>;
3889 hysteresis = <2000>;
3893 cpu5_crit: cpu_crit {
3894 temperature = <110000>;
3895 hysteresis = <1000>;
3902 trip = <&cpu5_alert0>;
3903 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3904 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3905 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3906 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3907 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3911 trip = <&cpu5_alert1>;
3912 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3913 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3914 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3915 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3916 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3917 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3922 cpu6_thermal: cpu6-thermal {
3923 polling-delay-passive = <250>;
3924 polling-delay = <0>;
3926 thermal-sensors = <&tsens0 9>;
3927 sustainable-power = <1425>;
3930 cpu6_alert0: trip-point0 {
3931 temperature = <90000>;
3932 hysteresis = <2000>;
3936 cpu6_alert1: trip-point1 {
3937 temperature = <95000>;
3938 hysteresis = <2000>;
3942 cpu6_crit: cpu_crit {
3943 temperature = <110000>;
3944 hysteresis = <1000>;
3951 trip = <&cpu6_alert0>;
3952 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3953 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3956 trip = <&cpu6_alert1>;
3957 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3958 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3963 cpu7_thermal: cpu7-thermal {
3964 polling-delay-passive = <250>;
3965 polling-delay = <0>;
3967 thermal-sensors = <&tsens0 10>;
3968 sustainable-power = <1425>;
3971 cpu7_alert0: trip-point0 {
3972 temperature = <90000>;
3973 hysteresis = <2000>;
3977 cpu7_alert1: trip-point1 {
3978 temperature = <95000>;
3979 hysteresis = <2000>;
3983 cpu7_crit: cpu_crit {
3984 temperature = <110000>;
3985 hysteresis = <1000>;
3992 trip = <&cpu7_alert0>;
3993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3997 trip = <&cpu7_alert1>;
3998 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4004 cpu8_thermal: cpu8-thermal {
4005 polling-delay-passive = <250>;
4006 polling-delay = <0>;
4008 thermal-sensors = <&tsens0 11>;
4009 sustainable-power = <1425>;
4012 cpu8_alert0: trip-point0 {
4013 temperature = <90000>;
4014 hysteresis = <2000>;
4018 cpu8_alert1: trip-point1 {
4019 temperature = <95000>;
4020 hysteresis = <2000>;
4024 cpu8_crit: cpu_crit {
4025 temperature = <110000>;
4026 hysteresis = <1000>;
4033 trip = <&cpu8_alert0>;
4034 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4038 trip = <&cpu8_alert1>;
4039 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4045 cpu9_thermal: cpu9-thermal {
4046 polling-delay-passive = <250>;
4047 polling-delay = <0>;
4049 thermal-sensors = <&tsens0 12>;
4050 sustainable-power = <1425>;
4053 cpu9_alert0: trip-point0 {
4054 temperature = <90000>;
4055 hysteresis = <2000>;
4059 cpu9_alert1: trip-point1 {
4060 temperature = <95000>;
4061 hysteresis = <2000>;
4065 cpu9_crit: cpu_crit {
4066 temperature = <110000>;
4067 hysteresis = <1000>;
4074 trip = <&cpu9_alert0>;
4075 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4079 trip = <&cpu9_alert1>;
4080 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4087 polling-delay-passive = <250>;
4088 polling-delay = <0>;
4090 thermal-sensors = <&tsens0 0>;
4093 aoss0_alert0: trip-point0 {
4094 temperature = <90000>;
4095 hysteresis = <2000>;
4099 aoss0_crit: aoss0_crit {
4100 temperature = <110000>;
4101 hysteresis = <2000>;
4108 polling-delay-passive = <250>;
4109 polling-delay = <0>;
4111 thermal-sensors = <&tsens0 7>;
4114 cpuss0_alert0: trip-point0 {
4115 temperature = <90000>;
4116 hysteresis = <2000>;
4119 cpuss0_crit: cluster0_crit {
4120 temperature = <110000>;
4121 hysteresis = <2000>;
4128 polling-delay-passive = <250>;
4129 polling-delay = <0>;
4131 thermal-sensors = <&tsens0 8>;
4134 cpuss1_alert0: trip-point0 {
4135 temperature = <90000>;
4136 hysteresis = <2000>;
4139 cpuss1_crit: cluster0_crit {
4140 temperature = <110000>;
4141 hysteresis = <2000>;
4148 polling-delay-passive = <250>;
4149 polling-delay = <0>;
4151 thermal-sensors = <&tsens0 13>;
4154 gpuss0_alert0: trip-point0 {
4155 temperature = <95000>;
4156 hysteresis = <2000>;
4160 gpuss0_crit: gpuss0_crit {
4161 temperature = <110000>;
4162 hysteresis = <2000>;
4169 trip = <&gpuss0_alert0>;
4170 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4176 polling-delay-passive = <250>;
4177 polling-delay = <0>;
4179 thermal-sensors = <&tsens0 14>;
4182 gpuss1_alert0: trip-point0 {
4183 temperature = <95000>;
4184 hysteresis = <2000>;
4188 gpuss1_crit: gpuss1_crit {
4189 temperature = <110000>;
4190 hysteresis = <2000>;
4197 trip = <&gpuss1_alert0>;
4198 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4204 polling-delay-passive = <250>;
4205 polling-delay = <0>;
4207 thermal-sensors = <&tsens1 0>;
4210 aoss1_alert0: trip-point0 {
4211 temperature = <90000>;
4212 hysteresis = <2000>;
4216 aoss1_crit: aoss1_crit {
4217 temperature = <110000>;
4218 hysteresis = <2000>;
4225 polling-delay-passive = <250>;
4226 polling-delay = <0>;
4228 thermal-sensors = <&tsens1 1>;
4231 cwlan_alert0: trip-point0 {
4232 temperature = <90000>;
4233 hysteresis = <2000>;
4237 cwlan_crit: cwlan_crit {
4238 temperature = <110000>;
4239 hysteresis = <2000>;
4246 polling-delay-passive = <250>;
4247 polling-delay = <0>;
4249 thermal-sensors = <&tsens1 2>;
4252 audio_alert0: trip-point0 {
4253 temperature = <90000>;
4254 hysteresis = <2000>;
4258 audio_crit: audio_crit {
4259 temperature = <110000>;
4260 hysteresis = <2000>;
4267 polling-delay-passive = <250>;
4268 polling-delay = <0>;
4270 thermal-sensors = <&tsens1 3>;
4273 ddr_alert0: trip-point0 {
4274 temperature = <90000>;
4275 hysteresis = <2000>;
4279 ddr_crit: ddr_crit {
4280 temperature = <110000>;
4281 hysteresis = <2000>;
4288 polling-delay-passive = <250>;
4289 polling-delay = <0>;
4291 thermal-sensors = <&tsens1 4>;
4294 q6_hvx_alert0: trip-point0 {
4295 temperature = <90000>;
4296 hysteresis = <2000>;
4300 q6_hvx_crit: q6_hvx_crit {
4301 temperature = <110000>;
4302 hysteresis = <2000>;
4309 polling-delay-passive = <250>;
4310 polling-delay = <0>;
4312 thermal-sensors = <&tsens1 5>;
4315 camera_alert0: trip-point0 {
4316 temperature = <90000>;
4317 hysteresis = <2000>;
4321 camera_crit: camera_crit {
4322 temperature = <110000>;
4323 hysteresis = <2000>;
4330 polling-delay-passive = <250>;
4331 polling-delay = <0>;
4333 thermal-sensors = <&tsens1 6>;
4336 mdm_alert0: trip-point0 {
4337 temperature = <90000>;
4338 hysteresis = <2000>;
4342 mdm_crit: mdm_crit {
4343 temperature = <110000>;
4344 hysteresis = <2000>;
4351 polling-delay-passive = <250>;
4352 polling-delay = <0>;
4354 thermal-sensors = <&tsens1 7>;
4357 mdm_dsp_alert0: trip-point0 {
4358 temperature = <90000>;
4359 hysteresis = <2000>;
4363 mdm_dsp_crit: mdm_dsp_crit {
4364 temperature = <110000>;
4365 hysteresis = <2000>;
4372 polling-delay-passive = <250>;
4373 polling-delay = <0>;
4375 thermal-sensors = <&tsens1 8>;
4378 npu_alert0: trip-point0 {
4379 temperature = <90000>;
4380 hysteresis = <2000>;
4384 npu_crit: npu_crit {
4385 temperature = <110000>;
4386 hysteresis = <2000>;
4393 polling-delay-passive = <250>;
4394 polling-delay = <0>;
4396 thermal-sensors = <&tsens1 9>;
4399 video_alert0: trip-point0 {
4400 temperature = <90000>;
4401 hysteresis = <2000>;
4405 video_crit: video_crit {
4406 temperature = <110000>;
4407 hysteresis = <2000>;
4415 compatible = "arm,armv8-timer";
4416 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4417 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4418 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4419 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;