arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/firmware/qcom,scm.h>
  15 #include <dt-bindings/interconnect/qcom,icc.h>
  16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  17 #include <dt-bindings/interconnect/qcom,sc7180.h>
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19 #include <dt-bindings/phy/phy-qcom-qmp.h>
  20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/soc/qcom,apr.h>
  26 #include <dt-bindings/sound/qcom,q6afe.h>
  27 #include <dt-bindings/thermal/thermal.h>
  28
  29 / {
  30         interrupt-parent = <&intc>;
  31
  32         #address-cells = <2>;
  33         #size-cells = <2>;
  34
  35         aliases {
  36                 mmc1 = &sdhc_1;
  37                 mmc2 = &sdhc_2;
  38                 i2c0 = &i2c0;
  39                 i2c1 = &i2c1;
  40                 i2c2 = &i2c2;
  41                 i2c3 = &i2c3;
  42                 i2c4 = &i2c4;
  43                 i2c5 = &i2c5;
  44                 i2c6 = &i2c6;
  45                 i2c7 = &i2c7;
  46                 i2c8 = &i2c8;
  47                 i2c9 = &i2c9;
  48                 i2c10 = &i2c10;
  49                 i2c11 = &i2c11;
  50                 spi0 = &spi0;
  51                 spi1 = &spi1;
  52                 spi3 = &spi3;
  53                 spi5 = &spi5;
  54                 spi6 = &spi6;
  55                 spi8 = &spi8;
  56                 spi10 = &spi10;
  57                 spi11 = &spi11;
  58         };
  59
  60         chosen { };
  61
  62         clocks {
  63                 xo_board: xo-board {
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <38400000>;
  66                         #clock-cells = <0>;
  67                 };
  68
  69                 sleep_clk: sleep-clk {
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32764>;
  72                         #clock-cells = <0>;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <2>;
  78                 #size-cells = <0>;
  79
  80                 CPU0: cpu@0 {
  81                         device_type = "cpu";
  82                         compatible = "qcom,kryo468";
  83                         reg = <0x0 0x0>;
  84                         clocks = <&cpufreq_hw 0>;
  85                         enable-method = "psci";
  86                         power-domains = <&CPU_PD0>;
  87                         power-domain-names = "psci";
  88                         capacity-dmips-mhz = <415>;
  89                         dynamic-power-coefficient = <137>;
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  92                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  93                         next-level-cache = <&L2_0>;
  94                         #cooling-cells = <2>;
  95                         qcom,freq-domain = <&cpufreq_hw 0>;
  96                         L2_0: l2-cache {
  97                                 compatible = "cache";
  98                                 cache-level = <2>;
  99                                 cache-unified;
 100                                 next-level-cache = <&L3_0>;
 101                                 L3_0: l3-cache {
 102                                         compatible = "cache";
 103                                         cache-level = <3>;
 104                                         cache-unified;
 105                                 };
 106                         };
 107                 };
 108
 109                 CPU1: cpu@100 {
 110                         device_type = "cpu";
 111                         compatible = "qcom,kryo468";
 112                         reg = <0x0 0x100>;
 113                         clocks = <&cpufreq_hw 0>;
 114                         enable-method = "psci";
 115                         power-domains = <&CPU_PD1>;
 116                         power-domain-names = "psci";
 117                         capacity-dmips-mhz = <415>;
 118                         dynamic-power-coefficient = <137>;
 119                         next-level-cache = <&L2_100>;
 120                         operating-points-v2 = <&cpu0_opp_table>;
 121                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 122                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 123                         #cooling-cells = <2>;
 124                         qcom,freq-domain = <&cpufreq_hw 0>;
 125                         L2_100: l2-cache {
 126                                 compatible = "cache";
 127                                 cache-level = <2>;
 128                                 cache-unified;
 129                                 next-level-cache = <&L3_0>;
 130                         };
 131                 };
 132
 133                 CPU2: cpu@200 {
 134                         device_type = "cpu";
 135                         compatible = "qcom,kryo468";
 136                         reg = <0x0 0x200>;
 137                         clocks = <&cpufreq_hw 0>;
 138                         enable-method = "psci";
 139                         power-domains = <&CPU_PD2>;
 140                         power-domain-names = "psci";
 141                         capacity-dmips-mhz = <415>;
 142                         dynamic-power-coefficient = <137>;
 143                         next-level-cache = <&L2_200>;
 144                         operating-points-v2 = <&cpu0_opp_table>;
 145                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 146                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 147                         #cooling-cells = <2>;
 148                         qcom,freq-domain = <&cpufreq_hw 0>;
 149                         L2_200: l2-cache {
 150                                 compatible = "cache";
 151                                 cache-level = <2>;
 152                                 cache-unified;
 153                                 next-level-cache = <&L3_0>;
 154                         };
 155                 };
 156
 157                 CPU3: cpu@300 {
 158                         device_type = "cpu";
 159                         compatible = "qcom,kryo468";
 160                         reg = <0x0 0x300>;
 161                         clocks = <&cpufreq_hw 0>;
 162                         enable-method = "psci";
 163                         power-domains = <&CPU_PD3>;
 164                         power-domain-names = "psci";
 165                         capacity-dmips-mhz = <415>;
 166                         dynamic-power-coefficient = <137>;
 167                         next-level-cache = <&L2_300>;
 168                         operating-points-v2 = <&cpu0_opp_table>;
 169                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 170                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 171                         #cooling-cells = <2>;
 172                         qcom,freq-domain = <&cpufreq_hw 0>;
 173                         L2_300: l2-cache {
 174                                 compatible = "cache";
 175                                 cache-level = <2>;
 176                                 cache-unified;
 177                                 next-level-cache = <&L3_0>;
 178                         };
 179                 };
 180
 181                 CPU4: cpu@400 {
 182                         device_type = "cpu";
 183                         compatible = "qcom,kryo468";
 184                         reg = <0x0 0x400>;
 185                         clocks = <&cpufreq_hw 0>;
 186                         enable-method = "psci";
 187                         power-domains = <&CPU_PD4>;
 188                         power-domain-names = "psci";
 189                         capacity-dmips-mhz = <415>;
 190                         dynamic-power-coefficient = <137>;
 191                         next-level-cache = <&L2_400>;
 192                         operating-points-v2 = <&cpu0_opp_table>;
 193                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 194                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 195                         #cooling-cells = <2>;
 196                         qcom,freq-domain = <&cpufreq_hw 0>;
 197                         L2_400: l2-cache {
 198                                 compatible = "cache";
 199                                 cache-level = <2>;
 200                                 cache-unified;
 201                                 next-level-cache = <&L3_0>;
 202                         };
 203                 };
 204
 205                 CPU5: cpu@500 {
 206                         device_type = "cpu";
 207                         compatible = "qcom,kryo468";
 208                         reg = <0x0 0x500>;
 209                         clocks = <&cpufreq_hw 0>;
 210                         enable-method = "psci";
 211                         power-domains = <&CPU_PD5>;
 212                         power-domain-names = "psci";
 213                         capacity-dmips-mhz = <415>;
 214                         dynamic-power-coefficient = <137>;
 215                         next-level-cache = <&L2_500>;
 216                         operating-points-v2 = <&cpu0_opp_table>;
 217                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 218                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 219                         #cooling-cells = <2>;
 220                         qcom,freq-domain = <&cpufreq_hw 0>;
 221                         L2_500: l2-cache {
 222                                 compatible = "cache";
 223                                 cache-level = <2>;
 224                                 cache-unified;
 225                                 next-level-cache = <&L3_0>;
 226                         };
 227                 };
 228
 229                 CPU6: cpu@600 {
 230                         device_type = "cpu";
 231                         compatible = "qcom,kryo468";
 232                         reg = <0x0 0x600>;
 233                         clocks = <&cpufreq_hw 1>;
 234                         enable-method = "psci";
 235                         power-domains = <&CPU_PD6>;
 236                         power-domain-names = "psci";
 237                         capacity-dmips-mhz = <1024>;
 238                         dynamic-power-coefficient = <480>;
 239                         next-level-cache = <&L2_600>;
 240                         operating-points-v2 = <&cpu6_opp_table>;
 241                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 242                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 243                         #cooling-cells = <2>;
 244                         qcom,freq-domain = <&cpufreq_hw 1>;
 245                         L2_600: l2-cache {
 246                                 compatible = "cache";
 247                                 cache-level = <2>;
 248                                 cache-unified;
 249                                 next-level-cache = <&L3_0>;
 250                         };
 251                 };
 252
 253                 CPU7: cpu@700 {
 254                         device_type = "cpu";
 255                         compatible = "qcom,kryo468";
 256                         reg = <0x0 0x700>;
 257                         clocks = <&cpufreq_hw 1>;
 258                         enable-method = "psci";
 259                         power-domains = <&CPU_PD7>;
 260                         power-domain-names = "psci";
 261                         capacity-dmips-mhz = <1024>;
 262                         dynamic-power-coefficient = <480>;
 263                         next-level-cache = <&L2_700>;
 264                         operating-points-v2 = <&cpu6_opp_table>;
 265                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 266                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 267                         #cooling-cells = <2>;
 268                         qcom,freq-domain = <&cpufreq_hw 1>;
 269                         L2_700: l2-cache {
 270                                 compatible = "cache";
 271                                 cache-level = <2>;
 272                                 cache-unified;
 273                                 next-level-cache = <&L3_0>;
 274                         };
 275                 };
 276
 277                 cpu-map {
 278                         cluster0 {
 279                                 core0 {
 280                                         cpu = <&CPU0>;
 281                                 };
 282
 283                                 core1 {
 284                                         cpu = <&CPU1>;
 285                                 };
 286
 287                                 core2 {
 288                                         cpu = <&CPU2>;
 289                                 };
 290
 291                                 core3 {
 292                                         cpu = <&CPU3>;
 293                                 };
 294
 295                                 core4 {
 296                                         cpu = <&CPU4>;
 297                                 };
 298
 299                                 core5 {
 300                                         cpu = <&CPU5>;
 301                                 };
 302
 303                                 core6 {
 304                                         cpu = <&CPU6>;
 305                                 };
 306
 307                                 core7 {
 308                                         cpu = <&CPU7>;
 309                                 };
 310                         };
 311                 };
 312
 313                 idle_states: idle-states {
 314                         entry-method = "psci";
 315
 316                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 317                                 compatible = "arm,idle-state";
 318                                 idle-state-name = "little-power-down";
 319                                 arm,psci-suspend-param = <0x40000003>;
 320                                 entry-latency-us = <549>;
 321                                 exit-latency-us = <901>;
 322                                 min-residency-us = <1774>;
 323                                 local-timer-stop;
 324                         };
 325
 326                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 327                                 compatible = "arm,idle-state";
 328                                 idle-state-name = "little-rail-power-down";
 329                                 arm,psci-suspend-param = <0x40000004>;
 330                                 entry-latency-us = <702>;
 331                                 exit-latency-us = <915>;
 332                                 min-residency-us = <4001>;
 333                                 local-timer-stop;
 334                         };
 335
 336                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 337                                 compatible = "arm,idle-state";
 338                                 idle-state-name = "big-power-down";
 339                                 arm,psci-suspend-param = <0x40000003>;
 340                                 entry-latency-us = <523>;
 341                                 exit-latency-us = <1244>;
 342                                 min-residency-us = <2207>;
 343                                 local-timer-stop;
 344                         };
 345
 346                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 347                                 compatible = "arm,idle-state";
 348                                 idle-state-name = "big-rail-power-down";
 349                                 arm,psci-suspend-param = <0x40000004>;
 350                                 entry-latency-us = <526>;
 351                                 exit-latency-us = <1854>;
 352                                 min-residency-us = <5555>;
 353                                 local-timer-stop;
 354                         };
 355                 };
 356
 357                 domain_idle_states: domain-idle-states {
 358                         CLUSTER_SLEEP_PC: cluster-sleep-0 {
 359                                 compatible = "domain-idle-state";
 360                                 idle-state-name = "cluster-l3-power-collapse";
 361                                 arm,psci-suspend-param = <0x41000044>;
 362                                 entry-latency-us = <2752>;
 363                                 exit-latency-us = <3048>;
 364                                 min-residency-us = <6118>;
 365                         };
 366
 367                         CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
 368                                 compatible = "domain-idle-state";
 369                                 idle-state-name = "cluster-cx-retention";
 370                                 arm,psci-suspend-param = <0x41001244>;
 371                                 entry-latency-us = <3638>;
 372                                 exit-latency-us = <4562>;
 373                                 min-residency-us = <8467>;
 374                         };
 375
 376                         CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
 377                                 compatible = "domain-idle-state";
 378                                 idle-state-name = "cluster-power-down";
 379                                 arm,psci-suspend-param = <0x4100b244>;
 380                                 entry-latency-us = <3263>;
 381                                 exit-latency-us = <6562>;
 382                                 min-residency-us = <9826>;
 383                         };
 384                 };
 385         };
 386
 387         firmware {
 388                 scm: scm {
 389                         compatible = "qcom,scm-sc7180", "qcom,scm";
 390                 };
 391         };
 392
 393         memory@80000000 {
 394                 device_type = "memory";
 395                 /* We expect the bootloader to fill in the size */
 396                 reg = <0 0x80000000 0 0>;
 397         };
 398
 399         cpu0_opp_table: opp-table-cpu0 {
 400                 compatible = "operating-points-v2";
 401                 opp-shared;
 402
 403                 cpu0_opp1: opp-300000000 {
 404                         opp-hz = /bits/ 64 <300000000>;
 405                         opp-peak-kBps = <1200000 4800000>;
 406                 };
 407
 408                 cpu0_opp2: opp-576000000 {
 409                         opp-hz = /bits/ 64 <576000000>;
 410                         opp-peak-kBps = <1200000 4800000>;
 411                 };
 412
 413                 cpu0_opp3: opp-768000000 {
 414                         opp-hz = /bits/ 64 <768000000>;
 415                         opp-peak-kBps = <1200000 4800000>;
 416                 };
 417
 418                 cpu0_opp4: opp-1017600000 {
 419                         opp-hz = /bits/ 64 <1017600000>;
 420                         opp-peak-kBps = <1804000 8908800>;
 421                 };
 422
 423                 cpu0_opp5: opp-1248000000 {
 424                         opp-hz = /bits/ 64 <1248000000>;
 425                         opp-peak-kBps = <2188000 12902400>;
 426                 };
 427
 428                 cpu0_opp6: opp-1324800000 {
 429                         opp-hz = /bits/ 64 <1324800000>;
 430                         opp-peak-kBps = <2188000 12902400>;
 431                 };
 432
 433                 cpu0_opp7: opp-1516800000 {
 434                         opp-hz = /bits/ 64 <1516800000>;
 435                         opp-peak-kBps = <3072000 15052800>;
 436                 };
 437
 438                 cpu0_opp8: opp-1612800000 {
 439                         opp-hz = /bits/ 64 <1612800000>;
 440                         opp-peak-kBps = <3072000 15052800>;
 441                 };
 442
 443                 cpu0_opp9: opp-1708800000 {
 444                         opp-hz = /bits/ 64 <1708800000>;
 445                         opp-peak-kBps = <3072000 15052800>;
 446                 };
 447
 448                 cpu0_opp10: opp-1804800000 {
 449                         opp-hz = /bits/ 64 <1804800000>;
 450                         opp-peak-kBps = <4068000 22425600>;
 451                 };
 452         };
 453
 454         cpu6_opp_table: opp-table-cpu6 {
 455                 compatible = "operating-points-v2";
 456                 opp-shared;
 457
 458                 cpu6_opp1: opp-300000000 {
 459                         opp-hz = /bits/ 64 <300000000>;
 460                         opp-peak-kBps = <2188000 8908800>;
 461                 };
 462
 463                 cpu6_opp2: opp-652800000 {
 464                         opp-hz = /bits/ 64 <652800000>;
 465                         opp-peak-kBps = <2188000 8908800>;
 466                 };
 467
 468                 cpu6_opp3: opp-825600000 {
 469                         opp-hz = /bits/ 64 <825600000>;
 470                         opp-peak-kBps = <2188000 8908800>;
 471                 };
 472
 473                 cpu6_opp4: opp-979200000 {
 474                         opp-hz = /bits/ 64 <979200000>;
 475                         opp-peak-kBps = <2188000 8908800>;
 476                 };
 477
 478                 cpu6_opp5: opp-1113600000 {
 479                         opp-hz = /bits/ 64 <1113600000>;
 480                         opp-peak-kBps = <2188000 8908800>;
 481                 };
 482
 483                 cpu6_opp6: opp-1267200000 {
 484                         opp-hz = /bits/ 64 <1267200000>;
 485                         opp-peak-kBps = <4068000 12902400>;
 486                 };
 487
 488                 cpu6_opp7: opp-1555200000 {
 489                         opp-hz = /bits/ 64 <1555200000>;
 490                         opp-peak-kBps = <4068000 15052800>;
 491                 };
 492
 493                 cpu6_opp8: opp-1708800000 {
 494                         opp-hz = /bits/ 64 <1708800000>;
 495                         opp-peak-kBps = <6220000 19353600>;
 496                 };
 497
 498                 cpu6_opp9: opp-1843200000 {
 499                         opp-hz = /bits/ 64 <1843200000>;
 500                         opp-peak-kBps = <6220000 19353600>;
 501                 };
 502
 503                 cpu6_opp10: opp-1900800000 {
 504                         opp-hz = /bits/ 64 <1900800000>;
 505                         opp-peak-kBps = <6220000 22425600>;
 506                 };
 507
 508                 cpu6_opp11: opp-1996800000 {
 509                         opp-hz = /bits/ 64 <1996800000>;
 510                         opp-peak-kBps = <6220000 22425600>;
 511                 };
 512
 513                 cpu6_opp12: opp-2112000000 {
 514                         opp-hz = /bits/ 64 <2112000000>;
 515                         opp-peak-kBps = <6220000 22425600>;
 516                 };
 517
 518                 cpu6_opp13: opp-2208000000 {
 519                         opp-hz = /bits/ 64 <2208000000>;
 520                         opp-peak-kBps = <7216000 22425600>;
 521                 };
 522
 523                 cpu6_opp14: opp-2323200000 {
 524                         opp-hz = /bits/ 64 <2323200000>;
 525                         opp-peak-kBps = <7216000 22425600>;
 526                 };
 527
 528                 cpu6_opp15: opp-2400000000 {
 529                         opp-hz = /bits/ 64 <2400000000>;
 530                         opp-peak-kBps = <8532000 23347200>;
 531                 };
 532
 533                 cpu6_opp16: opp-2553600000 {
 534                         opp-hz = /bits/ 64 <2553600000>;
 535                         opp-peak-kBps = <8532000 23347200>;
 536                 };
 537         };
 538
 539         qspi_opp_table: opp-table-qspi {
 540                 compatible = "operating-points-v2";
 541
 542                 opp-75000000 {
 543                         opp-hz = /bits/ 64 <75000000>;
 544                         required-opps = <&rpmhpd_opp_low_svs>;
 545                 };
 546
 547                 opp-150000000 {
 548                         opp-hz = /bits/ 64 <150000000>;
 549                         required-opps = <&rpmhpd_opp_svs>;
 550                 };
 551
 552                 opp-300000000 {
 553                         opp-hz = /bits/ 64 <300000000>;
 554                         required-opps = <&rpmhpd_opp_nom>;
 555                 };
 556         };
 557
 558         qup_opp_table: opp-table-qup {
 559                 compatible = "operating-points-v2";
 560
 561                 opp-75000000 {
 562                         opp-hz = /bits/ 64 <75000000>;
 563                         required-opps = <&rpmhpd_opp_low_svs>;
 564                 };
 565
 566                 opp-100000000 {
 567                         opp-hz = /bits/ 64 <100000000>;
 568                         required-opps = <&rpmhpd_opp_svs>;
 569                 };
 570
 571                 opp-128000000 {
 572                         opp-hz = /bits/ 64 <128000000>;
 573                         required-opps = <&rpmhpd_opp_nom>;
 574                 };
 575         };
 576
 577         pmu {
 578                 compatible = "arm,armv8-pmuv3";
 579                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 580         };
 581
 582         psci {
 583                 compatible = "arm,psci-1.0";
 584                 method = "smc";
 585
 586                 CPU_PD0: cpu0 {
 587                         #power-domain-cells = <0>;
 588                         power-domains = <&CLUSTER_PD>;
 589                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 590                 };
 591
 592                 CPU_PD1: cpu1 {
 593                         #power-domain-cells = <0>;
 594                         power-domains = <&CLUSTER_PD>;
 595                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 596                 };
 597
 598                 CPU_PD2: cpu2 {
 599                         #power-domain-cells = <0>;
 600                         power-domains = <&CLUSTER_PD>;
 601                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 602                 };
 603
 604                 CPU_PD3: cpu3 {
 605                         #power-domain-cells = <0>;
 606                         power-domains = <&CLUSTER_PD>;
 607                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 608                 };
 609
 610                 CPU_PD4: cpu4 {
 611                         #power-domain-cells = <0>;
 612                         power-domains = <&CLUSTER_PD>;
 613                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 614                 };
 615
 616                 CPU_PD5: cpu5 {
 617                         #power-domain-cells = <0>;
 618                         power-domains = <&CLUSTER_PD>;
 619                         domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 620                 };
 621
 622                 CPU_PD6: cpu6 {
 623                         #power-domain-cells = <0>;
 624                         power-domains = <&CLUSTER_PD>;
 625                         domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 626                 };
 627
 628                 CPU_PD7: cpu7 {
 629                         #power-domain-cells = <0>;
 630                         power-domains = <&CLUSTER_PD>;
 631                         domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 632                 };
 633
 634                 CLUSTER_PD: cpu-cluster0 {
 635                         #power-domain-cells = <0>;
 636                         domain-idle-states = <&CLUSTER_SLEEP_PC
 637                                               &CLUSTER_SLEEP_CX_RET
 638                                               &CLUSTER_AOSS_SLEEP>;
 639                 };
 640         };
 641
 642         reserved_memory: reserved-memory {
 643                 #address-cells = <2>;
 644                 #size-cells = <2>;
 645                 ranges;
 646
 647                 hyp_mem: memory@80000000 {
 648                         reg = <0x0 0x80000000 0x0 0x600000>;
 649                         no-map;
 650                 };
 651
 652                 xbl_mem: memory@80600000 {
 653                         reg = <0x0 0x80600000 0x0 0x200000>;
 654                         no-map;
 655                 };
 656
 657                 aop_mem: memory@80800000 {
 658                         reg = <0x0 0x80800000 0x0 0x20000>;
 659                         no-map;
 660                 };
 661
 662                 aop_cmd_db_mem: memory@80820000 {
 663                         reg = <0x0 0x80820000 0x0 0x20000>;
 664                         compatible = "qcom,cmd-db";
 665                         no-map;
 666                 };
 667
 668                 sec_apps_mem: memory@808ff000 {
 669                         reg = <0x0 0x808ff000 0x0 0x1000>;
 670                         no-map;
 671                 };
 672
 673                 smem_mem: memory@80900000 {
 674                         reg = <0x0 0x80900000 0x0 0x200000>;
 675                         no-map;
 676                 };
 677
 678                 tz_mem: memory@80b00000 {
 679                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 680                         no-map;
 681                 };
 682
 683                 ipa_fw_mem: memory@8b700000 {
 684                         reg = <0 0x8b700000 0 0x10000>;
 685                         no-map;
 686                 };
 687
 688                 rmtfs_mem: memory@94600000 {
 689                         compatible = "qcom,rmtfs-mem";
 690                         reg = <0x0 0x94600000 0x0 0x200000>;
 691                         no-map;
 692
 693                         qcom,client-id = <1>;
 694                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 695                 };
 696         };
 697
 698         smem {
 699                 compatible = "qcom,smem";
 700                 memory-region = <&smem_mem>;
 701                 hwlocks = <&tcsr_mutex 3>;
 702         };
 703
 704         smp2p-cdsp {
 705                 compatible = "qcom,smp2p";
 706                 qcom,smem = <94>, <432>;
 707
 708                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 709
 710                 mboxes = <&apss_shared 6>;
 711
 712                 qcom,local-pid = <0>;
 713                 qcom,remote-pid = <5>;
 714
 715                 cdsp_smp2p_out: master-kernel {
 716                         qcom,entry-name = "master-kernel";
 717                         #qcom,smem-state-cells = <1>;
 718                 };
 719
 720                 cdsp_smp2p_in: slave-kernel {
 721                         qcom,entry-name = "slave-kernel";
 722
 723                         interrupt-controller;
 724                         #interrupt-cells = <2>;
 725                 };
 726         };
 727
 728         smp2p-lpass {
 729                 compatible = "qcom,smp2p";
 730                 qcom,smem = <443>, <429>;
 731
 732                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 733
 734                 mboxes = <&apss_shared 10>;
 735
 736                 qcom,local-pid = <0>;
 737                 qcom,remote-pid = <2>;
 738
 739                 adsp_smp2p_out: master-kernel {
 740                         qcom,entry-name = "master-kernel";
 741                         #qcom,smem-state-cells = <1>;
 742                 };
 743
 744                 adsp_smp2p_in: slave-kernel {
 745                         qcom,entry-name = "slave-kernel";
 746
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749                 };
 750         };
 751
 752         smp2p-mpss {
 753                 compatible = "qcom,smp2p";
 754                 qcom,smem = <435>, <428>;
 755                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 756                 mboxes = <&apss_shared 14>;
 757                 qcom,local-pid = <0>;
 758                 qcom,remote-pid = <1>;
 759
 760                 modem_smp2p_out: master-kernel {
 761                         qcom,entry-name = "master-kernel";
 762                         #qcom,smem-state-cells = <1>;
 763                 };
 764
 765                 modem_smp2p_in: slave-kernel {
 766                         qcom,entry-name = "slave-kernel";
 767                         interrupt-controller;
 768                         #interrupt-cells = <2>;
 769                 };
 770
 771                 ipa_smp2p_out: ipa-ap-to-modem {
 772                         qcom,entry-name = "ipa";
 773                         #qcom,smem-state-cells = <1>;
 774                 };
 775
 776                 ipa_smp2p_in: ipa-modem-to-ap {
 777                         qcom,entry-name = "ipa";
 778                         interrupt-controller;
 779                         #interrupt-cells = <2>;
 780                 };
 781         };
 782
 783         soc: soc@0 {
 784                 #address-cells = <2>;
 785                 #size-cells = <2>;
 786                 ranges = <0 0 0 0 0x10 0>;
 787                 dma-ranges = <0 0 0 0 0x10 0>;
 788                 compatible = "simple-bus";
 789
 790                 gcc: clock-controller@100000 {
 791                         compatible = "qcom,gcc-sc7180";
 792                         reg = <0 0x00100000 0 0x1f0000>;
 793                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 794                                  <&rpmhcc RPMH_CXO_CLK_A>,
 795                                  <&sleep_clk>;
 796                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 797                         #clock-cells = <1>;
 798                         #reset-cells = <1>;
 799                         #power-domain-cells = <1>;
 800                         power-domains = <&rpmhpd SC7180_CX>;
 801                 };
 802
 803                 qfprom: efuse@784000 {
 804                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 805                         reg = <0 0x00784000 0 0x7a0>,
 806                               <0 0x00780000 0 0x7a0>,
 807                               <0 0x00782000 0 0x100>,
 808                               <0 0x00786000 0 0x1fff>;
 809
 810                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 811                         clock-names = "core";
 812                         #address-cells = <1>;
 813                         #size-cells = <1>;
 814
 815                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 816                                 reg = <0x25b 0x1>;
 817                                 bits = <1 3>;
 818                         };
 819
 820                         gpu_speed_bin: gpu_speed_bin@1d2 {
 821                                 reg = <0x1d2 0x2>;
 822                                 bits = <5 8>;
 823                         };
 824                 };
 825
 826                 sdhc_1: mmc@7c4000 {
 827                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 828                         reg = <0 0x007c4000 0 0x1000>,
 829                                 <0 0x007c5000 0 0x1000>;
 830                         reg-names = "hc", "cqhci";
 831
 832                         iommus = <&apps_smmu 0x60 0x0>;
 833                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 834                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 835                         interrupt-names = "hc_irq", "pwr_irq";
 836
 837                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 838                                  <&gcc GCC_SDCC1_APPS_CLK>,
 839                                  <&rpmhcc RPMH_CXO_CLK>;
 840                         clock-names = "iface", "core", "xo";
 841                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 842                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 843                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 844                         power-domains = <&rpmhpd SC7180_CX>;
 845                         operating-points-v2 = <&sdhc1_opp_table>;
 846
 847                         bus-width = <8>;
 848                         non-removable;
 849                         supports-cqe;
 850
 851                         mmc-ddr-1_8v;
 852                         mmc-hs200-1_8v;
 853                         mmc-hs400-1_8v;
 854                         mmc-hs400-enhanced-strobe;
 855
 856                         status = "disabled";
 857
 858                         sdhc1_opp_table: opp-table {
 859                                 compatible = "operating-points-v2";
 860
 861                                 opp-100000000 {
 862                                         opp-hz = /bits/ 64 <100000000>;
 863                                         required-opps = <&rpmhpd_opp_low_svs>;
 864                                         opp-peak-kBps = <1800000 600000>;
 865                                         opp-avg-kBps = <100000 0>;
 866                                 };
 867
 868                                 opp-384000000 {
 869                                         opp-hz = /bits/ 64 <384000000>;
 870                                         required-opps = <&rpmhpd_opp_nom>;
 871                                         opp-peak-kBps = <5400000 1600000>;
 872                                         opp-avg-kBps = <390000 0>;
 873                                 };
 874                         };
 875                 };
 876
 877                 qupv3_id_0: geniqup@8c0000 {
 878                         compatible = "qcom,geni-se-qup";
 879                         reg = <0 0x008c0000 0 0x6000>;
 880                         clock-names = "m-ahb", "s-ahb";
 881                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 882                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 883                         #address-cells = <2>;
 884                         #size-cells = <2>;
 885                         ranges;
 886                         iommus = <&apps_smmu 0x43 0x0>;
 887                         status = "disabled";
 888
 889                         i2c0: i2c@880000 {
 890                                 compatible = "qcom,geni-i2c";
 891                                 reg = <0 0x00880000 0 0x4000>;
 892                                 clock-names = "se";
 893                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 894                                 pinctrl-names = "default";
 895                                 pinctrl-0 = <&qup_i2c0_default>;
 896                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 897                                 #address-cells = <1>;
 898                                 #size-cells = <0>;
 899                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 900                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 901                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 902                                 interconnect-names = "qup-core", "qup-config",
 903                                                         "qup-memory";
 904                                 power-domains = <&rpmhpd SC7180_CX>;
 905                                 required-opps = <&rpmhpd_opp_low_svs>;
 906                                 status = "disabled";
 907                         };
 908
 909                         spi0: spi@880000 {
 910                                 compatible = "qcom,geni-spi";
 911                                 reg = <0 0x00880000 0 0x4000>;
 912                                 clock-names = "se";
 913                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 914                                 pinctrl-names = "default";
 915                                 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
 916                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 917                                 #address-cells = <1>;
 918                                 #size-cells = <0>;
 919                                 power-domains = <&rpmhpd SC7180_CX>;
 920                                 operating-points-v2 = <&qup_opp_table>;
 921                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 922                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 923                                 interconnect-names = "qup-core", "qup-config";
 924                                 status = "disabled";
 925                         };
 926
 927                         uart0: serial@880000 {
 928                                 compatible = "qcom,geni-uart";
 929                                 reg = <0 0x00880000 0 0x4000>;
 930                                 clock-names = "se";
 931                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 932                                 pinctrl-names = "default";
 933                                 pinctrl-0 = <&qup_uart0_default>;
 934                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 935                                 power-domains = <&rpmhpd SC7180_CX>;
 936                                 operating-points-v2 = <&qup_opp_table>;
 937                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 938                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 939                                 interconnect-names = "qup-core", "qup-config";
 940                                 status = "disabled";
 941                         };
 942
 943                         i2c1: i2c@884000 {
 944                                 compatible = "qcom,geni-i2c";
 945                                 reg = <0 0x00884000 0 0x4000>;
 946                                 clock-names = "se";
 947                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 948                                 pinctrl-names = "default";
 949                                 pinctrl-0 = <&qup_i2c1_default>;
 950                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 954                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 955                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 956                                 interconnect-names = "qup-core", "qup-config",
 957                                                         "qup-memory";
 958                                 power-domains = <&rpmhpd SC7180_CX>;
 959                                 required-opps = <&rpmhpd_opp_low_svs>;
 960                                 status = "disabled";
 961                         };
 962
 963                         spi1: spi@884000 {
 964                                 compatible = "qcom,geni-spi";
 965                                 reg = <0 0x00884000 0 0x4000>;
 966                                 clock-names = "se";
 967                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 968                                 pinctrl-names = "default";
 969                                 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
 970                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 power-domains = <&rpmhpd SC7180_CX>;
 974                                 operating-points-v2 = <&qup_opp_table>;
 975                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 976                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 977                                 interconnect-names = "qup-core", "qup-config";
 978                                 status = "disabled";
 979                         };
 980
 981                         uart1: serial@884000 {
 982                                 compatible = "qcom,geni-uart";
 983                                 reg = <0 0x00884000 0 0x4000>;
 984                                 clock-names = "se";
 985                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 986                                 pinctrl-names = "default";
 987                                 pinctrl-0 = <&qup_uart1_default>;
 988                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 989                                 power-domains = <&rpmhpd SC7180_CX>;
 990                                 operating-points-v2 = <&qup_opp_table>;
 991                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 992                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 993                                 interconnect-names = "qup-core", "qup-config";
 994                                 status = "disabled";
 995                         };
 996
 997                         i2c2: i2c@888000 {
 998                                 compatible = "qcom,geni-i2c";
 999                                 reg = <0 0x00888000 0 0x4000>;
1000                                 clock-names = "se";
1001                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1002                                 pinctrl-names = "default";
1003                                 pinctrl-0 = <&qup_i2c2_default>;
1004                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1005                                 #address-cells = <1>;
1006                                 #size-cells = <0>;
1007                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1009                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1010                                 interconnect-names = "qup-core", "qup-config",
1011                                                         "qup-memory";
1012                                 power-domains = <&rpmhpd SC7180_CX>;
1013                                 required-opps = <&rpmhpd_opp_low_svs>;
1014                                 status = "disabled";
1015                         };
1016
1017                         uart2: serial@888000 {
1018                                 compatible = "qcom,geni-uart";
1019                                 reg = <0 0x00888000 0 0x4000>;
1020                                 clock-names = "se";
1021                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1022                                 pinctrl-names = "default";
1023                                 pinctrl-0 = <&qup_uart2_default>;
1024                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025                                 power-domains = <&rpmhpd SC7180_CX>;
1026                                 operating-points-v2 = <&qup_opp_table>;
1027                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1028                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1029                                 interconnect-names = "qup-core", "qup-config";
1030                                 status = "disabled";
1031                         };
1032
1033                         i2c3: i2c@88c000 {
1034                                 compatible = "qcom,geni-i2c";
1035                                 reg = <0 0x0088c000 0 0x4000>;
1036                                 clock-names = "se";
1037                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1038                                 pinctrl-names = "default";
1039                                 pinctrl-0 = <&qup_i2c3_default>;
1040                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1041                                 #address-cells = <1>;
1042                                 #size-cells = <0>;
1043                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1044                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1045                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1046                                 interconnect-names = "qup-core", "qup-config",
1047                                                         "qup-memory";
1048                                 power-domains = <&rpmhpd SC7180_CX>;
1049                                 required-opps = <&rpmhpd_opp_low_svs>;
1050                                 status = "disabled";
1051                         };
1052
1053                         spi3: spi@88c000 {
1054                                 compatible = "qcom,geni-spi";
1055                                 reg = <0 0x0088c000 0 0x4000>;
1056                                 clock-names = "se";
1057                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1058                                 pinctrl-names = "default";
1059                                 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1060                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063                                 power-domains = <&rpmhpd SC7180_CX>;
1064                                 operating-points-v2 = <&qup_opp_table>;
1065                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1067                                 interconnect-names = "qup-core", "qup-config";
1068                                 status = "disabled";
1069                         };
1070
1071                         uart3: serial@88c000 {
1072                                 compatible = "qcom,geni-uart";
1073                                 reg = <0 0x0088c000 0 0x4000>;
1074                                 clock-names = "se";
1075                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1076                                 pinctrl-names = "default";
1077                                 pinctrl-0 = <&qup_uart3_default>;
1078                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1079                                 power-domains = <&rpmhpd SC7180_CX>;
1080                                 operating-points-v2 = <&qup_opp_table>;
1081                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1082                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1083                                 interconnect-names = "qup-core", "qup-config";
1084                                 status = "disabled";
1085                         };
1086
1087                         i2c4: i2c@890000 {
1088                                 compatible = "qcom,geni-i2c";
1089                                 reg = <0 0x00890000 0 0x4000>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1092                                 pinctrl-names = "default";
1093                                 pinctrl-0 = <&qup_i2c4_default>;
1094                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1098                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1099                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1100                                 interconnect-names = "qup-core", "qup-config",
1101                                                         "qup-memory";
1102                                 power-domains = <&rpmhpd SC7180_CX>;
1103                                 required-opps = <&rpmhpd_opp_low_svs>;
1104                                 status = "disabled";
1105                         };
1106
1107                         uart4: serial@890000 {
1108                                 compatible = "qcom,geni-uart";
1109                                 reg = <0 0x00890000 0 0x4000>;
1110                                 clock-names = "se";
1111                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1112                                 pinctrl-names = "default";
1113                                 pinctrl-0 = <&qup_uart4_default>;
1114                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1115                                 power-domains = <&rpmhpd SC7180_CX>;
1116                                 operating-points-v2 = <&qup_opp_table>;
1117                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1119                                 interconnect-names = "qup-core", "qup-config";
1120                                 status = "disabled";
1121                         };
1122
1123                         i2c5: i2c@894000 {
1124                                 compatible = "qcom,geni-i2c";
1125                                 reg = <0 0x00894000 0 0x4000>;
1126                                 clock-names = "se";
1127                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1128                                 pinctrl-names = "default";
1129                                 pinctrl-0 = <&qup_i2c5_default>;
1130                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1131                                 #address-cells = <1>;
1132                                 #size-cells = <0>;
1133                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1134                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1135                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1136                                 interconnect-names = "qup-core", "qup-config",
1137                                                         "qup-memory";
1138                                 power-domains = <&rpmhpd SC7180_CX>;
1139                                 required-opps = <&rpmhpd_opp_low_svs>;
1140                                 status = "disabled";
1141                         };
1142
1143                         spi5: spi@894000 {
1144                                 compatible = "qcom,geni-spi";
1145                                 reg = <0 0x00894000 0 0x4000>;
1146                                 clock-names = "se";
1147                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1148                                 pinctrl-names = "default";
1149                                 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1150                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1151                                 #address-cells = <1>;
1152                                 #size-cells = <0>;
1153                                 power-domains = <&rpmhpd SC7180_CX>;
1154                                 operating-points-v2 = <&qup_opp_table>;
1155                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1156                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1157                                 interconnect-names = "qup-core", "qup-config";
1158                                 status = "disabled";
1159                         };
1160
1161                         uart5: serial@894000 {
1162                                 compatible = "qcom,geni-uart";
1163                                 reg = <0 0x00894000 0 0x4000>;
1164                                 clock-names = "se";
1165                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1166                                 pinctrl-names = "default";
1167                                 pinctrl-0 = <&qup_uart5_default>;
1168                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1169                                 power-domains = <&rpmhpd SC7180_CX>;
1170                                 operating-points-v2 = <&qup_opp_table>;
1171                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1172                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1173                                 interconnect-names = "qup-core", "qup-config";
1174                                 status = "disabled";
1175                         };
1176                 };
1177
1178                 qupv3_id_1: geniqup@ac0000 {
1179                         compatible = "qcom,geni-se-qup";
1180                         reg = <0 0x00ac0000 0 0x6000>;
1181                         clock-names = "m-ahb", "s-ahb";
1182                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1183                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1184                         #address-cells = <2>;
1185                         #size-cells = <2>;
1186                         ranges;
1187                         iommus = <&apps_smmu 0x4c3 0x0>;
1188                         status = "disabled";
1189
1190                         i2c6: i2c@a80000 {
1191                                 compatible = "qcom,geni-i2c";
1192                                 reg = <0 0x00a80000 0 0x4000>;
1193                                 clock-names = "se";
1194                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1195                                 pinctrl-names = "default";
1196                                 pinctrl-0 = <&qup_i2c6_default>;
1197                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1198                                 #address-cells = <1>;
1199                                 #size-cells = <0>;
1200                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1202                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1203                                 interconnect-names = "qup-core", "qup-config",
1204                                                         "qup-memory";
1205                                 power-domains = <&rpmhpd SC7180_CX>;
1206                                 required-opps = <&rpmhpd_opp_low_svs>;
1207                                 status = "disabled";
1208                         };
1209
1210                         spi6: spi@a80000 {
1211                                 compatible = "qcom,geni-spi";
1212                                 reg = <0 0x00a80000 0 0x4000>;
1213                                 clock-names = "se";
1214                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1215                                 pinctrl-names = "default";
1216                                 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1217                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1218                                 #address-cells = <1>;
1219                                 #size-cells = <0>;
1220                                 power-domains = <&rpmhpd SC7180_CX>;
1221                                 operating-points-v2 = <&qup_opp_table>;
1222                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1223                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1224                                 interconnect-names = "qup-core", "qup-config";
1225                                 status = "disabled";
1226                         };
1227
1228                         uart6: serial@a80000 {
1229                                 compatible = "qcom,geni-uart";
1230                                 reg = <0 0x00a80000 0 0x4000>;
1231                                 clock-names = "se";
1232                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1233                                 pinctrl-names = "default";
1234                                 pinctrl-0 = <&qup_uart6_default>;
1235                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1236                                 power-domains = <&rpmhpd SC7180_CX>;
1237                                 operating-points-v2 = <&qup_opp_table>;
1238                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1240                                 interconnect-names = "qup-core", "qup-config";
1241                                 status = "disabled";
1242                         };
1243
1244                         i2c7: i2c@a84000 {
1245                                 compatible = "qcom,geni-i2c";
1246                                 reg = <0 0x00a84000 0 0x4000>;
1247                                 clock-names = "se";
1248                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1249                                 pinctrl-names = "default";
1250                                 pinctrl-0 = <&qup_i2c7_default>;
1251                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1252                                 #address-cells = <1>;
1253                                 #size-cells = <0>;
1254                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1256                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1257                                 interconnect-names = "qup-core", "qup-config",
1258                                                         "qup-memory";
1259                                 power-domains = <&rpmhpd SC7180_CX>;
1260                                 required-opps = <&rpmhpd_opp_low_svs>;
1261                                 status = "disabled";
1262                         };
1263
1264                         uart7: serial@a84000 {
1265                                 compatible = "qcom,geni-uart";
1266                                 reg = <0 0x00a84000 0 0x4000>;
1267                                 clock-names = "se";
1268                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1269                                 pinctrl-names = "default";
1270                                 pinctrl-0 = <&qup_uart7_default>;
1271                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1272                                 power-domains = <&rpmhpd SC7180_CX>;
1273                                 operating-points-v2 = <&qup_opp_table>;
1274                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1275                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1276                                 interconnect-names = "qup-core", "qup-config";
1277                                 status = "disabled";
1278                         };
1279
1280                         i2c8: i2c@a88000 {
1281                                 compatible = "qcom,geni-i2c";
1282                                 reg = <0 0x00a88000 0 0x4000>;
1283                                 clock-names = "se";
1284                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1285                                 pinctrl-names = "default";
1286                                 pinctrl-0 = <&qup_i2c8_default>;
1287                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1288                                 #address-cells = <1>;
1289                                 #size-cells = <0>;
1290                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1291                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1292                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1293                                 interconnect-names = "qup-core", "qup-config",
1294                                                         "qup-memory";
1295                                 power-domains = <&rpmhpd SC7180_CX>;
1296                                 required-opps = <&rpmhpd_opp_low_svs>;
1297                                 status = "disabled";
1298                         };
1299
1300                         spi8: spi@a88000 {
1301                                 compatible = "qcom,geni-spi";
1302                                 reg = <0 0x00a88000 0 0x4000>;
1303                                 clock-names = "se";
1304                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1305                                 pinctrl-names = "default";
1306                                 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1307                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1308                                 #address-cells = <1>;
1309                                 #size-cells = <0>;
1310                                 power-domains = <&rpmhpd SC7180_CX>;
1311                                 operating-points-v2 = <&qup_opp_table>;
1312                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1313                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1314                                 interconnect-names = "qup-core", "qup-config";
1315                                 status = "disabled";
1316                         };
1317
1318                         uart8: serial@a88000 {
1319                                 compatible = "qcom,geni-debug-uart";
1320                                 reg = <0 0x00a88000 0 0x4000>;
1321                                 clock-names = "se";
1322                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1323                                 pinctrl-names = "default";
1324                                 pinctrl-0 = <&qup_uart8_default>;
1325                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1326                                 power-domains = <&rpmhpd SC7180_CX>;
1327                                 operating-points-v2 = <&qup_opp_table>;
1328                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1329                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1330                                 interconnect-names = "qup-core", "qup-config";
1331                                 status = "disabled";
1332                         };
1333
1334                         i2c9: i2c@a8c000 {
1335                                 compatible = "qcom,geni-i2c";
1336                                 reg = <0 0x00a8c000 0 0x4000>;
1337                                 clock-names = "se";
1338                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1339                                 pinctrl-names = "default";
1340                                 pinctrl-0 = <&qup_i2c9_default>;
1341                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1342                                 #address-cells = <1>;
1343                                 #size-cells = <0>;
1344                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1345                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1346                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347                                 interconnect-names = "qup-core", "qup-config",
1348                                                         "qup-memory";
1349                                 power-domains = <&rpmhpd SC7180_CX>;
1350                                 required-opps = <&rpmhpd_opp_low_svs>;
1351                                 status = "disabled";
1352                         };
1353
1354                         uart9: serial@a8c000 {
1355                                 compatible = "qcom,geni-uart";
1356                                 reg = <0 0x00a8c000 0 0x4000>;
1357                                 clock-names = "se";
1358                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1359                                 pinctrl-names = "default";
1360                                 pinctrl-0 = <&qup_uart9_default>;
1361                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362                                 power-domains = <&rpmhpd SC7180_CX>;
1363                                 operating-points-v2 = <&qup_opp_table>;
1364                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1366                                 interconnect-names = "qup-core", "qup-config";
1367                                 status = "disabled";
1368                         };
1369
1370                         i2c10: i2c@a90000 {
1371                                 compatible = "qcom,geni-i2c";
1372                                 reg = <0 0x00a90000 0 0x4000>;
1373                                 clock-names = "se";
1374                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1375                                 pinctrl-names = "default";
1376                                 pinctrl-0 = <&qup_i2c10_default>;
1377                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1378                                 #address-cells = <1>;
1379                                 #size-cells = <0>;
1380                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1381                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1382                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1383                                 interconnect-names = "qup-core", "qup-config",
1384                                                         "qup-memory";
1385                                 power-domains = <&rpmhpd SC7180_CX>;
1386                                 required-opps = <&rpmhpd_opp_low_svs>;
1387                                 status = "disabled";
1388                         };
1389
1390                         spi10: spi@a90000 {
1391                                 compatible = "qcom,geni-spi";
1392                                 reg = <0 0x00a90000 0 0x4000>;
1393                                 clock-names = "se";
1394                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1395                                 pinctrl-names = "default";
1396                                 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1397                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1398                                 #address-cells = <1>;
1399                                 #size-cells = <0>;
1400                                 power-domains = <&rpmhpd SC7180_CX>;
1401                                 operating-points-v2 = <&qup_opp_table>;
1402                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1403                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1404                                 interconnect-names = "qup-core", "qup-config";
1405                                 status = "disabled";
1406                         };
1407
1408                         uart10: serial@a90000 {
1409                                 compatible = "qcom,geni-uart";
1410                                 reg = <0 0x00a90000 0 0x4000>;
1411                                 clock-names = "se";
1412                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1413                                 pinctrl-names = "default";
1414                                 pinctrl-0 = <&qup_uart10_default>;
1415                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1416                                 power-domains = <&rpmhpd SC7180_CX>;
1417                                 operating-points-v2 = <&qup_opp_table>;
1418                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1419                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1420                                 interconnect-names = "qup-core", "qup-config";
1421                                 status = "disabled";
1422                         };
1423
1424                         i2c11: i2c@a94000 {
1425                                 compatible = "qcom,geni-i2c";
1426                                 reg = <0 0x00a94000 0 0x4000>;
1427                                 clock-names = "se";
1428                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1429                                 pinctrl-names = "default";
1430                                 pinctrl-0 = <&qup_i2c11_default>;
1431                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1432                                 #address-cells = <1>;
1433                                 #size-cells = <0>;
1434                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1435                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1436                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1437                                 interconnect-names = "qup-core", "qup-config",
1438                                                         "qup-memory";
1439                                 power-domains = <&rpmhpd SC7180_CX>;
1440                                 required-opps = <&rpmhpd_opp_low_svs>;
1441                                 status = "disabled";
1442                         };
1443
1444                         spi11: spi@a94000 {
1445                                 compatible = "qcom,geni-spi";
1446                                 reg = <0 0x00a94000 0 0x4000>;
1447                                 clock-names = "se";
1448                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1449                                 pinctrl-names = "default";
1450                                 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1451                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1452                                 #address-cells = <1>;
1453                                 #size-cells = <0>;
1454                                 power-domains = <&rpmhpd SC7180_CX>;
1455                                 operating-points-v2 = <&qup_opp_table>;
1456                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1457                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1458                                 interconnect-names = "qup-core", "qup-config";
1459                                 status = "disabled";
1460                         };
1461
1462                         uart11: serial@a94000 {
1463                                 compatible = "qcom,geni-uart";
1464                                 reg = <0 0x00a94000 0 0x4000>;
1465                                 clock-names = "se";
1466                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1467                                 pinctrl-names = "default";
1468                                 pinctrl-0 = <&qup_uart11_default>;
1469                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1470                                 power-domains = <&rpmhpd SC7180_CX>;
1471                                 operating-points-v2 = <&qup_opp_table>;
1472                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1473                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1474                                 interconnect-names = "qup-core", "qup-config";
1475                                 status = "disabled";
1476                         };
1477                 };
1478
1479                 config_noc: interconnect@1500000 {
1480                         compatible = "qcom,sc7180-config-noc";
1481                         reg = <0 0x01500000 0 0x28000>;
1482                         #interconnect-cells = <2>;
1483                         qcom,bcm-voters = <&apps_bcm_voter>;
1484                 };
1485
1486                 system_noc: interconnect@1620000 {
1487                         compatible = "qcom,sc7180-system-noc";
1488                         reg = <0 0x01620000 0 0x17080>;
1489                         #interconnect-cells = <2>;
1490                         qcom,bcm-voters = <&apps_bcm_voter>;
1491                 };
1492
1493                 mc_virt: interconnect@1638000 {
1494                         compatible = "qcom,sc7180-mc-virt";
1495                         reg = <0 0x01638000 0 0x1000>;
1496                         #interconnect-cells = <2>;
1497                         qcom,bcm-voters = <&apps_bcm_voter>;
1498                 };
1499
1500                 qup_virt: interconnect@1650000 {
1501                         compatible = "qcom,sc7180-qup-virt";
1502                         reg = <0 0x01650000 0 0x1000>;
1503                         #interconnect-cells = <2>;
1504                         qcom,bcm-voters = <&apps_bcm_voter>;
1505                 };
1506
1507                 aggre1_noc: interconnect@16e0000 {
1508                         compatible = "qcom,sc7180-aggre1-noc";
1509                         reg = <0 0x016e0000 0 0x15080>;
1510                         #interconnect-cells = <2>;
1511                         qcom,bcm-voters = <&apps_bcm_voter>;
1512                 };
1513
1514                 aggre2_noc: interconnect@1705000 {
1515                         compatible = "qcom,sc7180-aggre2-noc";
1516                         reg = <0 0x01705000 0 0x9000>;
1517                         #interconnect-cells = <2>;
1518                         qcom,bcm-voters = <&apps_bcm_voter>;
1519                 };
1520
1521                 compute_noc: interconnect@170e000 {
1522                         compatible = "qcom,sc7180-compute-noc";
1523                         reg = <0 0x0170e000 0 0x6000>;
1524                         #interconnect-cells = <2>;
1525                         qcom,bcm-voters = <&apps_bcm_voter>;
1526                 };
1527
1528                 mmss_noc: interconnect@1740000 {
1529                         compatible = "qcom,sc7180-mmss-noc";
1530                         reg = <0 0x01740000 0 0x1c100>;
1531                         #interconnect-cells = <2>;
1532                         qcom,bcm-voters = <&apps_bcm_voter>;
1533                 };
1534
1535                 ipa: ipa@1e40000 {
1536                         compatible = "qcom,sc7180-ipa";
1537
1538                         iommus = <&apps_smmu 0x440 0x0>,
1539                                  <&apps_smmu 0x442 0x0>;
1540                         reg = <0 0x01e40000 0 0x7000>,
1541                               <0 0x01e47000 0 0x2000>,
1542                               <0 0x01e04000 0 0x2c000>;
1543                         reg-names = "ipa-reg",
1544                                     "ipa-shared",
1545                                     "gsi";
1546
1547                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1548                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1549                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1550                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1551                         interrupt-names = "ipa",
1552                                           "gsi",
1553                                           "ipa-clock-query",
1554                                           "ipa-setup-ready";
1555
1556                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1557                         clock-names = "core";
1558
1559                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1560                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1561                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1562                         interconnect-names = "memory",
1563                                              "imem",
1564                                              "config";
1565
1566                         qcom,qmp = <&aoss_qmp>;
1567
1568                         qcom,smem-states = <&ipa_smp2p_out 0>,
1569                                            <&ipa_smp2p_out 1>;
1570                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1571                                                 "ipa-clock-enabled";
1572
1573                         status = "disabled";
1574                 };
1575
1576                 tcsr_mutex: hwlock@1f40000 {
1577                         compatible = "qcom,tcsr-mutex";
1578                         reg = <0 0x01f40000 0 0x20000>;
1579                         #hwlock-cells = <1>;
1580                 };
1581
1582                 tcsr_regs_1: syscon@1f60000 {
1583                         compatible = "qcom,sc7180-tcsr", "syscon";
1584                         reg = <0 0x01f60000 0 0x20000>;
1585                 };
1586
1587                 tcsr_regs_2: syscon@1fc0000 {
1588                         compatible = "qcom,sc7180-tcsr", "syscon";
1589                         reg = <0 0x01fc0000 0 0x40000>;
1590                 };
1591
1592                 tlmm: pinctrl@3500000 {
1593                         compatible = "qcom,sc7180-pinctrl";
1594                         reg = <0 0x03500000 0 0x300000>,
1595                               <0 0x03900000 0 0x300000>,
1596                               <0 0x03d00000 0 0x300000>;
1597                         reg-names = "west", "north", "south";
1598                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1599                         gpio-controller;
1600                         #gpio-cells = <2>;
1601                         interrupt-controller;
1602                         #interrupt-cells = <2>;
1603                         gpio-ranges = <&tlmm 0 0 120>;
1604                         wakeup-parent = <&pdc>;
1605
1606                         dp_hot_plug_det: dp-hot-plug-det-state {
1607                                 pins = "gpio117";
1608                                 function = "dp_hot";
1609                         };
1610
1611                         qspi_clk: qspi-clk-state {
1612                                 pins = "gpio63";
1613                                 function = "qspi_clk";
1614                         };
1615
1616                         qspi_cs0: qspi-cs0-state {
1617                                 pins = "gpio68";
1618                                 function = "qspi_cs";
1619                         };
1620
1621                         qspi_cs1: qspi-cs1-state {
1622                                 pins = "gpio72";
1623                                 function = "qspi_cs";
1624                         };
1625
1626                         qspi_data0: qspi-data0-state {
1627                                 pins = "gpio64";
1628                                 function = "qspi_data";
1629                         };
1630
1631                         qspi_data1: qspi-data1-state {
1632                                 pins = "gpio65";
1633                                 function = "qspi_data";
1634                         };
1635
1636                         qspi_data23: qspi-data23-state {
1637                                 pins = "gpio66", "gpio67";
1638                                 function = "qspi_data";
1639                         };
1640
1641                         qup_i2c0_default: qup-i2c0-default-state {
1642                                 pins = "gpio34", "gpio35";
1643                                 function = "qup00";
1644                         };
1645
1646                         qup_i2c1_default: qup-i2c1-default-state {
1647                                 pins = "gpio0", "gpio1";
1648                                 function = "qup01";
1649                         };
1650
1651                         qup_i2c2_default: qup-i2c2-default-state {
1652                                 pins = "gpio15", "gpio16";
1653                                 function = "qup02_i2c";
1654                         };
1655
1656                         qup_i2c3_default: qup-i2c3-default-state {
1657                                 pins = "gpio38", "gpio39";
1658                                 function = "qup03";
1659                         };
1660
1661                         qup_i2c4_default: qup-i2c4-default-state {
1662                                 pins = "gpio115", "gpio116";
1663                                 function = "qup04_i2c";
1664                         };
1665
1666                         qup_i2c5_default: qup-i2c5-default-state {
1667                                 pins = "gpio25", "gpio26";
1668                                 function = "qup05";
1669                         };
1670
1671                         qup_i2c6_default: qup-i2c6-default-state {
1672                                 pins = "gpio59", "gpio60";
1673                                 function = "qup10";
1674                         };
1675
1676                         qup_i2c7_default: qup-i2c7-default-state {
1677                                 pins = "gpio6", "gpio7";
1678                                 function = "qup11_i2c";
1679                         };
1680
1681                         qup_i2c8_default: qup-i2c8-default-state {
1682                                 pins = "gpio42", "gpio43";
1683                                 function = "qup12";
1684                         };
1685
1686                         qup_i2c9_default: qup-i2c9-default-state {
1687                                 pins = "gpio46", "gpio47";
1688                                 function = "qup13_i2c";
1689                         };
1690
1691                         qup_i2c10_default: qup-i2c10-default-state {
1692                                 pins = "gpio86", "gpio87";
1693                                 function = "qup14";
1694                         };
1695
1696                         qup_i2c11_default: qup-i2c11-default-state {
1697                                 pins = "gpio53", "gpio54";
1698                                 function = "qup15";
1699                         };
1700
1701                         qup_spi0_spi: qup-spi0-spi-state {
1702                                 pins = "gpio34", "gpio35", "gpio36";
1703                                 function = "qup00";
1704                         };
1705
1706                         qup_spi0_cs: qup-spi0-cs-state {
1707                                 pins = "gpio37";
1708                                 function = "qup00";
1709                         };
1710
1711                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1712                                 pins = "gpio37";
1713                                 function = "gpio";
1714                         };
1715
1716                         qup_spi1_spi: qup-spi1-spi-state {
1717                                 pins = "gpio0", "gpio1", "gpio2";
1718                                 function = "qup01";
1719                         };
1720
1721                         qup_spi1_cs: qup-spi1-cs-state {
1722                                 pins = "gpio3";
1723                                 function = "qup01";
1724                         };
1725
1726                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1727                                 pins = "gpio3";
1728                                 function = "gpio";
1729                         };
1730
1731                         qup_spi3_spi: qup-spi3-spi-state {
1732                                 pins = "gpio38", "gpio39", "gpio40";
1733                                 function = "qup03";
1734                         };
1735
1736                         qup_spi3_cs: qup-spi3-cs-state {
1737                                 pins = "gpio41";
1738                                 function = "qup03";
1739                         };
1740
1741                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1742                                 pins = "gpio41";
1743                                 function = "gpio";
1744                         };
1745
1746                         qup_spi5_spi: qup-spi5-spi-state {
1747                                 pins = "gpio25", "gpio26", "gpio27";
1748                                 function = "qup05";
1749                         };
1750
1751                         qup_spi5_cs: qup-spi5-cs-state {
1752                                 pins = "gpio28";
1753                                 function = "qup05";
1754                         };
1755
1756                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1757                                 pins = "gpio28";
1758                                 function = "gpio";
1759                         };
1760
1761                         qup_spi6_spi: qup-spi6-spi-state {
1762                                 pins = "gpio59", "gpio60", "gpio61";
1763                                 function = "qup10";
1764                         };
1765
1766                         qup_spi6_cs: qup-spi6-cs-state {
1767                                 pins = "gpio62";
1768                                 function = "qup10";
1769                         };
1770
1771                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1772                                 pins = "gpio62";
1773                                 function = "gpio";
1774                         };
1775
1776                         qup_spi8_spi: qup-spi8-spi-state {
1777                                 pins = "gpio42", "gpio43", "gpio44";
1778                                 function = "qup12";
1779                         };
1780
1781                         qup_spi8_cs: qup-spi8-cs-state {
1782                                 pins = "gpio45";
1783                                 function = "qup12";
1784                         };
1785
1786                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1787                                 pins = "gpio45";
1788                                 function = "gpio";
1789                         };
1790
1791                         qup_spi10_spi: qup-spi10-spi-state {
1792                                 pins = "gpio86", "gpio87", "gpio88";
1793                                 function = "qup14";
1794                         };
1795
1796                         qup_spi10_cs: qup-spi10-cs-state {
1797                                 pins = "gpio89";
1798                                 function = "qup14";
1799                         };
1800
1801                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1802                                 pins = "gpio89";
1803                                 function = "gpio";
1804                         };
1805
1806                         qup_spi11_spi: qup-spi11-spi-state {
1807                                 pins = "gpio53", "gpio54", "gpio55";
1808                                 function = "qup15";
1809                         };
1810
1811                         qup_spi11_cs: qup-spi11-cs-state {
1812                                 pins = "gpio56";
1813                                 function = "qup15";
1814                         };
1815
1816                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1817                                 pins = "gpio56";
1818                                 function = "gpio";
1819                         };
1820
1821                         qup_uart0_default: qup-uart0-default-state {
1822                                 qup_uart0_cts: cts-pins {
1823                                         pins = "gpio34";
1824                                         function = "qup00";
1825                                 };
1826
1827                                 qup_uart0_rts: rts-pins {
1828                                         pins = "gpio35";
1829                                         function = "qup00";
1830                                 };
1831
1832                                 qup_uart0_tx: tx-pins {
1833                                         pins = "gpio36";
1834                                         function = "qup00";
1835                                 };
1836
1837                                 qup_uart0_rx: rx-pins {
1838                                         pins = "gpio37";
1839                                         function = "qup00";
1840                                 };
1841                         };
1842
1843                         qup_uart1_default: qup-uart1-default-state {
1844                                 qup_uart1_cts: cts-pins {
1845                                         pins = "gpio0";
1846                                         function = "qup01";
1847                                 };
1848
1849                                 qup_uart1_rts: rts-pins {
1850                                         pins = "gpio1";
1851                                         function = "qup01";
1852                                 };
1853
1854                                 qup_uart1_tx: tx-pins {
1855                                         pins = "gpio2";
1856                                         function = "qup01";
1857                                 };
1858
1859                                 qup_uart1_rx: rx-pins {
1860                                         pins = "gpio3";
1861                                         function = "qup01";
1862                                 };
1863                         };
1864
1865                         qup_uart2_default: qup-uart2-default-state {
1866                                 qup_uart2_tx: tx-pins {
1867                                         pins = "gpio15";
1868                                         function = "qup02_uart";
1869                                 };
1870
1871                                 qup_uart2_rx: rx-pins {
1872                                         pins = "gpio16";
1873                                         function = "qup02_uart";
1874                                 };
1875                         };
1876
1877                         qup_uart3_default: qup-uart3-default-state {
1878                                 qup_uart3_cts: cts-pins {
1879                                         pins = "gpio38";
1880                                         function = "qup03";
1881                                 };
1882
1883                                 qup_uart3_rts: rts-pins {
1884                                         pins = "gpio39";
1885                                         function = "qup03";
1886                                 };
1887
1888                                 qup_uart3_tx: tx-pins {
1889                                         pins = "gpio40";
1890                                         function = "qup03";
1891                                 };
1892
1893                                 qup_uart3_rx: rx-pins {
1894                                         pins = "gpio41";
1895                                         function = "qup03";
1896                                 };
1897                         };
1898
1899                         qup_uart4_default: qup-uart4-default-state {
1900                                 qup_uart4_tx: tx-pins {
1901                                         pins = "gpio115";
1902                                         function = "qup04_uart";
1903                                 };
1904
1905                                 qup_uart4_rx: rx-pins {
1906                                         pins = "gpio116";
1907                                         function = "qup04_uart";
1908                                 };
1909                         };
1910
1911                         qup_uart5_default: qup-uart5-default-state {
1912                                 qup_uart5_cts: cts-pins {
1913                                         pins = "gpio25";
1914                                         function = "qup05";
1915                                 };
1916
1917                                 qup_uart5_rts: rts-pins {
1918                                         pins = "gpio26";
1919                                         function = "qup05";
1920                                 };
1921
1922                                 qup_uart5_tx: tx-pins {
1923                                         pins = "gpio27";
1924                                         function = "qup05";
1925                                 };
1926
1927                                 qup_uart5_rx: rx-pins {
1928                                         pins = "gpio28";
1929                                         function = "qup05";
1930                                 };
1931                         };
1932
1933                         qup_uart6_default: qup-uart6-default-state {
1934                                 qup_uart6_cts: cts-pins {
1935                                         pins = "gpio59";
1936                                         function = "qup10";
1937                                 };
1938
1939                                 qup_uart6_rts: rts-pins {
1940                                         pins = "gpio60";
1941                                         function = "qup10";
1942                                 };
1943
1944                                 qup_uart6_tx: tx-pins {
1945                                         pins = "gpio61";
1946                                         function = "qup10";
1947                                 };
1948
1949                                 qup_uart6_rx: rx-pins {
1950                                         pins = "gpio62";
1951                                         function = "qup10";
1952                                 };
1953                         };
1954
1955                         qup_uart7_default: qup-uart7-default-state {
1956                                 qup_uart7_tx: tx-pins {
1957                                         pins = "gpio6";
1958                                         function = "qup11_uart";
1959                                 };
1960
1961                                 qup_uart7_rx: rx-pins {
1962                                         pins = "gpio7";
1963                                         function = "qup11_uart";
1964                                 };
1965                         };
1966
1967                         qup_uart8_default: qup-uart8-default-state {
1968                                 qup_uart8_tx: tx-pins {
1969                                         pins = "gpio44";
1970                                         function = "qup12";
1971                                 };
1972
1973                                 qup_uart8_rx: rx-pins {
1974                                         pins = "gpio45";
1975                                         function = "qup12";
1976                                 };
1977                         };
1978
1979                         qup_uart9_default: qup-uart9-default-state {
1980                                 qup_uart9_tx: tx-pins {
1981                                         pins = "gpio46";
1982                                         function = "qup13_uart";
1983                                 };
1984
1985                                 qup_uart9_rx: rx-pins {
1986                                         pins = "gpio47";
1987                                         function = "qup13_uart";
1988                                 };
1989                         };
1990
1991                         qup_uart10_default: qup-uart10-default-state {
1992                                 qup_uart10_cts: cts-pins {
1993                                         pins = "gpio86";
1994                                         function = "qup14";
1995                                 };
1996
1997                                 qup_uart10_rts: rts-pins {
1998                                         pins = "gpio87";
1999                                         function = "qup14";
2000                                 };
2001
2002                                 qup_uart10_tx: tx-pins {
2003                                         pins = "gpio88";
2004                                         function = "qup14";
2005                                 };
2006
2007                                 qup_uart10_rx: rx-pins {
2008                                         pins = "gpio89";
2009                                         function = "qup14";
2010                                 };
2011                         };
2012
2013                         qup_uart11_default: qup-uart11-default-state {
2014                                 qup_uart11_cts: cts-pins {
2015                                         pins = "gpio53";
2016                                         function = "qup15";
2017                                 };
2018
2019                                 qup_uart11_rts: rts-pins {
2020                                         pins = "gpio54";
2021                                         function = "qup15";
2022                                 };
2023
2024                                 qup_uart11_tx: tx-pins {
2025                                         pins = "gpio55";
2026                                         function = "qup15";
2027                                 };
2028
2029                                 qup_uart11_rx: rx-pins {
2030                                         pins = "gpio56";
2031                                         function = "qup15";
2032                                 };
2033                         };
2034
2035                         sec_mi2s_active: sec-mi2s-active-state {
2036                                 pins = "gpio49", "gpio50", "gpio51";
2037                                 function = "mi2s_1";
2038                         };
2039
2040                         pri_mi2s_active: pri-mi2s-active-state {
2041                                 pins = "gpio53", "gpio54", "gpio55", "gpio56";
2042                                 function = "mi2s_0";
2043                         };
2044
2045                         pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2046                                 pins = "gpio57";
2047                                 function = "lpass_ext";
2048                         };
2049
2050                         ter_mi2s_active: ter-mi2s-active-state {
2051                                 pins = "gpio63", "gpio64", "gpio65", "gpio66";
2052                                 function = "mi2s_2";
2053                         };
2054                 };
2055
2056                 remoteproc_mpss: remoteproc@4080000 {
2057                         compatible = "qcom,sc7180-mpss-pas";
2058                         reg = <0 0x04080000 0 0x4040>;
2059
2060                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2061                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2062                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2063                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2064                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2065                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2066                         interrupt-names = "wdog", "fatal", "ready", "handover",
2067                                           "stop-ack", "shutdown-ack";
2068
2069                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2070                         clock-names = "xo";
2071
2072                         power-domains = <&rpmhpd SC7180_CX>,
2073                                         <&rpmhpd SC7180_MX>,
2074                                         <&rpmhpd SC7180_MSS>;
2075                         power-domain-names = "cx", "mx", "mss";
2076
2077                         memory-region = <&mpss_mem>;
2078
2079                         qcom,qmp = <&aoss_qmp>;
2080
2081                         qcom,smem-states = <&modem_smp2p_out 0>;
2082                         qcom,smem-state-names = "stop";
2083
2084                         status = "disabled";
2085
2086                         glink-edge {
2087                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2088                                 label = "modem";
2089                                 qcom,remote-pid = <1>;
2090                                 mboxes = <&apss_shared 12>;
2091                         };
2092                 };
2093
2094                 gpu: gpu@5000000 {
2095                         compatible = "qcom,adreno-618.0", "qcom,adreno";
2096                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2097                                 <0 0x05061000 0 0x800>;
2098                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2099                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2100                         iommus = <&adreno_smmu 0>;
2101                         operating-points-v2 = <&gpu_opp_table>;
2102                         qcom,gmu = <&gmu>;
2103
2104                         #cooling-cells = <2>;
2105
2106                         nvmem-cells = <&gpu_speed_bin>;
2107                         nvmem-cell-names = "speed_bin";
2108
2109                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2110                         interconnect-names = "gfx-mem";
2111
2112                         gpu_opp_table: opp-table {
2113                                 compatible = "operating-points-v2";
2114
2115                                 opp-825000000 {
2116                                         opp-hz = /bits/ 64 <825000000>;
2117                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2118                                         opp-peak-kBps = <8532000>;
2119                                         opp-supported-hw = <0x04>;
2120                                 };
2121
2122                                 opp-800000000 {
2123                                         opp-hz = /bits/ 64 <800000000>;
2124                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2125                                         opp-peak-kBps = <8532000>;
2126                                         opp-supported-hw = <0x07>;
2127                                 };
2128
2129                                 opp-650000000 {
2130                                         opp-hz = /bits/ 64 <650000000>;
2131                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2132                                         opp-peak-kBps = <7216000>;
2133                                         opp-supported-hw = <0x07>;
2134                                 };
2135
2136                                 opp-565000000 {
2137                                         opp-hz = /bits/ 64 <565000000>;
2138                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2139                                         opp-peak-kBps = <5412000>;
2140                                         opp-supported-hw = <0x07>;
2141                                 };
2142
2143                                 opp-430000000 {
2144                                         opp-hz = /bits/ 64 <430000000>;
2145                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2146                                         opp-peak-kBps = <5412000>;
2147                                         opp-supported-hw = <0x07>;
2148                                 };
2149
2150                                 opp-355000000 {
2151                                         opp-hz = /bits/ 64 <355000000>;
2152                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2153                                         opp-peak-kBps = <3072000>;
2154                                         opp-supported-hw = <0x07>;
2155                                 };
2156
2157                                 opp-267000000 {
2158                                         opp-hz = /bits/ 64 <267000000>;
2159                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2160                                         opp-peak-kBps = <3072000>;
2161                                         opp-supported-hw = <0x07>;
2162                                 };
2163
2164                                 opp-180000000 {
2165                                         opp-hz = /bits/ 64 <180000000>;
2166                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2167                                         opp-peak-kBps = <1804000>;
2168                                         opp-supported-hw = <0x07>;
2169                                 };
2170                         };
2171                 };
2172
2173                 adreno_smmu: iommu@5040000 {
2174                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2175                         reg = <0 0x05040000 0 0x10000>;
2176                         #iommu-cells = <1>;
2177                         #global-interrupts = <2>;
2178                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2179                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2180                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2181                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2182                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2183                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2184                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2185                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2186                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2187                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2188
2189                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2190                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2191                         clock-names = "bus", "iface";
2192
2193                         power-domains = <&gpucc CX_GDSC>;
2194                 };
2195
2196                 gmu: gmu@506a000 {
2197                         compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2198                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2199                                 <0 0x0b490000 0 0x10000>;
2200                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2201                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2202                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2203                         interrupt-names = "hfi", "gmu";
2204                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2205                                <&gpucc GPU_CC_CXO_CLK>,
2206                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2207                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2208                         clock-names = "gmu", "cxo", "axi", "memnoc";
2209                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2210                         power-domain-names = "cx", "gx";
2211                         iommus = <&adreno_smmu 5>;
2212                         operating-points-v2 = <&gmu_opp_table>;
2213
2214                         gmu_opp_table: opp-table {
2215                                 compatible = "operating-points-v2";
2216
2217                                 opp-200000000 {
2218                                         opp-hz = /bits/ 64 <200000000>;
2219                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2220                                 };
2221                         };
2222                 };
2223
2224                 gpucc: clock-controller@5090000 {
2225                         compatible = "qcom,sc7180-gpucc";
2226                         reg = <0 0x05090000 0 0x9000>;
2227                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2228                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2229                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2230                         clock-names = "bi_tcxo",
2231                                       "gcc_gpu_gpll0_clk_src",
2232                                       "gcc_gpu_gpll0_div_clk_src";
2233                         #clock-cells = <1>;
2234                         #reset-cells = <1>;
2235                         #power-domain-cells = <1>;
2236                 };
2237
2238                 dma@10a2000 {
2239                         compatible = "qcom,sc7180-dcc", "qcom,dcc";
2240                         reg = <0x0 0x010a2000 0x0 0x1000>,
2241                               <0x0 0x010ae000 0x0 0x2000>;
2242                 };
2243
2244                 stm@6002000 {
2245                         compatible = "arm,coresight-stm", "arm,primecell";
2246                         reg = <0 0x06002000 0 0x1000>,
2247                               <0 0x16280000 0 0x180000>;
2248                         reg-names = "stm-base", "stm-stimulus-base";
2249
2250                         clocks = <&aoss_qmp>;
2251                         clock-names = "apb_pclk";
2252
2253                         out-ports {
2254                                 port {
2255                                         stm_out: endpoint {
2256                                                 remote-endpoint = <&funnel0_in7>;
2257                                         };
2258                                 };
2259                         };
2260                 };
2261
2262                 funnel@6041000 {
2263                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2264                         reg = <0 0x06041000 0 0x1000>;
2265
2266                         clocks = <&aoss_qmp>;
2267                         clock-names = "apb_pclk";
2268
2269                         out-ports {
2270                                 port {
2271                                         funnel0_out: endpoint {
2272                                                 remote-endpoint = <&merge_funnel_in0>;
2273                                         };
2274                                 };
2275                         };
2276
2277                         in-ports {
2278                                 #address-cells = <1>;
2279                                 #size-cells = <0>;
2280
2281                                 port@7 {
2282                                         reg = <7>;
2283                                         funnel0_in7: endpoint {
2284                                                 remote-endpoint = <&stm_out>;
2285                                         };
2286                                 };
2287                         };
2288                 };
2289
2290                 funnel@6042000 {
2291                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2292                         reg = <0 0x06042000 0 0x1000>;
2293
2294                         clocks = <&aoss_qmp>;
2295                         clock-names = "apb_pclk";
2296
2297                         out-ports {
2298                                 port {
2299                                         funnel1_out: endpoint {
2300                                                 remote-endpoint = <&merge_funnel_in1>;
2301                                         };
2302                                 };
2303                         };
2304
2305                         in-ports {
2306                                 #address-cells = <1>;
2307                                 #size-cells = <0>;
2308
2309                                 port@4 {
2310                                         reg = <4>;
2311                                         funnel1_in4: endpoint {
2312                                                 remote-endpoint = <&apss_merge_funnel_out>;
2313                                         };
2314                                 };
2315                         };
2316                 };
2317
2318                 funnel@6045000 {
2319                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2320                         reg = <0 0x06045000 0 0x1000>;
2321
2322                         clocks = <&aoss_qmp>;
2323                         clock-names = "apb_pclk";
2324
2325                         out-ports {
2326                                 port {
2327                                         merge_funnel_out: endpoint {
2328                                                 remote-endpoint = <&swao_funnel_in>;
2329                                         };
2330                                 };
2331                         };
2332
2333                         in-ports {
2334                                 #address-cells = <1>;
2335                                 #size-cells = <0>;
2336
2337                                 port@0 {
2338                                         reg = <0>;
2339                                         merge_funnel_in0: endpoint {
2340                                                 remote-endpoint = <&funnel0_out>;
2341                                         };
2342                                 };
2343
2344                                 port@1 {
2345                                         reg = <1>;
2346                                         merge_funnel_in1: endpoint {
2347                                                 remote-endpoint = <&funnel1_out>;
2348                                         };
2349                                 };
2350                         };
2351                 };
2352
2353                 replicator@6046000 {
2354                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2355                         reg = <0 0x06046000 0 0x1000>;
2356
2357                         clocks = <&aoss_qmp>;
2358                         clock-names = "apb_pclk";
2359
2360                         out-ports {
2361                                 port {
2362                                         replicator_out: endpoint {
2363                                                 remote-endpoint = <&etr_in>;
2364                                         };
2365                                 };
2366                         };
2367
2368                         in-ports {
2369                                 port {
2370                                         replicator_in: endpoint {
2371                                                 remote-endpoint = <&swao_replicator_out>;
2372                                         };
2373                                 };
2374                         };
2375                 };
2376
2377                 etr@6048000 {
2378                         compatible = "arm,coresight-tmc", "arm,primecell";
2379                         reg = <0 0x06048000 0 0x1000>;
2380                         iommus = <&apps_smmu 0x04a0 0x20>;
2381
2382                         clocks = <&aoss_qmp>;
2383                         clock-names = "apb_pclk";
2384                         arm,scatter-gather;
2385
2386                         in-ports {
2387                                 port {
2388                                         etr_in: endpoint {
2389                                                 remote-endpoint = <&replicator_out>;
2390                                         };
2391                                 };
2392                         };
2393                 };
2394
2395                 funnel@6b04000 {
2396                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2397                         reg = <0 0x06b04000 0 0x1000>;
2398
2399                         clocks = <&aoss_qmp>;
2400                         clock-names = "apb_pclk";
2401
2402                         out-ports {
2403                                 port {
2404                                         swao_funnel_out: endpoint {
2405                                                 remote-endpoint = <&etf_in>;
2406                                         };
2407                                 };
2408                         };
2409
2410                         in-ports {
2411                                 #address-cells = <1>;
2412                                 #size-cells = <0>;
2413
2414                                 port@7 {
2415                                         reg = <7>;
2416                                         swao_funnel_in: endpoint {
2417                                                 remote-endpoint = <&merge_funnel_out>;
2418                                         };
2419                                 };
2420                         };
2421                 };
2422
2423                 etf@6b05000 {
2424                         compatible = "arm,coresight-tmc", "arm,primecell";
2425                         reg = <0 0x06b05000 0 0x1000>;
2426
2427                         clocks = <&aoss_qmp>;
2428                         clock-names = "apb_pclk";
2429
2430                         out-ports {
2431                                 port {
2432                                         etf_out: endpoint {
2433                                                 remote-endpoint = <&swao_replicator_in>;
2434                                         };
2435                                 };
2436                         };
2437
2438                         in-ports {
2439                                 port {
2440                                         etf_in: endpoint {
2441                                                 remote-endpoint = <&swao_funnel_out>;
2442                                         };
2443                                 };
2444                         };
2445                 };
2446
2447                 replicator@6b06000 {
2448                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2449                         reg = <0 0x06b06000 0 0x1000>;
2450
2451                         clocks = <&aoss_qmp>;
2452                         clock-names = "apb_pclk";
2453                         qcom,replicator-loses-context;
2454
2455                         out-ports {
2456                                 port {
2457                                         swao_replicator_out: endpoint {
2458                                                 remote-endpoint = <&replicator_in>;
2459                                         };
2460                                 };
2461                         };
2462
2463                         in-ports {
2464                                 port {
2465                                         swao_replicator_in: endpoint {
2466                                                 remote-endpoint = <&etf_out>;
2467                                         };
2468                                 };
2469                         };
2470                 };
2471
2472                 etm@7040000 {
2473                         compatible = "arm,coresight-etm4x", "arm,primecell";
2474                         reg = <0 0x07040000 0 0x1000>;
2475
2476                         cpu = <&CPU0>;
2477
2478                         clocks = <&aoss_qmp>;
2479                         clock-names = "apb_pclk";
2480                         arm,coresight-loses-context-with-cpu;
2481                         qcom,skip-power-up;
2482
2483                         out-ports {
2484                                 port {
2485                                         etm0_out: endpoint {
2486                                                 remote-endpoint = <&apss_funnel_in0>;
2487                                         };
2488                                 };
2489                         };
2490                 };
2491
2492                 etm@7140000 {
2493                         compatible = "arm,coresight-etm4x", "arm,primecell";
2494                         reg = <0 0x07140000 0 0x1000>;
2495
2496                         cpu = <&CPU1>;
2497
2498                         clocks = <&aoss_qmp>;
2499                         clock-names = "apb_pclk";
2500                         arm,coresight-loses-context-with-cpu;
2501                         qcom,skip-power-up;
2502
2503                         out-ports {
2504                                 port {
2505                                         etm1_out: endpoint {
2506                                                 remote-endpoint = <&apss_funnel_in1>;
2507                                         };
2508                                 };
2509                         };
2510                 };
2511
2512                 etm@7240000 {
2513                         compatible = "arm,coresight-etm4x", "arm,primecell";
2514                         reg = <0 0x07240000 0 0x1000>;
2515
2516                         cpu = <&CPU2>;
2517
2518                         clocks = <&aoss_qmp>;
2519                         clock-names = "apb_pclk";
2520                         arm,coresight-loses-context-with-cpu;
2521                         qcom,skip-power-up;
2522
2523                         out-ports {
2524                                 port {
2525                                         etm2_out: endpoint {
2526                                                 remote-endpoint = <&apss_funnel_in2>;
2527                                         };
2528                                 };
2529                         };
2530                 };
2531
2532                 etm@7340000 {
2533                         compatible = "arm,coresight-etm4x", "arm,primecell";
2534                         reg = <0 0x07340000 0 0x1000>;
2535
2536                         cpu = <&CPU3>;
2537
2538                         clocks = <&aoss_qmp>;
2539                         clock-names = "apb_pclk";
2540                         arm,coresight-loses-context-with-cpu;
2541                         qcom,skip-power-up;
2542
2543                         out-ports {
2544                                 port {
2545                                         etm3_out: endpoint {
2546                                                 remote-endpoint = <&apss_funnel_in3>;
2547                                         };
2548                                 };
2549                         };
2550                 };
2551
2552                 etm@7440000 {
2553                         compatible = "arm,coresight-etm4x", "arm,primecell";
2554                         reg = <0 0x07440000 0 0x1000>;
2555
2556                         cpu = <&CPU4>;
2557
2558                         clocks = <&aoss_qmp>;
2559                         clock-names = "apb_pclk";
2560                         arm,coresight-loses-context-with-cpu;
2561                         qcom,skip-power-up;
2562
2563                         out-ports {
2564                                 port {
2565                                         etm4_out: endpoint {
2566                                                 remote-endpoint = <&apss_funnel_in4>;
2567                                         };
2568                                 };
2569                         };
2570                 };
2571
2572                 etm@7540000 {
2573                         compatible = "arm,coresight-etm4x", "arm,primecell";
2574                         reg = <0 0x07540000 0 0x1000>;
2575
2576                         cpu = <&CPU5>;
2577
2578                         clocks = <&aoss_qmp>;
2579                         clock-names = "apb_pclk";
2580                         arm,coresight-loses-context-with-cpu;
2581                         qcom,skip-power-up;
2582
2583                         out-ports {
2584                                 port {
2585                                         etm5_out: endpoint {
2586                                                 remote-endpoint = <&apss_funnel_in5>;
2587                                         };
2588                                 };
2589                         };
2590                 };
2591
2592                 etm@7640000 {
2593                         compatible = "arm,coresight-etm4x", "arm,primecell";
2594                         reg = <0 0x07640000 0 0x1000>;
2595
2596                         cpu = <&CPU6>;
2597
2598                         clocks = <&aoss_qmp>;
2599                         clock-names = "apb_pclk";
2600                         arm,coresight-loses-context-with-cpu;
2601                         qcom,skip-power-up;
2602
2603                         out-ports {
2604                                 port {
2605                                         etm6_out: endpoint {
2606                                                 remote-endpoint = <&apss_funnel_in6>;
2607                                         };
2608                                 };
2609                         };
2610                 };
2611
2612                 etm@7740000 {
2613                         compatible = "arm,coresight-etm4x", "arm,primecell";
2614                         reg = <0 0x07740000 0 0x1000>;
2615
2616                         cpu = <&CPU7>;
2617
2618                         clocks = <&aoss_qmp>;
2619                         clock-names = "apb_pclk";
2620                         arm,coresight-loses-context-with-cpu;
2621                         qcom,skip-power-up;
2622
2623                         out-ports {
2624                                 port {
2625                                         etm7_out: endpoint {
2626                                                 remote-endpoint = <&apss_funnel_in7>;
2627                                         };
2628                                 };
2629                         };
2630                 };
2631
2632                 funnel@7800000 { /* APSS Funnel */
2633                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2634                         reg = <0 0x07800000 0 0x1000>;
2635
2636                         clocks = <&aoss_qmp>;
2637                         clock-names = "apb_pclk";
2638
2639                         out-ports {
2640                                 port {
2641                                         apss_funnel_out: endpoint {
2642                                                 remote-endpoint = <&apss_merge_funnel_in>;
2643                                         };
2644                                 };
2645                         };
2646
2647                         in-ports {
2648                                 #address-cells = <1>;
2649                                 #size-cells = <0>;
2650
2651                                 port@0 {
2652                                         reg = <0>;
2653                                         apss_funnel_in0: endpoint {
2654                                                 remote-endpoint = <&etm0_out>;
2655                                         };
2656                                 };
2657
2658                                 port@1 {
2659                                         reg = <1>;
2660                                         apss_funnel_in1: endpoint {
2661                                                 remote-endpoint = <&etm1_out>;
2662                                         };
2663                                 };
2664
2665                                 port@2 {
2666                                         reg = <2>;
2667                                         apss_funnel_in2: endpoint {
2668                                                 remote-endpoint = <&etm2_out>;
2669                                         };
2670                                 };
2671
2672                                 port@3 {
2673                                         reg = <3>;
2674                                         apss_funnel_in3: endpoint {
2675                                                 remote-endpoint = <&etm3_out>;
2676                                         };
2677                                 };
2678
2679                                 port@4 {
2680                                         reg = <4>;
2681                                         apss_funnel_in4: endpoint {
2682                                                 remote-endpoint = <&etm4_out>;
2683                                         };
2684                                 };
2685
2686                                 port@5 {
2687                                         reg = <5>;
2688                                         apss_funnel_in5: endpoint {
2689                                                 remote-endpoint = <&etm5_out>;
2690                                         };
2691                                 };
2692
2693                                 port@6 {
2694                                         reg = <6>;
2695                                         apss_funnel_in6: endpoint {
2696                                                 remote-endpoint = <&etm6_out>;
2697                                         };
2698                                 };
2699
2700                                 port@7 {
2701                                         reg = <7>;
2702                                         apss_funnel_in7: endpoint {
2703                                                 remote-endpoint = <&etm7_out>;
2704                                         };
2705                                 };
2706                         };
2707                 };
2708
2709                 funnel@7810000 {
2710                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2711                         reg = <0 0x07810000 0 0x1000>;
2712
2713                         clocks = <&aoss_qmp>;
2714                         clock-names = "apb_pclk";
2715
2716                         out-ports {
2717                                 port {
2718                                         apss_merge_funnel_out: endpoint {
2719                                                 remote-endpoint = <&funnel1_in4>;
2720                                         };
2721                                 };
2722                         };
2723
2724                         in-ports {
2725                                 port {
2726                                         apss_merge_funnel_in: endpoint {
2727                                                 remote-endpoint = <&apss_funnel_out>;
2728                                         };
2729                                 };
2730                         };
2731                 };
2732
2733                 sdhc_2: mmc@8804000 {
2734                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2735                         reg = <0 0x08804000 0 0x1000>;
2736
2737                         iommus = <&apps_smmu 0x80 0>;
2738                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2739                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2740                         interrupt-names = "hc_irq", "pwr_irq";
2741
2742                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2743                                  <&gcc GCC_SDCC2_APPS_CLK>,
2744                                  <&rpmhcc RPMH_CXO_CLK>;
2745                         clock-names = "iface", "core", "xo";
2746
2747                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2748                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2749                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2750                         power-domains = <&rpmhpd SC7180_CX>;
2751                         operating-points-v2 = <&sdhc2_opp_table>;
2752
2753                         bus-width = <4>;
2754
2755                         status = "disabled";
2756
2757                         sdhc2_opp_table: opp-table {
2758                                 compatible = "operating-points-v2";
2759
2760                                 opp-100000000 {
2761                                         opp-hz = /bits/ 64 <100000000>;
2762                                         required-opps = <&rpmhpd_opp_low_svs>;
2763                                         opp-peak-kBps = <1800000 600000>;
2764                                         opp-avg-kBps = <100000 0>;
2765                                 };
2766
2767                                 opp-202000000 {
2768                                         opp-hz = /bits/ 64 <202000000>;
2769                                         required-opps = <&rpmhpd_opp_nom>;
2770                                         opp-peak-kBps = <5400000 1600000>;
2771                                         opp-avg-kBps = <200000 0>;
2772                                 };
2773                         };
2774                 };
2775
2776                 qspi: spi@88dc000 {
2777                         compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2778                         reg = <0 0x088dc000 0 0x600>;
2779                         iommus = <&apps_smmu 0x20 0x0>;
2780                         #address-cells = <1>;
2781                         #size-cells = <0>;
2782                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2783                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2784                                  <&gcc GCC_QSPI_CORE_CLK>;
2785                         clock-names = "iface", "core";
2786                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2787                                         &config_noc SLAVE_QSPI_0 0>;
2788                         interconnect-names = "qspi-config";
2789                         power-domains = <&rpmhpd SC7180_CX>;
2790                         operating-points-v2 = <&qspi_opp_table>;
2791                         status = "disabled";
2792                 };
2793
2794                 usb_1_hsphy: phy@88e3000 {
2795                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2796                         reg = <0 0x088e3000 0 0x400>;
2797                         status = "disabled";
2798                         #phy-cells = <0>;
2799                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2800                                  <&rpmhcc RPMH_CXO_CLK>;
2801                         clock-names = "cfg_ahb", "ref";
2802                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2803
2804                         nvmem-cells = <&qusb2p_hstx_trim>;
2805                 };
2806
2807                 usb_1_qmpphy: phy@88e8000 {
2808                         compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2809                         reg = <0 0x088e8000 0 0x3000>;
2810                         status = "disabled";
2811
2812                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2813                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2814                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2815                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
2816                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
2817                         clock-names = "aux",
2818                                       "ref",
2819                                       "com_aux",
2820                                       "usb3_pipe",
2821                                       "cfg_ahb";
2822
2823                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2824                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2825                         reset-names = "phy", "common";
2826
2827                         #clock-cells = <1>;
2828                         #phy-cells = <1>;
2829                 };
2830
2831                 pmu@90b6300 {
2832                         compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2833                         reg = <0 0x090b6300 0 0x600>;
2834                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2835
2836                         interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2837                                          &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
2838                         operating-points-v2 = <&cpu_bwmon_opp_table>;
2839
2840                         cpu_bwmon_opp_table: opp-table {
2841                                 compatible = "operating-points-v2";
2842
2843                                 opp-0 {
2844                                         opp-peak-kBps = <2288000>;
2845                                 };
2846
2847                                 opp-1 {
2848                                         opp-peak-kBps = <4577000>;
2849                                 };
2850
2851                                 opp-2 {
2852                                         opp-peak-kBps = <7110000>;
2853                                 };
2854
2855                                 opp-3 {
2856                                         opp-peak-kBps = <9155000>;
2857                                 };
2858
2859                                 opp-4 {
2860                                         opp-peak-kBps = <12298000>;
2861                                 };
2862
2863                                 opp-5 {
2864                                         opp-peak-kBps = <14236000>;
2865                                 };
2866                         };
2867                 };
2868
2869                 pmu@90cd000 {
2870                         compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2871                         reg = <0 0x090cd000 0 0x1000>;
2872                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
2873
2874                         interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
2875                                          &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
2876                         operating-points-v2 = <&llcc_bwmon_opp_table>;
2877
2878                         llcc_bwmon_opp_table: opp-table {
2879                                 compatible = "operating-points-v2";
2880
2881                                 opp-0 {
2882                                         opp-peak-kBps = <1144000>;
2883                                 };
2884
2885                                 opp-1 {
2886                                         opp-peak-kBps = <1720000>;
2887                                 };
2888
2889                                 opp-2 {
2890                                         opp-peak-kBps = <2086000>;
2891                                 };
2892
2893                                 opp-3 {
2894                                         opp-peak-kBps = <2929000>;
2895                                 };
2896
2897                                 opp-4 {
2898                                         opp-peak-kBps = <3879000>;
2899                                 };
2900
2901                                 opp-5 {
2902                                         opp-peak-kBps = <5931000>;
2903                                 };
2904
2905                                 opp-6 {
2906                                         opp-peak-kBps = <6881000>;
2907                                 };
2908
2909                                 opp-7 {
2910                                         opp-peak-kBps = <8137000>;
2911                                 };
2912                         };
2913                 };
2914
2915                 dc_noc: interconnect@9160000 {
2916                         compatible = "qcom,sc7180-dc-noc";
2917                         reg = <0 0x09160000 0 0x03200>;
2918                         #interconnect-cells = <2>;
2919                         qcom,bcm-voters = <&apps_bcm_voter>;
2920                 };
2921
2922                 system-cache-controller@9200000 {
2923                         compatible = "qcom,sc7180-llcc";
2924                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2925                         reg-names = "llcc0_base", "llcc_broadcast_base";
2926                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2927                 };
2928
2929                 gem_noc: interconnect@9680000 {
2930                         compatible = "qcom,sc7180-gem-noc";
2931                         reg = <0 0x09680000 0 0x3e200>;
2932                         #interconnect-cells = <2>;
2933                         qcom,bcm-voters = <&apps_bcm_voter>;
2934                 };
2935
2936                 npu_noc: interconnect@9990000 {
2937                         compatible = "qcom,sc7180-npu-noc";
2938                         reg = <0 0x09990000 0 0x1600>;
2939                         #interconnect-cells = <2>;
2940                         qcom,bcm-voters = <&apps_bcm_voter>;
2941                 };
2942
2943                 usb_1: usb@a6f8800 {
2944                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2945                         reg = <0 0x0a6f8800 0 0x400>;
2946                         status = "disabled";
2947                         #address-cells = <2>;
2948                         #size-cells = <2>;
2949                         ranges;
2950                         dma-ranges;
2951
2952                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2953                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2954                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2955                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2956                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2957                         clock-names = "cfg_noc",
2958                                       "core",
2959                                       "iface",
2960                                       "sleep",
2961                                       "mock_utmi";
2962
2963                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2964                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2965                         assigned-clock-rates = <19200000>, <150000000>;
2966
2967                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2968                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2969                                               <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2970                                               <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2971                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2972                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2973
2974                         power-domains = <&gcc USB30_PRIM_GDSC>;
2975                         required-opps = <&rpmhpd_opp_nom>;
2976
2977                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2978
2979                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2980                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2981                         interconnect-names = "usb-ddr", "apps-usb";
2982
2983                         wakeup-source;
2984
2985                         usb_1_dwc3: usb@a600000 {
2986                                 compatible = "snps,dwc3";
2987                                 reg = <0 0x0a600000 0 0xe000>;
2988                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2989                                 iommus = <&apps_smmu 0x540 0>;
2990                                 snps,dis_u2_susphy_quirk;
2991                                 snps,dis_enblslpm_quirk;
2992                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
2993                                 phy-names = "usb2-phy", "usb3-phy";
2994                                 maximum-speed = "super-speed";
2995                         };
2996                 };
2997
2998                 venus: video-codec@aa00000 {
2999                         compatible = "qcom,sc7180-venus";
3000                         reg = <0 0x0aa00000 0 0xff000>;
3001                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3002                         power-domains = <&videocc VENUS_GDSC>,
3003                                         <&videocc VCODEC0_GDSC>,
3004                                         <&rpmhpd SC7180_CX>;
3005                         power-domain-names = "venus", "vcodec0", "cx";
3006                         operating-points-v2 = <&venus_opp_table>;
3007                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
3008                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3009                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
3010                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
3011                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
3012                         clock-names = "core", "iface", "bus",
3013                                       "vcodec0_core", "vcodec0_bus";
3014                         iommus = <&apps_smmu 0x0c00 0x60>;
3015                         memory-region = <&venus_mem>;
3016                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3017                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3018                         interconnect-names = "video-mem", "cpu-cfg";
3019
3020                         video-decoder {
3021                                 compatible = "venus-decoder";
3022                         };
3023
3024                         video-encoder {
3025                                 compatible = "venus-encoder";
3026                         };
3027
3028                         venus_opp_table: opp-table {
3029                                 compatible = "operating-points-v2";
3030
3031                                 opp-150000000 {
3032                                         opp-hz = /bits/ 64 <150000000>;
3033                                         required-opps = <&rpmhpd_opp_low_svs>;
3034                                 };
3035
3036                                 opp-270000000 {
3037                                         opp-hz = /bits/ 64 <270000000>;
3038                                         required-opps = <&rpmhpd_opp_svs>;
3039                                 };
3040
3041                                 opp-340000000 {
3042                                         opp-hz = /bits/ 64 <340000000>;
3043                                         required-opps = <&rpmhpd_opp_svs_l1>;
3044                                 };
3045
3046                                 opp-434000000 {
3047                                         opp-hz = /bits/ 64 <434000000>;
3048                                         required-opps = <&rpmhpd_opp_nom>;
3049                                 };
3050
3051                                 opp-500000097 {
3052                                         opp-hz = /bits/ 64 <500000097>;
3053                                         required-opps = <&rpmhpd_opp_turbo>;
3054                                 };
3055                         };
3056                 };
3057
3058                 videocc: clock-controller@ab00000 {
3059                         compatible = "qcom,sc7180-videocc";
3060                         reg = <0 0x0ab00000 0 0x10000>;
3061                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3062                         clock-names = "bi_tcxo";
3063                         #clock-cells = <1>;
3064                         #reset-cells = <1>;
3065                         #power-domain-cells = <1>;
3066                 };
3067
3068                 camnoc_virt: interconnect@ac00000 {
3069                         compatible = "qcom,sc7180-camnoc-virt";
3070                         reg = <0 0x0ac00000 0 0x1000>;
3071                         #interconnect-cells = <2>;
3072                         qcom,bcm-voters = <&apps_bcm_voter>;
3073                 };
3074
3075                 camcc: clock-controller@ad00000 {
3076                         compatible = "qcom,sc7180-camcc";
3077                         reg = <0 0x0ad00000 0 0x10000>;
3078                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3079                                <&gcc GCC_CAMERA_AHB_CLK>,
3080                                <&gcc GCC_CAMERA_XO_CLK>;
3081                         clock-names = "bi_tcxo", "iface", "xo";
3082                         #clock-cells = <1>;
3083                         #reset-cells = <1>;
3084                         #power-domain-cells = <1>;
3085                 };
3086
3087                 mdss: display-subsystem@ae00000 {
3088                         compatible = "qcom,sc7180-mdss";
3089                         reg = <0 0x0ae00000 0 0x1000>;
3090                         reg-names = "mdss";
3091
3092                         power-domains = <&dispcc MDSS_GDSC>;
3093
3094                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3095                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
3096                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
3097                         clock-names = "iface", "ahb", "core";
3098
3099                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3100                         interrupt-controller;
3101                         #interrupt-cells = <1>;
3102
3103                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3104                         interconnect-names = "mdp0-mem";
3105
3106                         iommus = <&apps_smmu 0x800 0x2>;
3107
3108                         #address-cells = <2>;
3109                         #size-cells = <2>;
3110                         ranges;
3111
3112                         status = "disabled";
3113
3114                         mdp: display-controller@ae01000 {
3115                                 compatible = "qcom,sc7180-dpu";
3116                                 reg = <0 0x0ae01000 0 0x8f000>,
3117                                       <0 0x0aeb0000 0 0x2008>;
3118                                 reg-names = "mdp", "vbif";
3119
3120                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3121                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3122                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
3123                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3124                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3125                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3126                                 clock-names = "bus", "iface", "rot", "lut", "core",
3127                                               "vsync";
3128                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3129                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
3130                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
3131                                 assigned-clock-rates = <19200000>,
3132                                                        <19200000>,
3133                                                        <19200000>;
3134                                 operating-points-v2 = <&mdp_opp_table>;
3135                                 power-domains = <&rpmhpd SC7180_CX>;
3136
3137                                 interrupt-parent = <&mdss>;
3138                                 interrupts = <0>;
3139
3140                                 ports {
3141                                         #address-cells = <1>;
3142                                         #size-cells = <0>;
3143
3144                                         port@0 {
3145                                                 reg = <0>;
3146                                                 dpu_intf1_out: endpoint {
3147                                                         remote-endpoint = <&mdss_dsi0_in>;
3148                                                 };
3149                                         };
3150
3151                                         port@2 {
3152                                                 reg = <2>;
3153                                                 dpu_intf0_out: endpoint {
3154                                                         remote-endpoint = <&dp_in>;
3155                                                 };
3156                                         };
3157                                 };
3158
3159                                 mdp_opp_table: opp-table {
3160                                         compatible = "operating-points-v2";
3161
3162                                         opp-200000000 {
3163                                                 opp-hz = /bits/ 64 <200000000>;
3164                                                 required-opps = <&rpmhpd_opp_low_svs>;
3165                                         };
3166
3167                                         opp-300000000 {
3168                                                 opp-hz = /bits/ 64 <300000000>;
3169                                                 required-opps = <&rpmhpd_opp_svs>;
3170                                         };
3171
3172                                         opp-345000000 {
3173                                                 opp-hz = /bits/ 64 <345000000>;
3174                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3175                                         };
3176
3177                                         opp-460000000 {
3178                                                 opp-hz = /bits/ 64 <460000000>;
3179                                                 required-opps = <&rpmhpd_opp_nom>;
3180                                         };
3181                                 };
3182                         };
3183
3184                         mdss_dsi0: dsi@ae94000 {
3185                                 compatible = "qcom,sc7180-dsi-ctrl",
3186                                              "qcom,mdss-dsi-ctrl";
3187                                 reg = <0 0x0ae94000 0 0x400>;
3188                                 reg-names = "dsi_ctrl";
3189
3190                                 interrupt-parent = <&mdss>;
3191                                 interrupts = <4>;
3192
3193                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3194                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3195                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3196                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3197                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3198                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3199                                 clock-names = "byte",
3200                                               "byte_intf",
3201                                               "pixel",
3202                                               "core",
3203                                               "iface",
3204                                               "bus";
3205
3206                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3207                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3208
3209                                 operating-points-v2 = <&dsi_opp_table>;
3210                                 power-domains = <&rpmhpd SC7180_CX>;
3211
3212                                 phys = <&mdss_dsi0_phy>;
3213
3214                                 #address-cells = <1>;
3215                                 #size-cells = <0>;
3216
3217                                 status = "disabled";
3218
3219                                 ports {
3220                                         #address-cells = <1>;
3221                                         #size-cells = <0>;
3222
3223                                         port@0 {
3224                                                 reg = <0>;
3225                                                 mdss_dsi0_in: endpoint {
3226                                                         remote-endpoint = <&dpu_intf1_out>;
3227                                                 };
3228                                         };
3229
3230                                         port@1 {
3231                                                 reg = <1>;
3232                                                 mdss_dsi0_out: endpoint {
3233                                                 };
3234                                         };
3235                                 };
3236
3237                                 dsi_opp_table: opp-table {
3238                                         compatible = "operating-points-v2";
3239
3240                                         opp-187500000 {
3241                                                 opp-hz = /bits/ 64 <187500000>;
3242                                                 required-opps = <&rpmhpd_opp_low_svs>;
3243                                         };
3244
3245                                         opp-300000000 {
3246                                                 opp-hz = /bits/ 64 <300000000>;
3247                                                 required-opps = <&rpmhpd_opp_svs>;
3248                                         };
3249
3250                                         opp-358000000 {
3251                                                 opp-hz = /bits/ 64 <358000000>;
3252                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3253                                         };
3254                                 };
3255                         };
3256
3257                         mdss_dsi0_phy: phy@ae94400 {
3258                                 compatible = "qcom,dsi-phy-10nm";
3259                                 reg = <0 0x0ae94400 0 0x200>,
3260                                       <0 0x0ae94600 0 0x280>,
3261                                       <0 0x0ae94a00 0 0x1e0>;
3262                                 reg-names = "dsi_phy",
3263                                             "dsi_phy_lane",
3264                                             "dsi_pll";
3265
3266                                 #clock-cells = <1>;
3267                                 #phy-cells = <0>;
3268
3269                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3270                                          <&rpmhcc RPMH_CXO_CLK>;
3271                                 clock-names = "iface", "ref";
3272
3273                                 status = "disabled";
3274                         };
3275
3276                         mdss_dp: displayport-controller@ae90000 {
3277                                 compatible = "qcom,sc7180-dp";
3278                                 status = "disabled";
3279
3280                                 reg = <0 0x0ae90000 0 0x200>,
3281                                       <0 0x0ae90200 0 0x200>,
3282                                       <0 0x0ae90400 0 0xc00>,
3283                                       <0 0x0ae91000 0 0x400>,
3284                                       <0 0x0ae91400 0 0x400>;
3285
3286                                 interrupt-parent = <&mdss>;
3287                                 interrupts = <12>;
3288
3289                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3290                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3291                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3292                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3293                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3294                                 clock-names = "core_iface", "core_aux", "ctrl_link",
3295                                               "ctrl_link_iface", "stream_pixel";
3296                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3297                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3298                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3299                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3300                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3301                                 phy-names = "dp";
3302
3303                                 operating-points-v2 = <&dp_opp_table>;
3304                                 power-domains = <&rpmhpd SC7180_CX>;
3305
3306                                 #sound-dai-cells = <0>;
3307
3308                                 ports {
3309                                         #address-cells = <1>;
3310                                         #size-cells = <0>;
3311                                         port@0 {
3312                                                 reg = <0>;
3313                                                 dp_in: endpoint {
3314                                                         remote-endpoint = <&dpu_intf0_out>;
3315                                                 };
3316                                         };
3317
3318                                         port@1 {
3319                                                 reg = <1>;
3320                                                 mdss_dp_out: endpoint { };
3321                                         };
3322                                 };
3323
3324                                 dp_opp_table: opp-table {
3325                                         compatible = "operating-points-v2";
3326
3327                                         opp-160000000 {
3328                                                 opp-hz = /bits/ 64 <160000000>;
3329                                                 required-opps = <&rpmhpd_opp_low_svs>;
3330                                         };
3331
3332                                         opp-270000000 {
3333                                                 opp-hz = /bits/ 64 <270000000>;
3334                                                 required-opps = <&rpmhpd_opp_svs>;
3335                                         };
3336
3337                                         opp-540000000 {
3338                                                 opp-hz = /bits/ 64 <540000000>;
3339                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3340                                         };
3341
3342                                         opp-810000000 {
3343                                                 opp-hz = /bits/ 64 <810000000>;
3344                                                 required-opps = <&rpmhpd_opp_nom>;
3345                                         };
3346                                 };
3347                         };
3348                 };
3349
3350                 dispcc: clock-controller@af00000 {
3351                         compatible = "qcom,sc7180-dispcc";
3352                         reg = <0 0x0af00000 0 0x200000>;
3353                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3354                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3355                                  <&mdss_dsi0_phy 0>,
3356                                  <&mdss_dsi0_phy 1>,
3357                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3358                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3359                         clock-names = "bi_tcxo",
3360                                       "gcc_disp_gpll0_clk_src",
3361                                       "dsi0_phy_pll_out_byteclk",
3362                                       "dsi0_phy_pll_out_dsiclk",
3363                                       "dp_phy_pll_link_clk",
3364                                       "dp_phy_pll_vco_div_clk";
3365                         #clock-cells = <1>;
3366                         #reset-cells = <1>;
3367                         #power-domain-cells = <1>;
3368                 };
3369
3370                 pdc: interrupt-controller@b220000 {
3371                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3372                         reg = <0 0x0b220000 0 0x30000>;
3373                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3374                         #interrupt-cells = <2>;
3375                         interrupt-parent = <&intc>;
3376                         interrupt-controller;
3377                 };
3378
3379                 pdc_reset: reset-controller@b2e0000 {
3380                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3381                         reg = <0 0x0b2e0000 0 0x20000>;
3382                         #reset-cells = <1>;
3383                 };
3384
3385                 tsens0: thermal-sensor@c263000 {
3386                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3387                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3388                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3389                         #qcom,sensors = <15>;
3390                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3391                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3392                         interrupt-names = "uplow","critical";
3393                         #thermal-sensor-cells = <1>;
3394                 };
3395
3396                 tsens1: thermal-sensor@c265000 {
3397                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3398                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3399                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3400                         #qcom,sensors = <10>;
3401                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3402                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3403                         interrupt-names = "uplow","critical";
3404                         #thermal-sensor-cells = <1>;
3405                 };
3406
3407                 aoss_reset: reset-controller@c2a0000 {
3408                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3409                         reg = <0 0x0c2a0000 0 0x31000>;
3410                         #reset-cells = <1>;
3411                 };
3412
3413                 aoss_qmp: power-management@c300000 {
3414                         compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3415                         reg = <0 0x0c300000 0 0x400>;
3416                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3417                         mboxes = <&apss_shared 0>;
3418
3419                         #clock-cells = <0>;
3420                 };
3421
3422                 sram@c3f0000 {
3423                         compatible = "qcom,rpmh-stats";
3424                         reg = <0 0x0c3f0000 0 0x400>;
3425                 };
3426
3427                 spmi_bus: spmi@c440000 {
3428                         compatible = "qcom,spmi-pmic-arb";
3429                         reg = <0 0x0c440000 0 0x1100>,
3430                               <0 0x0c600000 0 0x2000000>,
3431                               <0 0x0e600000 0 0x100000>,
3432                               <0 0x0e700000 0 0xa0000>,
3433                               <0 0x0c40a000 0 0x26000>;
3434                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3435                         interrupt-names = "periph_irq";
3436                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3437                         qcom,ee = <0>;
3438                         qcom,channel = <0>;
3439                         #address-cells = <2>;
3440                         #size-cells = <0>;
3441                         interrupt-controller;
3442                         #interrupt-cells = <4>;
3443                 };
3444
3445                 sram@146aa000 {
3446                         compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3447                         reg = <0 0x146aa000 0 0x2000>;
3448
3449                         #address-cells = <1>;
3450                         #size-cells = <1>;
3451
3452                         ranges = <0 0 0x146aa000 0x2000>;
3453
3454                         pil-reloc@94c {
3455                                 compatible = "qcom,pil-reloc-info";
3456                                 reg = <0x94c 0xc8>;
3457                         };
3458                 };
3459
3460                 apps_smmu: iommu@15000000 {
3461                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3462                         reg = <0 0x15000000 0 0x100000>;
3463                         #iommu-cells = <2>;
3464                         #global-interrupts = <1>;
3465                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3466                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3467                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3468                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3469                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3470                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3471                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3472                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3473                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3474                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3475                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3476                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3477                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3478                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3479                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3480                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3481                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3482                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3483                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3484                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3485                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3486                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3487                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3488                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3489                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3490                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3491                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3492                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3493                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3494                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3495                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3496                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3497                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3498                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3499                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3500                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3501                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3502                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3503                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3504                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3505                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3506                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3507                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3508                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3509                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3510                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3511                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3512                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3513                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3514                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3515                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3516                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3517                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3518                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3519                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3520                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3521                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3522                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3523                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3524                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3525                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3526                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3527                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3528                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3529                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3530                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3531                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3532                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3533                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3534                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3535                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3536                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3537                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3538                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3539                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3540                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3541                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3542                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3543                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3544                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3545                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3546                 };
3547
3548                 intc: interrupt-controller@17a00000 {
3549                         compatible = "arm,gic-v3";
3550                         #address-cells = <2>;
3551                         #size-cells = <2>;
3552                         ranges;
3553                         #interrupt-cells = <3>;
3554                         interrupt-controller;
3555                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3556                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3557                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3558
3559                         msi-controller@17a40000 {
3560                                 compatible = "arm,gic-v3-its";
3561                                 msi-controller;
3562                                 #msi-cells = <1>;
3563                                 reg = <0 0x17a40000 0 0x20000>;
3564                                 status = "disabled";
3565                         };
3566                 };
3567
3568                 apss_shared: mailbox@17c00000 {
3569                         compatible = "qcom,sc7180-apss-shared",
3570                                      "qcom,sdm845-apss-shared";
3571                         reg = <0 0x17c00000 0 0x10000>;
3572                         #mbox-cells = <1>;
3573                 };
3574
3575                 watchdog@17c10000 {
3576                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3577                         reg = <0 0x17c10000 0 0x1000>;
3578                         clocks = <&sleep_clk>;
3579                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3580                 };
3581
3582                 timer@17c20000 {
3583                         #address-cells = <1>;
3584                         #size-cells = <1>;
3585                         ranges = <0 0 0 0x20000000>;
3586                         compatible = "arm,armv7-timer-mem";
3587                         reg = <0 0x17c20000 0 0x1000>;
3588
3589                         frame@17c21000 {
3590                                 frame-number = <0>;
3591                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3592                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3593                                 reg = <0x17c21000 0x1000>,
3594                                       <0x17c22000 0x1000>;
3595                         };
3596
3597                         frame@17c23000 {
3598                                 frame-number = <1>;
3599                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3600                                 reg = <0x17c23000 0x1000>;
3601                                 status = "disabled";
3602                         };
3603
3604                         frame@17c25000 {
3605                                 frame-number = <2>;
3606                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3607                                 reg = <0x17c25000 0x1000>;
3608                                 status = "disabled";
3609                         };
3610
3611                         frame@17c27000 {
3612                                 frame-number = <3>;
3613                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3614                                 reg = <0x17c27000 0x1000>;
3615                                 status = "disabled";
3616                         };
3617
3618                         frame@17c29000 {
3619                                 frame-number = <4>;
3620                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3621                                 reg = <0x17c29000 0x1000>;
3622                                 status = "disabled";
3623                         };
3624
3625                         frame@17c2b000 {
3626                                 frame-number = <5>;
3627                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3628                                 reg = <0x17c2b000 0x1000>;
3629                                 status = "disabled";
3630                         };
3631
3632                         frame@17c2d000 {
3633                                 frame-number = <6>;
3634                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3635                                 reg = <0x17c2d000 0x1000>;
3636                                 status = "disabled";
3637                         };
3638                 };
3639
3640                 apps_rsc: rsc@18200000 {
3641                         compatible = "qcom,rpmh-rsc";
3642                         reg = <0 0x18200000 0 0x10000>,
3643                               <0 0x18210000 0 0x10000>,
3644                               <0 0x18220000 0 0x10000>;
3645                         reg-names = "drv-0", "drv-1", "drv-2";
3646                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3647                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3648                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3649                         qcom,tcs-offset = <0xd00>;
3650                         qcom,drv-id = <2>;
3651                         qcom,tcs-config = <ACTIVE_TCS  2>,
3652                                           <SLEEP_TCS   3>,
3653                                           <WAKE_TCS    3>,
3654                                           <CONTROL_TCS 1>;
3655                         power-domains = <&CLUSTER_PD>;
3656
3657                         rpmhcc: clock-controller {
3658                                 compatible = "qcom,sc7180-rpmh-clk";
3659                                 clocks = <&xo_board>;
3660                                 clock-names = "xo";
3661                                 #clock-cells = <1>;
3662                         };
3663
3664                         rpmhpd: power-controller {
3665                                 compatible = "qcom,sc7180-rpmhpd";
3666                                 #power-domain-cells = <1>;
3667                                 operating-points-v2 = <&rpmhpd_opp_table>;
3668
3669                                 rpmhpd_opp_table: opp-table {
3670                                         compatible = "operating-points-v2";
3671
3672                                         rpmhpd_opp_ret: opp1 {
3673                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3674                                         };
3675
3676                                         rpmhpd_opp_min_svs: opp2 {
3677                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3678                                         };
3679
3680                                         rpmhpd_opp_low_svs: opp3 {
3681                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3682                                         };
3683
3684                                         rpmhpd_opp_svs: opp4 {
3685                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3686                                         };
3687
3688                                         rpmhpd_opp_svs_l1: opp5 {
3689                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3690                                         };
3691
3692                                         rpmhpd_opp_svs_l2: opp6 {
3693                                                 opp-level = <224>;
3694                                         };
3695
3696                                         rpmhpd_opp_nom: opp7 {
3697                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3698                                         };
3699
3700                                         rpmhpd_opp_nom_l1: opp8 {
3701                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3702                                         };
3703
3704                                         rpmhpd_opp_nom_l2: opp9 {
3705                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3706                                         };
3707
3708                                         rpmhpd_opp_turbo: opp10 {
3709                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3710                                         };
3711
3712                                         rpmhpd_opp_turbo_l1: opp11 {
3713                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3714                                         };
3715                                 };
3716                         };
3717
3718                         apps_bcm_voter: bcm-voter {
3719                                 compatible = "qcom,bcm-voter";
3720                         };
3721                 };
3722
3723                 osm_l3: interconnect@18321000 {
3724                         compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3725                         reg = <0 0x18321000 0 0x1400>;
3726
3727                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3728                         clock-names = "xo", "alternate";
3729
3730                         #interconnect-cells = <1>;
3731                 };
3732
3733                 cpufreq_hw: cpufreq@18323000 {
3734                         compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3735                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3736                         reg-names = "freq-domain0", "freq-domain1";
3737
3738                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3739                         clock-names = "xo", "alternate";
3740
3741                         #freq-domain-cells = <1>;
3742                         #clock-cells = <1>;
3743                 };
3744
3745                 wifi: wifi@18800000 {
3746                         compatible = "qcom,wcn3990-wifi";
3747                         reg = <0 0x18800000 0 0x800000>;
3748                         reg-names = "membase";
3749                         iommus = <&apps_smmu 0xc0 0x1>;
3750                         interrupts =
3751                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3752                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3753                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3754                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3755                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3756                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3757                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3758                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3759                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3760                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3761                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3762                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3763                         memory-region = <&wlan_mem>;
3764                         qcom,msa-fixed-perm;
3765                         status = "disabled";
3766                 };
3767
3768                 remoteproc_adsp: remoteproc@62400000 {
3769                         compatible = "qcom,sc7180-adsp-pas";
3770                         reg = <0 0x62400000 0 0x100>;
3771
3772                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3773                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3774                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3775                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3776                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3777                         interrupt-names = "wdog",
3778                                           "fatal",
3779                                           "ready",
3780                                           "handover",
3781                                           "stop-ack";
3782
3783                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3784                         clock-names = "xo";
3785
3786                         power-domains = <&rpmhpd SC7180_LCX>,
3787                                         <&rpmhpd SC7180_LMX>;
3788                         power-domain-names = "lcx", "lmx";
3789
3790                         qcom,qmp = <&aoss_qmp>;
3791                         qcom,smem-states = <&adsp_smp2p_out 0>;
3792                         qcom,smem-state-names = "stop";
3793
3794                         status = "disabled";
3795
3796                         glink-edge {
3797                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3798                                 label = "lpass";
3799                                 qcom,remote-pid = <2>;
3800                                 mboxes = <&apss_shared 8>;
3801
3802                                 apr {
3803                                         compatible = "qcom,apr-v2";
3804                                         qcom,glink-channels = "apr_audio_svc";
3805                                         qcom,domain = <APR_DOMAIN_ADSP>;
3806                                         #address-cells = <1>;
3807                                         #size-cells = <0>;
3808
3809                                         service@3 {
3810                                                 compatible = "qcom,q6core";
3811                                                 reg = <APR_SVC_ADSP_CORE>;
3812                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3813                                         };
3814
3815                                         q6afe: service@4 {
3816                                                 compatible = "qcom,q6afe";
3817                                                 reg = <APR_SVC_AFE>;
3818                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3819
3820                                                 q6afedai: dais {
3821                                                         compatible = "qcom,q6afe-dais";
3822                                                         #address-cells = <1>;
3823                                                         #size-cells = <0>;
3824                                                         #sound-dai-cells = <1>;
3825                                                 };
3826
3827                                                 q6afecc: clock-controller {
3828                                                         compatible = "qcom,q6afe-clocks";
3829                                                         #clock-cells = <2>;
3830                                                 };
3831                                         };
3832
3833                                         q6asm: service@7 {
3834                                                 compatible = "qcom,q6asm";
3835                                                 reg = <APR_SVC_ASM>;
3836                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3837
3838                                                 q6asmdai: dais {
3839                                                         compatible = "qcom,q6asm-dais";
3840                                                         #address-cells = <1>;
3841                                                         #size-cells = <0>;
3842                                                         #sound-dai-cells = <1>;
3843                                                         iommus = <&apps_smmu 0x1001 0x0>;
3844                                                 };
3845                                         };
3846
3847                                         q6adm: service@8 {
3848                                                 compatible = "qcom,q6adm";
3849                                                 reg = <APR_SVC_ADM>;
3850                                                 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
3851
3852                                                 q6routing: routing {
3853                                                         compatible = "qcom,q6adm-routing";
3854                                                         #sound-dai-cells = <0>;
3855                                                 };
3856                                         };
3857                                 };
3858
3859                                 fastrpc {
3860                                         compatible = "qcom,fastrpc";
3861                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3862                                         label = "adsp";
3863                                         #address-cells = <1>;
3864                                         #size-cells = <0>;
3865
3866                                         compute-cb@3 {
3867                                                 compatible = "qcom,fastrpc-compute-cb";
3868                                                 reg = <3>;
3869                                                 iommus = <&apps_smmu 0x1003 0x0>;
3870                                         };
3871
3872                                         compute-cb@4 {
3873                                                 compatible = "qcom,fastrpc-compute-cb";
3874                                                 reg = <4>;
3875                                                 iommus = <&apps_smmu 0x1004 0x0>;
3876                                         };
3877
3878                                         compute-cb@5 {
3879                                                 compatible = "qcom,fastrpc-compute-cb";
3880                                                 reg = <5>;
3881                                                 iommus = <&apps_smmu 0x1005 0x0>;
3882                                                 qcom,nsessions = <5>;
3883                                         };
3884                                 };
3885                         };
3886                 };
3887
3888                 lpasscc: clock-controller@62d00000 {
3889                         compatible = "qcom,sc7180-lpasscorecc";
3890                         reg = <0 0x62d00000 0 0x50000>,
3891                               <0 0x62780000 0 0x30000>;
3892                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3893                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3894                                  <&rpmhcc RPMH_CXO_CLK>;
3895                         clock-names = "iface", "bi_tcxo";
3896                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3897                         #clock-cells = <1>;
3898                         #power-domain-cells = <1>;
3899
3900                         status = "reserved"; /* Controlled by ADSP */
3901                 };
3902
3903                 lpass_cpu: lpass@62d87000 {
3904                         compatible = "qcom,sc7180-lpass-cpu";
3905
3906                         reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3907                         reg-names = "lpass-hdmiif", "lpass-lpaif";
3908
3909                         iommus = <&apps_smmu 0x1020 0>,
3910                                 <&apps_smmu 0x1021 0>,
3911                                 <&apps_smmu 0x1032 0>;
3912
3913                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3914                         required-opps = <&rpmhpd_opp_nom>;
3915
3916                         status = "disabled";
3917
3918                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3919                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3920                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3921                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3922                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3923                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3924
3925                         clock-names = "pcnoc-sway-clk", "audio-core",
3926                                         "mclk0", "pcnoc-mport-clk",
3927                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3928
3929
3930                         #sound-dai-cells = <1>;
3931                         #address-cells = <1>;
3932                         #size-cells = <0>;
3933
3934                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
3935                                         <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3936                         interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3937                 };
3938
3939                 lpass_hm: clock-controller@63000000 {
3940                         compatible = "qcom,sc7180-lpasshm";
3941                         reg = <0 0x63000000 0 0x28>;
3942                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3943                                  <&rpmhcc RPMH_CXO_CLK>;
3944                         clock-names = "iface", "bi_tcxo";
3945                         power-domains = <&rpmhpd SC7180_CX>;
3946
3947                         #clock-cells = <1>;
3948                         #power-domain-cells = <1>;
3949
3950                         status = "reserved"; /* Controlled by ADSP */
3951                 };
3952         };
3953
3954         thermal-zones {
3955                 cpu0_thermal: cpu0-thermal {
3956                         polling-delay-passive = <250>;
3957                         polling-delay = <0>;
3958
3959                         thermal-sensors = <&tsens0 1>;
3960                         sustainable-power = <1052>;
3961
3962                         trips {
3963                                 cpu0_alert0: trip-point0 {
3964                                         temperature = <90000>;
3965                                         hysteresis = <2000>;
3966                                         type = "passive";
3967                                 };
3968
3969                                 cpu0_alert1: trip-point1 {
3970                                         temperature = <95000>;
3971                                         hysteresis = <2000>;
3972                                         type = "passive";
3973                                 };
3974
3975                                 cpu0_crit: cpu-crit {
3976                                         temperature = <110000>;
3977                                         hysteresis = <1000>;
3978                                         type = "critical";
3979                                 };
3980                         };
3981
3982                         cooling-maps {
3983                                 map0 {
3984                                         trip = <&cpu0_alert0>;
3985                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3986                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3987                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3988                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3989                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3990                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3991                                 };
3992                                 map1 {
3993                                         trip = <&cpu0_alert1>;
3994                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3995                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3996                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3997                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3998                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3999                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4000                                 };
4001                         };
4002                 };
4003
4004                 cpu1_thermal: cpu1-thermal {
4005                         polling-delay-passive = <250>;
4006                         polling-delay = <0>;
4007
4008                         thermal-sensors = <&tsens0 2>;
4009                         sustainable-power = <1052>;
4010
4011                         trips {
4012                                 cpu1_alert0: trip-point0 {
4013                                         temperature = <90000>;
4014                                         hysteresis = <2000>;
4015                                         type = "passive";
4016                                 };
4017
4018                                 cpu1_alert1: trip-point1 {
4019                                         temperature = <95000>;
4020                                         hysteresis = <2000>;
4021                                         type = "passive";
4022                                 };
4023
4024                                 cpu1_crit: cpu-crit {
4025                                         temperature = <110000>;
4026                                         hysteresis = <1000>;
4027                                         type = "critical";
4028                                 };
4029                         };
4030
4031                         cooling-maps {
4032                                 map0 {
4033                                         trip = <&cpu1_alert0>;
4034                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4035                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4036                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4037                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4038                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4039                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4040                                 };
4041                                 map1 {
4042                                         trip = <&cpu1_alert1>;
4043                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4044                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4045                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4046                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4047                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4048                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4049                                 };
4050                         };
4051                 };
4052
4053                 cpu2_thermal: cpu2-thermal {
4054                         polling-delay-passive = <250>;
4055                         polling-delay = <0>;
4056
4057                         thermal-sensors = <&tsens0 3>;
4058                         sustainable-power = <1052>;
4059
4060                         trips {
4061                                 cpu2_alert0: trip-point0 {
4062                                         temperature = <90000>;
4063                                         hysteresis = <2000>;
4064                                         type = "passive";
4065                                 };
4066
4067                                 cpu2_alert1: trip-point1 {
4068                                         temperature = <95000>;
4069                                         hysteresis = <2000>;
4070                                         type = "passive";
4071                                 };
4072
4073                                 cpu2_crit: cpu-crit {
4074                                         temperature = <110000>;
4075                                         hysteresis = <1000>;
4076                                         type = "critical";
4077                                 };
4078                         };
4079
4080                         cooling-maps {
4081                                 map0 {
4082                                         trip = <&cpu2_alert0>;
4083                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4084                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4085                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4086                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4087                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4088                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4089                                 };
4090                                 map1 {
4091                                         trip = <&cpu2_alert1>;
4092                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4093                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4094                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4095                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4096                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4097                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4098                                 };
4099                         };
4100                 };
4101
4102                 cpu3_thermal: cpu3-thermal {
4103                         polling-delay-passive = <250>;
4104                         polling-delay = <0>;
4105
4106                         thermal-sensors = <&tsens0 4>;
4107                         sustainable-power = <1052>;
4108
4109                         trips {
4110                                 cpu3_alert0: trip-point0 {
4111                                         temperature = <90000>;
4112                                         hysteresis = <2000>;
4113                                         type = "passive";
4114                                 };
4115
4116                                 cpu3_alert1: trip-point1 {
4117                                         temperature = <95000>;
4118                                         hysteresis = <2000>;
4119                                         type = "passive";
4120                                 };
4121
4122                                 cpu3_crit: cpu-crit {
4123                                         temperature = <110000>;
4124                                         hysteresis = <1000>;
4125                                         type = "critical";
4126                                 };
4127                         };
4128
4129                         cooling-maps {
4130                                 map0 {
4131                                         trip = <&cpu3_alert0>;
4132                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4133                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4134                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4135                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4136                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4137                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4138                                 };
4139                                 map1 {
4140                                         trip = <&cpu3_alert1>;
4141                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4142                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4143                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4144                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4145                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4146                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4147                                 };
4148                         };
4149                 };
4150
4151                 cpu4_thermal: cpu4-thermal {
4152                         polling-delay-passive = <250>;
4153                         polling-delay = <0>;
4154
4155                         thermal-sensors = <&tsens0 5>;
4156                         sustainable-power = <1052>;
4157
4158                         trips {
4159                                 cpu4_alert0: trip-point0 {
4160                                         temperature = <90000>;
4161                                         hysteresis = <2000>;
4162                                         type = "passive";
4163                                 };
4164
4165                                 cpu4_alert1: trip-point1 {
4166                                         temperature = <95000>;
4167                                         hysteresis = <2000>;
4168                                         type = "passive";
4169                                 };
4170
4171                                 cpu4_crit: cpu-crit {
4172                                         temperature = <110000>;
4173                                         hysteresis = <1000>;
4174                                         type = "critical";
4175                                 };
4176                         };
4177
4178                         cooling-maps {
4179                                 map0 {
4180                                         trip = <&cpu4_alert0>;
4181                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4182                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4183                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4184                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4185                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4186                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4187                                 };
4188                                 map1 {
4189                                         trip = <&cpu4_alert1>;
4190                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4191                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4192                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4193                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4194                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4195                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4196                                 };
4197                         };
4198                 };
4199
4200                 cpu5_thermal: cpu5-thermal {
4201                         polling-delay-passive = <250>;
4202                         polling-delay = <0>;
4203
4204                         thermal-sensors = <&tsens0 6>;
4205                         sustainable-power = <1052>;
4206
4207                         trips {
4208                                 cpu5_alert0: trip-point0 {
4209                                         temperature = <90000>;
4210                                         hysteresis = <2000>;
4211                                         type = "passive";
4212                                 };
4213
4214                                 cpu5_alert1: trip-point1 {
4215                                         temperature = <95000>;
4216                                         hysteresis = <2000>;
4217                                         type = "passive";
4218                                 };
4219
4220                                 cpu5_crit: cpu-crit {
4221                                         temperature = <110000>;
4222                                         hysteresis = <1000>;
4223                                         type = "critical";
4224                                 };
4225                         };
4226
4227                         cooling-maps {
4228                                 map0 {
4229                                         trip = <&cpu5_alert0>;
4230                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4231                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4232                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4233                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4234                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4235                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4236                                 };
4237                                 map1 {
4238                                         trip = <&cpu5_alert1>;
4239                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4240                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4241                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4242                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4243                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4244                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4245                                 };
4246                         };
4247                 };
4248
4249                 cpu6_thermal: cpu6-thermal {
4250                         polling-delay-passive = <250>;
4251                         polling-delay = <0>;
4252
4253                         thermal-sensors = <&tsens0 9>;
4254                         sustainable-power = <1425>;
4255
4256                         trips {
4257                                 cpu6_alert0: trip-point0 {
4258                                         temperature = <90000>;
4259                                         hysteresis = <2000>;
4260                                         type = "passive";
4261                                 };
4262
4263                                 cpu6_alert1: trip-point1 {
4264                                         temperature = <95000>;
4265                                         hysteresis = <2000>;
4266                                         type = "passive";
4267                                 };
4268
4269                                 cpu6_crit: cpu-crit {
4270                                         temperature = <110000>;
4271                                         hysteresis = <1000>;
4272                                         type = "critical";
4273                                 };
4274                         };
4275
4276                         cooling-maps {
4277                                 map0 {
4278                                         trip = <&cpu6_alert0>;
4279                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4280                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4281                                 };
4282                                 map1 {
4283                                         trip = <&cpu6_alert1>;
4284                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4285                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4286                                 };
4287                         };
4288                 };
4289
4290                 cpu7_thermal: cpu7-thermal {
4291                         polling-delay-passive = <250>;
4292                         polling-delay = <0>;
4293
4294                         thermal-sensors = <&tsens0 10>;
4295                         sustainable-power = <1425>;
4296
4297                         trips {
4298                                 cpu7_alert0: trip-point0 {
4299                                         temperature = <90000>;
4300                                         hysteresis = <2000>;
4301                                         type = "passive";
4302                                 };
4303
4304                                 cpu7_alert1: trip-point1 {
4305                                         temperature = <95000>;
4306                                         hysteresis = <2000>;
4307                                         type = "passive";
4308                                 };
4309
4310                                 cpu7_crit: cpu-crit {
4311                                         temperature = <110000>;
4312                                         hysteresis = <1000>;
4313                                         type = "critical";
4314                                 };
4315                         };
4316
4317                         cooling-maps {
4318                                 map0 {
4319                                         trip = <&cpu7_alert0>;
4320                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4321                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4322                                 };
4323                                 map1 {
4324                                         trip = <&cpu7_alert1>;
4325                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4326                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4327                                 };
4328                         };
4329                 };
4330
4331                 cpu8_thermal: cpu8-thermal {
4332                         polling-delay-passive = <250>;
4333                         polling-delay = <0>;
4334
4335                         thermal-sensors = <&tsens0 11>;
4336                         sustainable-power = <1425>;
4337
4338                         trips {
4339                                 cpu8_alert0: trip-point0 {
4340                                         temperature = <90000>;
4341                                         hysteresis = <2000>;
4342                                         type = "passive";
4343                                 };
4344
4345                                 cpu8_alert1: trip-point1 {
4346                                         temperature = <95000>;
4347                                         hysteresis = <2000>;
4348                                         type = "passive";
4349                                 };
4350
4351                                 cpu8_crit: cpu-crit {
4352                                         temperature = <110000>;
4353                                         hysteresis = <1000>;
4354                                         type = "critical";
4355                                 };
4356                         };
4357
4358                         cooling-maps {
4359                                 map0 {
4360                                         trip = <&cpu8_alert0>;
4361                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4362                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4363                                 };
4364                                 map1 {
4365                                         trip = <&cpu8_alert1>;
4366                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4367                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4368                                 };
4369                         };
4370                 };
4371
4372                 cpu9_thermal: cpu9-thermal {
4373                         polling-delay-passive = <250>;
4374                         polling-delay = <0>;
4375
4376                         thermal-sensors = <&tsens0 12>;
4377                         sustainable-power = <1425>;
4378
4379                         trips {
4380                                 cpu9_alert0: trip-point0 {
4381                                         temperature = <90000>;
4382                                         hysteresis = <2000>;
4383                                         type = "passive";
4384                                 };
4385
4386                                 cpu9_alert1: trip-point1 {
4387                                         temperature = <95000>;
4388                                         hysteresis = <2000>;
4389                                         type = "passive";
4390                                 };
4391
4392                                 cpu9_crit: cpu-crit {
4393                                         temperature = <110000>;
4394                                         hysteresis = <1000>;
4395                                         type = "critical";
4396                                 };
4397                         };
4398
4399                         cooling-maps {
4400                                 map0 {
4401                                         trip = <&cpu9_alert0>;
4402                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4403                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4404                                 };
4405                                 map1 {
4406                                         trip = <&cpu9_alert1>;
4407                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4408                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4409                                 };
4410                         };
4411                 };
4412
4413                 aoss0-thermal {
4414                         polling-delay-passive = <250>;
4415                         polling-delay = <0>;
4416
4417                         thermal-sensors = <&tsens0 0>;
4418
4419                         trips {
4420                                 aoss0_alert0: trip-point0 {
4421                                         temperature = <90000>;
4422                                         hysteresis = <2000>;
4423                                         type = "hot";
4424                                 };
4425
4426                                 aoss0_crit: aoss0-crit {
4427                                         temperature = <110000>;
4428                                         hysteresis = <2000>;
4429                                         type = "critical";
4430                                 };
4431                         };
4432                 };
4433
4434                 cpuss0-thermal {
4435                         polling-delay-passive = <250>;
4436                         polling-delay = <0>;
4437
4438                         thermal-sensors = <&tsens0 7>;
4439
4440                         trips {
4441                                 cpuss0_alert0: trip-point0 {
4442                                         temperature = <90000>;
4443                                         hysteresis = <2000>;
4444                                         type = "hot";
4445                                 };
4446                                 cpuss0_crit: cluster0-crit {
4447                                         temperature = <110000>;
4448                                         hysteresis = <2000>;
4449                                         type = "critical";
4450                                 };
4451                         };
4452                 };
4453
4454                 cpuss1-thermal {
4455                         polling-delay-passive = <250>;
4456                         polling-delay = <0>;
4457
4458                         thermal-sensors = <&tsens0 8>;
4459
4460                         trips {
4461                                 cpuss1_alert0: trip-point0 {
4462                                         temperature = <90000>;
4463                                         hysteresis = <2000>;
4464                                         type = "hot";
4465                                 };
4466                                 cpuss1_crit: cluster0-crit {
4467                                         temperature = <110000>;
4468                                         hysteresis = <2000>;
4469                                         type = "critical";
4470                                 };
4471                         };
4472                 };
4473
4474                 gpuss0-thermal {
4475                         polling-delay-passive = <250>;
4476                         polling-delay = <0>;
4477
4478                         thermal-sensors = <&tsens0 13>;
4479
4480                         trips {
4481                                 gpuss0_alert0: trip-point0 {
4482                                         temperature = <95000>;
4483                                         hysteresis = <2000>;
4484                                         type = "passive";
4485                                 };
4486
4487                                 gpuss0_crit: gpuss0-crit {
4488                                         temperature = <110000>;
4489                                         hysteresis = <2000>;
4490                                         type = "critical";
4491                                 };
4492                         };
4493
4494                         cooling-maps {
4495                                 map0 {
4496                                         trip = <&gpuss0_alert0>;
4497                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4498                                 };
4499                         };
4500                 };
4501
4502                 gpuss1-thermal {
4503                         polling-delay-passive = <250>;
4504                         polling-delay = <0>;
4505
4506                         thermal-sensors = <&tsens0 14>;
4507
4508                         trips {
4509                                 gpuss1_alert0: trip-point0 {
4510                                         temperature = <95000>;
4511                                         hysteresis = <2000>;
4512                                         type = "passive";
4513                                 };
4514
4515                                 gpuss1_crit: gpuss1-crit {
4516                                         temperature = <110000>;
4517                                         hysteresis = <2000>;
4518                                         type = "critical";
4519                                 };
4520                         };
4521
4522                         cooling-maps {
4523                                 map0 {
4524                                         trip = <&gpuss1_alert0>;
4525                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4526                                 };
4527                         };
4528                 };
4529
4530                 aoss1-thermal {
4531                         polling-delay-passive = <250>;
4532                         polling-delay = <0>;
4533
4534                         thermal-sensors = <&tsens1 0>;
4535
4536                         trips {
4537                                 aoss1_alert0: trip-point0 {
4538                                         temperature = <90000>;
4539                                         hysteresis = <2000>;
4540                                         type = "hot";
4541                                 };
4542
4543                                 aoss1_crit: aoss1-crit {
4544                                         temperature = <110000>;
4545                                         hysteresis = <2000>;
4546                                         type = "critical";
4547                                 };
4548                         };
4549                 };
4550
4551                 cwlan-thermal {
4552                         polling-delay-passive = <250>;
4553                         polling-delay = <0>;
4554
4555                         thermal-sensors = <&tsens1 1>;
4556
4557                         trips {
4558                                 cwlan_alert0: trip-point0 {
4559                                         temperature = <90000>;
4560                                         hysteresis = <2000>;
4561                                         type = "hot";
4562                                 };
4563
4564                                 cwlan_crit: cwlan-crit {
4565                                         temperature = <110000>;
4566                                         hysteresis = <2000>;
4567                                         type = "critical";
4568                                 };
4569                         };
4570                 };
4571
4572                 audio-thermal {
4573                         polling-delay-passive = <250>;
4574                         polling-delay = <0>;
4575
4576                         thermal-sensors = <&tsens1 2>;
4577
4578                         trips {
4579                                 audio_alert0: trip-point0 {
4580                                         temperature = <90000>;
4581                                         hysteresis = <2000>;
4582                                         type = "hot";
4583                                 };
4584
4585                                 audio_crit: audio-crit {
4586                                         temperature = <110000>;
4587                                         hysteresis = <2000>;
4588                                         type = "critical";
4589                                 };
4590                         };
4591                 };
4592
4593                 ddr-thermal {
4594                         polling-delay-passive = <250>;
4595                         polling-delay = <0>;
4596
4597                         thermal-sensors = <&tsens1 3>;
4598
4599                         trips {
4600                                 ddr_alert0: trip-point0 {
4601                                         temperature = <90000>;
4602                                         hysteresis = <2000>;
4603                                         type = "hot";
4604                                 };
4605
4606                                 ddr_crit: ddr-crit {
4607                                         temperature = <110000>;
4608                                         hysteresis = <2000>;
4609                                         type = "critical";
4610                                 };
4611                         };
4612                 };
4613
4614                 q6-hvx-thermal {
4615                         polling-delay-passive = <250>;
4616                         polling-delay = <0>;
4617
4618                         thermal-sensors = <&tsens1 4>;
4619
4620                         trips {
4621                                 q6_hvx_alert0: trip-point0 {
4622                                         temperature = <90000>;
4623                                         hysteresis = <2000>;
4624                                         type = "hot";
4625                                 };
4626
4627                                 q6_hvx_crit: q6-hvx-crit {
4628                                         temperature = <110000>;
4629                                         hysteresis = <2000>;
4630                                         type = "critical";
4631                                 };
4632                         };
4633                 };
4634
4635                 camera-thermal {
4636                         polling-delay-passive = <250>;
4637                         polling-delay = <0>;
4638
4639                         thermal-sensors = <&tsens1 5>;
4640
4641                         trips {
4642                                 camera_alert0: trip-point0 {
4643                                         temperature = <90000>;
4644                                         hysteresis = <2000>;
4645                                         type = "hot";
4646                                 };
4647
4648                                 camera_crit: camera-crit {
4649                                         temperature = <110000>;
4650                                         hysteresis = <2000>;
4651                                         type = "critical";
4652                                 };
4653                         };
4654                 };
4655
4656                 mdm-core-thermal {
4657                         polling-delay-passive = <250>;
4658                         polling-delay = <0>;
4659
4660                         thermal-sensors = <&tsens1 6>;
4661
4662                         trips {
4663                                 mdm_alert0: trip-point0 {
4664                                         temperature = <90000>;
4665                                         hysteresis = <2000>;
4666                                         type = "hot";
4667                                 };
4668
4669                                 mdm_crit: mdm-crit {
4670                                         temperature = <110000>;
4671                                         hysteresis = <2000>;
4672                                         type = "critical";
4673                                 };
4674                         };
4675                 };
4676
4677                 mdm-dsp-thermal {
4678                         polling-delay-passive = <250>;
4679                         polling-delay = <0>;
4680
4681                         thermal-sensors = <&tsens1 7>;
4682
4683                         trips {
4684                                 mdm_dsp_alert0: trip-point0 {
4685                                         temperature = <90000>;
4686                                         hysteresis = <2000>;
4687                                         type = "hot";
4688                                 };
4689
4690                                 mdm_dsp_crit: mdm-dsp-crit {
4691                                         temperature = <110000>;
4692                                         hysteresis = <2000>;
4693                                         type = "critical";
4694                                 };
4695                         };
4696                 };
4697
4698                 npu-thermal {
4699                         polling-delay-passive = <250>;
4700                         polling-delay = <0>;
4701
4702                         thermal-sensors = <&tsens1 8>;
4703
4704                         trips {
4705                                 npu_alert0: trip-point0 {
4706                                         temperature = <90000>;
4707                                         hysteresis = <2000>;
4708                                         type = "hot";
4709                                 };
4710
4711                                 npu_crit: npu-crit {
4712                                         temperature = <110000>;
4713                                         hysteresis = <2000>;
4714                                         type = "critical";
4715                                 };
4716                         };
4717                 };
4718
4719                 video-thermal {
4720                         polling-delay-passive = <250>;
4721                         polling-delay = <0>;
4722
4723                         thermal-sensors = <&tsens1 9>;
4724
4725                         trips {
4726                                 video_alert0: trip-point0 {
4727                                         temperature = <90000>;
4728                                         hysteresis = <2000>;
4729                                         type = "hot";
4730                                 };
4731
4732                                 video_crit: video-crit {
4733                                         temperature = <110000>;
4734                                         hysteresis = <2000>;
4735                                         type = "critical";
4736                                 };
4737                         };
4738                 };
4739         };
4740
4741         timer {
4742                 compatible = "arm,armv8-timer";
4743                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4744                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4745                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4746                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4747         };
4748 };