arch/arm64/boot/dts/qcom/sa8775p.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2023, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interconnect/qcom,icc.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
  10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
  11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
  12 #include <dt-bindings/mailbox/qcom-ipcc.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         clocks {
  23                 xo_board_clk: xo-board-clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                 };
  27
  28                 sleep_clk: sleep-clk {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                 };
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 CPU0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "qcom,kryo";
  41                         reg = <0x0 0x0>;
  42                         enable-method = "psci";
  43                         qcom,freq-domain = <&cpufreq_hw 0>;
  44                         next-level-cache = <&L2_0>;
  45                         L2_0: l2-cache {
  46                                 compatible = "cache";
  47                                 cache-level = <2>;
  48                                 cache-unified;
  49                                 next-level-cache = <&L3_0>;
  50                                 L3_0: l3-cache {
  51                                         compatible = "cache";
  52                                         cache-level = <3>;
  53                                         cache-unified;
  54                                 };
  55                         };
  56                 };
  57
  58                 CPU1: cpu@100 {
  59                         device_type = "cpu";
  60                         compatible = "qcom,kryo";
  61                         reg = <0x0 0x100>;
  62                         enable-method = "psci";
  63                         qcom,freq-domain = <&cpufreq_hw 0>;
  64                         next-level-cache = <&L2_1>;
  65                         L2_1: l2-cache {
  66                                 compatible = "cache";
  67                                 cache-level = <2>;
  68                                 cache-unified;
  69                                 next-level-cache = <&L3_0>;
  70                         };
  71                 };
  72
  73                 CPU2: cpu@200 {
  74                         device_type = "cpu";
  75                         compatible = "qcom,kryo";
  76                         reg = <0x0 0x200>;
  77                         enable-method = "psci";
  78                         qcom,freq-domain = <&cpufreq_hw 0>;
  79                         next-level-cache = <&L2_2>;
  80                         L2_2: l2-cache {
  81                                 compatible = "cache";
  82                                 cache-level = <2>;
  83                                 cache-unified;
  84                                 next-level-cache = <&L3_0>;
  85                         };
  86                 };
  87
  88                 CPU3: cpu@300 {
  89                         device_type = "cpu";
  90                         compatible = "qcom,kryo";
  91                         reg = <0x0 0x300>;
  92                         enable-method = "psci";
  93                         qcom,freq-domain = <&cpufreq_hw 0>;
  94                         next-level-cache = <&L2_3>;
  95                         L2_3: l2-cache {
  96                                 compatible = "cache";
  97                                 cache-level = <2>;
  98                                 cache-unified;
  99                                 next-level-cache = <&L3_0>;
 100                         };
 101                 };
 102
 103                 CPU4: cpu@10000 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo";
 106                         reg = <0x0 0x10000>;
 107                         enable-method = "psci";
 108                         qcom,freq-domain = <&cpufreq_hw 1>;
 109                         next-level-cache = <&L2_4>;
 110                         L2_4: l2-cache {
 111                                 compatible = "cache";
 112                                 cache-level = <2>;
 113                                 cache-unified;
 114                                 next-level-cache = <&L3_1>;
 115                                 L3_1: l3-cache {
 116                                         compatible = "cache";
 117                                         cache-level = <3>;
 118                                         cache-unified;
 119                                 };
 120
 121                         };
 122                 };
 123
 124                 CPU5: cpu@10100 {
 125                         device_type = "cpu";
 126                         compatible = "qcom,kryo";
 127                         reg = <0x0 0x10100>;
 128                         enable-method = "psci";
 129                         qcom,freq-domain = <&cpufreq_hw 1>;
 130                         next-level-cache = <&L2_5>;
 131                         L2_5: l2-cache {
 132                                 compatible = "cache";
 133                                 cache-level = <2>;
 134                                 cache-unified;
 135                                 next-level-cache = <&L3_1>;
 136                         };
 137                 };
 138
 139                 CPU6: cpu@10200 {
 140                         device_type = "cpu";
 141                         compatible = "qcom,kryo";
 142                         reg = <0x0 0x10200>;
 143                         enable-method = "psci";
 144                         qcom,freq-domain = <&cpufreq_hw 1>;
 145                         next-level-cache = <&L2_6>;
 146                         L2_6: l2-cache {
 147                                 compatible = "cache";
 148                                 cache-level = <2>;
 149                                 cache-unified;
 150                                 next-level-cache = <&L3_1>;
 151                         };
 152                 };
 153
 154                 CPU7: cpu@10300 {
 155                         device_type = "cpu";
 156                         compatible = "qcom,kryo";
 157                         reg = <0x0 0x10300>;
 158                         enable-method = "psci";
 159                         qcom,freq-domain = <&cpufreq_hw 1>;
 160                         next-level-cache = <&L2_7>;
 161                         L2_7: l2-cache {
 162                                 compatible = "cache";
 163                                 cache-level = <2>;
 164                                 cache-unified;
 165                                 next-level-cache = <&L3_1>;
 166                         };
 167                 };
 168
 169                 cpu-map {
 170                         cluster0 {
 171                                 core0 {
 172                                         cpu = <&CPU0>;
 173                                 };
 174
 175                                 core1 {
 176                                         cpu = <&CPU1>;
 177                                 };
 178
 179                                 core2 {
 180                                         cpu = <&CPU2>;
 181                                 };
 182
 183                                 core3 {
 184                                         cpu = <&CPU3>;
 185                                 };
 186                         };
 187
 188                         cluster1 {
 189                                 core0 {
 190                                         cpu = <&CPU4>;
 191                                 };
 192
 193                                 core1 {
 194                                         cpu = <&CPU5>;
 195                                 };
 196
 197                                 core2 {
 198                                         cpu = <&CPU6>;
 199                                 };
 200
 201                                 core3 {
 202                                         cpu = <&CPU7>;
 203                                 };
 204                         };
 205                 };
 206         };
 207
 208         firmware {
 209                 scm {
 210                         compatible = "qcom,scm-sa8775p", "qcom,scm";
 211                 };
 212         };
 213
 214         aggre1_noc: interconnect-aggre1-noc {
 215                 compatible = "qcom,sa8775p-aggre1-noc";
 216                 #interconnect-cells = <2>;
 217                 qcom,bcm-voters = <&apps_bcm_voter>;
 218         };
 219
 220         aggre2_noc: interconnect-aggre2-noc {
 221                 compatible = "qcom,sa8775p-aggre2-noc";
 222                 #interconnect-cells = <2>;
 223                 qcom,bcm-voters = <&apps_bcm_voter>;
 224         };
 225
 226         clk_virt: interconnect-clk-virt {
 227                 compatible = "qcom,sa8775p-clk-virt";
 228                 #interconnect-cells = <2>;
 229                 qcom,bcm-voters = <&apps_bcm_voter>;
 230         };
 231
 232         config_noc: interconnect-config-noc {
 233                 compatible = "qcom,sa8775p-config-noc";
 234                 #interconnect-cells = <2>;
 235                 qcom,bcm-voters = <&apps_bcm_voter>;
 236         };
 237
 238         dc_noc: interconnect-dc-noc {
 239                 compatible = "qcom,sa8775p-dc-noc";
 240                 #interconnect-cells = <2>;
 241                 qcom,bcm-voters = <&apps_bcm_voter>;
 242         };
 243
 244         gem_noc: interconnect-gem-noc {
 245                 compatible = "qcom,sa8775p-gem-noc";
 246                 #interconnect-cells = <2>;
 247                 qcom,bcm-voters = <&apps_bcm_voter>;
 248         };
 249
 250         gpdsp_anoc: interconnect-gpdsp-anoc {
 251                 compatible = "qcom,sa8775p-gpdsp-anoc";
 252                 #interconnect-cells = <2>;
 253                 qcom,bcm-voters = <&apps_bcm_voter>;
 254         };
 255
 256         lpass_ag_noc: interconnect-lpass-ag-noc {
 257                 compatible = "qcom,sa8775p-lpass-ag-noc";
 258                 #interconnect-cells = <2>;
 259                 qcom,bcm-voters = <&apps_bcm_voter>;
 260         };
 261
 262         mc_virt: interconnect-mc-virt {
 263                 compatible = "qcom,sa8775p-mc-virt";
 264                 #interconnect-cells = <2>;
 265                 qcom,bcm-voters = <&apps_bcm_voter>;
 266         };
 267
 268         mmss_noc: interconnect-mmss-noc {
 269                 compatible = "qcom,sa8775p-mmss-noc";
 270                 #interconnect-cells = <2>;
 271                 qcom,bcm-voters = <&apps_bcm_voter>;
 272         };
 273
 274         nspa_noc: interconnect-nspa-noc {
 275                 compatible = "qcom,sa8775p-nspa-noc";
 276                 #interconnect-cells = <2>;
 277                 qcom,bcm-voters = <&apps_bcm_voter>;
 278         };
 279
 280         nspb_noc: interconnect-nspb-noc {
 281                 compatible = "qcom,sa8775p-nspb-noc";
 282                 #interconnect-cells = <2>;
 283                 qcom,bcm-voters = <&apps_bcm_voter>;
 284         };
 285
 286         pcie_anoc: interconnect-pcie-anoc {
 287                 compatible = "qcom,sa8775p-pcie-anoc";
 288                 #interconnect-cells = <2>;
 289                 qcom,bcm-voters = <&apps_bcm_voter>;
 290         };
 291
 292         system_noc: interconnect-system-noc {
 293                 compatible = "qcom,sa8775p-system-noc";
 294                 #interconnect-cells = <2>;
 295                 qcom,bcm-voters = <&apps_bcm_voter>;
 296         };
 297
 298         /* Will be updated by the bootloader. */
 299         memory@80000000 {
 300                 device_type = "memory";
 301                 reg = <0x0 0x80000000 0x0 0x0>;
 302         };
 303
 304         qup_opp_table_100mhz: opp-table-qup100mhz {
 305                 compatible = "operating-points-v2";
 306
 307                 opp-100000000 {
 308                         opp-hz = /bits/ 64 <100000000>;
 309                         required-opps = <&rpmhpd_opp_svs_l1>;
 310                 };
 311         };
 312
 313         pmu {
 314                 compatible = "arm,armv8-pmuv3";
 315                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 316         };
 317
 318         psci {
 319                 compatible = "arm,psci-1.0";
 320                 method = "smc";
 321         };
 322
 323         reserved-memory {
 324                 #address-cells = <2>;
 325                 #size-cells = <2>;
 326                 ranges;
 327
 328                 sail_ss_mem: sail-ss@80000000 {
 329                         reg = <0x0 0x80000000 0x0 0x10000000>;
 330                         no-map;
 331                 };
 332
 333                 hyp_mem: hyp@90000000 {
 334                         reg = <0x0 0x90000000 0x0 0x600000>;
 335                         no-map;
 336                 };
 337
 338                 xbl_boot_mem: xbl-boot@90600000 {
 339                         reg = <0x0 0x90600000 0x0 0x200000>;
 340                         no-map;
 341                 };
 342
 343                 aop_image_mem: aop-image@90800000 {
 344                         reg = <0x0 0x90800000 0x0 0x60000>;
 345                         no-map;
 346                 };
 347
 348                 aop_cmd_db_mem: aop-cmd-db@90860000 {
 349                         compatible = "qcom,cmd-db";
 350                         reg = <0x0 0x90860000 0x0 0x20000>;
 351                         no-map;
 352                 };
 353
 354                 uefi_log: uefi-log@908b0000 {
 355                         reg = <0x0 0x908b0000 0x0 0x10000>;
 356                         no-map;
 357                 };
 358
 359                 reserved_mem: reserved@908f0000 {
 360                         reg = <0x0 0x908f0000 0x0 0xf000>;
 361                         no-map;
 362                 };
 363
 364                 secdata_apss_mem: secdata-apss@908ff000 {
 365                         reg = <0x0 0x908ff000 0x0 0x1000>;
 366                         no-map;
 367                 };
 368
 369                 smem_mem: smem@90900000 {
 370                         compatible = "qcom,smem";
 371                         reg = <0x0 0x90900000 0x0 0x200000>;
 372                         no-map;
 373                         hwlocks = <&tcsr_mutex 3>;
 374                 };
 375
 376                 cpucp_fw_mem: cpucp-fw@90b00000 {
 377                         reg = <0x0 0x90b00000 0x0 0x100000>;
 378                         no-map;
 379                 };
 380
 381                 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
 382                         reg = <0x0 0x93b00000 0x0 0xf00000>;
 383                         no-map;
 384                 };
 385
 386                 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
 387                         reg = <0x0 0x94a00000 0x0 0x800000>;
 388                         no-map;
 389                 };
 390
 391                 pil_camera_mem: pil-camera@95200000 {
 392                         reg = <0x0 0x95200000 0x0 0x500000>;
 393                         no-map;
 394                 };
 395
 396                 pil_adsp_mem: pil-adsp@95c00000 {
 397                         reg = <0x0 0x95c00000 0x0 0x1e00000>;
 398                         no-map;
 399                 };
 400
 401                 pil_gdsp0_mem: pil-gdsp0@97b00000 {
 402                         reg = <0x0 0x97b00000 0x0 0x1e00000>;
 403                         no-map;
 404                 };
 405
 406                 pil_gdsp1_mem: pil-gdsp1@99900000 {
 407                         reg = <0x0 0x99900000 0x0 0x1e00000>;
 408                         no-map;
 409                 };
 410
 411                 pil_cdsp0_mem: pil-cdsp0@9b800000 {
 412                         reg = <0x0 0x9b800000 0x0 0x1e00000>;
 413                         no-map;
 414                 };
 415
 416                 pil_gpu_mem: pil-gpu@9d600000 {
 417                         reg = <0x0 0x9d600000 0x0 0x2000>;
 418                         no-map;
 419                 };
 420
 421                 pil_cdsp1_mem: pil-cdsp1@9d700000 {
 422                         reg = <0x0 0x9d700000 0x0 0x1e00000>;
 423                         no-map;
 424                 };
 425
 426                 pil_cvp_mem: pil-cvp@9f500000 {
 427                         reg = <0x0 0x9f500000 0x0 0x700000>;
 428                         no-map;
 429                 };
 430
 431                 pil_video_mem: pil-video@9fc00000 {
 432                         reg = <0x0 0x9fc00000 0x0 0x700000>;
 433                         no-map;
 434                 };
 435
 436                 hyptz_reserved_mem: hyptz-reserved@beb00000 {
 437                         reg = <0x0 0xbeb00000 0x0 0x11500000>;
 438                         no-map;
 439                 };
 440
 441                 tz_stat_mem: tz-stat@d0000000 {
 442                         reg = <0x0 0xd0000000 0x0 0x100000>;
 443                         no-map;
 444                 };
 445
 446                 tags_mem: tags@d0100000 {
 447                         reg = <0x0 0xd0100000 0x0 0x1200000>;
 448                         no-map;
 449                 };
 450
 451                 qtee_mem: qtee@d1300000 {
 452                         reg = <0x0 0xd1300000 0x0 0x500000>;
 453                         no-map;
 454                 };
 455
 456                 trusted_apps_mem: trusted-apps@d1800000 {
 457                         reg = <0x0 0xd1800000 0x0 0x3900000>;
 458                         no-map;
 459                 };
 460         };
 461
 462         soc: soc@0 {
 463                 compatible = "simple-bus";
 464                 #address-cells = <2>;
 465                 #size-cells = <2>;
 466                 ranges = <0 0 0 0 0x10 0>;
 467
 468                 gcc: clock-controller@100000 {
 469                         compatible = "qcom,sa8775p-gcc";
 470                         reg = <0x0 0x00100000 0x0 0xc7018>;
 471                         #clock-cells = <1>;
 472                         #reset-cells = <1>;
 473                         #power-domain-cells = <1>;
 474                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 475                                  <&sleep_clk>,
 476                                  <0>,
 477                                  <0>,
 478                                  <0>,
 479                                  <&usb_0_qmpphy>,
 480                                  <&usb_1_qmpphy>,
 481                                  <0>,
 482                                  <0>,
 483                                  <0>,
 484                                  <&pcie0_phy>,
 485                                  <&pcie1_phy>,
 486                                  <0>,
 487                                  <0>,
 488                                  <0>;
 489                         power-domains = <&rpmhpd SA8775P_CX>;
 490                 };
 491
 492                 ipcc: mailbox@408000 {
 493                         compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
 494                         reg = <0x0 0x00408000 0x0 0x1000>;
 495                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 496                         interrupt-controller;
 497                         #interrupt-cells = <3>;
 498                         #mbox-cells = <2>;
 499                 };
 500
 501                 qupv3_id_2: geniqup@8c0000 {
 502                         compatible = "qcom,geni-se-qup";
 503                         reg = <0x0 0x008c0000 0x0 0x6000>;
 504                         ranges;
 505                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 506                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 507                         clock-names = "m-ahb", "s-ahb";
 508                         iommus = <&apps_smmu 0x5a3 0x0>;
 509                         #address-cells = <2>;
 510                         #size-cells = <2>;
 511                         status = "disabled";
 512
 513                         i2c14: i2c@880000 {
 514                                 compatible = "qcom,geni-i2c";
 515                                 reg = <0x0 0x880000 0x0 0x4000>;
 516                                 #address-cells = <1>;
 517                                 #size-cells = <0>;
 518                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 519                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 520                                 clock-names = "se";
 521                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 522                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 523                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 524                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 525                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 526                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 527                                 interconnect-names = "qup-core",
 528                                                      "qup-config",
 529                                                      "qup-memory";
 530                                 power-domains = <&rpmhpd SA8775P_CX>;
 531                                 status = "disabled";
 532                         };
 533
 534                         spi14: spi@880000 {
 535                                 compatible = "qcom,geni-spi";
 536                                 reg = <0x0 0x880000 0x0 0x4000>;
 537                                 #address-cells = <1>;
 538                                 #size-cells = <0>;
 539                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 540                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 541                                 clock-names = "se";
 542                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 543                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 544                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 545                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 546                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 547                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 548                                 interconnect-names = "qup-core",
 549                                                      "qup-config",
 550                                                      "qup-memory";
 551                                 power-domains = <&rpmhpd SA8775P_CX>;
 552                                 status = "disabled";
 553                         };
 554
 555                         i2c15: i2c@884000 {
 556                                 compatible = "qcom,geni-i2c";
 557                                 reg = <0x0 0x884000 0x0 0x4000>;
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 561                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 562                                 clock-names = "se";
 563                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 564                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 565                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 566                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 567                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 568                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 569                                 interconnect-names = "qup-core",
 570                                                      "qup-config",
 571                                                      "qup-memory";
 572                                 power-domains = <&rpmhpd SA8775P_CX>;
 573                                 status = "disabled";
 574                         };
 575
 576                         spi15: spi@884000 {
 577                                 compatible = "qcom,geni-spi";
 578                                 reg = <0x0 0x884000 0x0 0x4000>;
 579                                 #address-cells = <1>;
 580                                 #size-cells = <0>;
 581                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 582                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 583                                 clock-names = "se";
 584                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 585                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 586                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 587                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 588                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 589                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 590                                 interconnect-names = "qup-core",
 591                                                      "qup-config",
 592                                                      "qup-memory";
 593                                 power-domains = <&rpmhpd SA8775P_CX>;
 594                                 status = "disabled";
 595                         };
 596
 597                         i2c16: i2c@888000 {
 598                                 compatible = "qcom,geni-i2c";
 599                                 reg = <0x0 0x888000 0x0 0x4000>;
 600                                 #address-cells = <1>;
 601                                 #size-cells = <0>;
 602                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 603                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 604                                 clock-names = "se";
 605                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 606                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 607                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 608                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 609                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 610                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 611                                 interconnect-names = "qup-core",
 612                                                      "qup-config",
 613                                                      "qup-memory";
 614                                 power-domains = <&rpmhpd SA8775P_CX>;
 615                                 status = "disabled";
 616                         };
 617
 618                         spi16: spi@888000 {
 619                                 compatible = "qcom,geni-spi";
 620                                 reg = <0x0 0x00888000 0x0 0x4000>;
 621                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 622                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 623                                 clock-names = "se";
 624                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 625                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 626                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 627                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 628                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 629                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 630                                 interconnect-names = "qup-core",
 631                                                      "qup-config",
 632                                                      "qup-memory";
 633                                 power-domains = <&rpmhpd SA8775P_CX>;
 634                                 #address-cells = <1>;
 635                                 #size-cells = <0>;
 636                                 status = "disabled";
 637                         };
 638
 639                         i2c17: i2c@88c000 {
 640                                 compatible = "qcom,geni-i2c";
 641                                 reg = <0x0 0x88c000 0x0 0x4000>;
 642                                 #address-cells = <1>;
 643                                 #size-cells = <0>;
 644                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 645                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 646                                 clock-names = "se";
 647                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 648                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 649                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 650                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 651                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 652                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 653                                 interconnect-names = "qup-core",
 654                                                      "qup-config",
 655                                                      "qup-memory";
 656                                 power-domains = <&rpmhpd SA8775P_CX>;
 657                                 status = "disabled";
 658                         };
 659
 660                         spi17: spi@88c000 {
 661                                 compatible = "qcom,geni-spi";
 662                                 reg = <0x0 0x88c000 0x0 0x4000>;
 663                                 #address-cells = <1>;
 664                                 #size-cells = <0>;
 665                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 666                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 667                                 clock-names = "se";
 668                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 669                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 670                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 671                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 672                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 673                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 674                                 interconnect-names = "qup-core",
 675                                                      "qup-config",
 676                                                      "qup-memory";
 677                                 power-domains = <&rpmhpd SA8775P_CX>;
 678                                 status = "disabled";
 679                         };
 680
 681                         uart17: serial@88c000 {
 682                                 compatible = "qcom,geni-uart";
 683                                 reg = <0x0 0x0088c000 0x0 0x4000>;
 684                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 685                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 686                                 clock-names = "se";
 687                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 688                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 689                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 690                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
 691                                 interconnect-names = "qup-core", "qup-config";
 692                                 power-domains = <&rpmhpd SA8775P_CX>;
 693                                 status = "disabled";
 694                         };
 695
 696                         i2c18: i2c@890000 {
 697                                 compatible = "qcom,geni-i2c";
 698                                 reg = <0x0 0x00890000 0x0 0x4000>;
 699                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 700                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 701                                 clock-names = "se";
 702                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 703                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 704                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 705                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 706                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 707                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 708                                 interconnect-names = "qup-core",
 709                                                      "qup-config",
 710                                                      "qup-memory";
 711                                 power-domains = <&rpmhpd SA8775P_CX>;
 712                                 #address-cells = <1>;
 713                                 #size-cells = <0>;
 714                                 status = "disabled";
 715                         };
 716
 717                         spi18: spi@890000 {
 718                                 compatible = "qcom,geni-spi";
 719                                 reg = <0x0 0x890000 0x0 0x4000>;
 720                                 #address-cells = <1>;
 721                                 #size-cells = <0>;
 722                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 723                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 724                                 clock-names = "se";
 725                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 726                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 727                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 728                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 729                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 730                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 731                                 interconnect-names = "qup-core",
 732                                                      "qup-config",
 733                                                      "qup-memory";
 734                                 power-domains = <&rpmhpd SA8775P_CX>;
 735                                 status = "disabled";
 736                         };
 737
 738                         i2c19: i2c@894000 {
 739                                 compatible = "qcom,geni-i2c";
 740                                 reg = <0x0 0x894000 0x0 0x4000>;
 741                                 #address-cells = <1>;
 742                                 #size-cells = <0>;
 743                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 744                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 745                                 clock-names = "se";
 746                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 747                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 748                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 749                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 750                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 751                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 752                                 interconnect-names = "qup-core",
 753                                                      "qup-config",
 754                                                      "qup-memory";
 755                                 power-domains = <&rpmhpd SA8775P_CX>;
 756                                 status = "disabled";
 757                         };
 758
 759                         spi19: spi@894000 {
 760                                 compatible = "qcom,geni-spi";
 761                                 reg = <0x0 0x894000 0x0 0x4000>;
 762                                 #address-cells = <1>;
 763                                 #size-cells = <0>;
 764                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 765                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 766                                 clock-names = "se";
 767                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 768                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 769                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 770                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 771                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 772                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 773                                 interconnect-names = "qup-core",
 774                                                      "qup-config",
 775                                                      "qup-memory";
 776                                 power-domains = <&rpmhpd SA8775P_CX>;
 777                                 status = "disabled";
 778                         };
 779
 780                         i2c20: i2c@898000 {
 781                                 compatible = "qcom,geni-i2c";
 782                                 reg = <0x0 0x898000 0x0 0x4000>;
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
 786                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
 787                                 clock-names = "se";
 788                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 789                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 790                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 791                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 792                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 793                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 794                                 interconnect-names = "qup-core",
 795                                                      "qup-config",
 796                                                      "qup-memory";
 797                                 power-domains = <&rpmhpd SA8775P_CX>;
 798                                 status = "disabled";
 799                         };
 800
 801                         spi20: spi@898000 {
 802                                 compatible = "qcom,geni-spi";
 803                                 reg = <0x0 0x898000 0x0 0x4000>;
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
 808                                 clock-names = "se";
 809                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 810                                                  &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 811                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 812                                                  &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
 813                                                 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 814                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 815                                 interconnect-names = "qup-core",
 816                                                      "qup-config",
 817                                                      "qup-memory";
 818                                 power-domains = <&rpmhpd SA8775P_CX>;
 819                                 status = "disabled";
 820                         };
 821                 };
 822
 823                 qupv3_id_0: geniqup@9c0000 {
 824                         compatible = "qcom,geni-se-qup";
 825                         reg = <0x0 0x9c0000 0x0 0x6000>;
 826                         #address-cells = <2>;
 827                         #size-cells = <2>;
 828                         ranges;
 829                         clock-names = "m-ahb", "s-ahb";
 830                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 831                                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 832                         iommus = <&apps_smmu 0x403 0x0>;
 833                         status = "disabled";
 834
 835                         i2c0: i2c@980000 {
 836                                 compatible = "qcom,geni-i2c";
 837                                 reg = <0x0 0x980000 0x0 0x4000>;
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
 841                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 842                                 clock-names = "se";
 843                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 844                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 845                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 846                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 847                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 848                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 849                                 interconnect-names = "qup-core",
 850                                                      "qup-config",
 851                                                      "qup-memory";
 852                                 power-domains = <&rpmhpd SA8775P_CX>;
 853                                 status = "disabled";
 854                         };
 855
 856                         spi0: spi@980000 {
 857                                 compatible = "qcom,geni-spi";
 858                                 reg = <0x0 0x980000 0x0 0x4000>;
 859                                 #address-cells = <1>;
 860                                 #size-cells = <0>;
 861                                 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
 862                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 863                                 clock-names = "se";
 864                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 865                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 866                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 867                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 868                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 869                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 870                                 interconnect-names = "qup-core",
 871                                                      "qup-config",
 872                                                      "qup-memory";
 873                                 power-domains = <&rpmhpd SA8775P_CX>;
 874                                 status = "disabled";
 875                         };
 876
 877                         i2c1: i2c@984000 {
 878                                 compatible = "qcom,geni-i2c";
 879                                 reg = <0x0 0x984000 0x0 0x4000>;
 880                                 #address-cells = <1>;
 881                                 #size-cells = <0>;
 882                                 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
 883                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 884                                 clock-names = "se";
 885                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 886                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 887                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 888                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 889                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 890                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 891                                 interconnect-names = "qup-core",
 892                                                      "qup-config",
 893                                                      "qup-memory";
 894                                 power-domains = <&rpmhpd SA8775P_CX>;
 895                                 status = "disabled";
 896                         };
 897
 898                         spi1: spi@984000 {
 899                                 compatible = "qcom,geni-spi";
 900                                 reg = <0x0 0x984000 0x0 0x4000>;
 901                                 #address-cells = <1>;
 902                                 #size-cells = <0>;
 903                                 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
 904                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 905                                 clock-names = "se";
 906                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 907                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 908                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 909                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 910                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 911                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 912                                 interconnect-names = "qup-core",
 913                                                      "qup-config",
 914                                                      "qup-memory";
 915                                 power-domains = <&rpmhpd SA8775P_CX>;
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c2: i2c@988000 {
 920                                 compatible = "qcom,geni-i2c";
 921                                 reg = <0x0 0x988000 0x0 0x4000>;
 922                                 #address-cells = <1>;
 923                                 #size-cells = <0>;
 924                                 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
 925                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 926                                 clock-names = "se";
 927                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 928                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 929                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 930                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 931                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 932                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 933                                 interconnect-names = "qup-core",
 934                                                      "qup-config",
 935                                                      "qup-memory";
 936                                 power-domains = <&rpmhpd SA8775P_CX>;
 937                                 status = "disabled";
 938                         };
 939
 940                         spi2: spi@988000 {
 941                                 compatible = "qcom,geni-spi";
 942                                 reg = <0x0 0x988000 0x0 0x4000>;
 943                                 #address-cells = <1>;
 944                                 #size-cells = <0>;
 945                                 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
 946                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 947                                 clock-names = "se";
 948                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 949                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 950                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 951                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 952                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 953                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 954                                 interconnect-names = "qup-core",
 955                                                      "qup-config",
 956                                                      "qup-memory";
 957                                 power-domains = <&rpmhpd SA8775P_CX>;
 958                                 status = "disabled";
 959                         };
 960
 961                         i2c3: i2c@98c000 {
 962                                 compatible = "qcom,geni-i2c";
 963                                 reg = <0x0 0x98c000 0x0 0x4000>;
 964                                 #address-cells = <1>;
 965                                 #size-cells = <0>;
 966                                 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
 967                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 968                                 clock-names = "se";
 969                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 970                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 971                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 972                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 973                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 974                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 975                                 interconnect-names = "qup-core",
 976                                                      "qup-config",
 977                                                      "qup-memory";
 978                                 power-domains = <&rpmhpd SA8775P_CX>;
 979                                 status = "disabled";
 980                         };
 981
 982                         spi3: spi@98c000 {
 983                                 compatible = "qcom,geni-spi";
 984                                 reg = <0x0 0x98c000 0x0 0x4000>;
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
 988                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 989                                 clock-names = "se";
 990                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 991                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 992                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 993                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 994                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 995                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 996                                 interconnect-names = "qup-core",
 997                                                      "qup-config",
 998                                                      "qup-memory";
 999                                 power-domains = <&rpmhpd SA8775P_CX>;
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c4: i2c@990000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0x0 0x990000 0x0 0x4000>;
1006                                 #address-cells = <1>;
1007                                 #size-cells = <0>;
1008                                 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1009                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1010                                 clock-names = "se";
1011                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1012                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1013                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1014                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1015                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1016                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1017                                 interconnect-names = "qup-core",
1018                                                      "qup-config",
1019                                                      "qup-memory";
1020                                 power-domains = <&rpmhpd SA8775P_CX>;
1021                                 status = "disabled";
1022                         };
1023
1024                         spi4: spi@990000 {
1025                                 compatible = "qcom,geni-spi";
1026                                 reg = <0x0 0x990000 0x0 0x4000>;
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029                                 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1030                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1031                                 clock-names = "se";
1032                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1033                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1034                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1035                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1036                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1037                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1038                                 interconnect-names = "qup-core",
1039                                                      "qup-config",
1040                                                      "qup-memory";
1041                                 power-domains = <&rpmhpd SA8775P_CX>;
1042                                 status = "disabled";
1043                         };
1044
1045                         i2c5: i2c@994000 {
1046                                 compatible = "qcom,geni-i2c";
1047                                 reg = <0x0 0x994000 0x0 0x4000>;
1048                                 #address-cells = <1>;
1049                                 #size-cells = <0>;
1050                                 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1051                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1052                                 clock-names = "se";
1053                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1054                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1055                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1056                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1057                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1058                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1059                                 interconnect-names = "qup-core",
1060                                                      "qup-config",
1061                                                      "qup-memory";
1062                                 power-domains = <&rpmhpd SA8775P_CX>;
1063                                 status = "disabled";
1064                         };
1065
1066                         spi5: spi@994000 {
1067                                 compatible = "qcom,geni-spi";
1068                                 reg = <0x0 0x994000 0x0 0x4000>;
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1072                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1073                                 clock-names = "se";
1074                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1075                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1076                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1077                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1078                                                 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1079                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1080                                 interconnect-names = "qup-core",
1081                                                      "qup-config",
1082                                                      "qup-memory";
1083                                 power-domains = <&rpmhpd SA8775P_CX>;
1084                                 status = "disabled";
1085                         };
1086
1087                         uart5: serial@994000 {
1088                                 compatible = "qcom,geni-uart";
1089                                 reg = <0x0 0x994000 0x0 0x4000>;
1090                                 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1091                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1092                                 clock-names = "se";
1093                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1094                                                  &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1095                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1096                                                  &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1097                                 interconnect-names = "qup-core", "qup-config";
1098                                 power-domains = <&rpmhpd SA8775P_CX>;
1099                                 status = "disabled";
1100                         };
1101                 };
1102
1103                 qupv3_id_1: geniqup@ac0000 {
1104                         compatible = "qcom,geni-se-qup";
1105                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1106                         #address-cells = <2>;
1107                         #size-cells = <2>;
1108                         ranges;
1109                         clock-names = "m-ahb", "s-ahb";
1110                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1111                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1112                         iommus = <&apps_smmu 0x443 0x0>;
1113                         status = "disabled";
1114
1115                         i2c7: i2c@a80000 {
1116                                 compatible = "qcom,geni-i2c";
1117                                 reg = <0x0 0xa80000 0x0 0x4000>;
1118                                 #address-cells = <1>;
1119                                 #size-cells = <0>;
1120                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1121                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1122                                 clock-names = "se";
1123                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1124                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1125                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1126                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1127                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1128                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1129                                 interconnect-names = "qup-core",
1130                                                      "qup-config",
1131                                                      "qup-memory";
1132                                 power-domains = <&rpmhpd SA8775P_CX>;
1133                                 status = "disabled";
1134                         };
1135
1136                         spi7: spi@a80000 {
1137                                 compatible = "qcom,geni-spi";
1138                                 reg = <0x0 0xa80000 0x0 0x4000>;
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1142                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1143                                 clock-names = "se";
1144                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1145                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1146                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1147                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1148                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1149                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1150                                 interconnect-names = "qup-core",
1151                                                      "qup-config",
1152                                                      "qup-memory";
1153                                 power-domains = <&rpmhpd SA8775P_CX>;
1154                                 status = "disabled";
1155                         };
1156
1157                         i2c8: i2c@a84000 {
1158                                 compatible = "qcom,geni-i2c";
1159                                 reg = <0x0 0xa84000 0x0 0x4000>;
1160                                 #address-cells = <1>;
1161                                 #size-cells = <0>;
1162                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1163                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1164                                 clock-names = "se";
1165                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1166                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1167                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1168                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1169                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1170                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1171                                 interconnect-names = "qup-core",
1172                                                      "qup-config",
1173                                                      "qup-memory";
1174                                 power-domains = <&rpmhpd SA8775P_CX>;
1175                                 status = "disabled";
1176                         };
1177
1178                         spi8: spi@a84000 {
1179                                 compatible = "qcom,geni-spi";
1180                                 reg = <0x0 0xa84000 0x0 0x4000>;
1181                                 #address-cells = <1>;
1182                                 #size-cells = <0>;
1183                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1184                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1185                                 clock-names = "se";
1186                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1187                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1188                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1189                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1190                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1191                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1192                                 interconnect-names = "qup-core",
1193                                                      "qup-config",
1194                                                      "qup-memory";
1195                                 power-domains = <&rpmhpd SA8775P_CX>;
1196                                 status = "disabled";
1197                         };
1198
1199                         i2c9: i2c@a88000 {
1200                                 compatible = "qcom,geni-i2c";
1201                                 reg = <0x0 0xa88000 0x0 0x4000>;
1202                                 #address-cells = <1>;
1203                                 #size-cells = <0>;
1204                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1205                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1206                                 clock-names = "se";
1207                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1208                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1209                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1210                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1211                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1212                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1213                                 interconnect-names = "qup-core",
1214                                                      "qup-config",
1215                                                      "qup-memory";
1216                                 power-domains = <&rpmhpd SA8775P_CX>;
1217                                 status = "disabled";
1218                         };
1219
1220                         spi9: spi@a88000 {
1221                                 compatible = "qcom,geni-spi";
1222                                 reg = <0x0 0xa88000 0x0 0x4000>;
1223                                 #address-cells = <1>;
1224                                 #size-cells = <0>;
1225                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1226                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1227                                 clock-names = "se";
1228                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1229                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1230                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1231                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1232                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1233                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1234                                 interconnect-names = "qup-core",
1235                                                      "qup-config",
1236                                                      "qup-memory";
1237                                 power-domains = <&rpmhpd SA8775P_CX>;
1238                                 status = "disabled";
1239                         };
1240
1241                         uart9: serial@a88000 {
1242                                 compatible = "qcom,geni-uart";
1243                                 reg = <0x0 0xa88000 0x0 0x4000>;
1244                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1245                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1246                                 clock-names = "se";
1247                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1248                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1249                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1250                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1251                                 interconnect-names = "qup-core", "qup-config";
1252                                 power-domains = <&rpmhpd SA8775P_CX>;
1253                                 status = "disabled";
1254                         };
1255
1256                         i2c10: i2c@a8c000 {
1257                                 compatible = "qcom,geni-i2c";
1258                                 reg = <0x0 0xa8c000 0x0 0x4000>;
1259                                 #address-cells = <1>;
1260                                 #size-cells = <0>;
1261                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1262                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1263                                 clock-names = "se";
1264                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1265                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1266                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1267                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1268                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1269                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1270                                 interconnect-names = "qup-core",
1271                                                      "qup-config",
1272                                                      "qup-memory";
1273                                 power-domains = <&rpmhpd SA8775P_CX>;
1274                                 status = "disabled";
1275                         };
1276
1277                         spi10: spi@a8c000 {
1278                                 compatible = "qcom,geni-spi";
1279                                 reg = <0x0 0xa8c000 0x0 0x4000>;
1280                                 #address-cells = <1>;
1281                                 #size-cells = <0>;
1282                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1283                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1284                                 clock-names = "se";
1285                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1286                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1287                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1288                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1289                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1290                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1291                                 interconnect-names = "qup-core",
1292                                                      "qup-config",
1293                                                      "qup-memory";
1294                                 power-domains = <&rpmhpd SA8775P_CX>;
1295                                 status = "disabled";
1296                         };
1297
1298                         uart10: serial@a8c000 {
1299                                 compatible = "qcom,geni-uart";
1300                                 reg = <0x0 0x00a8c000 0x0 0x4000>;
1301                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1302                                 clock-names = "se";
1303                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1304                                 interconnect-names = "qup-core", "qup-config";
1305                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1306                                                  &clk_virt SLAVE_QUP_CORE_1 0>,
1307                                                 <&gem_noc MASTER_APPSS_PROC 0
1308                                                  &config_noc SLAVE_QUP_1 0>;
1309                                 power-domains = <&rpmhpd SA8775P_CX>;
1310                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1311                                 status = "disabled";
1312                         };
1313
1314                         i2c11: i2c@a90000 {
1315                                 compatible = "qcom,geni-i2c";
1316                                 reg = <0x0 0xa90000 0x0 0x4000>;
1317                                 #address-cells = <1>;
1318                                 #size-cells = <0>;
1319                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1320                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1321                                 clock-names = "se";
1322                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1323                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1324                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1325                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1326                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1327                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1328                                 interconnect-names = "qup-core",
1329                                                      "qup-config",
1330                                                      "qup-memory";
1331                                 power-domains = <&rpmhpd SA8775P_CX>;
1332                                 status = "disabled";
1333                         };
1334
1335                         spi11: spi@a90000 {
1336                                 compatible = "qcom,geni-spi";
1337                                 reg = <0x0 0xa90000 0x0 0x4000>;
1338                                 #address-cells = <1>;
1339                                 #size-cells = <0>;
1340                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1341                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1342                                 clock-names = "se";
1343                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1344                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1345                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1346                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1347                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1348                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1349                                 interconnect-names = "qup-core",
1350                                                      "qup-config",
1351                                                      "qup-memory";
1352                                 power-domains = <&rpmhpd SA8775P_CX>;
1353                                 status = "disabled";
1354                         };
1355
1356                         i2c12: i2c@a94000 {
1357                                 compatible = "qcom,geni-i2c";
1358                                 reg = <0x0 0xa94000 0x0 0x4000>;
1359                                 #address-cells = <1>;
1360                                 #size-cells = <0>;
1361                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1362                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1363                                 clock-names = "se";
1364                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1365                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1366                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1367                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1368                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1369                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1370                                 interconnect-names = "qup-core",
1371                                                      "qup-config",
1372                                                      "qup-memory";
1373                                 power-domains = <&rpmhpd SA8775P_CX>;
1374                                 status = "disabled";
1375                         };
1376
1377                         spi12: spi@a94000 {
1378                                 compatible = "qcom,geni-spi";
1379                                 reg = <0x0 0xa94000 0x0 0x4000>;
1380                                 #address-cells = <1>;
1381                                 #size-cells = <0>;
1382                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1383                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1384                                 clock-names = "se";
1385                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1386                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1387                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1389                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1390                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1391                                 interconnect-names = "qup-core",
1392                                                      "qup-config",
1393                                                      "qup-memory";
1394                                 power-domains = <&rpmhpd SA8775P_CX>;
1395                                 status = "disabled";
1396                         };
1397
1398                         uart12: serial@a94000 {
1399                                 compatible = "qcom,geni-uart";
1400                                 reg = <0x0 0x00a94000 0x0 0x4000>;
1401                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1402                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1403                                 clock-names = "se";
1404                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1405                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1406                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1407                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1408                                 interconnect-names = "qup-core", "qup-config";
1409                                 power-domains = <&rpmhpd SA8775P_CX>;
1410                                 status = "disabled";
1411                         };
1412
1413                         i2c13: i2c@a98000 {
1414                                 compatible = "qcom,geni-i2c";
1415                                 reg = <0x0 0xa98000 0x0 0x4000>;
1416                                 #address-cells = <1>;
1417                                 #size-cells = <0>;
1418                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1419                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1420                                 clock-names = "se";
1421                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1422                                                  &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1423                                                 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1424                                                  &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1425                                                 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1426                                                  &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1427                                 interconnect-names = "qup-core",
1428                                                      "qup-config",
1429                                                      "qup-memory";
1430                                 power-domains = <&rpmhpd SA8775P_CX>;
1431                                 status = "disabled";
1432                         };
1433                 };
1434
1435                 qupv3_id_3: geniqup@bc0000 {
1436                         compatible = "qcom,geni-se-qup";
1437                         reg = <0x0 0xbc0000 0x0 0x6000>;
1438                         #address-cells = <2>;
1439                         #size-cells = <2>;
1440                         ranges;
1441                         clock-names = "m-ahb", "s-ahb";
1442                         clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1443                                 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1444                         iommus = <&apps_smmu 0x43 0x0>;
1445                         status = "disabled";
1446
1447                         i2c21: i2c@b80000 {
1448                                 compatible = "qcom,geni-i2c";
1449                                 reg = <0x0 0xb80000 0x0 0x4000>;
1450                                 #address-cells = <1>;
1451                                 #size-cells = <0>;
1452                                 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1453                                 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1454                                 clock-names = "se";
1455                                 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1456                                                 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1457                                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1458                                                 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1459                                            <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1460                                                 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1461                                 interconnect-names = "qup-core",
1462                                                          "qup-config",
1463                                                          "qup-memory";
1464                                 power-domains = <&rpmhpd SA8775P_CX>;
1465                                 status = "disabled";
1466                         };
1467
1468                         spi21: spi@b80000 {
1469                                 compatible = "qcom,geni-spi";
1470                                 reg = <0x0 0xb80000 0x0 0x4000>;
1471                                 #address-cells = <1>;
1472                                 #size-cells = <0>;
1473                                 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1474                                 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1475                                 clock-names = "se";
1476                                 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1477                                                 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1478                                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1479                                                 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1480                                            <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1481                                                 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1482                                 interconnect-names = "qup-core",
1483                                                          "qup-config",
1484                                                          "qup-memory";
1485                                 power-domains = <&rpmhpd SA8775P_CX>;
1486                                 status = "disabled";
1487                         };
1488                 };
1489
1490                 ufs_mem_hc: ufs@1d84000 {
1491                         compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1492                         reg = <0x0 0x01d84000 0x0 0x3000>;
1493                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1494                         phys = <&ufs_mem_phy>;
1495                         phy-names = "ufsphy";
1496                         lanes-per-direction = <2>;
1497                         #reset-cells = <1>;
1498                         resets = <&gcc GCC_UFS_PHY_BCR>;
1499                         reset-names = "rst";
1500                         power-domains = <&gcc UFS_PHY_GDSC>;
1501                         required-opps = <&rpmhpd_opp_nom>;
1502                         iommus = <&apps_smmu 0x100 0x0>;
1503                         dma-coherent;
1504                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1505                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1506                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1507                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1508                                  <&rpmhcc RPMH_CXO_CLK>,
1509                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1510                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1511                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1512                         clock-names = "core_clk",
1513                                       "bus_aggr_clk",
1514                                       "iface_clk",
1515                                       "core_clk_unipro",
1516                                       "ref_clk",
1517                                       "tx_lane0_sync_clk",
1518                                       "rx_lane0_sync_clk",
1519                                       "rx_lane1_sync_clk";
1520                         freq-table-hz = <75000000 300000000>,
1521                                         <0 0>,
1522                                         <0 0>,
1523                                         <75000000 300000000>,
1524                                         <0 0>,
1525                                         <0 0>,
1526                                         <0 0>,
1527                                         <0 0>;
1528                         qcom,ice = <&ice>;
1529                         status = "disabled";
1530                 };
1531
1532                 ufs_mem_phy: phy@1d87000 {
1533                         compatible = "qcom,sa8775p-qmp-ufs-phy";
1534                         reg = <0x0 0x01d87000 0x0 0xe10>;
1535                         /*
1536                          * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1537                          * enables the CXO clock to eDP *and* UFS PHY.
1538                          */
1539                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1540                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1541                                  <&gcc GCC_EDP_REF_CLKREF_EN>;
1542                         clock-names = "ref", "ref_aux", "qref";
1543                         power-domains = <&gcc UFS_PHY_GDSC>;
1544                         resets = <&ufs_mem_hc 0>;
1545                         reset-names = "ufsphy";
1546                         #phy-cells = <0>;
1547                         status = "disabled";
1548                 };
1549
1550                 ice: crypto@1d88000 {
1551                         compatible = "qcom,sa8775p-inline-crypto-engine",
1552                                      "qcom,inline-crypto-engine";
1553                         reg = <0x0 0x01d88000 0x0 0x8000>;
1554                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1555                 };
1556
1557                 usb_0_hsphy: phy@88e4000 {
1558                         compatible = "qcom,sa8775p-usb-hs-phy",
1559                                      "qcom,usb-snps-hs-5nm-phy";
1560                         reg = <0 0x088e4000 0 0x120>;
1561                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1562                         clock-names = "ref";
1563                         resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
1564
1565                         #phy-cells = <0>;
1566
1567                         status = "disabled";
1568                 };
1569
1570                 usb_0_qmpphy: phy@88e8000 {
1571                         compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
1572                         reg = <0 0x088e8000 0 0x2000>;
1573
1574                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1575                                  <&gcc GCC_USB_CLKREF_EN>,
1576                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1577                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1578                         clock-names = "aux", "ref", "com_aux", "pipe";
1579
1580                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1581                                  <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
1582                         reset-names = "phy", "phy_phy";
1583
1584                         power-domains = <&gcc USB30_PRIM_GDSC>;
1585
1586                         #clock-cells = <0>;
1587                         clock-output-names = "usb3_prim_phy_pipe_clk_src";
1588
1589                         #phy-cells = <0>;
1590
1591                         status = "disabled";
1592                 };
1593
1594                 usb_0: usb@a6f8800 {
1595                         compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1596                         reg = <0 0x0a6f8800 0 0x400>;
1597                         #address-cells = <2>;
1598                         #size-cells = <2>;
1599                         ranges;
1600
1601                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1602                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1603                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1604                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1605                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1606                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1607
1608                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1609                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1610                         assigned-clock-rates = <19200000>, <200000000>;
1611
1612                         interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
1613                                               <&pdc 14 IRQ_TYPE_EDGE_RISING>,
1614                                               <&pdc 15 IRQ_TYPE_EDGE_RISING>,
1615                                               <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
1616                         interrupt-names = "pwr_event",
1617                                           "dp_hs_phy_irq",
1618                                           "dm_hs_phy_irq",
1619                                           "ss_phy_irq";
1620
1621                         power-domains = <&gcc USB30_PRIM_GDSC>;
1622                         required-opps = <&rpmhpd_opp_nom>;
1623
1624                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1625
1626                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1627                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1628                         interconnect-names = "usb-ddr", "apps-usb";
1629
1630                         wakeup-source;
1631
1632                         status = "disabled";
1633
1634                         usb_0_dwc3: usb@a600000 {
1635                                 compatible = "snps,dwc3";
1636                                 reg = <0 0x0a600000 0 0xe000>;
1637                                 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1638                                 iommus = <&apps_smmu 0x080 0x0>;
1639                                 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
1640                                 phy-names = "usb2-phy", "usb3-phy";
1641                         };
1642                 };
1643
1644                 usb_1_hsphy: phy@88e6000 {
1645                         compatible = "qcom,sa8775p-usb-hs-phy",
1646                                      "qcom,usb-snps-hs-5nm-phy";
1647                         reg = <0 0x088e6000 0 0x120>;
1648                         clocks = <&gcc GCC_USB_CLKREF_EN>;
1649                         clock-names = "ref";
1650                         resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
1651
1652                         #phy-cells = <0>;
1653
1654                         status = "disabled";
1655                 };
1656
1657                 usb_1_qmpphy: phy@88ea000 {
1658                         compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
1659                         reg = <0 0x088ea000 0 0x2000>;
1660
1661                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1662                                  <&gcc GCC_USB_CLKREF_EN>,
1663                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1664                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1665                         clock-names = "aux", "ref", "com_aux", "pipe";
1666
1667                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1668                                  <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
1669                         reset-names = "phy", "phy_phy";
1670
1671                         power-domains = <&gcc USB30_SEC_GDSC>;
1672
1673                         #clock-cells = <0>;
1674                         clock-output-names = "usb3_sec_phy_pipe_clk_src";
1675
1676                         #phy-cells = <0>;
1677
1678                         status = "disabled";
1679                 };
1680
1681                 usb_1: usb@a8f8800 {
1682                         compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1683                         reg = <0 0x0a8f8800 0 0x400>;
1684                         #address-cells = <2>;
1685                         #size-cells = <2>;
1686                         ranges;
1687
1688                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1689                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
1690                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1691                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1692                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
1693                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1694
1695                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1696                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
1697                         assigned-clock-rates = <19200000>, <200000000>;
1698
1699                         interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
1700                                               <&pdc 8 IRQ_TYPE_EDGE_RISING>,
1701                                               <&pdc 7 IRQ_TYPE_EDGE_RISING>,
1702                                               <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
1703                         interrupt-names = "pwr_event",
1704                                           "dp_hs_phy_irq",
1705                                           "dm_hs_phy_irq",
1706                                           "ss_phy_irq";
1707
1708                         power-domains = <&gcc USB30_SEC_GDSC>;
1709                         required-opps = <&rpmhpd_opp_nom>;
1710
1711                         resets = <&gcc GCC_USB30_SEC_BCR>;
1712
1713                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1714                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1715                         interconnect-names = "usb-ddr", "apps-usb";
1716
1717                         wakeup-source;
1718
1719                         status = "disabled";
1720
1721                         usb_1_dwc3: usb@a800000 {
1722                                 compatible = "snps,dwc3";
1723                                 reg = <0 0x0a800000 0 0xe000>;
1724                                 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
1725                                 iommus = <&apps_smmu 0x0a0 0x0>;
1726                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
1727                                 phy-names = "usb2-phy", "usb3-phy";
1728                         };
1729                 };
1730
1731                 usb_2_hsphy: phy@88e7000 {
1732                         compatible = "qcom,sa8775p-usb-hs-phy",
1733                                      "qcom,usb-snps-hs-5nm-phy";
1734                         reg = <0 0x088e7000 0 0x120>;
1735                         clocks = <&gcc GCC_USB_CLKREF_EN>;
1736                         clock-names = "ref";
1737                         resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
1738
1739                         #phy-cells = <0>;
1740
1741                         status = "disabled";
1742                 };
1743
1744                 usb_2: usb@a4f8800 {
1745                         compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1746                         reg = <0 0x0a4f8800 0 0x400>;
1747                         #address-cells = <2>;
1748                         #size-cells = <2>;
1749                         ranges;
1750
1751                         clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
1752                                  <&gcc GCC_USB20_MASTER_CLK>,
1753                                  <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
1754                                  <&gcc GCC_USB20_SLEEP_CLK>,
1755                                  <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1756                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1757
1758                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1759                                           <&gcc GCC_USB20_MASTER_CLK>;
1760                         assigned-clock-rates = <19200000>, <200000000>;
1761
1762                         interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
1763                                               <&pdc 10 IRQ_TYPE_EDGE_RISING>,
1764                                               <&pdc 9 IRQ_TYPE_EDGE_RISING>;
1765                         interrupt-names = "pwr_event",
1766                                           "dp_hs_phy_irq",
1767                                           "dm_hs_phy_irq";
1768
1769                         power-domains = <&gcc USB20_PRIM_GDSC>;
1770                         required-opps = <&rpmhpd_opp_nom>;
1771
1772                         resets = <&gcc GCC_USB20_PRIM_BCR>;
1773
1774                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
1775                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
1776                         interconnect-names = "usb-ddr", "apps-usb";
1777
1778                         wakeup-source;
1779
1780                         status = "disabled";
1781
1782                         usb_2_dwc3: usb@a400000 {
1783                                 compatible = "snps,dwc3";
1784                                 reg = <0 0x0a400000 0 0xe000>;
1785                                 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
1786                                 iommus = <&apps_smmu 0x020 0x0>;
1787                                 phys = <&usb_2_hsphy>;
1788                                 phy-names = "usb2-phy";
1789                         };
1790                 };
1791
1792                 tcsr_mutex: hwlock@1f40000 {
1793                         compatible = "qcom,tcsr-mutex";
1794                         reg = <0x0 0x01f40000 0x0 0x20000>;
1795                         #hwlock-cells = <1>;
1796                 };
1797
1798                 gpucc: clock-controller@3d90000 {
1799                         compatible = "qcom,sa8775p-gpucc";
1800                         reg = <0x0 0x03d90000 0x0 0xa000>;
1801                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1802                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1803                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1804                         clock-names = "bi_tcxo",
1805                                       "gcc_gpu_gpll0_clk_src",
1806                                       "gcc_gpu_gpll0_div_clk_src";
1807                         #clock-cells = <1>;
1808                         #reset-cells = <1>;
1809                         #power-domain-cells = <1>;
1810                 };
1811
1812                 adreno_smmu: iommu@3da0000 {
1813                         compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
1814                                      "qcom,smmu-500", "arm,mmu-500";
1815                         reg = <0x0 0x03da0000 0x0 0x20000>;
1816                         #iommu-cells = <2>;
1817                         #global-interrupts = <2>;
1818                         dma-coherent;
1819                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
1820                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1821                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1822                                  <&gpucc GPU_CC_AHB_CLK>,
1823                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1824                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1825                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1826                                  <&gpucc GPU_CC_HUB_AON_CLK>;
1827                         clock-names = "gcc_gpu_memnoc_gfx_clk",
1828                                       "gcc_gpu_snoc_dvm_gfx_clk",
1829                                       "gpu_cc_ahb_clk",
1830                                       "gpu_cc_hlos1_vote_gpu_smmu_clk",
1831                                       "gpu_cc_cx_gmu_clk",
1832                                       "gpu_cc_hub_cx_int_clk",
1833                                       "gpu_cc_hub_aon_clk";
1834                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1835                                      <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
1836                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1837                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1838                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1839                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1840                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1841                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1842                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1843                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1844                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1845                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1846                 };
1847
1848                 serdes0: phy@8901000 {
1849                         compatible = "qcom,sa8775p-dwmac-sgmii-phy";
1850                         reg = <0x0 0x08901000 0x0 0xe10>;
1851                         clocks = <&gcc GCC_SGMI_CLKREF_EN>;
1852                         clock-names = "sgmi_ref";
1853                         #phy-cells = <0>;
1854                         status = "disabled";
1855                 };
1856
1857                 serdes1: phy@8902000 {
1858                         compatible = "qcom,sa8775p-dwmac-sgmii-phy";
1859                         reg = <0x0 0x08902000 0x0 0xe10>;
1860                         clocks = <&gcc GCC_SGMI_CLKREF_EN>;
1861                         clock-names = "sgmi_ref";
1862                         #phy-cells = <0>;
1863                         status = "disabled";
1864                 };
1865
1866                 pdc: interrupt-controller@b220000 {
1867                         compatible = "qcom,sa8775p-pdc", "qcom,pdc";
1868                         reg = <0x0 0x0b220000 0x0 0x30000>,
1869                               <0x0 0x17c000f0 0x0 0x64>;
1870                         qcom,pdc-ranges = <0 480 40>,
1871                                           <40 140 14>,
1872                                           <54 263 1>,
1873                                           <55 306 4>,
1874                                           <59 312 3>,
1875                                           <62 374 2>,
1876                                           <64 434 2>,
1877                                           <66 438 2>,
1878                                           <70 520 1>,
1879                                           <73 523 1>,
1880                                           <118 568 6>,
1881                                           <124 609 3>,
1882                                           <159 638 1>,
1883                                           <160 720 3>,
1884                                           <169 728 30>,
1885                                           <199 416 2>,
1886                                           <201 449 1>,
1887                                           <202 89 1>,
1888                                           <203 451 1>,
1889                                           <204 462 1>,
1890                                           <205 264 1>,
1891                                           <206 579 1>,
1892                                           <207 653 1>,
1893                                           <208 656 1>,
1894                                           <209 659 1>,
1895                                           <210 122 1>,
1896                                           <211 699 1>,
1897                                           <212 705 1>,
1898                                           <213 450 1>,
1899                                           <214 643 2>,
1900                                           <216 646 5>,
1901                                           <221 390 5>,
1902                                           <226 700 2>,
1903                                           <228 440 1>,
1904                                           <229 663 1>,
1905                                           <230 524 2>,
1906                                           <232 612 3>,
1907                                           <235 723 5>;
1908                         #interrupt-cells = <2>;
1909                         interrupt-parent = <&intc>;
1910                         interrupt-controller;
1911                 };
1912
1913                 aoss_qmp: power-management@c300000 {
1914                         compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
1915                         reg = <0x0 0x0c300000 0x0 0x400>;
1916                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1917                                                IPCC_MPROC_SIGNAL_GLINK_QMP
1918                                                IRQ_TYPE_EDGE_RISING>;
1919                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1920                         #clock-cells = <0>;
1921                 };
1922
1923                 spmi_bus: spmi@c440000 {
1924                         compatible = "qcom,spmi-pmic-arb";
1925                         reg = <0x0 0x0c440000 0x0 0x1100>,
1926                               <0x0 0x0c600000 0x0 0x2000000>,
1927                               <0x0 0x0e600000 0x0 0x100000>,
1928                               <0x0 0x0e700000 0x0 0xa0000>,
1929                               <0x0 0x0c40a000 0x0 0x26000>;
1930                         reg-names = "core",
1931                                     "chnls",
1932                                     "obsrvr",
1933                                     "intr",
1934                                     "cnfg";
1935                         qcom,channel = <0>;
1936                         qcom,ee = <0>;
1937                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1938                         interrupt-names = "periph_irq";
1939                         interrupt-controller;
1940                         #interrupt-cells = <4>;
1941                         #address-cells = <2>;
1942                         #size-cells = <0>;
1943                 };
1944
1945                 tlmm: pinctrl@f000000 {
1946                         compatible = "qcom,sa8775p-tlmm";
1947                         reg = <0x0 0x0f000000 0x0 0x1000000>;
1948                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1949                         gpio-controller;
1950                         #gpio-cells = <2>;
1951                         interrupt-controller;
1952                         #interrupt-cells = <2>;
1953                         gpio-ranges = <&tlmm 0 0 149>;
1954                         wakeup-parent = <&pdc>;
1955                 };
1956
1957                 apps_smmu: iommu@15000000 {
1958                         compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1959                         reg = <0x0 0x15000000 0x0 0x100000>;
1960                         #iommu-cells = <2>;
1961                         #global-interrupts = <2>;
1962
1963                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1964                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1965                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1966                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1967                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1968                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1969                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1970                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1971                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1972                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1973                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1974                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1975                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1976                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1977                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1978                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1979                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1980                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1981                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1982                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1983                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1984                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1985                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1986                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1987                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1988                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1989                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1990                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1991                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1992                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1993                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1994                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1995                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1996                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1997                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1998                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1999                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2000                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2001                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2002                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2003                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2004                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2005                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2006                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2007                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2008                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2009                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2010                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2011                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2012                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2013                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2014                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2015                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2016                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2017                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2018                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2019                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2020                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2021                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2022                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2023                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2024                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2025                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2026                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2027                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2028                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2029                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2030                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2031                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2032                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2033                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2034                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2035                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2036                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2037                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2038                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2039                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2040                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2041                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2042                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2043                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2044                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
2045                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2046                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2047                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2048                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2049                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2050                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2051                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2052                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2053                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2054                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2055                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2056                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2057                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2058                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2059                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2060                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2061                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2062                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2063                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2064                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2065                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2066                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2067                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2068                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2069                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2070                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2071                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2072                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2073                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2074                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2075                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2076                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2077                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2078                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2079                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2080                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2081                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2082                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2083                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2084                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2085                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2086                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2087                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2088                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2089                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2090                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2091                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2092                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
2093                 };
2094
2095                 pcie_smmu: iommu@15200000 {
2096                         compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2097                         reg = <0x0 0x15200000 0x0 0x80000>;
2098                         #iommu-cells = <2>;
2099                         #global-interrupts = <2>;
2100
2101                         interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
2102                                      <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
2103                                      <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
2104                                      <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
2105                                      <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
2106                                      <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
2107                                      <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
2108                                      <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
2109                                      <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
2110                                      <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
2111                                      <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
2112                                      <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
2113                                      <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
2114                                      <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
2115                                      <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
2116                                      <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
2117                                      <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
2118                                      <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
2119                                      <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
2120                                      <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
2121                                      <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
2122                                      <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
2123                                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
2124                                      <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
2125                                      <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
2126                                      <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
2127                                      <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2128                                      <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2129                                      <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
2130                                      <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
2131                                      <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
2132                                      <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
2133                                      <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
2134                                      <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
2135                                      <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
2136                                      <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
2137                                      <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
2138                                      <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
2139                                      <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
2140                                      <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
2141                                      <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
2142                                      <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
2143                                      <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
2144                                      <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
2145                                      <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
2146                                      <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
2147                                      <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
2148                                      <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
2149                                      <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
2150                                      <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
2151                                      <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2152                                      <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2153                                      <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2154                                      <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
2155                                      <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
2156                                      <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
2157                                      <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
2158                                      <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
2159                                      <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
2160                                      <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
2161                                      <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
2162                                      <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
2163                                      <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
2164                                      <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
2165                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
2166                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
2167                 };
2168
2169                 intc: interrupt-controller@17a00000 {
2170                         compatible = "arm,gic-v3";
2171                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2172                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2173                         interrupt-controller;
2174                         #interrupt-cells = <3>;
2175                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2176                         #redistributor-regions = <1>;
2177                         redistributor-stride = <0x0 0x20000>;
2178                 };
2179
2180                 watchdog@17c10000 {
2181                         compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
2182                         reg = <0x0 0x17c10000 0x0 0x1000>;
2183                         clocks = <&sleep_clk>;
2184                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2185                 };
2186
2187                 memtimer: timer@17c20000 {
2188                         compatible = "arm,armv7-timer-mem";
2189                         reg = <0x0 0x17c20000 0x0 0x1000>;
2190                         ranges = <0x0 0x0 0x0 0x20000000>;
2191                         #address-cells = <1>;
2192                         #size-cells = <1>;
2193
2194                         frame@17c21000 {
2195                                 reg = <0x17c21000 0x1000>,
2196                                       <0x17c22000 0x1000>;
2197                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2198                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2199                                 frame-number = <0>;
2200                         };
2201
2202                         frame@17c23000 {
2203                                 reg = <0x17c23000 0x1000>;
2204                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2205                                 frame-number = <1>;
2206                                 status = "disabled";
2207                         };
2208
2209                         frame@17c25000 {
2210                                 reg = <0x17c25000 0x1000>;
2211                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2212                                 frame-number = <2>;
2213                                 status = "disabled";
2214                         };
2215
2216                         frame@17c27000 {
2217                                 reg = <0x17c27000 0x1000>;
2218                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2219                                 frame-number = <3>;
2220                                 status = "disabled";
2221                         };
2222
2223                         frame@17c29000 {
2224                                 reg = <0x17c29000 0x1000>;
2225                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2226                                 frame-number = <4>;
2227                                 status = "disabled";
2228                         };
2229
2230                         frame@17c2b000 {
2231                                 reg = <0x17c2b000 0x1000>;
2232                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2233                                 frame-number = <5>;
2234                                 status = "disabled";
2235                         };
2236
2237                         frame@17c2d000 {
2238                                 reg = <0x17c2d000 0x1000>;
2239                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2240                                 frame-number = <6>;
2241                                 status = "disabled";
2242                         };
2243                 };
2244
2245                 apps_rsc: rsc@18200000 {
2246                         compatible = "qcom,rpmh-rsc";
2247                         reg = <0x0 0x18200000 0x0 0x10000>,
2248                               <0x0 0x18210000 0x0 0x10000>,
2249                               <0x0 0x18220000 0x0 0x10000>;
2250                         reg-names = "drv-0", "drv-1", "drv-2";
2251                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2252                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2253                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2254                         qcom,tcs-offset = <0xd00>;
2255                         qcom,drv-id = <2>;
2256                         qcom,tcs-config = <ACTIVE_TCS 2>,
2257                                           <SLEEP_TCS 3>,
2258                                           <WAKE_TCS 3>,
2259                                           <CONTROL_TCS 0>;
2260                         label = "apps_rsc";
2261
2262                         apps_bcm_voter: bcm-voter {
2263                                 compatible = "qcom,bcm-voter";
2264                         };
2265
2266                         rpmhcc: clock-controller {
2267                                 compatible = "qcom,sa8775p-rpmh-clk";
2268                                 #clock-cells = <1>;
2269                                 clock-names = "xo";
2270                                 clocks = <&xo_board_clk>;
2271                         };
2272
2273                         rpmhpd: power-controller {
2274                                 compatible = "qcom,sa8775p-rpmhpd";
2275                                 #power-domain-cells = <1>;
2276                                 operating-points-v2 = <&rpmhpd_opp_table>;
2277
2278                                 rpmhpd_opp_table: opp-table {
2279                                         compatible = "operating-points-v2";
2280
2281                                         rpmhpd_opp_ret: opp-0 {
2282                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2283                                         };
2284
2285                                         rpmhpd_opp_min_svs: opp-1 {
2286                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2287                                         };
2288
2289                                         rpmhpd_opp_low_svs: opp2 {
2290                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2291                                         };
2292
2293                                         rpmhpd_opp_svs: opp3 {
2294                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295                                         };
2296
2297                                         rpmhpd_opp_svs_l1: opp-4 {
2298                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2299                                         };
2300
2301                                         rpmhpd_opp_nom: opp-5 {
2302                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2303                                         };
2304
2305                                         rpmhpd_opp_nom_l1: opp-6 {
2306                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2307                                         };
2308
2309                                         rpmhpd_opp_nom_l2: opp-7 {
2310                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2311                                         };
2312
2313                                         rpmhpd_opp_turbo: opp-8 {
2314                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2315                                         };
2316
2317                                         rpmhpd_opp_turbo_l1: opp-9 {
2318                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2319                                         };
2320                                 };
2321                         };
2322                 };
2323
2324                 cpufreq_hw: cpufreq@18591000 {
2325                         compatible = "qcom,sa8775p-cpufreq-epss",
2326                                      "qcom,cpufreq-epss";
2327                         reg = <0x0 0x18591000 0x0 0x1000>,
2328                               <0x0 0x18593000 0x0 0x1000>;
2329                         reg-names = "freq-domain0", "freq-domain1";
2330
2331                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2332                         clock-names = "xo", "alternate";
2333
2334                         #freq-domain-cells = <1>;
2335                 };
2336
2337                 ethernet1: ethernet@23000000 {
2338                         compatible = "qcom,sa8775p-ethqos";
2339                         reg = <0x0 0x23000000 0x0 0x10000>,
2340                               <0x0 0x23016000 0x0 0x100>;
2341                         reg-names = "stmmaceth", "rgmii";
2342
2343                         interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
2344                         interrupt-names = "macirq";
2345
2346                         clocks = <&gcc GCC_EMAC1_AXI_CLK>,
2347                                  <&gcc GCC_EMAC1_SLV_AHB_CLK>,
2348                                  <&gcc GCC_EMAC1_PTP_CLK>,
2349                                  <&gcc GCC_EMAC1_PHY_AUX_CLK>;
2350                         clock-names = "stmmaceth",
2351                                       "pclk",
2352                                       "ptp_ref",
2353                                       "phyaux";
2354
2355                         power-domains = <&gcc EMAC1_GDSC>;
2356
2357                         phys = <&serdes1>;
2358                         phy-names = "serdes";
2359
2360                         iommus = <&apps_smmu 0x140 0xf>;
2361
2362                         snps,tso;
2363                         snps,pbl = <32>;
2364                         rx-fifo-depth = <16384>;
2365                         tx-fifo-depth = <16384>;
2366
2367                         status = "disabled";
2368                 };
2369
2370                 ethernet0: ethernet@23040000 {
2371                         compatible = "qcom,sa8775p-ethqos";
2372                         reg = <0x0 0x23040000 0x0 0x10000>,
2373                               <0x0 0x23056000 0x0 0x100>;
2374                         reg-names = "stmmaceth", "rgmii";
2375
2376                         interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
2377                         interrupt-names = "macirq";
2378
2379                         clocks = <&gcc GCC_EMAC0_AXI_CLK>,
2380                                  <&gcc GCC_EMAC0_SLV_AHB_CLK>,
2381                                  <&gcc GCC_EMAC0_PTP_CLK>,
2382                                  <&gcc GCC_EMAC0_PHY_AUX_CLK>;
2383                         clock-names = "stmmaceth",
2384                                       "pclk",
2385                                       "ptp_ref",
2386                                       "phyaux";
2387
2388                         power-domains = <&gcc EMAC0_GDSC>;
2389
2390                         phys = <&serdes0>;
2391                         phy-names = "serdes";
2392
2393                         iommus = <&apps_smmu 0x120 0xf>;
2394
2395                         snps,tso;
2396                         snps,pbl = <32>;
2397                         rx-fifo-depth = <16384>;
2398                         tx-fifo-depth = <16384>;
2399
2400                         status = "disabled";
2401                 };
2402         };
2403
2404         arch_timer: timer {
2405                 compatible = "arm,armv8-timer";
2406                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2407                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2408                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2409                              <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2410         };
2411
2412         pcie0: pci@1c00000{
2413                 compatible = "qcom,pcie-sa8775p";
2414                 reg = <0x0 0x01c00000 0x0 0x3000>,
2415                       <0x0 0x40000000 0x0 0xf20>,
2416                       <0x0 0x40000f20 0x0 0xa8>,
2417                       <0x0 0x40001000 0x0 0x4000>,
2418                       <0x0 0x40100000 0x0 0x100000>,
2419                       <0x0 0x01c03000 0x0 0x1000>;
2420                 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2421                 device_type = "pci";
2422
2423                 #address-cells = <3>;
2424                 #size-cells = <2>;
2425                 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2426                          <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2427                 bus-range = <0x00 0xff>;
2428
2429                 dma-coherent;
2430
2431                 linux,pci-domain = <0>;
2432                 num-lanes = <2>;
2433
2434                 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2435                              <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2436                              <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
2437                              <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
2438                              <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
2439                              <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
2440                              <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
2441                              <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
2442                 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2443                                   "msi4", "msi5", "msi6", "msi7";
2444                 #interrupt-cells = <1>;
2445                 interrupt-map-mask = <0 0 0 0x7>;
2446                 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2447                                 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2448                                 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
2449                                 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
2450
2451                 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2452                          <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2453                          <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2454                          <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2455                          <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
2456
2457                 clock-names = "aux",
2458                               "cfg",
2459                               "bus_master",
2460                               "bus_slave",
2461                               "slave_q2a";
2462
2463                 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
2464                 assigned-clock-rates = <19200000>;
2465
2466                 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
2467                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
2468                 interconnect-names = "pcie-mem", "cpu-pcie";
2469
2470                 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
2471                             <0x100 &pcie_smmu 0x0001 0x1>;
2472
2473                 resets = <&gcc GCC_PCIE_0_BCR>;
2474                 reset-names = "pci";
2475                 power-domains = <&gcc PCIE_0_GDSC>;
2476
2477                 phys = <&pcie0_phy>;
2478                 phy-names = "pciephy";
2479
2480                 status = "disabled";
2481         };
2482
2483         pcie0_phy: phy@1c04000 {
2484                 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
2485                 reg = <0x0 0x1c04000 0x0 0x2000>;
2486
2487                 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2488                          <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2489                          <&gcc GCC_PCIE_CLKREF_EN>,
2490                          <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
2491                          <&gcc GCC_PCIE_0_PIPE_CLK>,
2492                          <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
2493                          <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
2494
2495                 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
2496                               "pipediv2", "phy_aux";
2497
2498                 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2499                 assigned-clock-rates = <100000000>;
2500
2501                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2502                 reset-names = "phy";
2503
2504                 #clock-cells = <0>;
2505                 clock-output-names = "pcie_0_pipe_clk";
2506
2507                 #phy-cells = <0>;
2508
2509                 status = "disabled";
2510         };
2511
2512         pcie1: pci@1c10000{
2513                 compatible = "qcom,pcie-sa8775p";
2514                 reg = <0x0 0x01c10000 0x0 0x3000>,
2515                       <0x0 0x60000000 0x0 0xf20>,
2516                       <0x0 0x60000f20 0x0 0xa8>,
2517                       <0x0 0x60001000 0x0 0x4000>,
2518                       <0x0 0x60100000 0x0 0x100000>,
2519                       <0x0 0x01c13000 0x0 0x1000>;
2520                 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2521                 device_type = "pci";
2522
2523                 #address-cells = <3>;
2524                 #size-cells = <2>;
2525                 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2526                          <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
2527                 bus-range = <0x00 0xff>;
2528
2529                 dma-coherent;
2530
2531                 linux,pci-domain = <1>;
2532                 num-lanes = <4>;
2533
2534                 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
2535                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2536                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2537                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2538                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2539                              <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2540                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2541                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2542                 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2543                                   "msi4", "msi5", "msi6", "msi7";
2544                 #interrupt-cells = <1>;
2545                 interrupt-map-mask = <0 0 0 0x7>;
2546                 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2547                                 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2548                                 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2549                                 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2550
2551                 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2552                          <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2553                          <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2554                          <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2555                          <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
2556
2557                 clock-names = "aux",
2558                               "cfg",
2559                               "bus_master",
2560                               "bus_slave",
2561                               "slave_q2a";
2562
2563                 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2564                 assigned-clock-rates = <19200000>;
2565
2566                 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
2567                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
2568                 interconnect-names = "pcie-mem", "cpu-pcie";
2569
2570                 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
2571                             <0x100 &pcie_smmu 0x0081 0x1>;
2572
2573                 resets = <&gcc GCC_PCIE_1_BCR>;
2574                 reset-names = "pci";
2575                 power-domains = <&gcc PCIE_1_GDSC>;
2576
2577                 phys = <&pcie1_phy>;
2578                 phy-names = "pciephy";
2579
2580                 status = "disabled";
2581         };
2582
2583         pcie1_phy: phy@1c14000 {
2584                 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
2585                 reg = <0x0 0x1c14000 0x0 0x4000>;
2586
2587                 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2588                          <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2589                          <&gcc GCC_PCIE_CLKREF_EN>,
2590                          <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2591                          <&gcc GCC_PCIE_1_PIPE_CLK>,
2592                          <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
2593                          <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
2594
2595                 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
2596                               "pipediv2", "phy_aux";
2597
2598                 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2599                 assigned-clock-rates = <100000000>;
2600
2601                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2602                 reset-names = "phy";
2603
2604                 #clock-cells = <0>;
2605                 clock-output-names = "pcie_1_pipe_clk";
2606
2607                 #phy-cells = <0>;
2608
2609                 status = "disabled";
2610         };
2611 };