arch/arm64/boot/dts/qcom/qcs404.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
   8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
   9 #include <dt-bindings/clock/qcom,rpmcc.h>
  10 #include <dt-bindings/power/qcom-rpmpd.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         chosen { };
  20
  21         clocks {
  22                 xo_board: xo-board {
  23                         compatible = "fixed-clock";
  24                         #clock-cells = <0>;
  25                         clock-frequency = <19200000>;
  26                 };
  27
  28                 sleep_clk: sleep-clk {
  29                         compatible = "fixed-clock";
  30                         #clock-cells = <0>;
  31                         clock-frequency = <32768>;
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@100 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         reg = <0x100>;
  43                         enable-method = "psci";
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                         next-level-cache = <&L2_0>;
  46                         #cooling-cells = <2>;
  47                         clocks = <&apcs_glb>;
  48                         operating-points-v2 = <&cpu_opp_table>;
  49                         power-domains = <&cpr>;
  50                         power-domain-names = "cpr";
  51                 };
  52
  53                 CPU1: cpu@101 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         reg = <0x101>;
  57                         enable-method = "psci";
  58                         cpu-idle-states = <&CPU_SLEEP_0>;
  59                         next-level-cache = <&L2_0>;
  60                         #cooling-cells = <2>;
  61                         clocks = <&apcs_glb>;
  62                         operating-points-v2 = <&cpu_opp_table>;
  63                         power-domains = <&cpr>;
  64                         power-domain-names = "cpr";
  65                 };
  66
  67                 CPU2: cpu@102 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a53";
  70                         reg = <0x102>;
  71                         enable-method = "psci";
  72                         cpu-idle-states = <&CPU_SLEEP_0>;
  73                         next-level-cache = <&L2_0>;
  74                         #cooling-cells = <2>;
  75                         clocks = <&apcs_glb>;
  76                         operating-points-v2 = <&cpu_opp_table>;
  77                         power-domains = <&cpr>;
  78                         power-domain-names = "cpr";
  79                 };
  80
  81                 CPU3: cpu@103 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53";
  84                         reg = <0x103>;
  85                         enable-method = "psci";
  86                         cpu-idle-states = <&CPU_SLEEP_0>;
  87                         next-level-cache = <&L2_0>;
  88                         #cooling-cells = <2>;
  89                         clocks = <&apcs_glb>;
  90                         operating-points-v2 = <&cpu_opp_table>;
  91                         power-domains = <&cpr>;
  92                         power-domain-names = "cpr";
  93                 };
  94
  95                 L2_0: l2-cache {
  96                         compatible = "cache";
  97                         cache-level = <2>;
  98                         cache-unified;
  99                 };
 100
 101                 idle-states {
 102                         entry-method = "psci";
 103
 104                         CPU_SLEEP_0: cpu-sleep-0 {
 105                                 compatible = "arm,idle-state";
 106                                 idle-state-name = "standalone-power-collapse";
 107                                 arm,psci-suspend-param = <0x40000003>;
 108                                 entry-latency-us = <125>;
 109                                 exit-latency-us = <180>;
 110                                 min-residency-us = <595>;
 111                                 local-timer-stop;
 112                         };
 113                 };
 114         };
 115
 116         cpu_opp_table: opp-table-cpu {
 117                 compatible = "operating-points-v2-kryo-cpu";
 118                 opp-shared;
 119
 120                 opp-1094400000 {
 121                         opp-hz = /bits/ 64 <1094400000>;
 122                         required-opps = <&cpr_opp1>;
 123                 };
 124                 opp-1248000000 {
 125                         opp-hz = /bits/ 64 <1248000000>;
 126                         required-opps = <&cpr_opp2>;
 127                 };
 128                 opp-1401600000 {
 129                         opp-hz = /bits/ 64 <1401600000>;
 130                         required-opps = <&cpr_opp3>;
 131                 };
 132         };
 133
 134         cpr_opp_table: opp-table-cpr {
 135                 compatible = "operating-points-v2-qcom-level";
 136
 137                 cpr_opp1: opp1 {
 138                         opp-level = <1>;
 139                         qcom,opp-fuse-level = <1>;
 140                 };
 141                 cpr_opp2: opp2 {
 142                         opp-level = <2>;
 143                         qcom,opp-fuse-level = <2>;
 144                 };
 145                 cpr_opp3: opp3 {
 146                         opp-level = <3>;
 147                         qcom,opp-fuse-level = <3>;
 148                 };
 149         };
 150
 151         firmware {
 152                 scm: scm {
 153                         compatible = "qcom,scm-qcs404", "qcom,scm";
 154                         #reset-cells = <1>;
 155                 };
 156         };
 157
 158         memory@80000000 {
 159                 device_type = "memory";
 160                 /* We expect the bootloader to fill in the size */
 161                 reg = <0 0x80000000 0 0>;
 162         };
 163
 164         psci {
 165                 compatible = "arm,psci-1.0";
 166                 method = "smc";
 167         };
 168
 169         rpm: remoteproc {
 170                 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc";
 171
 172                 glink-edge {
 173                         compatible = "qcom,glink-rpm";
 174
 175                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 176                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 177                         mboxes = <&apcs_glb 0>;
 178
 179                         rpm_requests: rpm-requests {
 180                                 compatible = "qcom,rpm-qcs404";
 181                                 qcom,glink-channels = "rpm_requests";
 182
 183                                 rpmcc: clock-controller {
 184                                         compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
 185                                         #clock-cells = <1>;
 186                                         clocks = <&xo_board>;
 187                                         clock-names = "xo";
 188                                 };
 189
 190                                 rpmpd: power-controller {
 191                                         compatible = "qcom,qcs404-rpmpd";
 192                                         #power-domain-cells = <1>;
 193                                         operating-points-v2 = <&rpmpd_opp_table>;
 194
 195                                         rpmpd_opp_table: opp-table {
 196                                                 compatible = "operating-points-v2";
 197
 198                                                 rpmpd_opp_ret: opp1 {
 199                                                         opp-level = <16>;
 200                                                 };
 201
 202                                                 rpmpd_opp_ret_plus: opp2 {
 203                                                         opp-level = <32>;
 204                                                 };
 205
 206                                                 rpmpd_opp_min_svs: opp3 {
 207                                                         opp-level = <48>;
 208                                                 };
 209
 210                                                 rpmpd_opp_low_svs: opp4 {
 211                                                         opp-level = <64>;
 212                                                 };
 213
 214                                                 rpmpd_opp_svs: opp5 {
 215                                                         opp-level = <128>;
 216                                                 };
 217
 218                                                 rpmpd_opp_svs_plus: opp6 {
 219                                                         opp-level = <192>;
 220                                                 };
 221
 222                                                 rpmpd_opp_nom: opp7 {
 223                                                         opp-level = <256>;
 224                                                 };
 225
 226                                                 rpmpd_opp_nom_plus: opp8 {
 227                                                         opp-level = <320>;
 228                                                 };
 229
 230                                                 rpmpd_opp_turbo: opp9 {
 231                                                         opp-level = <384>;
 232                                                 };
 233
 234                                                 rpmpd_opp_turbo_no_cpr: opp10 {
 235                                                         opp-level = <416>;
 236                                                 };
 237
 238                                                 rpmpd_opp_turbo_plus: opp11 {
 239                                                         opp-level = <512>;
 240                                                 };
 241                                         };
 242                                 };
 243                         };
 244                 };
 245         };
 246
 247         reserved-memory {
 248                 #address-cells = <2>;
 249                 #size-cells = <2>;
 250                 ranges;
 251
 252                 tz_apps_mem: memory@85900000 {
 253                         reg = <0 0x85900000 0 0x500000>;
 254                         no-map;
 255                 };
 256
 257                 xbl_mem: memory@85e00000 {
 258                         reg = <0 0x85e00000 0 0x100000>;
 259                         no-map;
 260                 };
 261
 262                 smem_region: memory@85f00000 {
 263                         reg = <0 0x85f00000 0 0x200000>;
 264                         no-map;
 265                 };
 266
 267                 tz_mem: memory@86100000 {
 268                         reg = <0 0x86100000 0 0x300000>;
 269                         no-map;
 270                 };
 271
 272                 wlan_fw_mem: memory@86400000 {
 273                         reg = <0 0x86400000 0 0x1100000>;
 274                         no-map;
 275                 };
 276
 277                 adsp_fw_mem: memory@87500000 {
 278                         reg = <0 0x87500000 0 0x1a00000>;
 279                         no-map;
 280                 };
 281
 282                 cdsp_fw_mem: memory@88f00000 {
 283                         reg = <0 0x88f00000 0 0x600000>;
 284                         no-map;
 285                 };
 286
 287                 wlan_msa_mem: memory@89500000 {
 288                         reg = <0 0x89500000 0 0x100000>;
 289                         no-map;
 290                 };
 291
 292                 uefi_mem: memory@9f800000 {
 293                         reg = <0 0x9f800000 0 0x800000>;
 294                         no-map;
 295                 };
 296         };
 297
 298         smem {
 299                 compatible = "qcom,smem";
 300
 301                 memory-region = <&smem_region>;
 302                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 303
 304                 hwlocks = <&tcsr_mutex 3>;
 305         };
 306
 307         soc: soc@0 {
 308                 #address-cells = <1>;
 309                 #size-cells = <1>;
 310                 ranges = <0 0 0 0xffffffff>;
 311                 compatible = "simple-bus";
 312
 313                 turingcc: clock-controller@800000 {
 314                         compatible = "qcom,qcs404-turingcc";
 315                         reg = <0x00800000 0x30000>;
 316                         clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
 317
 318                         #clock-cells = <1>;
 319                         #reset-cells = <1>;
 320
 321                         status = "disabled";
 322                 };
 323
 324                 rpm_msg_ram: sram@60000 {
 325                         compatible = "qcom,rpm-msg-ram";
 326                         reg = <0x00060000 0x6000>;
 327                 };
 328
 329                 usb3_phy: phy@78000 {
 330                         compatible = "qcom,usb-ss-28nm-phy";
 331                         reg = <0x00078000 0x400>;
 332                         #phy-cells = <0>;
 333                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 334                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 335                                  <&gcc GCC_USB3_PHY_PIPE_CLK>;
 336                         clock-names = "ref", "ahb", "pipe";
 337                         resets = <&gcc GCC_USB3_PHY_BCR>,
 338                                  <&gcc GCC_USB3PHY_PHY_BCR>;
 339                         reset-names = "com", "phy";
 340                         status = "disabled";
 341                 };
 342
 343                 usb2_phy_prim: phy@7a000 {
 344                         compatible = "qcom,usb-hs-28nm-femtophy";
 345                         reg = <0x0007a000 0x200>;
 346                         #phy-cells = <0>;
 347                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 348                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 349                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 350                         clock-names = "ref", "ahb", "sleep";
 351                         resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
 352                                  <&gcc GCC_USB2A_PHY_BCR>;
 353                         reset-names = "phy", "por";
 354                         status = "disabled";
 355                 };
 356
 357                 usb2_phy_sec: phy@7c000 {
 358                         compatible = "qcom,usb-hs-28nm-femtophy";
 359                         reg = <0x0007c000 0x200>;
 360                         #phy-cells = <0>;
 361                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 362                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
 363                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 364                         clock-names = "ref", "ahb", "sleep";
 365                         resets = <&gcc GCC_QUSB2_PHY_BCR>,
 366                                  <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
 367                         reset-names = "phy", "por";
 368                         status = "disabled";
 369                 };
 370
 371                 qfprom: qfprom@a4000 {
 372                         compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
 373                         reg = <0x000a4000 0x1000>;
 374                         #address-cells = <1>;
 375                         #size-cells = <1>;
 376                         cpr_efuse_speedbin: speedbin@13c {
 377                                 reg = <0x13c 0x4>;
 378                                 bits = <2 3>;
 379                         };
 380
 381                         tsens_s0_p1: s0-p1@1f8 {
 382                                 reg = <0x1f8 0x1>;
 383                                 bits = <0 6>;
 384                         };
 385
 386                         tsens_s0_p2: s0-p2@1f8 {
 387                                 reg = <0x1f8 0x2>;
 388                                 bits = <6 6>;
 389                         };
 390
 391                         tsens_s1_p1: s1-p1@1f9 {
 392                                 reg = <0x1f9 0x2>;
 393                                 bits = <4 6>;
 394                         };
 395
 396                         tsens_s1_p2: s1-p2@1fa {
 397                                 reg = <0x1fa 0x1>;
 398                                 bits = <2 6>;
 399                         };
 400
 401                         tsens_s2_p1: s2-p1@1fb {
 402                                 reg = <0x1fb 0x1>;
 403                                 bits = <0 6>;
 404                         };
 405
 406                         tsens_s2_p2: s2-p2@1fb {
 407                                 reg = <0x1fb 0x2>;
 408                                 bits = <6 6>;
 409                         };
 410
 411                         tsens_s3_p1: s3-p1@1fc {
 412                                 reg = <0x1fc 0x2>;
 413                                 bits = <4 6>;
 414                         };
 415
 416                         tsens_s3_p2: s3-p2@1fd {
 417                                 reg = <0x1fd 0x1>;
 418                                 bits = <2 6>;
 419                         };
 420
 421                         tsens_s4_p1: s4-p1@1fe {
 422                                 reg = <0x1fe 0x1>;
 423                                 bits = <0 6>;
 424                         };
 425
 426                         tsens_s4_p2: s4-p2@1fe {
 427                                 reg = <0x1fe 0x2>;
 428                                 bits = <6 6>;
 429                         };
 430
 431                         tsens_s5_p1: s5-p1@200 {
 432                                 reg = <0x200 0x1>;
 433                                 bits = <0 6>;
 434                         };
 435
 436                         tsens_s5_p2: s5-p2@200 {
 437                                 reg = <0x200 0x2>;
 438                                 bits = <6 6>;
 439                         };
 440
 441                         tsens_s6_p1: s6-p1@201 {
 442                                 reg = <0x201 0x2>;
 443                                 bits = <4 6>;
 444                         };
 445
 446                         tsens_s6_p2: s6-p2@202 {
 447                                 reg = <0x202 0x1>;
 448                                 bits = <2 6>;
 449                         };
 450
 451                         tsens_s7_p1: s7-p1@203 {
 452                                 reg = <0x203 0x1>;
 453                                 bits = <0 6>;
 454                         };
 455
 456                         tsens_s7_p2: s7-p2@203 {
 457                                 reg = <0x203 0x2>;
 458                                 bits = <6 6>;
 459                         };
 460
 461                         tsens_s8_p1: s8-p1@204 {
 462                                 reg = <0x204 0x2>;
 463                                 bits = <4 6>;
 464                         };
 465
 466                         tsens_s8_p2: s8-p2@205 {
 467                                 reg = <0x205 0x1>;
 468                                 bits = <2 6>;
 469                         };
 470
 471                         tsens_s9_p1: s9-p1@206 {
 472                                 reg = <0x206 0x1>;
 473                                 bits = <0 6>;
 474                         };
 475
 476                         tsens_s9_p2: s9-p2@206 {
 477                                 reg = <0x206 0x2>;
 478                                 bits = <6 6>;
 479                         };
 480
 481                         tsens_mode: mode@208 {
 482                                 reg = <0x208 1>;
 483                                 bits = <0 3>;
 484                         };
 485
 486                         tsens_base1: base1@208 {
 487                                 reg = <0x208 2>;
 488                                 bits = <3 8>;
 489                         };
 490
 491                         tsens_base2: base2@208 {
 492                                 reg = <0x209 2>;
 493                                 bits = <3 8>;
 494                         };
 495
 496                         cpr_efuse_quot_offset1: qoffset1@231 {
 497                                 reg = <0x231 0x4>;
 498                                 bits = <4 7>;
 499                         };
 500                         cpr_efuse_quot_offset2: qoffset2@232 {
 501                                 reg = <0x232 0x4>;
 502                                 bits = <3 7>;
 503                         };
 504                         cpr_efuse_quot_offset3: qoffset3@233 {
 505                                 reg = <0x233 0x4>;
 506                                 bits = <2 7>;
 507                         };
 508                         cpr_efuse_init_voltage1: ivoltage1@229 {
 509                                 reg = <0x229 0x4>;
 510                                 bits = <4 6>;
 511                         };
 512                         cpr_efuse_init_voltage2: ivoltage2@22a {
 513                                 reg = <0x22a 0x4>;
 514                                 bits = <2 6>;
 515                         };
 516                         cpr_efuse_init_voltage3: ivoltage3@22b {
 517                                 reg = <0x22b 0x4>;
 518                                 bits = <0 6>;
 519                         };
 520                         cpr_efuse_quot1: quot1@22b {
 521                                 reg = <0x22b 0x4>;
 522                                 bits = <6 12>;
 523                         };
 524                         cpr_efuse_quot2: quot2@22d {
 525                                 reg = <0x22d 0x4>;
 526                                 bits = <2 12>;
 527                         };
 528                         cpr_efuse_quot3: quot3@230 {
 529                                 reg = <0x230 0x4>;
 530                                 bits = <0 12>;
 531                         };
 532                         cpr_efuse_ring1: ring1@228 {
 533                                 reg = <0x228 0x4>;
 534                                 bits = <0 3>;
 535                         };
 536                         cpr_efuse_ring2: ring2@228 {
 537                                 reg = <0x228 0x4>;
 538                                 bits = <4 3>;
 539                         };
 540                         cpr_efuse_ring3: ring3@229 {
 541                                 reg = <0x229 0x4>;
 542                                 bits = <0 3>;
 543                         };
 544                         cpr_efuse_revision: revision@218 {
 545                                 reg = <0x218 0x4>;
 546                                 bits = <3 3>;
 547                         };
 548                 };
 549
 550                 rng: rng@e3000 {
 551                         compatible = "qcom,prng-ee";
 552                         reg = <0x000e3000 0x1000>;
 553                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 554                         clock-names = "core";
 555                 };
 556
 557                 bimc: interconnect@400000 {
 558                         reg = <0x00400000 0x80000>;
 559                         compatible = "qcom,qcs404-bimc";
 560                         #interconnect-cells = <1>;
 561                         clock-names = "bus", "bus_a";
 562                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 563                                 <&rpmcc RPM_SMD_BIMC_A_CLK>;
 564                 };
 565
 566                 tsens: thermal-sensor@4a9000 {
 567                         compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
 568                         reg = <0x004a9000 0x1000>, /* TM */
 569                               <0x004a8000 0x1000>; /* SROT */
 570                         nvmem-cells = <&tsens_mode>,
 571                                       <&tsens_base1>, <&tsens_base2>,
 572                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
 573                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
 574                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
 575                                       <&tsens_s3_p1>, <&tsens_s3_p2>,
 576                                       <&tsens_s4_p1>, <&tsens_s4_p2>,
 577                                       <&tsens_s5_p1>, <&tsens_s5_p2>,
 578                                       <&tsens_s6_p1>, <&tsens_s6_p2>,
 579                                       <&tsens_s7_p1>, <&tsens_s7_p2>,
 580                                       <&tsens_s8_p1>, <&tsens_s8_p2>,
 581                                       <&tsens_s9_p1>, <&tsens_s9_p2>;
 582                         nvmem-cell-names = "mode",
 583                                            "base1", "base2",
 584                                            "s0_p1", "s0_p2",
 585                                            "s1_p1", "s1_p2",
 586                                            "s2_p1", "s2_p2",
 587                                            "s3_p1", "s3_p2",
 588                                            "s4_p1", "s4_p2",
 589                                            "s5_p1", "s5_p2",
 590                                            "s6_p1", "s6_p2",
 591                                            "s7_p1", "s7_p2",
 592                                            "s8_p1", "s8_p2",
 593                                            "s9_p1", "s9_p2";
 594                         #qcom,sensors = <10>;
 595                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 596                         interrupt-names = "uplow";
 597                         #thermal-sensor-cells = <1>;
 598                 };
 599
 600                 pcnoc: interconnect@500000 {
 601                         reg = <0x00500000 0x15080>;
 602                         compatible = "qcom,qcs404-pcnoc";
 603                         #interconnect-cells = <1>;
 604                         clock-names = "bus", "bus_a";
 605                         clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
 606                                 <&rpmcc RPM_SMD_PNOC_A_CLK>;
 607                 };
 608
 609                 snoc: interconnect@580000 {
 610                         reg = <0x00580000 0x23080>;
 611                         compatible = "qcom,qcs404-snoc";
 612                         #interconnect-cells = <1>;
 613                         clock-names = "bus", "bus_a";
 614                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 615                                 <&rpmcc RPM_SMD_SNOC_A_CLK>;
 616                 };
 617
 618                 remoteproc_cdsp: remoteproc@b00000 {
 619                         compatible = "qcom,qcs404-cdsp-pas";
 620                         reg = <0x00b00000 0x4040>;
 621
 622                         interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
 623                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 624                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 625                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 626                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 627                         interrupt-names = "wdog", "fatal", "ready",
 628                                           "handover", "stop-ack";
 629
 630                         clocks = <&xo_board>;
 631                         clock-names = "xo";
 632
 633                         /*
 634                          * If the node was using the PIL binding, then include properties:
 635                          * clocks = <&xo_board>,
 636                          *          <&gcc GCC_CDSP_CFG_AHB_CLK>,
 637                          *          <&gcc GCC_CDSP_TBU_CLK>,
 638                          *          <&gcc GCC_BIMC_CDSP_CLK>,
 639                          *          <&turingcc TURING_WRAPPER_AON_CLK>,
 640                          *          <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
 641                          *          <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
 642                          *          <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
 643                          * clock-names = "xo",
 644                          *               "sway",
 645                          *               "tbu",
 646                          *               "bimc",
 647                          *               "ahb_aon",
 648                          *               "q6ss_slave",
 649                          *               "q6ss_master",
 650                          *               "q6_axim";
 651                          * resets = <&gcc GCC_CDSP_RESTART>;
 652                          * reset-names = "restart";
 653                          * qcom,halt-regs = <&tcsr 0x19004>;
 654                          */
 655
 656                         memory-region = <&cdsp_fw_mem>;
 657
 658                         qcom,smem-states = <&cdsp_smp2p_out 0>;
 659                         qcom,smem-state-names = "stop";
 660
 661                         status = "disabled";
 662
 663                         glink-edge {
 664                                 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
 665
 666                                 qcom,remote-pid = <5>;
 667                                 mboxes = <&apcs_glb 12>;
 668
 669                                 label = "cdsp";
 670                         };
 671                 };
 672
 673                 usb3: usb@7678800 {
 674                         compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
 675                         reg = <0x07678800 0x400>;
 676                         #address-cells = <1>;
 677                         #size-cells = <1>;
 678                         ranges;
 679                         clocks = <&gcc GCC_USB30_MASTER_CLK>,
 680                                  <&gcc GCC_SYS_NOC_USB3_CLK>,
 681                                  <&gcc GCC_USB30_SLEEP_CLK>,
 682                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
 683                         clock-names = "core", "iface", "sleep", "mock_utmi";
 684                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 685                                           <&gcc GCC_USB30_MASTER_CLK>;
 686                         assigned-clock-rates = <19200000>, <200000000>;
 687                         status = "disabled";
 688
 689                         usb3_dwc3: usb@7580000 {
 690                                 compatible = "snps,dwc3";
 691                                 reg = <0x07580000 0xcd00>;
 692                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 693                                 phys = <&usb2_phy_prim>, <&usb3_phy>;
 694                                 phy-names = "usb2-phy", "usb3-phy";
 695                                 snps,has-lpm-erratum;
 696                                 snps,hird-threshold = /bits/ 8 <0x10>;
 697                                 snps,usb3_lpm_capable;
 698                                 dr_mode = "otg";
 699                         };
 700                 };
 701
 702                 usb2: usb@79b8800 {
 703                         compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
 704                         reg = <0x079b8800 0x400>;
 705                         #address-cells = <1>;
 706                         #size-cells = <1>;
 707                         ranges;
 708                         clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
 709                                  <&gcc GCC_PCNOC_USB2_CLK>,
 710                                  <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
 711                                  <&gcc GCC_USB20_MOCK_UTMI_CLK>;
 712                         clock-names = "core", "iface", "sleep", "mock_utmi";
 713                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 714                                           <&gcc GCC_USB_HS_SYSTEM_CLK>;
 715                         assigned-clock-rates = <19200000>, <133333333>;
 716                         status = "disabled";
 717
 718                         usb@78c0000 {
 719                                 compatible = "snps,dwc3";
 720                                 reg = <0x078c0000 0xcc00>;
 721                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 722                                 phys = <&usb2_phy_sec>;
 723                                 phy-names = "usb2-phy";
 724                                 snps,has-lpm-erratum;
 725                                 snps,hird-threshold = /bits/ 8 <0x10>;
 726                                 snps,usb3_lpm_capable;
 727                                 dr_mode = "peripheral";
 728                         };
 729                 };
 730
 731                 tlmm: pinctrl@1000000 {
 732                         compatible = "qcom,qcs404-pinctrl";
 733                         reg = <0x01000000 0x200000>,
 734                               <0x01300000 0x200000>,
 735                               <0x07b00000 0x200000>;
 736                         reg-names = "south", "north", "east";
 737                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 738                         gpio-ranges = <&tlmm 0 0 120>;
 739                         gpio-controller;
 740                         #gpio-cells = <2>;
 741                         interrupt-controller;
 742                         #interrupt-cells = <2>;
 743
 744                         blsp1_i2c0_default: blsp1-i2c0-default-state {
 745                                 pins = "gpio32", "gpio33";
 746                                 function = "blsp_i2c0";
 747                         };
 748
 749                         blsp1_i2c1_default: blsp1-i2c1-default-state {
 750                                 pins = "gpio24", "gpio25";
 751                                 function = "blsp_i2c1";
 752                         };
 753
 754                         blsp1_i2c2_default: blsp1-i2c2-default-state {
 755                                 sda-pins {
 756                                         pins = "gpio19";
 757                                         function = "blsp_i2c_sda_a2";
 758                                 };
 759
 760                                 scl-pins {
 761                                         pins = "gpio20";
 762                                         function = "blsp_i2c_scl_a2";
 763                                 };
 764                         };
 765
 766                         blsp1_i2c3_default: blsp1-i2c3-default-state {
 767                                 pins = "gpio84", "gpio85";
 768                                 function = "blsp_i2c3";
 769                         };
 770
 771                         blsp1_i2c4_default: blsp1-i2c4-default-state {
 772                                 pins = "gpio117", "gpio118";
 773                                 function = "blsp_i2c4";
 774                         };
 775
 776                         blsp1_uart0_default: blsp1-uart0-default-state {
 777                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 778                                 function = "blsp_uart0";
 779                         };
 780
 781                         blsp1_uart1_default: blsp1-uart1-default-state {
 782                                 pins = "gpio22", "gpio23";
 783                                 function = "blsp_uart1";
 784                         };
 785
 786                         blsp1_uart2_default: blsp1-uart2-default-state {
 787                                 rx-pins {
 788                                         pins = "gpio18";
 789                                         function = "blsp_uart_rx_a2";
 790                                 };
 791
 792                                 tx-pins {
 793                                         pins = "gpio17";
 794                                         function = "blsp_uart_tx_a2";
 795                                 };
 796                         };
 797
 798                         blsp1_uart3_default: blsp1-uart3-default-state {
 799                                 cts-pins {
 800                                         pins = "gpio84";
 801                                         function = "blsp_uart3";
 802                                 };
 803
 804                                 rts-tx-pins {
 805                                         pins = "gpio85", "gpio82";
 806                                         function = "blsp_uart3";
 807                                 };
 808
 809                                 rx-pins {
 810                                         pins = "gpio83";
 811                                         function = "blsp_uart3";
 812                                 };
 813                         };
 814
 815                         blsp2_i2c0_default: blsp2-i2c0-default-state {
 816                                 pins = "gpio28", "gpio29";
 817                                 function = "blsp_i2c5";
 818                         };
 819
 820                         blsp1_spi0_default: blsp1-spi0-default-state {
 821                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 822                                 function = "blsp_spi0";
 823                         };
 824
 825                         blsp1_spi1_default: blsp1-spi1-default-state {
 826                                 mosi-pins {
 827                                         pins = "gpio22";
 828                                         function = "blsp_spi_mosi_a1";
 829                                 };
 830
 831                                 miso-pins {
 832                                         pins = "gpio23";
 833                                         function = "blsp_spi_miso_a1";
 834                                 };
 835
 836                                 cs-n-pins {
 837                                         pins = "gpio24";
 838                                         function = "blsp_spi_cs_n_a1";
 839                                 };
 840
 841                                 clk-pins {
 842                                         pins = "gpio25";
 843                                         function = "blsp_spi_clk_a1";
 844                                 };
 845                         };
 846
 847                         blsp1_spi2_default: blsp1-spi2-default-state {
 848                                 pins = "gpio17", "gpio18", "gpio19", "gpio20";
 849                                 function = "blsp_spi2";
 850                         };
 851
 852                         blsp1_spi3_default: blsp1-spi3-default-state {
 853                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 854                                 function = "blsp_spi3";
 855                         };
 856
 857                         blsp1_spi4_default: blsp1-spi4-default-state {
 858                                 pins = "gpio37", "gpio38", "gpio117", "gpio118";
 859                                 function = "blsp_spi4";
 860                         };
 861
 862                         blsp2_spi0_default: blsp2-spi0-default-state {
 863                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 864                                 function = "blsp_spi5";
 865                         };
 866
 867                         blsp2_uart0_default: blsp2-uart0-default-state {
 868                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 869                                 function = "blsp_uart5";
 870                         };
 871                 };
 872
 873                 gcc: clock-controller@1800000 {
 874                         compatible = "qcom,gcc-qcs404";
 875                         reg = <0x01800000 0x80000>;
 876                         #clock-cells = <1>;
 877                         #reset-cells = <1>;
 878                         #power-domain-cells = <1>;
 879
 880                         clocks = <&xo_board>,
 881                                  <&sleep_clk>,
 882                                  <&pcie_phy>,
 883                                  <0>,
 884                                  <0>,
 885                                  <0>;
 886
 887                         assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
 888                         assigned-clock-rates = <19200000>;
 889                 };
 890
 891                 tcsr_mutex: hwlock@1905000 {
 892                         compatible = "qcom,tcsr-mutex";
 893                         reg = <0x01905000 0x20000>;
 894                         #hwlock-cells = <1>;
 895                 };
 896
 897                 tcsr: syscon@1937000 {
 898                         compatible = "qcom,qcs404-tcsr", "syscon";
 899                         reg = <0x01937000 0x25000>;
 900                 };
 901
 902                 sram@290000 {
 903                         compatible = "qcom,rpm-stats";
 904                         reg = <0x00290000 0x10000>;
 905                 };
 906
 907                 spmi_bus: spmi@200f000 {
 908                         compatible = "qcom,spmi-pmic-arb";
 909                         reg = <0x0200f000 0x001000>,
 910                               <0x02400000 0x800000>,
 911                               <0x02c00000 0x800000>,
 912                               <0x03800000 0x200000>,
 913                               <0x0200a000 0x002100>;
 914                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 915                         interrupt-names = "periph_irq";
 916                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 917                         qcom,ee = <0>;
 918                         qcom,channel = <0>;
 919                         #address-cells = <2>;
 920                         #size-cells = <0>;
 921                         interrupt-controller;
 922                         #interrupt-cells = <4>;
 923                 };
 924
 925                 remoteproc_wcss: remoteproc@7400000 {
 926                         compatible = "qcom,qcs404-wcss-pas";
 927                         reg = <0x07400000 0x4040>;
 928
 929                         interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
 930                                               <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 931                                               <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 932                                               <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 933                                               <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 934                         interrupt-names = "wdog", "fatal", "ready",
 935                                           "handover", "stop-ack";
 936
 937                         clocks = <&xo_board>;
 938                         clock-names = "xo";
 939
 940                         memory-region = <&wlan_fw_mem>;
 941
 942                         qcom,smem-states = <&wcss_smp2p_out 0>;
 943                         qcom,smem-state-names = "stop";
 944
 945                         status = "disabled";
 946
 947                         glink-edge {
 948                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 949
 950                                 qcom,remote-pid = <1>;
 951                                 mboxes = <&apcs_glb 16>;
 952
 953                                 label = "wcss";
 954                         };
 955                 };
 956
 957                 pcie_phy: phy@7786000 {
 958                         compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
 959                         reg = <0x07786000 0xb8>;
 960
 961                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 962                         resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
 963                                  <&gcc GCC_PCIE_0_PIPE_ARES>;
 964                         reset-names = "phy", "pipe";
 965
 966                         clock-output-names = "pcie_0_pipe_clk";
 967                         #clock-cells = <0>;
 968                         #phy-cells = <0>;
 969
 970                         status = "disabled";
 971                 };
 972
 973                 sdcc1: mmc@7804000 {
 974                         compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
 975                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
 976                         reg-names = "hc", "cqhci";
 977
 978                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 979                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 980                         interrupt-names = "hc_irq", "pwr_irq";
 981
 982                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 983                                  <&gcc GCC_SDCC1_APPS_CLK>,
 984                                  <&xo_board>;
 985                         clock-names = "iface", "core", "xo";
 986
 987                         status = "disabled";
 988                 };
 989
 990                 blsp1_dma: dma-controller@7884000 {
 991                         compatible = "qcom,bam-v1.7.0";
 992                         reg = <0x07884000 0x25000>;
 993                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 994                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 995                         clock-names = "bam_clk";
 996                         #dma-cells = <1>;
 997                         qcom,ee = <0>;
 998                         status = "okay";
 999                 };
1000
1001                 blsp1_uart0: serial@78af000 {
1002                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1003                         reg = <0x078af000 0x200>;
1004                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1005                         clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1006                         clock-names = "core", "iface";
1007                         dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1008                         dma-names = "tx", "rx";
1009                         pinctrl-names = "default";
1010                         pinctrl-0 = <&blsp1_uart0_default>;
1011                         status = "disabled";
1012                 };
1013
1014                 blsp1_uart1: serial@78b0000 {
1015                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1016                         reg = <0x078b0000 0x200>;
1017                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1018                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1019                         clock-names = "core", "iface";
1020                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1021                         dma-names = "tx", "rx";
1022                         pinctrl-names = "default";
1023                         pinctrl-0 = <&blsp1_uart1_default>;
1024                         status = "disabled";
1025                 };
1026
1027                 blsp1_uart2: serial@78b1000 {
1028                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1029                         reg = <0x078b1000 0x200>;
1030                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1031                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1032                         clock-names = "core", "iface";
1033                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1034                         dma-names = "tx", "rx";
1035                         pinctrl-names = "default";
1036                         pinctrl-0 = <&blsp1_uart2_default>;
1037                         status = "okay";
1038                 };
1039
1040                 ethernet: ethernet@7a80000 {
1041                         compatible = "qcom,qcs404-ethqos";
1042                         reg = <0x07a80000 0x10000>,
1043                                 <0x07a96000 0x100>;
1044                         reg-names = "stmmaceth", "rgmii";
1045                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
1046                         clocks = <&gcc GCC_ETH_AXI_CLK>,
1047                                 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
1048                                 <&gcc GCC_ETH_PTP_CLK>,
1049                                 <&gcc GCC_ETH_RGMII_CLK>;
1050                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1051                                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1052                         interrupt-names = "macirq", "eth_lpi";
1053
1054                         snps,tso;
1055                         rx-fifo-depth = <4096>;
1056                         tx-fifo-depth = <4096>;
1057
1058                         status = "disabled";
1059                 };
1060
1061                 wifi: wifi@a000000 {
1062                         compatible = "qcom,wcn3990-wifi";
1063                         reg = <0xa000000 0x800000>;
1064                         reg-names = "membase";
1065                         memory-region = <&wlan_msa_mem>;
1066                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
1067                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
1068                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1069                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1070                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1071                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1072                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1073                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1074                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
1075                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
1076                                      <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
1077                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1078                         status = "disabled";
1079                 };
1080
1081                 blsp1_uart3: serial@78b2000 {
1082                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1083                         reg = <0x078b2000 0x200>;
1084                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1085                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1086                         clock-names = "core", "iface";
1087                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1088                         dma-names = "tx", "rx";
1089                         pinctrl-names = "default";
1090                         pinctrl-0 = <&blsp1_uart3_default>;
1091                         status = "disabled";
1092                 };
1093
1094                 blsp1_i2c0: i2c@78b5000 {
1095                         compatible = "qcom,i2c-qup-v2.2.1";
1096                         reg = <0x078b5000 0x600>;
1097                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1098                         clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
1099                                  <&gcc GCC_BLSP1_AHB_CLK>;
1100                         clock-names = "core", "iface";
1101                         pinctrl-names = "default";
1102                         pinctrl-0 = <&blsp1_i2c0_default>;
1103                         #address-cells = <1>;
1104                         #size-cells = <0>;
1105                         status = "disabled";
1106                 };
1107
1108                 blsp1_spi0: spi@78b5000 {
1109                         compatible = "qcom,spi-qup-v2.2.1";
1110                         reg = <0x078b5000 0x600>;
1111                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1112                         clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
1113                                  <&gcc GCC_BLSP1_AHB_CLK>;
1114                         clock-names = "core", "iface";
1115                         pinctrl-names = "default";
1116                         pinctrl-0 = <&blsp1_spi0_default>;
1117                         #address-cells = <1>;
1118                         #size-cells = <0>;
1119                         status = "disabled";
1120                 };
1121
1122                 blsp1_i2c1: i2c@78b6000 {
1123                         compatible = "qcom,i2c-qup-v2.2.1";
1124                         reg = <0x078b6000 0x600>;
1125                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1126                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1127                                  <&gcc GCC_BLSP1_AHB_CLK>;
1128                         clock-names = "core", "iface";
1129                         pinctrl-names = "default";
1130                         pinctrl-0 = <&blsp1_i2c1_default>;
1131                         #address-cells = <1>;
1132                         #size-cells = <0>;
1133                         status = "disabled";
1134                 };
1135
1136                 blsp1_spi1: spi@78b6000 {
1137                         compatible = "qcom,spi-qup-v2.2.1";
1138                         reg = <0x078b6000 0x600>;
1139                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1140                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1141                                  <&gcc GCC_BLSP1_AHB_CLK>;
1142                         clock-names = "core", "iface";
1143                         pinctrl-names = "default";
1144                         pinctrl-0 = <&blsp1_spi1_default>;
1145                         #address-cells = <1>;
1146                         #size-cells = <0>;
1147                         status = "disabled";
1148                 };
1149
1150                 blsp1_i2c2: i2c@78b7000 {
1151                         compatible = "qcom,i2c-qup-v2.2.1";
1152                         reg = <0x078b7000 0x600>;
1153                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1154                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1155                                  <&gcc GCC_BLSP1_AHB_CLK>;
1156                         clock-names = "core", "iface";
1157                         pinctrl-names = "default";
1158                         pinctrl-0 = <&blsp1_i2c2_default>;
1159                         #address-cells = <1>;
1160                         #size-cells = <0>;
1161                         status = "disabled";
1162                 };
1163
1164                 blsp1_spi2: spi@78b7000 {
1165                         compatible = "qcom,spi-qup-v2.2.1";
1166                         reg = <0x078b7000 0x600>;
1167                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1168                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1169                                  <&gcc GCC_BLSP1_AHB_CLK>;
1170                         clock-names = "core", "iface";
1171                         pinctrl-names = "default";
1172                         pinctrl-0 = <&blsp1_spi2_default>;
1173                         #address-cells = <1>;
1174                         #size-cells = <0>;
1175                         status = "disabled";
1176                 };
1177
1178                 blsp1_i2c3: i2c@78b8000 {
1179                         compatible = "qcom,i2c-qup-v2.2.1";
1180                         reg = <0x078b8000 0x600>;
1181                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1182                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1183                                  <&gcc GCC_BLSP1_AHB_CLK>;
1184                         clock-names = "core", "iface";
1185                         pinctrl-names = "default";
1186                         pinctrl-0 = <&blsp1_i2c3_default>;
1187                         #address-cells = <1>;
1188                         #size-cells = <0>;
1189                         status = "disabled";
1190                 };
1191
1192                 blsp1_spi3: spi@78b8000 {
1193                         compatible = "qcom,spi-qup-v2.2.1";
1194                         reg = <0x078b8000 0x600>;
1195                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1196                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1197                                  <&gcc GCC_BLSP1_AHB_CLK>;
1198                         clock-names = "core", "iface";
1199                         pinctrl-names = "default";
1200                         pinctrl-0 = <&blsp1_spi3_default>;
1201                         #address-cells = <1>;
1202                         #size-cells = <0>;
1203                         status = "disabled";
1204                 };
1205
1206                 blsp1_i2c4: i2c@78b9000 {
1207                         compatible = "qcom,i2c-qup-v2.2.1";
1208                         reg = <0x078b9000 0x600>;
1209                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1210                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1211                                  <&gcc GCC_BLSP1_AHB_CLK>;
1212                         clock-names = "core", "iface";
1213                         pinctrl-names = "default";
1214                         pinctrl-0 = <&blsp1_i2c4_default>;
1215                         #address-cells = <1>;
1216                         #size-cells = <0>;
1217                         status = "disabled";
1218                 };
1219
1220                 blsp1_spi4: spi@78b9000 {
1221                         compatible = "qcom,spi-qup-v2.2.1";
1222                         reg = <0x078b9000 0x600>;
1223                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1224                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1225                                  <&gcc GCC_BLSP1_AHB_CLK>;
1226                         clock-names = "core", "iface";
1227                         pinctrl-names = "default";
1228                         pinctrl-0 = <&blsp1_spi4_default>;
1229                         #address-cells = <1>;
1230                         #size-cells = <0>;
1231                         status = "disabled";
1232                 };
1233
1234                 blsp2_dma: dma-controller@7ac4000 {
1235                         compatible = "qcom,bam-v1.7.0";
1236                         reg = <0x07ac4000 0x17000>;
1237                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1238                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1239                         clock-names = "bam_clk";
1240                         #dma-cells = <1>;
1241                         qcom,ee = <0>;
1242                         status = "disabled";
1243                 };
1244
1245                 blsp2_uart0: serial@7aef000 {
1246                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1247                         reg = <0x07aef000 0x200>;
1248                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1249                         clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1250                         clock-names = "core", "iface";
1251                         dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1252                         dma-names = "tx", "rx";
1253                         pinctrl-names = "default";
1254                         pinctrl-0 = <&blsp2_uart0_default>;
1255                         status = "disabled";
1256                 };
1257
1258                 blsp2_i2c0: i2c@7af5000 {
1259                         compatible = "qcom,i2c-qup-v2.2.1";
1260                         reg = <0x07af5000 0x600>;
1261                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1262                         clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
1263                                  <&gcc GCC_BLSP2_AHB_CLK>;
1264                         clock-names = "core", "iface";
1265                         pinctrl-names = "default";
1266                         pinctrl-0 = <&blsp2_i2c0_default>;
1267                         #address-cells = <1>;
1268                         #size-cells = <0>;
1269                         status = "disabled";
1270                 };
1271
1272                 blsp2_spi0: spi@7af5000 {
1273                         compatible = "qcom,spi-qup-v2.2.1";
1274                         reg = <0x07af5000 0x600>;
1275                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1276                         clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
1277                                  <&gcc GCC_BLSP2_AHB_CLK>;
1278                         clock-names = "core", "iface";
1279                         pinctrl-names = "default";
1280                         pinctrl-0 = <&blsp2_spi0_default>;
1281                         #address-cells = <1>;
1282                         #size-cells = <0>;
1283                         status = "disabled";
1284                 };
1285
1286                 sram@8600000 {
1287                         compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
1288                         reg = <0x08600000 0x1000>;
1289
1290                         #address-cells = <1>;
1291                         #size-cells = <1>;
1292
1293                         ranges = <0 0x08600000 0x1000>;
1294
1295                         pil-reloc@94c {
1296                                 compatible = "qcom,pil-reloc-info";
1297                                 reg = <0x94c 0xc8>;
1298                         };
1299                 };
1300
1301                 intc: interrupt-controller@b000000 {
1302                         compatible = "qcom,msm-qgic2";
1303                         interrupt-controller;
1304                         #interrupt-cells = <3>;
1305                         reg = <0x0b000000 0x1000>,
1306                               <0x0b002000 0x1000>;
1307                 };
1308
1309                 apcs_glb: mailbox@b011000 {
1310                         compatible = "qcom,qcs404-apcs-apps-global",
1311                                      "qcom,msm8916-apcs-kpss-global", "syscon";
1312                         reg = <0x0b011000 0x1000>;
1313                         #mbox-cells = <1>;
1314                         clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1315                         clock-names = "pll", "aux";
1316                         #clock-cells = <0>;
1317                 };
1318
1319                 apcs_hfpll: clock-controller@b016000 {
1320                         compatible = "qcom,hfpll";
1321                         reg = <0x0b016000 0x30>;
1322                         #clock-cells = <0>;
1323                         clock-output-names = "apcs_hfpll";
1324                         clocks = <&xo_board>;
1325                         clock-names = "xo";
1326                 };
1327
1328                 watchdog@b017000 {
1329                         compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
1330                         reg = <0x0b017000 0x1000>;
1331                         clocks = <&sleep_clk>;
1332                 };
1333
1334                 cpr: power-controller@b018000 {
1335                         compatible = "qcom,qcs404-cpr", "qcom,cpr";
1336                         reg = <0x0b018000 0x1000>;
1337                         interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
1338                         clocks = <&xo_board>;
1339                         clock-names = "ref";
1340                         vdd-apc-supply = <&pms405_s3>;
1341                         #power-domain-cells = <0>;
1342                         operating-points-v2 = <&cpr_opp_table>;
1343                         acc-syscon = <&tcsr>;
1344
1345                         nvmem-cells = <&cpr_efuse_quot_offset1>,
1346                                 <&cpr_efuse_quot_offset2>,
1347                                 <&cpr_efuse_quot_offset3>,
1348                                 <&cpr_efuse_init_voltage1>,
1349                                 <&cpr_efuse_init_voltage2>,
1350                                 <&cpr_efuse_init_voltage3>,
1351                                 <&cpr_efuse_quot1>,
1352                                 <&cpr_efuse_quot2>,
1353                                 <&cpr_efuse_quot3>,
1354                                 <&cpr_efuse_ring1>,
1355                                 <&cpr_efuse_ring2>,
1356                                 <&cpr_efuse_ring3>,
1357                                 <&cpr_efuse_revision>;
1358                         nvmem-cell-names = "cpr_quotient_offset1",
1359                                 "cpr_quotient_offset2",
1360                                 "cpr_quotient_offset3",
1361                                 "cpr_init_voltage1",
1362                                 "cpr_init_voltage2",
1363                                 "cpr_init_voltage3",
1364                                 "cpr_quotient1",
1365                                 "cpr_quotient2",
1366                                 "cpr_quotient3",
1367                                 "cpr_ring_osc1",
1368                                 "cpr_ring_osc2",
1369                                 "cpr_ring_osc3",
1370                                 "cpr_fuse_revision";
1371                 };
1372
1373                 timer@b120000 {
1374                         #address-cells = <1>;
1375                         #size-cells = <1>;
1376                         ranges;
1377                         compatible = "arm,armv7-timer-mem";
1378                         reg = <0x0b120000 0x1000>;
1379                         clock-frequency = <19200000>;
1380
1381                         frame@b121000 {
1382                                 frame-number = <0>;
1383                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1384                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1385                                 reg = <0x0b121000 0x1000>,
1386                                       <0x0b122000 0x1000>;
1387                         };
1388
1389                         frame@b123000 {
1390                                 frame-number = <1>;
1391                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1392                                 reg = <0x0b123000 0x1000>;
1393                                 status = "disabled";
1394                         };
1395
1396                         frame@b124000 {
1397                                 frame-number = <2>;
1398                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1399                                 reg = <0x0b124000 0x1000>;
1400                                 status = "disabled";
1401                         };
1402
1403                         frame@b125000 {
1404                                 frame-number = <3>;
1405                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1406                                 reg = <0x0b125000 0x1000>;
1407                                 status = "disabled";
1408                         };
1409
1410                         frame@b126000 {
1411                                 frame-number = <4>;
1412                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1413                                 reg = <0x0b126000 0x1000>;
1414                                 status = "disabled";
1415                         };
1416
1417                         frame@b127000 {
1418                                 frame-number = <5>;
1419                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1420                                 reg = <0xb127000 0x1000>;
1421                                 status = "disabled";
1422                         };
1423
1424                         frame@b128000 {
1425                                 frame-number = <6>;
1426                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1427                                 reg = <0x0b128000 0x1000>;
1428                                 status = "disabled";
1429                         };
1430                 };
1431
1432                 remoteproc_adsp: remoteproc@c700000 {
1433                         compatible = "qcom,qcs404-adsp-pas";
1434                         reg = <0x0c700000 0x4040>;
1435
1436                         interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
1437                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1438                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1439                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1440                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1441                         interrupt-names = "wdog", "fatal", "ready",
1442                                           "handover", "stop-ack";
1443
1444                         clocks = <&xo_board>;
1445                         clock-names = "xo";
1446
1447                         memory-region = <&adsp_fw_mem>;
1448
1449                         qcom,smem-states = <&adsp_smp2p_out 0>;
1450                         qcom,smem-state-names = "stop";
1451
1452                         status = "disabled";
1453
1454                         glink-edge {
1455                                 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
1456
1457                                 qcom,remote-pid = <2>;
1458                                 mboxes = <&apcs_glb 8>;
1459
1460                                 label = "adsp";
1461                         };
1462                 };
1463
1464                 pcie: pci@10000000 {
1465                         compatible = "qcom,pcie-qcs404";
1466                         reg = <0x10000000 0xf1d>,
1467                               <0x10000f20 0xa8>,
1468                               <0x07780000 0x2000>,
1469                               <0x10001000 0x2000>;
1470                         reg-names = "dbi", "elbi", "parf", "config";
1471                         device_type = "pci";
1472                         linux,pci-domain = <0>;
1473                         bus-range = <0x00 0xff>;
1474                         num-lanes = <1>;
1475                         #address-cells = <3>;
1476                         #size-cells = <2>;
1477
1478                         ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
1479                                  <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
1480
1481                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1482                         interrupt-names = "msi";
1483                         #interrupt-cells = <1>;
1484                         interrupt-map-mask = <0 0 0 0x7>;
1485                         interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1486                                         <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1487                                         <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1488                                         <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1489                         clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1490                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1491                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1492                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1493                         clock-names = "iface", "aux", "master_bus", "slave_bus";
1494
1495                         resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
1496                                  <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
1497                                  <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
1498                                  <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
1499                                  <&gcc GCC_PCIE_0_BCR>,
1500                                  <&gcc GCC_PCIE_0_AHB_ARES>;
1501                         reset-names = "axi_m",
1502                                       "axi_s",
1503                                       "axi_m_sticky",
1504                                       "pipe_sticky",
1505                                       "pwr",
1506                                       "ahb";
1507
1508                         phys = <&pcie_phy>;
1509                         phy-names = "pciephy";
1510
1511                         status = "disabled";
1512                 };
1513         };
1514
1515         timer {
1516                 compatible = "arm,armv8-timer";
1517                 interrupts = <GIC_PPI 2 0xff08>,
1518                              <GIC_PPI 3 0xff08>,
1519                              <GIC_PPI 4 0xff08>,
1520                              <GIC_PPI 1 0xff08>;
1521         };
1522
1523         smp2p-adsp {
1524                 compatible = "qcom,smp2p";
1525                 qcom,smem = <443>, <429>;
1526                 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
1527                 mboxes = <&apcs_glb 10>;
1528                 qcom,local-pid = <0>;
1529                 qcom,remote-pid = <2>;
1530
1531                 adsp_smp2p_out: master-kernel {
1532                         qcom,entry-name = "master-kernel";
1533                         #qcom,smem-state-cells = <1>;
1534                 };
1535
1536                 adsp_smp2p_in: slave-kernel {
1537                         qcom,entry-name = "slave-kernel";
1538                         interrupt-controller;
1539                         #interrupt-cells = <2>;
1540                 };
1541         };
1542
1543         smp2p-cdsp {
1544                 compatible = "qcom,smp2p";
1545                 qcom,smem = <94>, <432>;
1546                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
1547                 mboxes = <&apcs_glb 14>;
1548                 qcom,local-pid = <0>;
1549                 qcom,remote-pid = <5>;
1550
1551                 cdsp_smp2p_out: master-kernel {
1552                         qcom,entry-name = "master-kernel";
1553                         #qcom,smem-state-cells = <1>;
1554                 };
1555
1556                 cdsp_smp2p_in: slave-kernel {
1557                         qcom,entry-name = "slave-kernel";
1558                         interrupt-controller;
1559                         #interrupt-cells = <2>;
1560                 };
1561         };
1562
1563         smp2p-wcss {
1564                 compatible = "qcom,smp2p";
1565                 qcom,smem = <435>, <428>;
1566                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1567                 mboxes = <&apcs_glb 18>;
1568                 qcom,local-pid = <0>;
1569                 qcom,remote-pid = <1>;
1570
1571                 wcss_smp2p_out: master-kernel {
1572                         qcom,entry-name = "master-kernel";
1573                         #qcom,smem-state-cells = <1>;
1574                 };
1575
1576                 wcss_smp2p_in: slave-kernel {
1577                         qcom,entry-name = "slave-kernel";
1578                         interrupt-controller;
1579                         #interrupt-cells = <2>;
1580                 };
1581         };
1582
1583         thermal-zones {
1584                 aoss-thermal {
1585                         polling-delay-passive = <250>;
1586                         polling-delay = <1000>;
1587
1588                         thermal-sensors = <&tsens 0>;
1589
1590                         trips {
1591                                 aoss_alert0: trip-point0 {
1592                                         temperature = <105000>;
1593                                         hysteresis = <2000>;
1594                                         type = "hot";
1595                                 };
1596                         };
1597                 };
1598
1599                 q6-hvx-thermal {
1600                         polling-delay-passive = <250>;
1601                         polling-delay = <1000>;
1602
1603                         thermal-sensors = <&tsens 1>;
1604
1605                         trips {
1606                                 q6_hvx_alert0: trip-point0 {
1607                                         temperature = <105000>;
1608                                         hysteresis = <2000>;
1609                                         type = "hot";
1610                                 };
1611                         };
1612                 };
1613
1614                 lpass-thermal {
1615                         polling-delay-passive = <250>;
1616                         polling-delay = <1000>;
1617
1618                         thermal-sensors = <&tsens 2>;
1619
1620                         trips {
1621                                 lpass_alert0: trip-point0 {
1622                                         temperature = <105000>;
1623                                         hysteresis = <2000>;
1624                                         type = "hot";
1625                                 };
1626                         };
1627                 };
1628
1629                 wlan-thermal {
1630                         polling-delay-passive = <250>;
1631                         polling-delay = <1000>;
1632
1633                         thermal-sensors = <&tsens 3>;
1634
1635                         trips {
1636                                 wlan_alert0: trip-point0 {
1637                                         temperature = <105000>;
1638                                         hysteresis = <2000>;
1639                                         type = "hot";
1640                                 };
1641                         };
1642                 };
1643
1644                 cluster-thermal {
1645                         polling-delay-passive = <250>;
1646                         polling-delay = <1000>;
1647
1648                         thermal-sensors = <&tsens 4>;
1649
1650                         trips {
1651                                 cluster_alert0: trip-point0 {
1652                                         temperature = <95000>;
1653                                         hysteresis = <2000>;
1654                                         type = "hot";
1655                                 };
1656                                 cluster_alert1: trip-point1 {
1657                                         temperature = <105000>;
1658                                         hysteresis = <2000>;
1659                                         type = "passive";
1660                                 };
1661                                 cluster_crit: cluster-crit {
1662                                         temperature = <120000>;
1663                                         hysteresis = <2000>;
1664                                         type = "critical";
1665                                 };
1666                         };
1667                         cooling-maps {
1668                                 map0 {
1669                                         trip = <&cluster_alert1>;
1670                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1671                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1672                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1673                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1674                                 };
1675                         };
1676                 };
1677
1678                 cpu0-thermal {
1679                         polling-delay-passive = <250>;
1680                         polling-delay = <1000>;
1681
1682                         thermal-sensors = <&tsens 5>;
1683
1684                         trips {
1685                                 cpu0_alert0: trip-point0 {
1686                                         temperature = <95000>;
1687                                         hysteresis = <2000>;
1688                                         type = "hot";
1689                                 };
1690                                 cpu0_alert1: trip-point1 {
1691                                         temperature = <105000>;
1692                                         hysteresis = <2000>;
1693                                         type = "passive";
1694                                 };
1695                                 cpu0_crit: cpu-crit {
1696                                         temperature = <120000>;
1697                                         hysteresis = <2000>;
1698                                         type = "critical";
1699                                 };
1700                         };
1701                         cooling-maps {
1702                                 map0 {
1703                                         trip = <&cpu0_alert1>;
1704                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1705                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1706                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1707                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1708                                 };
1709                         };
1710                 };
1711
1712                 cpu1-thermal {
1713                         polling-delay-passive = <250>;
1714                         polling-delay = <1000>;
1715
1716                         thermal-sensors = <&tsens 6>;
1717
1718                         trips {
1719                                 cpu1_alert0: trip-point0 {
1720                                         temperature = <95000>;
1721                                         hysteresis = <2000>;
1722                                         type = "hot";
1723                                 };
1724                                 cpu1_alert1: trip-point1 {
1725                                         temperature = <105000>;
1726                                         hysteresis = <2000>;
1727                                         type = "passive";
1728                                 };
1729                                 cpu1_crit: cpu-crit {
1730                                         temperature = <120000>;
1731                                         hysteresis = <2000>;
1732                                         type = "critical";
1733                                 };
1734                         };
1735                         cooling-maps {
1736                                 map0 {
1737                                         trip = <&cpu1_alert1>;
1738                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1739                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1740                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1741                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1742                                 };
1743                         };
1744                 };
1745
1746                 cpu2-thermal {
1747                         polling-delay-passive = <250>;
1748                         polling-delay = <1000>;
1749
1750                         thermal-sensors = <&tsens 7>;
1751
1752                         trips {
1753                                 cpu2_alert0: trip-point0 {
1754                                         temperature = <95000>;
1755                                         hysteresis = <2000>;
1756                                         type = "hot";
1757                                 };
1758                                 cpu2_alert1: trip-point1 {
1759                                         temperature = <105000>;
1760                                         hysteresis = <2000>;
1761                                         type = "passive";
1762                                 };
1763                                 cpu2_crit: cpu-crit {
1764                                         temperature = <120000>;
1765                                         hysteresis = <2000>;
1766                                         type = "critical";
1767                                 };
1768                         };
1769                         cooling-maps {
1770                                 map0 {
1771                                         trip = <&cpu2_alert1>;
1772                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1773                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1774                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1775                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1776                                 };
1777                         };
1778                 };
1779
1780                 cpu3-thermal {
1781                         polling-delay-passive = <250>;
1782                         polling-delay = <1000>;
1783
1784                         thermal-sensors = <&tsens 8>;
1785
1786                         trips {
1787                                 cpu3_alert0: trip-point0 {
1788                                         temperature = <95000>;
1789                                         hysteresis = <2000>;
1790                                         type = "hot";
1791                                 };
1792                                 cpu3_alert1: trip-point1 {
1793                                         temperature = <105000>;
1794                                         hysteresis = <2000>;
1795                                         type = "passive";
1796                                 };
1797                                 cpu3_crit: cpu-crit {
1798                                         temperature = <120000>;
1799                                         hysteresis = <2000>;
1800                                         type = "critical";
1801                                 };
1802                         };
1803                         cooling-maps {
1804                                 map0 {
1805                                         trip = <&cpu3_alert1>;
1806                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1807                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1808                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1809                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1810                                 };
1811                         };
1812                 };
1813
1814                 gpu-thermal {
1815                         polling-delay-passive = <250>;
1816                         polling-delay = <1000>;
1817
1818                         thermal-sensors = <&tsens 9>;
1819
1820                         trips {
1821                                 gpu_alert0: trip-point0 {
1822                                         temperature = <95000>;
1823                                         hysteresis = <2000>;
1824                                         type = "hot";
1825                                 };
1826                         };
1827                 };
1828         };
1829 };