1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, Linaro Limited
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/thermal/thermal.h>
12 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
33 compatible = "arm,cortex-a53";
35 enable-method = "psci";
36 cpu-idle-states = <&CPU_SLEEP_0>;
37 next-level-cache = <&L2_0>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 cpu-idle-states = <&CPU_SLEEP_0>;
47 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
57 next-level-cache = <&L2_0>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 cpu-idle-states = <&CPU_SLEEP_0>;
67 next-level-cache = <&L2_0>;
77 entry-method = "psci";
79 CPU_SLEEP_0: cpu-sleep-0 {
80 compatible = "arm,idle-state";
81 idle-state-name = "standalone-power-collapse";
82 arm,psci-suspend-param = <0x40000003>;
83 entry-latency-us = <125>;
84 exit-latency-us = <180>;
85 min-residency-us = <595>;
93 compatible = "qcom,scm-qcs404", "qcom,scm";
99 device_type = "memory";
100 /* We expect the bootloader to fill in the size */
101 reg = <0 0x80000000 0 0>;
105 compatible = "arm,psci-1.0";
110 #address-cells = <2>;
114 tz_apps_mem: memory@85900000 {
115 reg = <0 0x85900000 0 0x500000>;
119 xbl_mem: memory@85e00000 {
120 reg = <0 0x85e00000 0 0x100000>;
124 smem_region: memory@85f00000 {
125 reg = <0 0x85f00000 0 0x200000>;
129 tz_mem: memory@86100000 {
130 reg = <0 0x86100000 0 0x300000>;
134 wlan_fw_mem: memory@86400000 {
135 reg = <0 0x86400000 0 0x1100000>;
139 adsp_fw_mem: memory@87500000 {
140 reg = <0 0x87500000 0 0x1a00000>;
144 cdsp_fw_mem: memory@88f00000 {
145 reg = <0 0x88f00000 0 0x600000>;
149 wlan_msa_mem: memory@89500000 {
150 reg = <0 0x89500000 0 0x100000>;
154 uefi_mem: memory@9f800000 {
155 reg = <0 0x9f800000 0 0x800000>;
161 compatible = "qcom,glink-rpm";
163 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
164 qcom,rpm-msg-ram = <&rpm_msg_ram>;
165 mboxes = <&apcs_glb 0>;
167 rpm_requests: glink-channel {
168 compatible = "qcom,rpm-qcs404";
169 qcom,glink-channels = "rpm_requests";
171 rpmcc: clock-controller {
172 compatible = "qcom,rpmcc-qcs404";
176 rpmpd: power-controller {
177 compatible = "qcom,qcs404-rpmpd";
178 #power-domain-cells = <1>;
179 operating-points-v2 = <&rpmpd_opp_table>;
181 rpmpd_opp_table: opp-table {
182 compatible = "operating-points-v2";
184 rpmpd_opp_ret: opp1 {
188 rpmpd_opp_ret_plus: opp2 {
192 rpmpd_opp_min_svs: opp3 {
196 rpmpd_opp_low_svs: opp4 {
200 rpmpd_opp_svs: opp5 {
204 rpmpd_opp_svs_plus: opp6 {
208 rpmpd_opp_nom: opp7 {
212 rpmpd_opp_nom_plus: opp8 {
216 rpmpd_opp_turbo: opp9 {
220 rpmpd_opp_turbo_no_cpr: opp10 {
224 rpmpd_opp_turbo_plus: opp11 {
233 compatible = "qcom,smem";
235 memory-region = <&smem_region>;
236 qcom,rpm-msg-ram = <&rpm_msg_ram>;
238 hwlocks = <&tcsr_mutex 3>;
242 compatible = "qcom,tcsr-mutex";
243 syscon = <&tcsr_mutex_regs 0 0x1000>;
248 #address-cells = <1>;
250 ranges = <0 0 0 0xffffffff>;
251 compatible = "simple-bus";
253 turingcc: clock-controller@800000 {
254 compatible = "qcom,qcs404-turingcc";
255 reg = <0x00800000 0x30000>;
256 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
264 rpm_msg_ram: memory@60000 {
265 compatible = "qcom,rpm-msg-ram";
266 reg = <0x00060000 0x6000>;
269 qfprom: qfprom@a4000 {
270 compatible = "qcom,qfprom";
271 reg = <0x000a4000 0x1000>;
272 #address-cells = <1>;
274 tsens_caldata: caldata@d0 {
280 compatible = "qcom,prng-ee";
281 reg = <0x000e3000 0x1000>;
282 clocks = <&gcc GCC_PRNG_AHB_CLK>;
283 clock-names = "core";
286 tsens: thermal-sensor@4a9000 {
287 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
288 reg = <0x004a9000 0x1000>, /* TM */
289 <0x004a8000 0x1000>; /* SROT */
290 nvmem-cells = <&tsens_caldata>;
291 nvmem-cell-names = "calib";
292 #qcom,sensors = <10>;
293 #thermal-sensor-cells = <1>;
296 remoteproc_cdsp: remoteproc@b00000 {
297 compatible = "qcom,qcs404-cdsp-pas";
298 reg = <0x00b00000 0x4040>;
300 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
301 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
302 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
303 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
304 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
305 interrupt-names = "wdog", "fatal", "ready",
306 "handover", "stop-ack";
308 clocks = <&xo_board>,
309 <&gcc GCC_CDSP_CFG_AHB_CLK>,
310 <&gcc GCC_CDSP_TBU_CLK>,
311 <&gcc GCC_BIMC_CDSP_CLK>,
312 <&turingcc TURING_WRAPPER_AON_CLK>,
313 <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
314 <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
315 <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
325 resets = <&gcc GCC_CDSP_RESTART>;
326 reset-names = "restart";
328 qcom,halt-regs = <&tcsr 0x19004>;
330 memory-region = <&cdsp_fw_mem>;
332 qcom,smem-states = <&cdsp_smp2p_out 0>;
333 qcom,smem-state-names = "stop";
338 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
340 qcom,remote-pid = <5>;
341 mboxes = <&apcs_glb 12>;
347 tlmm: pinctrl@1000000 {
348 compatible = "qcom,qcs404-pinctrl";
349 reg = <0x01000000 0x200000>,
350 <0x01300000 0x200000>,
351 <0x07b00000 0x200000>;
352 reg-names = "south", "north", "east";
353 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
354 gpio-ranges = <&tlmm 0 0 120>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
360 blsp1_i2c0_default: blsp1-i2c0-default {
361 pins = "gpio32", "gpio33";
362 function = "blsp_i2c0";
365 blsp1_i2c1_default: blsp1-i2c1-default {
366 pins = "gpio24", "gpio25";
367 function = "blsp_i2c1";
370 blsp1_i2c2_default: blsp1-i2c2-default {
373 function = "blsp_i2c_sda_a2";
378 function = "blsp_i2c_scl_a2";
382 blsp1_i2c3_default: blsp1-i2c3-default {
383 pins = "gpio84", "gpio85";
384 function = "blsp_i2c3";
387 blsp1_i2c4_default: blsp1-i2c4-default {
388 pins = "gpio117", "gpio118";
389 function = "blsp_i2c4";
392 blsp1_uart0_default: blsp1-uart0-default {
393 pins = "gpio30", "gpio31", "gpio32", "gpio33";
394 function = "blsp_uart0";
397 blsp1_uart1_default: blsp1-uart1-default {
398 pins = "gpio22", "gpio23";
399 function = "blsp_uart1";
402 blsp1_uart2_default: blsp1-uart2-default {
405 function = "blsp_uart_rx_a2";
410 function = "blsp_uart_tx_a2";
414 blsp1_uart3_default: blsp1-uart3-default {
415 pins = "gpio82", "gpio83", "gpio84", "gpio85";
416 function = "blsp_uart3";
419 blsp2_i2c0_default: blsp2-i2c0-default {
420 pins = "gpio28", "gpio29";
421 function = "blsp_i2c5";
424 blsp1_spi0_default: blsp1-spi0-default {
425 pins = "gpio30", "gpio31", "gpio32", "gpio33";
426 function = "blsp_spi0";
429 blsp1_spi1_default: blsp1-spi1-default {
430 pins = "gpio22", "gpio23", "gpio24", "gpio25";
431 function = "blsp_spi1";
434 blsp1_spi2_default: blsp1-spi2-default {
435 pins = "gpio17", "gpio18", "gpio19", "gpio20";
436 function = "blsp_spi2";
439 blsp1_spi3_default: blsp1-spi3-default {
440 pins = "gpio82", "gpio83", "gpio84", "gpio85";
441 function = "blsp_spi3";
444 blsp1_spi4_default: blsp1-spi4-default {
445 pins = "gpio37", "gpio38", "gpio117", "gpio118";
446 function = "blsp_spi4";
449 blsp2_spi0_default: blsp2-spi0-default {
450 pins = "gpio26", "gpio27", "gpio28", "gpio29";
451 function = "blsp_spi5";
454 blsp2_uart0_default: blsp2-uart0-default {
455 pins = "gpio26", "gpio27", "gpio28", "gpio29";
456 function = "blsp_uart5";
460 gcc: clock-controller@1800000 {
461 compatible = "qcom,gcc-qcs404";
462 reg = <0x01800000 0x80000>;
466 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
467 assigned-clock-rates = <19200000>;
470 tcsr_mutex_regs: syscon@1905000 {
471 compatible = "syscon";
472 reg = <0x01905000 0x20000>;
475 tcsr: syscon@1937000 {
476 compatible = "syscon";
477 reg = <0x01937000 0x25000>;
480 spmi_bus: spmi@200f000 {
481 compatible = "qcom,spmi-pmic-arb";
482 reg = <0x0200f000 0x001000>,
483 <0x02400000 0x800000>,
484 <0x02c00000 0x800000>,
485 <0x03800000 0x200000>,
486 <0x0200a000 0x002100>;
487 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
488 interrupt-names = "periph_irq";
489 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
492 #address-cells = <2>;
494 interrupt-controller;
495 #interrupt-cells = <4>;
498 remoteproc_wcss: remoteproc@7400000 {
499 compatible = "qcom,qcs404-wcss-pas";
500 reg = <0x07400000 0x4040>;
502 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
503 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
504 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
505 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
506 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
507 interrupt-names = "wdog", "fatal", "ready",
508 "handover", "stop-ack";
510 clocks = <&xo_board>;
513 memory-region = <&wlan_fw_mem>;
515 qcom,smem-states = <&wcss_smp2p_out 0>;
516 qcom,smem-state-names = "stop";
521 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
523 qcom,remote-pid = <1>;
524 mboxes = <&apcs_glb 16>;
530 pcie_phy: phy@7786000 {
531 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
532 reg = <0x07786000 0xb8>;
534 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
535 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
536 <&gcc GCC_PCIE_0_PIPE_ARES>;
537 reset-names = "phy", "pipe";
539 clock-output-names = "pcie_0_pipe_clk";
545 sdcc1: sdcc@7804000 {
546 compatible = "qcom,sdhci-msm-v5";
547 reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
548 reg-names = "hc_mem", "cmdq_mem";
550 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
552 interrupt-names = "hc_irq", "pwr_irq";
554 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
555 <&gcc GCC_SDCC1_AHB_CLK>,
557 clock-names = "core", "iface", "xo";
562 blsp1_dma: dma@7884000 {
563 compatible = "qcom,bam-v1.7.0";
564 reg = <0x07884000 0x25000>;
565 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
567 clock-names = "bam_clk";
573 blsp1_uart0: serial@78af000 {
574 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
575 reg = <0x078af000 0x200>;
576 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
578 clock-names = "core", "iface";
579 dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
580 dma-names = "rx", "tx";
581 pinctrl-names = "default";
582 pinctrl-0 = <&blsp1_uart0_default>;
586 blsp1_uart1: serial@78b0000 {
587 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
588 reg = <0x078b0000 0x200>;
589 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
591 clock-names = "core", "iface";
592 dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
593 dma-names = "rx", "tx";
594 pinctrl-names = "default";
595 pinctrl-0 = <&blsp1_uart1_default>;
599 blsp1_uart2: serial@78b1000 {
600 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
601 reg = <0x078b1000 0x200>;
602 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
604 clock-names = "core", "iface";
605 dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
606 dma-names = "rx", "tx";
607 pinctrl-names = "default";
608 pinctrl-0 = <&blsp1_uart2_default>;
612 ethernet: ethernet@7a80000 {
613 compatible = "qcom,qcs404-ethqos";
614 reg = <0x07a80000 0x10000>,
616 reg-names = "stmmaceth", "rgmii";
617 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
618 clocks = <&gcc GCC_ETH_AXI_CLK>,
619 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
620 <&gcc GCC_ETH_PTP_CLK>,
621 <&gcc GCC_ETH_RGMII_CLK>;
622 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "macirq", "eth_lpi";
627 rx-fifo-depth = <4096>;
628 tx-fifo-depth = <4096>;
634 compatible = "qcom,wcn3990-wifi";
635 reg = <0xa000000 0x800000>;
636 reg-names = "membase";
637 memory-region = <&wlan_msa_mem>;
638 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
653 blsp1_uart3: serial@78b2000 {
654 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
655 reg = <0x078b2000 0x200>;
656 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
658 clock-names = "core", "iface";
659 dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
660 dma-names = "rx", "tx";
661 pinctrl-names = "default";
662 pinctrl-0 = <&blsp1_uart3_default>;
666 blsp1_i2c0: i2c@78b5000 {
667 compatible = "qcom,i2c-qup-v2.2.1";
668 reg = <0x078b5000 0x600>;
669 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
671 <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
672 clock-names = "iface", "core";
673 pinctrl-names = "default";
674 pinctrl-0 = <&blsp1_i2c0_default>;
675 #address-cells = <1>;
680 blsp1_spi0: spi@78b5000 {
681 compatible = "qcom,spi-qup-v2.2.1";
682 reg = <0x078b5000 0x600>;
683 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
685 <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
686 clock-names = "iface", "core";
687 pinctrl-names = "default";
688 pinctrl-0 = <&blsp1_spi0_default>;
689 #address-cells = <1>;
694 blsp1_i2c1: i2c@78b6000 {
695 compatible = "qcom,i2c-qup-v2.2.1";
696 reg = <0x078b6000 0x600>;
697 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
699 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
700 clock-names = "iface", "core";
701 pinctrl-names = "default";
702 pinctrl-0 = <&blsp1_i2c1_default>;
703 #address-cells = <1>;
708 blsp1_spi1: spi@78b6000 {
709 compatible = "qcom,spi-qup-v2.2.1";
710 reg = <0x078b6000 0x600>;
711 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
713 <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
714 clock-names = "iface", "core";
715 pinctrl-names = "default";
716 pinctrl-0 = <&blsp1_spi1_default>;
717 #address-cells = <1>;
722 blsp1_i2c2: i2c@78b7000 {
723 compatible = "qcom,i2c-qup-v2.2.1";
724 reg = <0x078b7000 0x600>;
725 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
727 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
728 clock-names = "iface", "core";
729 pinctrl-names = "default";
730 pinctrl-0 = <&blsp1_i2c2_default>;
731 #address-cells = <1>;
736 blsp1_spi2: spi@78b7000 {
737 compatible = "qcom,spi-qup-v2.2.1";
738 reg = <0x078b7000 0x600>;
739 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
741 <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
742 clock-names = "iface", "core";
743 pinctrl-names = "default";
744 pinctrl-0 = <&blsp1_spi2_default>;
745 #address-cells = <1>;
750 blsp1_i2c3: i2c@78b8000 {
751 compatible = "qcom,i2c-qup-v2.2.1";
752 reg = <0x078b8000 0x600>;
753 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
755 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
756 clock-names = "iface", "core";
757 pinctrl-names = "default";
758 pinctrl-0 = <&blsp1_i2c3_default>;
759 #address-cells = <1>;
764 blsp1_spi3: spi@78b8000 {
765 compatible = "qcom,spi-qup-v2.2.1";
766 reg = <0x078b8000 0x600>;
767 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
769 <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
770 clock-names = "iface", "core";
771 pinctrl-names = "default";
772 pinctrl-0 = <&blsp1_spi3_default>;
773 #address-cells = <1>;
778 blsp1_i2c4: i2c@78b9000 {
779 compatible = "qcom,i2c-qup-v2.2.1";
780 reg = <0x078b9000 0x600>;
781 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
783 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
784 clock-names = "iface", "core";
785 pinctrl-names = "default";
786 pinctrl-0 = <&blsp1_i2c4_default>;
787 #address-cells = <1>;
792 blsp1_spi4: spi@78b9000 {
793 compatible = "qcom,spi-qup-v2.2.1";
794 reg = <0x078b9000 0x600>;
795 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
797 <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
798 clock-names = "iface", "core";
799 pinctrl-names = "default";
800 pinctrl-0 = <&blsp1_spi4_default>;
801 #address-cells = <1>;
806 blsp2_dma: dma@7ac4000 {
807 compatible = "qcom,bam-v1.7.0";
808 reg = <0x07ac4000 0x17000>;
809 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
811 clock-names = "bam_clk";
817 blsp2_uart0: serial@7aef000 {
818 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
819 reg = <0x07aef000 0x200>;
820 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
822 clock-names = "core", "iface";
823 dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
824 dma-names = "rx", "tx";
825 pinctrl-names = "default";
826 pinctrl-0 = <&blsp2_uart0_default>;
830 blsp2_i2c0: i2c@7af5000 {
831 compatible = "qcom,i2c-qup-v2.2.1";
832 reg = <0x07af5000 0x600>;
833 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
835 <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
836 clock-names = "iface", "core";
837 pinctrl-names = "default";
838 pinctrl-0 = <&blsp2_i2c0_default>;
839 #address-cells = <1>;
844 blsp2_spi0: spi@7af5000 {
845 compatible = "qcom,spi-qup-v2.2.1";
846 reg = <0x07af5000 0x600>;
847 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
849 <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
850 clock-names = "iface", "core";
851 pinctrl-names = "default";
852 pinctrl-0 = <&blsp2_spi0_default>;
853 #address-cells = <1>;
858 intc: interrupt-controller@b000000 {
859 compatible = "qcom,msm-qgic2";
860 interrupt-controller;
861 #interrupt-cells = <3>;
862 reg = <0x0b000000 0x1000>,
866 apcs_glb: mailbox@b011000 {
867 compatible = "qcom,qcs404-apcs-apps-global", "syscon";
868 reg = <0x0b011000 0x1000>;
873 #address-cells = <1>;
876 compatible = "arm,armv7-timer-mem";
877 reg = <0x0b120000 0x1000>;
878 clock-frequency = <19200000>;
882 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
884 reg = <0x0b121000 0x1000>,
890 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
891 reg = <0x0b123000 0x1000>;
897 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
898 reg = <0x0b124000 0x1000>;
904 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
905 reg = <0x0b125000 0x1000>;
911 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
912 reg = <0x0b126000 0x1000>;
918 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
919 reg = <0xb127000 0x1000>;
925 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
926 reg = <0x0b128000 0x1000>;
931 remoteproc_adsp: remoteproc@c700000 {
932 compatible = "qcom,qcs404-adsp-pas";
933 reg = <0x0c700000 0x4040>;
935 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
936 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
937 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
938 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
939 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
940 interrupt-names = "wdog", "fatal", "ready",
941 "handover", "stop-ack";
943 clocks = <&xo_board>;
946 memory-region = <&adsp_fw_mem>;
948 qcom,smem-states = <&adsp_smp2p_out 0>;
949 qcom,smem-state-names = "stop";
954 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
956 qcom,remote-pid = <2>;
957 mboxes = <&apcs_glb 8>;
964 compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
965 reg = <0x10000000 0xf1d>,
969 reg-names = "dbi", "elbi", "parf", "config";
971 linux,pci-domain = <0>;
972 bus-range = <0x00 0xff>;
974 #address-cells = <3>;
977 ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
978 <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
980 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
981 interrupt-names = "msi";
982 #interrupt-cells = <1>;
983 interrupt-map-mask = <0 0 0 0x7>;
984 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
985 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
986 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
987 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
988 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
989 <&gcc GCC_PCIE_0_AUX_CLK>,
990 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
991 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
992 clock-names = "iface", "aux", "master_bus", "slave_bus";
994 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
995 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
996 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
997 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
998 <&gcc GCC_PCIE_0_BCR>,
999 <&gcc GCC_PCIE_0_AHB_ARES>;
1000 reset-names = "axi_m",
1008 phy-names = "pciephy";
1010 status = "disabled";
1015 compatible = "arm,armv8-timer";
1016 interrupts = <GIC_PPI 2 0xff08>,
1023 compatible = "qcom,smp2p";
1024 qcom,smem = <443>, <429>;
1025 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
1026 mboxes = <&apcs_glb 10>;
1027 qcom,local-pid = <0>;
1028 qcom,remote-pid = <2>;
1030 adsp_smp2p_out: master-kernel {
1031 qcom,entry-name = "master-kernel";
1032 #qcom,smem-state-cells = <1>;
1035 adsp_smp2p_in: slave-kernel {
1036 qcom,entry-name = "slave-kernel";
1037 interrupt-controller;
1038 #interrupt-cells = <2>;
1043 compatible = "qcom,smp2p";
1044 qcom,smem = <94>, <432>;
1045 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
1046 mboxes = <&apcs_glb 14>;
1047 qcom,local-pid = <0>;
1048 qcom,remote-pid = <5>;
1050 cdsp_smp2p_out: master-kernel {
1051 qcom,entry-name = "master-kernel";
1052 #qcom,smem-state-cells = <1>;
1055 cdsp_smp2p_in: slave-kernel {
1056 qcom,entry-name = "slave-kernel";
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1063 compatible = "qcom,smp2p";
1064 qcom,smem = <435>, <428>;
1065 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1066 mboxes = <&apcs_glb 18>;
1067 qcom,local-pid = <0>;
1068 qcom,remote-pid = <1>;
1070 wcss_smp2p_out: master-kernel {
1071 qcom,entry-name = "master-kernel";
1072 #qcom,smem-state-cells = <1>;
1075 wcss_smp2p_in: slave-kernel {
1076 qcom,entry-name = "slave-kernel";
1077 interrupt-controller;
1078 #interrupt-cells = <2>;
1084 polling-delay-passive = <250>;
1085 polling-delay = <1000>;
1087 thermal-sensors = <&tsens 0>;
1090 aoss_alert0: trip-point0 {
1091 temperature = <105000>;
1092 hysteresis = <2000>;
1099 polling-delay-passive = <250>;
1100 polling-delay = <1000>;
1102 thermal-sensors = <&tsens 1>;
1105 q6_hvx_alert0: trip-point0 {
1106 temperature = <105000>;
1107 hysteresis = <2000>;
1114 polling-delay-passive = <250>;
1115 polling-delay = <1000>;
1117 thermal-sensors = <&tsens 2>;
1120 lpass_alert0: trip-point0 {
1121 temperature = <105000>;
1122 hysteresis = <2000>;
1129 polling-delay-passive = <250>;
1130 polling-delay = <1000>;
1132 thermal-sensors = <&tsens 3>;
1135 wlan_alert0: trip-point0 {
1136 temperature = <105000>;
1137 hysteresis = <2000>;
1144 polling-delay-passive = <250>;
1145 polling-delay = <1000>;
1147 thermal-sensors = <&tsens 4>;
1150 cluster_alert0: trip-point0 {
1151 temperature = <95000>;
1152 hysteresis = <2000>;
1155 cluster_alert1: trip-point1 {
1156 temperature = <105000>;
1157 hysteresis = <2000>;
1160 cluster_crit: cluster_crit {
1161 temperature = <120000>;
1162 hysteresis = <2000>;
1168 trip = <&cluster_alert1>;
1169 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1170 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1171 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1172 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1178 polling-delay-passive = <250>;
1179 polling-delay = <1000>;
1181 thermal-sensors = <&tsens 5>;
1184 cpu0_alert0: trip-point0 {
1185 temperature = <95000>;
1186 hysteresis = <2000>;
1189 cpu0_alert1: trip-point1 {
1190 temperature = <105000>;
1191 hysteresis = <2000>;
1194 cpu0_crit: cpu_crit {
1195 temperature = <120000>;
1196 hysteresis = <2000>;
1202 trip = <&cpu0_alert1>;
1203 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1204 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1205 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1206 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1212 polling-delay-passive = <250>;
1213 polling-delay = <1000>;
1215 thermal-sensors = <&tsens 6>;
1218 cpu1_alert0: trip-point0 {
1219 temperature = <95000>;
1220 hysteresis = <2000>;
1223 cpu1_alert1: trip-point1 {
1224 temperature = <105000>;
1225 hysteresis = <2000>;
1228 cpu1_crit: cpu_crit {
1229 temperature = <120000>;
1230 hysteresis = <2000>;
1236 trip = <&cpu1_alert1>;
1237 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1238 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1239 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1240 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1246 polling-delay-passive = <250>;
1247 polling-delay = <1000>;
1249 thermal-sensors = <&tsens 7>;
1252 cpu2_alert0: trip-point0 {
1253 temperature = <95000>;
1254 hysteresis = <2000>;
1257 cpu2_alert1: trip-point1 {
1258 temperature = <105000>;
1259 hysteresis = <2000>;
1262 cpu2_crit: cpu_crit {
1263 temperature = <120000>;
1264 hysteresis = <2000>;
1270 trip = <&cpu2_alert1>;
1271 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1272 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1273 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1274 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1280 polling-delay-passive = <250>;
1281 polling-delay = <1000>;
1283 thermal-sensors = <&tsens 8>;
1286 cpu3_alert0: trip-point0 {
1287 temperature = <95000>;
1288 hysteresis = <2000>;
1291 cpu3_alert1: trip-point1 {
1292 temperature = <105000>;
1293 hysteresis = <2000>;
1296 cpu3_crit: cpu_crit {
1297 temperature = <120000>;
1298 hysteresis = <2000>;
1304 trip = <&cpu3_alert1>;
1305 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1306 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1307 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1308 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1314 polling-delay-passive = <250>;
1315 polling-delay = <1000>;
1317 thermal-sensors = <&tsens 9>;
1320 gpu_alert0: trip-point0 {
1321 temperature = <95000>;
1322 hysteresis = <2000>;