1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (c) 2023, Linaro Ltd
5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
8 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
26 compatible = "fixed-clock";
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32764>;
43 compatible = "arm,cortex-a53";
45 clocks = <&cpufreq_hw 0>;
46 capacity-dmips-mhz = <1024>;
47 dynamic-power-coefficient = <100>;
48 enable-method = "psci";
49 next-level-cache = <&L2_0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
51 power-domains = <&CPU_PD0>;
52 power-domain-names = "psci";
62 compatible = "arm,cortex-a53";
64 clocks = <&cpufreq_hw 0>;
65 capacity-dmips-mhz = <1024>;
66 dynamic-power-coefficient = <100>;
67 enable-method = "psci";
68 next-level-cache = <&L2_0>;
69 qcom,freq-domain = <&cpufreq_hw 0>;
70 power-domains = <&CPU_PD1>;
71 power-domain-names = "psci";
76 compatible = "arm,cortex-a53";
78 clocks = <&cpufreq_hw 0>;
79 capacity-dmips-mhz = <1024>;
80 dynamic-power-coefficient = <100>;
81 enable-method = "psci";
82 next-level-cache = <&L2_0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 power-domains = <&CPU_PD2>;
85 power-domain-names = "psci";
90 compatible = "arm,cortex-a53";
92 clocks = <&cpufreq_hw 0>;
93 capacity-dmips-mhz = <1024>;
94 dynamic-power-coefficient = <100>;
95 enable-method = "psci";
96 next-level-cache = <&L2_0>;
97 qcom,freq-domain = <&cpufreq_hw 0>;
98 power-domains = <&CPU_PD3>;
99 power-domain-names = "psci";
123 CLUSTER_SLEEP: cluster-sleep-0 {
124 compatible = "domain-idle-state";
125 arm,psci-suspend-param = <0x41000043>;
126 entry-latency-us = <800>;
127 exit-latency-us = <2118>;
128 min-residency-us = <7376>;
133 entry-method = "psci";
135 CPU_SLEEP: cpu-sleep-0 {
136 compatible = "arm,idle-state";
137 idle-state-name = "power-collapse";
138 arm,psci-suspend-param = <0x40000003>;
139 entry-latency-us = <290>;
140 exit-latency-us = <376>;
141 min-residency-us = <1182>;
149 compatible = "qcom,scm-qcm2290", "qcom,scm";
150 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
151 clock-names = "core";
157 device_type = "memory";
158 /* We expect the bootloader to fill in the size */
159 reg = <0 0x40000000 0 0>;
163 compatible = "arm,armv8-pmuv3";
164 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
168 compatible = "arm,psci-1.0";
171 CPU_PD0: power-domain-cpu0 {
172 #power-domain-cells = <0>;
173 power-domains = <&CLUSTER_PD>;
174 domain-idle-states = <&CPU_SLEEP>;
177 CPU_PD1: power-domain-cpu1 {
178 #power-domain-cells = <0>;
179 power-domains = <&CLUSTER_PD>;
180 domain-idle-states = <&CPU_SLEEP>;
183 CPU_PD2: power-domain-cpu2 {
184 #power-domain-cells = <0>;
185 power-domains = <&CLUSTER_PD>;
186 domain-idle-states = <&CPU_SLEEP>;
189 CPU_PD3: power-domain-cpu3 {
190 #power-domain-cells = <0>;
191 power-domains = <&CLUSTER_PD>;
192 domain-idle-states = <&CPU_SLEEP>;
195 CLUSTER_PD: power-domain-cpu-cluster {
196 #power-domain-cells = <0>;
197 domain-idle-states = <&CLUSTER_SLEEP>;
202 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
205 compatible = "qcom,glink-rpm";
206 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
207 qcom,rpm-msg-ram = <&rpm_msg_ram>;
208 mboxes = <&apcs_glb 0>;
210 rpm_requests: rpm-requests {
211 compatible = "qcom,rpm-qcm2290";
212 qcom,glink-channels = "rpm_requests";
214 rpmcc: clock-controller {
215 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
216 clocks = <&xo_board>;
221 rpmpd: power-controller {
222 compatible = "qcom,qcm2290-rpmpd";
223 #power-domain-cells = <1>;
224 operating-points-v2 = <&rpmpd_opp_table>;
226 rpmpd_opp_table: opp-table {
227 compatible = "operating-points-v2";
229 rpmpd_opp_min_svs: opp1 {
230 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
233 rpmpd_opp_low_svs: opp2 {
234 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
237 rpmpd_opp_svs: opp3 {
238 opp-level = <RPM_SMD_LEVEL_SVS>;
241 rpmpd_opp_svs_plus: opp4 {
242 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
245 rpmpd_opp_nom: opp5 {
246 opp-level = <RPM_SMD_LEVEL_NOM>;
249 rpmpd_opp_nom_plus: opp6 {
250 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
253 rpmpd_opp_turbo: opp7 {
254 opp-level = <RPM_SMD_LEVEL_TURBO>;
257 rpmpd_opp_turbo_plus: opp8 {
258 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
266 reserved_memory: reserved-memory {
267 #address-cells = <2>;
271 hyp_mem: hyp@45700000 {
272 reg = <0x0 0x45700000 0x0 0x600000>;
276 xbl_aop_mem: xbl-aop@45e00000 {
277 reg = <0x0 0x45e00000 0x0 0x140000>;
281 sec_apps_mem: sec-apps@45fff000 {
282 reg = <0x0 0x45fff000 0x0 0x1000>;
286 smem_mem: smem@46000000 {
287 compatible = "qcom,smem";
288 reg = <0x0 0x46000000 0x0 0x200000>;
291 hwlocks = <&tcsr_mutex 3>;
292 qcom,rpm-msg-ram = <&rpm_msg_ram>;
295 pil_modem_mem: modem@4ab00000 {
296 reg = <0x0 0x4ab00000 0x0 0x6900000>;
300 pil_video_mem: video@51400000 {
301 reg = <0x0 0x51400000 0x0 0x500000>;
305 wlan_msa_mem: wlan-msa@51900000 {
306 reg = <0x0 0x51900000 0x0 0x100000>;
310 pil_adsp_mem: adsp@51a00000 {
311 reg = <0x0 0x51a00000 0x0 0x1c00000>;
315 pil_ipa_fw_mem: ipa-fw@53600000 {
316 reg = <0x0 0x53600000 0x0 0x10000>;
320 pil_ipa_gsi_mem: ipa-gsi@53610000 {
321 reg = <0x0 0x53610000 0x0 0x5000>;
325 pil_gpu_mem: zap@53615000 {
326 compatible = "shared-dma-pool";
327 reg = <0x0 0x53615000 0x0 0x2000>;
331 cont_splash_memory: framebuffer@5c000000 {
332 reg = <0x0 0x5c000000 0x0 0x00f00000>;
336 dfps_data_memory: dpfs-data@5cf00000 {
337 reg = <0x0 0x5cf00000 0x0 0x0100000>;
341 removed_mem: reserved@60000000 {
342 reg = <0x0 0x60000000 0x0 0x3900000>;
346 rmtfs_mem: memory@89b01000 {
347 compatible = "qcom,rmtfs-mem";
348 reg = <0x0 0x89b01000 0x0 0x200000>;
351 qcom,client-id = <1>;
352 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
357 compatible = "qcom,smp2p";
358 qcom,smem = <443>, <429>;
360 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
362 mboxes = <&apcs_glb 10>;
364 qcom,local-pid = <0>;
365 qcom,remote-pid = <2>;
367 adsp_smp2p_out: master-kernel {
368 qcom,entry-name = "master-kernel";
369 #qcom,smem-state-cells = <1>;
372 adsp_smp2p_in: slave-kernel {
373 qcom,entry-name = "slave-kernel";
374 interrupt-controller;
375 #interrupt-cells = <2>;
380 compatible = "qcom,smp2p";
381 qcom,smem = <435>, <428>;
383 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
385 mboxes = <&apcs_glb 14>;
387 qcom,local-pid = <0>;
388 qcom,remote-pid = <1>;
390 modem_smp2p_out: master-kernel {
391 qcom,entry-name = "master-kernel";
392 #qcom,smem-state-cells = <1>;
395 modem_smp2p_in: slave-kernel {
396 qcom,entry-name = "slave-kernel";
397 interrupt-controller;
398 #interrupt-cells = <2>;
401 wlan_smp2p_in: wlan-wpss-to-ap {
402 qcom,entry-name = "wlan";
403 interrupt-controller;
404 #interrupt-cells = <2>;
409 compatible = "simple-bus";
410 #address-cells = <2>;
412 ranges = <0 0 0 0 0x10 0>;
413 dma-ranges = <0 0 0 0 0x10 0>;
415 tcsr_mutex: hwlock@340000 {
416 compatible = "qcom,tcsr-mutex";
417 reg = <0x0 0x00340000 0x0 0x20000>;
421 tlmm: pinctrl@500000 {
422 compatible = "qcom,qcm2290-tlmm";
423 reg = <0x0 0x00500000 0x0 0x300000>;
424 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
426 gpio-ranges = <&tlmm 0 0 127>;
428 interrupt-controller;
429 #interrupt-cells = <2>;
431 qup_i2c0_default: qup-i2c0-default-state {
432 pins = "gpio0", "gpio1";
434 drive-strength = <2>;
438 qup_i2c1_default: qup-i2c1-default-state {
439 pins = "gpio4", "gpio5";
441 drive-strength = <2>;
445 qup_i2c2_default: qup-i2c2-default-state {
446 pins = "gpio6", "gpio7";
448 drive-strength = <2>;
452 qup_i2c3_default: qup-i2c3-default-state {
453 pins = "gpio8", "gpio9";
455 drive-strength = <2>;
459 qup_i2c4_default: qup-i2c4-default-state {
460 pins = "gpio12", "gpio13";
462 drive-strength = <2>;
466 qup_i2c5_default: qup-i2c5-default-state {
467 pins = "gpio14", "gpio15";
469 drive-strength = <2>;
473 qup_spi0_default: qup-spi0-default-state {
474 pins = "gpio0", "gpio1","gpio2", "gpio3";
476 drive-strength = <2>;
480 qup_spi1_default: qup-spi1-default-state {
481 pins = "gpio4", "gpio5", "gpio69", "gpio70";
483 drive-strength = <2>;
487 qup_spi2_default: qup-spi2-default-state {
488 pins = "gpio6", "gpio7", "gpio71", "gpio80";
490 drive-strength = <2>;
494 qup_spi3_default: qup-spi3-default-state {
495 pins = "gpio8", "gpio9", "gpio10", "gpio11";
497 drive-strength = <2>;
501 qup_spi4_default: qup-spi4-default-state {
502 pins = "gpio12", "gpio13", "gpio96", "gpio97";
504 drive-strength = <2>;
508 qup_spi5_default: qup-spi5-default-state {
509 pins = "gpio14", "gpio15", "gpio16", "gpio17";
511 drive-strength = <2>;
515 qup_uart0_default: qup-uart0-default-state {
516 pins = "gpio0", "gpio1", "gpio2", "gpio3";
518 drive-strength = <2>;
522 qup_uart4_default: qup-uart4-default-state {
523 pins = "gpio12", "gpio13";
525 drive-strength = <2>;
529 sdc1_state_on: sdc1-on-state {
532 drive-strength = <16>;
538 drive-strength = <10>;
544 drive-strength = <10>;
554 sdc1_state_off: sdc1-off-state {
557 drive-strength = <2>;
563 drive-strength = <2>;
569 drive-strength = <2>;
579 sdc2_state_on: sdc2-on-state {
582 drive-strength = <16>;
588 drive-strength = <10>;
594 drive-strength = <10>;
599 sdc2_state_off: sdc2-off-state {
602 drive-strength = <2>;
608 drive-strength = <2>;
614 drive-strength = <2>;
620 gcc: clock-controller@1400000 {
621 compatible = "qcom,gcc-qcm2290";
622 reg = <0x0 0x01400000 0x0 0x1f0000>;
623 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
624 clock-names = "bi_tcxo", "sleep_clk";
627 #power-domain-cells = <1>;
630 usb_hsphy: phy@1613000 {
631 compatible = "qcom,qcm2290-qusb2-phy";
632 reg = <0x0 0x01613000 0x0 0x180>;
634 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
635 <&rpmcc RPM_SMD_XO_CLK_SRC>;
636 clock-names = "cfg_ahb", "ref";
638 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
639 nvmem-cells = <&qusb2_hstx_trim>;
645 usb_qmpphy: phy@1615000 {
646 compatible = "qcom,qcm2290-qmp-usb3-phy";
647 reg = <0x0 0x01615000 0x0 0x1000>;
649 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
650 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
651 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
652 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
653 clock-names = "cfg_ahb",
658 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
659 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
664 clock-output-names = "usb3_phy_pipe_clk_src";
672 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
673 reg = <0x0 0x01b44000 0x0 0x3000>;
674 #address-cells = <1>;
677 qusb2_hstx_trim: hstx-trim@25b {
683 spmi_bus: spmi@1c40000 {
684 compatible = "qcom,spmi-pmic-arb";
685 reg = <0x0 0x01c40000 0x0 0x1100>,
686 <0x0 0x01e00000 0x0 0x2000000>,
687 <0x0 0x03e00000 0x0 0x100000>,
688 <0x0 0x03f00000 0x0 0xa0000>,
689 <0x0 0x01c0a000 0x0 0x26000>;
695 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
696 interrupt-names = "periph_irq";
699 #address-cells = <2>;
701 interrupt-controller;
702 #interrupt-cells = <4>;
705 tsens0: thermal-sensor@4411000 {
706 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
707 reg = <0x0 0x04411000 0x0 0x1ff>,
708 <0x0 0x04410000 0x0 0x8>;
709 #qcom,sensors = <10>;
710 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
712 interrupt-names = "uplow", "critical";
713 #thermal-sensor-cells = <1>;
717 compatible = "qcom,prng-ee";
718 reg = <0x0 0x04453000 0x0 0x1000>;
719 clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
720 clock-names = "core";
723 rpm_msg_ram: sram@45f0000 {
724 compatible = "qcom,rpm-msg-ram";
725 reg = <0x0 0x045f0000 0x0 0x7000>;
729 compatible = "qcom,rpm-stats";
730 reg = <0x0 0x04690000 0x0 0x10000>;
733 sdhc_1: mmc@4744000 {
734 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
735 reg = <0x0 0x04744000 0x0 0x1000>,
736 <0x0 0x04745000 0x0 0x1000>,
737 <0x0 0x04748000 0x0 0x8000>;
742 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
744 interrupt-names = "hc_irq", "pwr_irq";
746 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
747 <&gcc GCC_SDCC1_APPS_CLK>,
748 <&rpmcc RPM_SMD_XO_CLK_SRC>,
749 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
750 clock-names = "iface",
755 resets = <&gcc GCC_SDCC1_BCR>;
757 power-domains = <&rpmpd QCM2290_VDDCX>;
758 iommus = <&apps_smmu 0xc0 0x0>;
760 qcom,dll-config = <0x000f642c>;
761 qcom,ddr-config = <0x80040868>;
767 sdhc_2: mmc@4784000 {
768 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
769 reg = <0x0 0x04784000 0x0 0x1000>;
772 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
774 interrupt-names = "hc_irq", "pwr_irq";
776 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
777 <&gcc GCC_SDCC2_APPS_CLK>,
778 <&rpmcc RPM_SMD_XO_CLK_SRC>;
779 clock-names = "iface",
783 resets = <&gcc GCC_SDCC2_BCR>;
785 power-domains = <&rpmpd QCM2290_VDDCX>;
786 operating-points-v2 = <&sdhc2_opp_table>;
787 iommus = <&apps_smmu 0xa0 0x0>;
789 qcom,dll-config = <0x0007642c>;
790 qcom,ddr-config = <0x80040868>;
795 sdhc2_opp_table: opp-table {
796 compatible = "operating-points-v2";
799 opp-hz = /bits/ 64 <100000000>;
800 required-opps = <&rpmpd_opp_low_svs>;
804 opp-hz = /bits/ 64 <202000000>;
805 required-opps = <&rpmpd_opp_svs_plus>;
810 gpi_dma0: dma-controller@4a00000 {
811 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
812 reg = <0x0 0x04a00000 0x0 0x60000>;
813 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
818 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
824 dma-channel-mask = <0x1f>;
825 iommus = <&apps_smmu 0xf6 0x0>;
830 qupv3_id_0: geniqup@4ac0000 {
831 compatible = "qcom,geni-se-qup";
832 reg = <0x0 0x04ac0000 0x0 0x2000>;
833 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
834 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
835 clock-names = "m-ahb", "s-ahb";
836 iommus = <&apps_smmu 0xe3 0x0>;
837 #address-cells = <2>;
843 compatible = "qcom,geni-i2c";
844 reg = <0x0 0x04a80000 0x0 0x4000>;
845 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
848 pinctrl-0 = <&qup_i2c0_default>;
849 pinctrl-names = "default";
850 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
851 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
852 dma-names = "tx", "rx";
853 #address-cells = <1>;
859 compatible = "qcom,geni-spi";
860 reg = <0x0 0x04a80000 0x0 0x4000>;
861 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
864 pinctrl-0 = <&qup_spi0_default>;
865 pinctrl-names = "default";
866 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
867 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
868 dma-names = "tx", "rx";
869 #address-cells = <1>;
874 uart0: serial@4a80000 {
875 compatible = "qcom,geni-uart";
876 reg = <0x0 0x04a80000 0x0 0x4000>;
877 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
878 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
880 pinctrl-0 = <&qup_uart0_default>;
881 pinctrl-names = "default";
886 compatible = "qcom,geni-i2c";
887 reg = <0x0 0x04a84000 0x0 0x4000>;
888 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
891 pinctrl-0 = <&qup_i2c1_default>;
892 pinctrl-names = "default";
893 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
894 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
895 dma-names = "tx", "rx";
896 #address-cells = <1>;
902 compatible = "qcom,geni-spi";
903 reg = <0x0 0x04a84000 0x0 0x4000>;
904 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
907 pinctrl-0 = <&qup_spi1_default>;
908 pinctrl-names = "default";
909 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
910 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
911 dma-names = "tx", "rx";
912 #address-cells = <1>;
918 compatible = "qcom,geni-i2c";
919 reg = <0x0 0x04a88000 0x0 0x4000>;
920 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
923 pinctrl-0 = <&qup_i2c2_default>;
924 pinctrl-names = "default";
925 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
926 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
927 dma-names = "tx", "rx";
928 #address-cells = <1>;
934 compatible = "qcom,geni-spi";
935 reg = <0x0 0x04a88000 0x0 0x4000>;
936 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
939 pinctrl-0 = <&qup_spi2_default>;
940 pinctrl-names = "default";
941 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
942 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
943 dma-names = "tx", "rx";
944 #address-cells = <1>;
950 compatible = "qcom,geni-i2c";
951 reg = <0x0 0x04a8c000 0x0 0x4000>;
952 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
955 pinctrl-0 = <&qup_i2c3_default>;
956 pinctrl-names = "default";
957 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
958 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
959 dma-names = "tx", "rx";
960 #address-cells = <1>;
966 compatible = "qcom,geni-spi";
967 reg = <0x0 0x04a8c000 0x0 0x4000>;
968 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
971 pinctrl-0 = <&qup_spi3_default>;
972 pinctrl-names = "default";
973 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
974 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
975 dma-names = "tx", "rx";
976 #address-cells = <1>;
982 compatible = "qcom,geni-i2c";
983 reg = <0x0 0x04a90000 0x0 0x4000>;
984 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
987 pinctrl-0 = <&qup_i2c4_default>;
988 pinctrl-names = "default";
989 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
990 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
991 dma-names = "tx", "rx";
992 #address-cells = <1>;
998 compatible = "qcom,geni-spi";
999 reg = <0x0 0x04a90000 0x0 0x4000>;
1000 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&qup_spi4_default>;
1005 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1006 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1007 dma-names = "tx", "rx";
1008 #address-cells = <1>;
1010 status = "disabled";
1013 uart4: serial@4a90000 {
1014 compatible = "qcom,geni-uart";
1015 reg = <0x0 0x04a90000 0x0 0x4000>;
1016 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1019 pinctrl-0 = <&qup_uart4_default>;
1020 pinctrl-names = "default";
1021 status = "disabled";
1025 compatible = "qcom,geni-i2c";
1026 reg = <0x0 0x04a94000 0x0 0x4000>;
1027 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1030 pinctrl-0 = <&qup_i2c5_default>;
1031 pinctrl-names = "default";
1032 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1033 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1034 dma-names = "tx", "rx";
1035 #address-cells = <1>;
1037 status = "disabled";
1041 compatible = "qcom,geni-spi";
1042 reg = <0x0 0x04a94000 0x0 0x4000>;
1043 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1046 pinctrl-0 = <&qup_spi5_default>;
1047 pinctrl-names = "default";
1048 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1049 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1050 dma-names = "tx", "rx";
1051 #address-cells = <1>;
1053 status = "disabled";
1058 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1059 reg = <0x0 0x04ef8800 0x0 0x400>;
1060 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1064 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1065 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1066 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1067 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1068 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1069 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1070 clock-names = "cfg_noc",
1077 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1078 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1079 assigned-clock-rates = <19200000>, <133333333>;
1081 resets = <&gcc GCC_USB30_PRIM_BCR>;
1082 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1085 #address-cells = <2>;
1089 status = "disabled";
1091 usb_dwc3: usb@4e00000 {
1092 compatible = "snps,dwc3";
1093 reg = <0x0 0x04e00000 0x0 0xcd00>;
1094 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1095 phys = <&usb_hsphy>, <&usb_qmpphy>;
1096 phy-names = "usb2-phy", "usb3-phy";
1097 iommus = <&apps_smmu 0x120 0x0>;
1098 snps,dis_u2_susphy_quirk;
1099 snps,dis_enblslpm_quirk;
1100 snps,has-lpm-erratum;
1101 snps,hird-threshold = /bits/ 8 <0x10>;
1102 snps,usb3_lpm_capable;
1103 maximum-speed = "super-speed";
1108 remoteproc_mpss: remoteproc@6080000 {
1109 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1110 reg = <0x0 0x06080000 0x0 0x100>;
1112 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1113 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1114 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1115 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1116 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1117 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1118 interrupt-names = "wdog",
1125 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1128 power-domains = <&rpmpd QCM2290_VDDCX>;
1130 memory-region = <&pil_modem_mem>;
1132 qcom,smem-states = <&modem_smp2p_out 0>;
1133 qcom,smem-state-names = "stop";
1135 status = "disabled";
1138 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1140 qcom,remote-pid = <1>;
1141 mboxes = <&apcs_glb 12>;
1145 remoteproc_adsp: remoteproc@ab00000 {
1146 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1147 reg = <0x0 0x0ab00000 0x0 0x100>;
1149 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1150 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1151 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1152 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1153 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1154 interrupt-names = "wdog",
1160 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1163 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1164 <&rpmpd QCM2290_VDD_LPI_MX>;
1166 memory-region = <&pil_adsp_mem>;
1168 qcom,smem-states = <&adsp_smp2p_out 0>;
1169 qcom,smem-state-names = "stop";
1171 status = "disabled";
1174 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1176 qcom,remote-pid = <2>;
1177 mboxes = <&apcs_glb 8>;
1181 apps_smmu: iommu@c600000 {
1182 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1183 reg = <0x0 0x0c600000 0x0 0x80000>;
1185 #global-interrupts = <1>;
1187 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1254 wifi: wifi@c800000 {
1255 compatible = "qcom,wcn3990-wifi";
1256 reg = <0x0 0x0c800000 0x0 0x800000>;
1257 reg-names = "membase";
1258 memory-region = <&wlan_msa_mem>;
1259 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1271 iommus = <&apps_smmu 0x1a0 0x1>;
1272 qcom,msa-fixed-perm;
1273 status = "disabled";
1277 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1278 reg = <0x0 0x0f017000 0x0 0x1000>;
1279 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1280 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&sleep_clk>;
1284 apcs_glb: mailbox@f111000 {
1285 compatible = "qcom,qcm2290-apcs-hmss-global";
1286 reg = <0x0 0x0f111000 0x0 0x1000>;
1291 compatible = "arm,armv7-timer-mem";
1292 reg = <0x0 0x0f120000 0x0 0x1000>;
1293 #address-cells = <1>;
1295 ranges = <0 0x0 0x0f121000 0x8000>;
1300 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1306 reg = <0x2000 0x1000>;
1307 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1309 status = "disabled";
1313 reg = <0x3000 0x1000>;
1314 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1316 status = "disabled";
1320 reg = <0x4000 0x1000>;
1321 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1323 status = "disabled";
1327 reg = <0x5000 0x1000>;
1328 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1330 status = "disabled";
1334 reg = <0x6000 0x1000>;
1335 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1337 status = "disabled";
1341 reg = <0x7000 0x1000>;
1342 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1344 status = "disabled";
1348 intc: interrupt-controller@f200000 {
1349 compatible = "arm,gic-v3";
1350 reg = <0x0 0x0f200000 0x0 0x10000>,
1351 <0x0 0x0f300000 0x0 0x100000>;
1352 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1353 #interrupt-cells = <3>;
1354 interrupt-controller;
1355 interrupt-parent = <&intc>;
1356 #redistributor-regions = <1>;
1357 redistributor-stride = <0x0 0x20000>;
1360 cpufreq_hw: cpufreq@f521000 {
1361 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
1362 reg = <0x0 0x0f521000 0x0 0x1000>;
1363 reg-names = "freq-domain0";
1364 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1365 interrupt-names = "dcvsh-irq-0";
1366 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
1367 clock-names = "xo", "alternate";
1369 #freq-domain-cells = <1>;
1376 polling-delay-passive = <0>;
1377 polling-delay = <0>;
1379 thermal-sensors = <&tsens0 0>;
1382 mapss_alert0: trip-point0 {
1383 temperature = <90000>;
1384 hysteresis = <2000>;
1388 mapss_alert1: trip-point1 {
1389 temperature = <95000>;
1390 hysteresis = <2000>;
1394 mapss_crit: mapss-crit {
1395 temperature = <110000>;
1396 hysteresis = <1000>;
1403 polling-delay-passive = <0>;
1404 polling-delay = <0>;
1406 thermal-sensors = <&tsens0 1>;
1409 video_alert0: trip-point0 {
1410 temperature = <90000>;
1411 hysteresis = <2000>;
1415 video_alert1: trip-point1 {
1416 temperature = <95000>;
1417 hysteresis = <2000>;
1421 video_crit: video-crit {
1422 temperature = <110000>;
1423 hysteresis = <1000>;
1430 polling-delay-passive = <0>;
1431 polling-delay = <0>;
1433 thermal-sensors = <&tsens0 2>;
1436 wlan_alert0: trip-point0 {
1437 temperature = <90000>;
1438 hysteresis = <2000>;
1442 wlan_alert1: trip-point1 {
1443 temperature = <95000>;
1444 hysteresis = <2000>;
1448 wlan_crit: wlan-crit {
1449 temperature = <110000>;
1450 hysteresis = <1000>;
1457 polling-delay-passive = <0>;
1458 polling-delay = <0>;
1460 thermal-sensors = <&tsens0 3>;
1463 cpuss0_alert0: trip-point0 {
1464 temperature = <90000>;
1465 hysteresis = <2000>;
1469 cpuss0_alert1: trip-point1 {
1470 temperature = <95000>;
1471 hysteresis = <2000>;
1475 cpuss0_crit: cpuss0-crit {
1476 temperature = <110000>;
1477 hysteresis = <1000>;
1484 polling-delay-passive = <0>;
1485 polling-delay = <0>;
1487 thermal-sensors = <&tsens0 4>;
1490 cpuss1_alert0: trip-point0 {
1491 temperature = <90000>;
1492 hysteresis = <2000>;
1496 cpuss1_alert1: trip-point1 {
1497 temperature = <95000>;
1498 hysteresis = <2000>;
1502 cpuss1_crit: cpuss1-crit {
1503 temperature = <110000>;
1504 hysteresis = <1000>;
1511 polling-delay-passive = <0>;
1512 polling-delay = <0>;
1514 thermal-sensors = <&tsens0 5>;
1517 mdm0_alert0: trip-point0 {
1518 temperature = <90000>;
1519 hysteresis = <2000>;
1523 mdm0_alert1: trip-point1 {
1524 temperature = <95000>;
1525 hysteresis = <2000>;
1529 mdm0_crit: mdm0-crit {
1530 temperature = <110000>;
1531 hysteresis = <1000>;
1538 polling-delay-passive = <0>;
1539 polling-delay = <0>;
1541 thermal-sensors = <&tsens0 6>;
1544 mdm1_alert0: trip-point0 {
1545 temperature = <90000>;
1546 hysteresis = <2000>;
1550 mdm1_alert1: trip-point1 {
1551 temperature = <95000>;
1552 hysteresis = <2000>;
1556 mdm1_crit: mdm1-crit {
1557 temperature = <110000>;
1558 hysteresis = <1000>;
1565 polling-delay-passive = <0>;
1566 polling-delay = <0>;
1568 thermal-sensors = <&tsens0 7>;
1571 gpu_alert0: trip-point0 {
1572 temperature = <90000>;
1573 hysteresis = <2000>;
1577 gpu_alert1: trip-point1 {
1578 temperature = <95000>;
1579 hysteresis = <2000>;
1583 gpu_crit: gpu-crit {
1584 temperature = <110000>;
1585 hysteresis = <1000>;
1592 polling-delay-passive = <0>;
1593 polling-delay = <0>;
1595 thermal-sensors = <&tsens0 8>;
1598 hm_center_alert0: trip-point0 {
1599 temperature = <90000>;
1600 hysteresis = <2000>;
1604 hm_center_alert1: trip-point1 {
1605 temperature = <95000>;
1606 hysteresis = <2000>;
1610 hm_center_crit: hm-center-crit {
1611 temperature = <110000>;
1612 hysteresis = <1000>;
1619 polling-delay-passive = <0>;
1620 polling-delay = <0>;
1622 thermal-sensors = <&tsens0 9>;
1625 camera_alert0: trip-point0 {
1626 temperature = <90000>;
1627 hysteresis = <2000>;
1631 camera_alert1: trip-point1 {
1632 temperature = <95000>;
1633 hysteresis = <2000>;
1637 camera_crit: camera-crit {
1638 temperature = <110000>;
1639 hysteresis = <1000>;
1647 compatible = "arm,armv8-timer";
1648 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1649 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1650 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1651 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;