arch/arm64/boot/dts/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/firmware/qcom,scm.h>
  10 #include <dt-bindings/power/qcom-rpmpd.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         qcom,msm-id = <292 0x0>;
  17
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         memory@80000000 {
  24                 device_type = "memory";
  25                 /* We expect the bootloader to fill in the reg */
  26                 reg = <0x0 0x80000000 0x0 0x0>;
  27         };
  28
  29         reserved-memory {
  30                 #address-cells = <2>;
  31                 #size-cells = <2>;
  32                 ranges;
  33
  34                 hyp_mem: memory@85800000 {
  35                         reg = <0x0 0x85800000 0x0 0x600000>;
  36                         no-map;
  37                 };
  38
  39                 xbl_mem: memory@85e00000 {
  40                         reg = <0x0 0x85e00000 0x0 0x100000>;
  41                         no-map;
  42                 };
  43
  44                 smem_mem: smem-mem@86000000 {
  45                         reg = <0x0 0x86000000 0x0 0x200000>;
  46                         no-map;
  47                 };
  48
  49                 tz_mem: memory@86200000 {
  50                         reg = <0x0 0x86200000 0x0 0x2d00000>;
  51                         no-map;
  52                 };
  53
  54                 rmtfs_mem: memory@88f00000 {
  55                         compatible = "qcom,rmtfs-mem";
  56                         reg = <0x0 0x88f00000 0x0 0x200000>;
  57                         no-map;
  58
  59                         qcom,client-id = <1>;
  60                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
  61                 };
  62
  63                 spss_mem: memory@8ab00000 {
  64                         reg = <0x0 0x8ab00000 0x0 0x700000>;
  65                         no-map;
  66                 };
  67
  68                 adsp_mem: memory@8b200000 {
  69                         reg = <0x0 0x8b200000 0x0 0x1a00000>;
  70                         no-map;
  71                 };
  72
  73                 mpss_mem: memory@8cc00000 {
  74                         reg = <0x0 0x8cc00000 0x0 0x7000000>;
  75                         no-map;
  76                 };
  77
  78                 venus_mem: memory@93c00000 {
  79                         reg = <0x0 0x93c00000 0x0 0x500000>;
  80                         no-map;
  81                 };
  82
  83                 mba_mem: memory@94100000 {
  84                         reg = <0x0 0x94100000 0x0 0x200000>;
  85                         no-map;
  86                 };
  87
  88                 slpi_mem: memory@94300000 {
  89                         reg = <0x0 0x94300000 0x0 0xf00000>;
  90                         no-map;
  91                 };
  92
  93                 ipa_fw_mem: memory@95200000 {
  94                         reg = <0x0 0x95200000 0x0 0x10000>;
  95                         no-map;
  96                 };
  97
  98                 ipa_gsi_mem: memory@95210000 {
  99                         reg = <0x0 0x95210000 0x0 0x5000>;
 100                         no-map;
 101                 };
 102
 103                 gpu_mem: memory@95600000 {
 104                         reg = <0x0 0x95600000 0x0 0x100000>;
 105                         no-map;
 106                 };
 107
 108                 wlan_msa_mem: memory@95700000 {
 109                         reg = <0x0 0x95700000 0x0 0x100000>;
 110                         no-map;
 111                 };
 112
 113                 mdata_mem: mpss-metadata {
 114                         alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
 115                         size = <0x0 0x4000>;
 116                         no-map;
 117                 };
 118         };
 119
 120         clocks {
 121                 xo: xo-board {
 122                         compatible = "fixed-clock";
 123                         #clock-cells = <0>;
 124                         clock-frequency = <19200000>;
 125                         clock-output-names = "xo_board";
 126                 };
 127
 128                 sleep_clk: sleep-clk {
 129                         compatible = "fixed-clock";
 130                         #clock-cells = <0>;
 131                         clock-frequency = <32764>;
 132                 };
 133         };
 134
 135         cpus {
 136                 #address-cells = <2>;
 137                 #size-cells = <0>;
 138
 139                 CPU0: cpu@0 {
 140                         device_type = "cpu";
 141                         compatible = "qcom,kryo280";
 142                         reg = <0x0 0x0>;
 143                         enable-method = "psci";
 144                         capacity-dmips-mhz = <1024>;
 145                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 146                         next-level-cache = <&L2_0>;
 147                         L2_0: l2-cache {
 148                                 compatible = "cache";
 149                                 cache-level = <2>;
 150                                 cache-unified;
 151                         };
 152                 };
 153
 154                 CPU1: cpu@1 {
 155                         device_type = "cpu";
 156                         compatible = "qcom,kryo280";
 157                         reg = <0x0 0x1>;
 158                         enable-method = "psci";
 159                         capacity-dmips-mhz = <1024>;
 160                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 161                         next-level-cache = <&L2_0>;
 162                 };
 163
 164                 CPU2: cpu@2 {
 165                         device_type = "cpu";
 166                         compatible = "qcom,kryo280";
 167                         reg = <0x0 0x2>;
 168                         enable-method = "psci";
 169                         capacity-dmips-mhz = <1024>;
 170                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 171                         next-level-cache = <&L2_0>;
 172                 };
 173
 174                 CPU3: cpu@3 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo280";
 177                         reg = <0x0 0x3>;
 178                         enable-method = "psci";
 179                         capacity-dmips-mhz = <1024>;
 180                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 181                         next-level-cache = <&L2_0>;
 182                 };
 183
 184                 CPU4: cpu@100 {
 185                         device_type = "cpu";
 186                         compatible = "qcom,kryo280";
 187                         reg = <0x0 0x100>;
 188                         enable-method = "psci";
 189                         capacity-dmips-mhz = <1536>;
 190                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 191                         next-level-cache = <&L2_1>;
 192                         L2_1: l2-cache {
 193                                 compatible = "cache";
 194                                 cache-level = <2>;
 195                                 cache-unified;
 196                         };
 197                 };
 198
 199                 CPU5: cpu@101 {
 200                         device_type = "cpu";
 201                         compatible = "qcom,kryo280";
 202                         reg = <0x0 0x101>;
 203                         enable-method = "psci";
 204                         capacity-dmips-mhz = <1536>;
 205                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 206                         next-level-cache = <&L2_1>;
 207                 };
 208
 209                 CPU6: cpu@102 {
 210                         device_type = "cpu";
 211                         compatible = "qcom,kryo280";
 212                         reg = <0x0 0x102>;
 213                         enable-method = "psci";
 214                         capacity-dmips-mhz = <1536>;
 215                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 216                         next-level-cache = <&L2_1>;
 217                 };
 218
 219                 CPU7: cpu@103 {
 220                         device_type = "cpu";
 221                         compatible = "qcom,kryo280";
 222                         reg = <0x0 0x103>;
 223                         enable-method = "psci";
 224                         capacity-dmips-mhz = <1536>;
 225                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 226                         next-level-cache = <&L2_1>;
 227                 };
 228
 229                 cpu-map {
 230                         cluster0 {
 231                                 core0 {
 232                                         cpu = <&CPU0>;
 233                                 };
 234
 235                                 core1 {
 236                                         cpu = <&CPU1>;
 237                                 };
 238
 239                                 core2 {
 240                                         cpu = <&CPU2>;
 241                                 };
 242
 243                                 core3 {
 244                                         cpu = <&CPU3>;
 245                                 };
 246                         };
 247
 248                         cluster1 {
 249                                 core0 {
 250                                         cpu = <&CPU4>;
 251                                 };
 252
 253                                 core1 {
 254                                         cpu = <&CPU5>;
 255                                 };
 256
 257                                 core2 {
 258                                         cpu = <&CPU6>;
 259                                 };
 260
 261                                 core3 {
 262                                         cpu = <&CPU7>;
 263                                 };
 264                         };
 265                 };
 266
 267                 idle-states {
 268                         entry-method = "psci";
 269
 270                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 271                                 compatible = "arm,idle-state";
 272                                 idle-state-name = "little-retention";
 273                                 /* CPU Retention (C2D), L2 Active */
 274                                 arm,psci-suspend-param = <0x00000002>;
 275                                 entry-latency-us = <81>;
 276                                 exit-latency-us = <86>;
 277                                 min-residency-us = <504>;
 278                         };
 279
 280                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 281                                 compatible = "arm,idle-state";
 282                                 idle-state-name = "little-power-collapse";
 283                                 /* CPU + L2 Power Collapse (C3, D4) */
 284                                 arm,psci-suspend-param = <0x40000003>;
 285                                 entry-latency-us = <814>;
 286                                 exit-latency-us = <4562>;
 287                                 min-residency-us = <9183>;
 288                                 local-timer-stop;
 289                         };
 290
 291                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 292                                 compatible = "arm,idle-state";
 293                                 idle-state-name = "big-retention";
 294                                 /* CPU Retention (C2D), L2 Active */
 295                                 arm,psci-suspend-param = <0x00000002>;
 296                                 entry-latency-us = <79>;
 297                                 exit-latency-us = <82>;
 298                                 min-residency-us = <1302>;
 299                         };
 300
 301                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 302                                 compatible = "arm,idle-state";
 303                                 idle-state-name = "big-power-collapse";
 304                                 /* CPU + L2 Power Collapse (C3, D4) */
 305                                 arm,psci-suspend-param = <0x40000003>;
 306                                 entry-latency-us = <724>;
 307                                 exit-latency-us = <2027>;
 308                                 min-residency-us = <9419>;
 309                                 local-timer-stop;
 310                         };
 311                 };
 312         };
 313
 314         firmware {
 315                 scm {
 316                         compatible = "qcom,scm-msm8998", "qcom,scm";
 317                 };
 318         };
 319
 320         dsi_opp_table: opp-table-dsi {
 321                 compatible = "operating-points-v2";
 322
 323                 opp-131250000 {
 324                         opp-hz = /bits/ 64 <131250000>;
 325                         required-opps = <&rpmpd_opp_low_svs>;
 326                 };
 327
 328                 opp-210000000 {
 329                         opp-hz = /bits/ 64 <210000000>;
 330                         required-opps = <&rpmpd_opp_svs>;
 331                 };
 332
 333                 opp-312500000 {
 334                         opp-hz = /bits/ 64 <312500000>;
 335                         required-opps = <&rpmpd_opp_nom>;
 336                 };
 337         };
 338
 339         psci {
 340                 compatible = "arm,psci-1.0";
 341                 method = "smc";
 342         };
 343
 344         rpm: remoteproc {
 345                 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
 346
 347                 glink-edge {
 348                         compatible = "qcom,glink-rpm";
 349
 350                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 351                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 352                         mboxes = <&apcs_glb 0>;
 353
 354                         rpm_requests: rpm-requests {
 355                                 compatible = "qcom,rpm-msm8998";
 356                                 qcom,glink-channels = "rpm_requests";
 357
 358                                 rpmcc: clock-controller {
 359                                         compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
 360                                         clocks = <&xo>;
 361                                         clock-names = "xo";
 362                                         #clock-cells = <1>;
 363                                 };
 364
 365                                 rpmpd: power-controller {
 366                                         compatible = "qcom,msm8998-rpmpd";
 367                                         #power-domain-cells = <1>;
 368                                         operating-points-v2 = <&rpmpd_opp_table>;
 369
 370                                         rpmpd_opp_table: opp-table {
 371                                                 compatible = "operating-points-v2";
 372
 373                                                 rpmpd_opp_ret: opp1 {
 374                                                         opp-level = <RPM_SMD_LEVEL_RETENTION>;
 375                                                 };
 376
 377                                                 rpmpd_opp_ret_plus: opp2 {
 378                                                         opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
 379                                                 };
 380
 381                                                 rpmpd_opp_min_svs: opp3 {
 382                                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 383                                                 };
 384
 385                                                 rpmpd_opp_low_svs: opp4 {
 386                                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 387                                                 };
 388
 389                                                 rpmpd_opp_svs: opp5 {
 390                                                         opp-level = <RPM_SMD_LEVEL_SVS>;
 391                                                 };
 392
 393                                                 rpmpd_opp_svs_plus: opp6 {
 394                                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 395                                                 };
 396
 397                                                 rpmpd_opp_nom: opp7 {
 398                                                         opp-level = <RPM_SMD_LEVEL_NOM>;
 399                                                 };
 400
 401                                                 rpmpd_opp_nom_plus: opp8 {
 402                                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 403                                                 };
 404
 405                                                 rpmpd_opp_turbo: opp9 {
 406                                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
 407                                                 };
 408
 409                                                 rpmpd_opp_turbo_plus: opp10 {
 410                                                         opp-level = <RPM_SMD_LEVEL_BINNING>;
 411                                                 };
 412                                         };
 413                                 };
 414                         };
 415                 };
 416         };
 417
 418         smem {
 419                 compatible = "qcom,smem";
 420                 memory-region = <&smem_mem>;
 421                 hwlocks = <&tcsr_mutex 3>;
 422         };
 423
 424         smp2p-lpass {
 425                 compatible = "qcom,smp2p";
 426                 qcom,smem = <443>, <429>;
 427
 428                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 429
 430                 mboxes = <&apcs_glb 10>;
 431
 432                 qcom,local-pid = <0>;
 433                 qcom,remote-pid = <2>;
 434
 435                 adsp_smp2p_out: master-kernel {
 436                         qcom,entry-name = "master-kernel";
 437                         #qcom,smem-state-cells = <1>;
 438                 };
 439
 440                 adsp_smp2p_in: slave-kernel {
 441                         qcom,entry-name = "slave-kernel";
 442
 443                         interrupt-controller;
 444                         #interrupt-cells = <2>;
 445                 };
 446         };
 447
 448         smp2p-mpss {
 449                 compatible = "qcom,smp2p";
 450                 qcom,smem = <435>, <428>;
 451                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 452                 mboxes = <&apcs_glb 14>;
 453                 qcom,local-pid = <0>;
 454                 qcom,remote-pid = <1>;
 455
 456                 modem_smp2p_out: master-kernel {
 457                         qcom,entry-name = "master-kernel";
 458                         #qcom,smem-state-cells = <1>;
 459                 };
 460
 461                 modem_smp2p_in: slave-kernel {
 462                         qcom,entry-name = "slave-kernel";
 463                         interrupt-controller;
 464                         #interrupt-cells = <2>;
 465                 };
 466         };
 467
 468         smp2p-slpi {
 469                 compatible = "qcom,smp2p";
 470                 qcom,smem = <481>, <430>;
 471                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 472                 mboxes = <&apcs_glb 26>;
 473                 qcom,local-pid = <0>;
 474                 qcom,remote-pid = <3>;
 475
 476                 slpi_smp2p_out: master-kernel {
 477                         qcom,entry-name = "master-kernel";
 478                         #qcom,smem-state-cells = <1>;
 479                 };
 480
 481                 slpi_smp2p_in: slave-kernel {
 482                         qcom,entry-name = "slave-kernel";
 483                         interrupt-controller;
 484                         #interrupt-cells = <2>;
 485                 };
 486         };
 487
 488         thermal-zones {
 489                 cpu0-thermal {
 490                         polling-delay-passive = <250>;
 491                         polling-delay = <1000>;
 492
 493                         thermal-sensors = <&tsens0 1>;
 494
 495                         trips {
 496                                 cpu0_alert0: trip-point0 {
 497                                         temperature = <75000>;
 498                                         hysteresis = <2000>;
 499                                         type = "passive";
 500                                 };
 501
 502                                 cpu0_crit: cpu-crit {
 503                                         temperature = <110000>;
 504                                         hysteresis = <2000>;
 505                                         type = "critical";
 506                                 };
 507                         };
 508                 };
 509
 510                 cpu1-thermal {
 511                         polling-delay-passive = <250>;
 512                         polling-delay = <1000>;
 513
 514                         thermal-sensors = <&tsens0 2>;
 515
 516                         trips {
 517                                 cpu1_alert0: trip-point0 {
 518                                         temperature = <75000>;
 519                                         hysteresis = <2000>;
 520                                         type = "passive";
 521                                 };
 522
 523                                 cpu1_crit: cpu-crit {
 524                                         temperature = <110000>;
 525                                         hysteresis = <2000>;
 526                                         type = "critical";
 527                                 };
 528                         };
 529                 };
 530
 531                 cpu2-thermal {
 532                         polling-delay-passive = <250>;
 533                         polling-delay = <1000>;
 534
 535                         thermal-sensors = <&tsens0 3>;
 536
 537                         trips {
 538                                 cpu2_alert0: trip-point0 {
 539                                         temperature = <75000>;
 540                                         hysteresis = <2000>;
 541                                         type = "passive";
 542                                 };
 543
 544                                 cpu2_crit: cpu-crit {
 545                                         temperature = <110000>;
 546                                         hysteresis = <2000>;
 547                                         type = "critical";
 548                                 };
 549                         };
 550                 };
 551
 552                 cpu3-thermal {
 553                         polling-delay-passive = <250>;
 554                         polling-delay = <1000>;
 555
 556                         thermal-sensors = <&tsens0 4>;
 557
 558                         trips {
 559                                 cpu3_alert0: trip-point0 {
 560                                         temperature = <75000>;
 561                                         hysteresis = <2000>;
 562                                         type = "passive";
 563                                 };
 564
 565                                 cpu3_crit: cpu-crit {
 566                                         temperature = <110000>;
 567                                         hysteresis = <2000>;
 568                                         type = "critical";
 569                                 };
 570                         };
 571                 };
 572
 573                 cpu4-thermal {
 574                         polling-delay-passive = <250>;
 575                         polling-delay = <1000>;
 576
 577                         thermal-sensors = <&tsens0 7>;
 578
 579                         trips {
 580                                 cpu4_alert0: trip-point0 {
 581                                         temperature = <75000>;
 582                                         hysteresis = <2000>;
 583                                         type = "passive";
 584                                 };
 585
 586                                 cpu4_crit: cpu-crit {
 587                                         temperature = <110000>;
 588                                         hysteresis = <2000>;
 589                                         type = "critical";
 590                                 };
 591                         };
 592                 };
 593
 594                 cpu5-thermal {
 595                         polling-delay-passive = <250>;
 596                         polling-delay = <1000>;
 597
 598                         thermal-sensors = <&tsens0 8>;
 599
 600                         trips {
 601                                 cpu5_alert0: trip-point0 {
 602                                         temperature = <75000>;
 603                                         hysteresis = <2000>;
 604                                         type = "passive";
 605                                 };
 606
 607                                 cpu5_crit: cpu-crit {
 608                                         temperature = <110000>;
 609                                         hysteresis = <2000>;
 610                                         type = "critical";
 611                                 };
 612                         };
 613                 };
 614
 615                 cpu6-thermal {
 616                         polling-delay-passive = <250>;
 617                         polling-delay = <1000>;
 618
 619                         thermal-sensors = <&tsens0 9>;
 620
 621                         trips {
 622                                 cpu6_alert0: trip-point0 {
 623                                         temperature = <75000>;
 624                                         hysteresis = <2000>;
 625                                         type = "passive";
 626                                 };
 627
 628                                 cpu6_crit: cpu-crit {
 629                                         temperature = <110000>;
 630                                         hysteresis = <2000>;
 631                                         type = "critical";
 632                                 };
 633                         };
 634                 };
 635
 636                 cpu7-thermal {
 637                         polling-delay-passive = <250>;
 638                         polling-delay = <1000>;
 639
 640                         thermal-sensors = <&tsens0 10>;
 641
 642                         trips {
 643                                 cpu7_alert0: trip-point0 {
 644                                         temperature = <75000>;
 645                                         hysteresis = <2000>;
 646                                         type = "passive";
 647                                 };
 648
 649                                 cpu7_crit: cpu-crit {
 650                                         temperature = <110000>;
 651                                         hysteresis = <2000>;
 652                                         type = "critical";
 653                                 };
 654                         };
 655                 };
 656
 657                 gpu-bottom-thermal {
 658                         polling-delay-passive = <250>;
 659                         polling-delay = <1000>;
 660
 661                         thermal-sensors = <&tsens0 12>;
 662
 663                         trips {
 664                                 gpu1_alert0: trip-point0 {
 665                                         temperature = <90000>;
 666                                         hysteresis = <2000>;
 667                                         type = "hot";
 668                                 };
 669                         };
 670                 };
 671
 672                 gpu-top-thermal {
 673                         polling-delay-passive = <250>;
 674                         polling-delay = <1000>;
 675
 676                         thermal-sensors = <&tsens0 13>;
 677
 678                         trips {
 679                                 gpu2_alert0: trip-point0 {
 680                                         temperature = <90000>;
 681                                         hysteresis = <2000>;
 682                                         type = "hot";
 683                                 };
 684                         };
 685                 };
 686
 687                 clust0-mhm-thermal {
 688                         polling-delay-passive = <250>;
 689                         polling-delay = <1000>;
 690
 691                         thermal-sensors = <&tsens0 5>;
 692
 693                         trips {
 694                                 cluster0_mhm_alert0: trip-point0 {
 695                                         temperature = <90000>;
 696                                         hysteresis = <2000>;
 697                                         type = "hot";
 698                                 };
 699                         };
 700                 };
 701
 702                 clust1-mhm-thermal {
 703                         polling-delay-passive = <250>;
 704                         polling-delay = <1000>;
 705
 706                         thermal-sensors = <&tsens0 6>;
 707
 708                         trips {
 709                                 cluster1_mhm_alert0: trip-point0 {
 710                                         temperature = <90000>;
 711                                         hysteresis = <2000>;
 712                                         type = "hot";
 713                                 };
 714                         };
 715                 };
 716
 717                 cluster1-l2-thermal {
 718                         polling-delay-passive = <250>;
 719                         polling-delay = <1000>;
 720
 721                         thermal-sensors = <&tsens0 11>;
 722
 723                         trips {
 724                                 cluster1_l2_alert0: trip-point0 {
 725                                         temperature = <90000>;
 726                                         hysteresis = <2000>;
 727                                         type = "hot";
 728                                 };
 729                         };
 730                 };
 731
 732                 modem-thermal {
 733                         polling-delay-passive = <250>;
 734                         polling-delay = <1000>;
 735
 736                         thermal-sensors = <&tsens1 1>;
 737
 738                         trips {
 739                                 modem_alert0: trip-point0 {
 740                                         temperature = <90000>;
 741                                         hysteresis = <2000>;
 742                                         type = "hot";
 743                                 };
 744                         };
 745                 };
 746
 747                 mem-thermal {
 748                         polling-delay-passive = <250>;
 749                         polling-delay = <1000>;
 750
 751                         thermal-sensors = <&tsens1 2>;
 752
 753                         trips {
 754                                 mem_alert0: trip-point0 {
 755                                         temperature = <90000>;
 756                                         hysteresis = <2000>;
 757                                         type = "hot";
 758                                 };
 759                         };
 760                 };
 761
 762                 wlan-thermal {
 763                         polling-delay-passive = <250>;
 764                         polling-delay = <1000>;
 765
 766                         thermal-sensors = <&tsens1 3>;
 767
 768                         trips {
 769                                 wlan_alert0: trip-point0 {
 770                                         temperature = <90000>;
 771                                         hysteresis = <2000>;
 772                                         type = "hot";
 773                                 };
 774                         };
 775                 };
 776
 777                 q6-dsp-thermal {
 778                         polling-delay-passive = <250>;
 779                         polling-delay = <1000>;
 780
 781                         thermal-sensors = <&tsens1 4>;
 782
 783                         trips {
 784                                 q6_dsp_alert0: trip-point0 {
 785                                         temperature = <90000>;
 786                                         hysteresis = <2000>;
 787                                         type = "hot";
 788                                 };
 789                         };
 790                 };
 791
 792                 camera-thermal {
 793                         polling-delay-passive = <250>;
 794                         polling-delay = <1000>;
 795
 796                         thermal-sensors = <&tsens1 5>;
 797
 798                         trips {
 799                                 camera_alert0: trip-point0 {
 800                                         temperature = <90000>;
 801                                         hysteresis = <2000>;
 802                                         type = "hot";
 803                                 };
 804                         };
 805                 };
 806
 807                 multimedia-thermal {
 808                         polling-delay-passive = <250>;
 809                         polling-delay = <1000>;
 810
 811                         thermal-sensors = <&tsens1 6>;
 812
 813                         trips {
 814                                 multimedia_alert0: trip-point0 {
 815                                         temperature = <90000>;
 816                                         hysteresis = <2000>;
 817                                         type = "hot";
 818                                 };
 819                         };
 820                 };
 821         };
 822
 823         timer {
 824                 compatible = "arm,armv8-timer";
 825                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 826                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 827                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 828                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 829         };
 830
 831         soc: soc@0 {
 832                 #address-cells = <1>;
 833                 #size-cells = <1>;
 834                 ranges = <0 0 0 0xffffffff>;
 835                 compatible = "simple-bus";
 836
 837                 gcc: clock-controller@100000 {
 838                         compatible = "qcom,gcc-msm8998";
 839                         #clock-cells = <1>;
 840                         #reset-cells = <1>;
 841                         #power-domain-cells = <1>;
 842                         reg = <0x00100000 0xb0000>;
 843
 844                         clock-names = "xo", "sleep_clk";
 845                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
 846
 847                         /*
 848                          * The hypervisor typically configures the memory region where these clocks
 849                          * reside as read-only for the HLOS. If the HLOS tried to enable or disable
 850                          * these clocks on a device with such configuration (e.g. because they are
 851                          * enabled but unused during boot-up), the device will most likely decide
 852                          * to reboot.
 853                          * In light of that, we are conservative here and we list all such clocks
 854                          * as protected. The board dts (or a user-supplied dts) can override the
 855                          * list of protected clocks if it differs from the norm, and it is in fact
 856                          * desired for the HLOS to manage these clocks
 857                          */
 858                         protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
 859                                            <SSC_XO>,
 860                                            <SSC_CNOC_AHBS_CLK>;
 861                 };
 862
 863                 rpm_msg_ram: sram@778000 {
 864                         compatible = "qcom,rpm-msg-ram";
 865                         reg = <0x00778000 0x7000>;
 866                 };
 867
 868                 qfprom: qfprom@784000 {
 869                         compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
 870                         reg = <0x00784000 0x621c>;
 871                         #address-cells = <1>;
 872                         #size-cells = <1>;
 873
 874                         qusb2_hstx_trim: hstx-trim@23a {
 875                                 reg = <0x23a 0x1>;
 876                                 bits = <0 4>;
 877                         };
 878                 };
 879
 880                 tsens0: thermal@10ab000 {
 881                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 882                         reg = <0x010ab000 0x1000>, /* TM */
 883                               <0x010aa000 0x1000>; /* SROT */
 884                         #qcom,sensors = <14>;
 885                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 886                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 887                         interrupt-names = "uplow", "critical";
 888                         #thermal-sensor-cells = <1>;
 889                 };
 890
 891                 tsens1: thermal@10ae000 {
 892                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 893                         reg = <0x010ae000 0x1000>, /* TM */
 894                               <0x010ad000 0x1000>; /* SROT */
 895                         #qcom,sensors = <8>;
 896                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 897                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 898                         interrupt-names = "uplow", "critical";
 899                         #thermal-sensor-cells = <1>;
 900                 };
 901
 902                 anoc1_smmu: iommu@1680000 {
 903                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 904                         reg = <0x01680000 0x10000>;
 905                         #iommu-cells = <1>;
 906
 907                         #global-interrupts = <0>;
 908                         interrupts =
 909                                 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 910                                 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 911                                 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
 912                                 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
 913                                 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
 914                                 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 915                 };
 916
 917                 anoc2_smmu: iommu@16c0000 {
 918                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 919                         reg = <0x016c0000 0x40000>;
 920                         #iommu-cells = <1>;
 921
 922                         #global-interrupts = <0>;
 923                         interrupts =
 924                                 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
 925                                 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
 926                                 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
 927                                 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
 928                                 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
 929                                 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
 930                                 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
 931                                 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
 932                                 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
 933                                 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
 934                 };
 935
 936                 pcie0: pci@1c00000 {
 937                         compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
 938                         reg = <0x01c00000 0x2000>,
 939                               <0x1b000000 0xf1d>,
 940                               <0x1b000f20 0xa8>,
 941                               <0x1b100000 0x100000>;
 942                         reg-names = "parf", "dbi", "elbi", "config";
 943                         device_type = "pci";
 944                         linux,pci-domain = <0>;
 945                         bus-range = <0x00 0xff>;
 946                         #address-cells = <3>;
 947                         #size-cells = <2>;
 948                         num-lanes = <1>;
 949                         phys = <&pcie_phy>;
 950                         phy-names = "pciephy";
 951                         status = "disabled";
 952
 953                         ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
 954                                  <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
 955
 956                         #interrupt-cells = <1>;
 957                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 958                         interrupt-names = "msi";
 959                         interrupt-map-mask = <0 0 0 0x7>;
 960                         interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
 961                                         <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
 962                                         <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
 963                                         <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
 964
 965                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 966                                  <&gcc GCC_PCIE_0_AUX_CLK>,
 967                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 968                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 969                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 970                         clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
 971
 972                         power-domains = <&gcc PCIE_0_GDSC>;
 973                         iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
 974                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
 975                 };
 976
 977                 pcie_phy: phy@1c06000 {
 978                         compatible = "qcom,msm8998-qmp-pcie-phy";
 979                         reg = <0x01c06000 0x1000>;
 980                         status = "disabled";
 981
 982                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 983                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 984                                  <&gcc GCC_PCIE_CLKREF_CLK>,
 985                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
 986                         clock-names = "aux",
 987                                       "cfg_ahb",
 988                                       "ref",
 989                                       "pipe";
 990
 991                         clock-output-names = "pcie_0_pipe_clk_src";
 992                         #clock-cells = <0>;
 993
 994                         #phy-cells = <0>;
 995
 996                         resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
 997                         reset-names = "phy", "common";
 998
 999                         vdda-phy-supply = <&vreg_l1a_0p875>;
1000                         vdda-pll-supply = <&vreg_l2a_1p2>;
1001                 };
1002
1003                 ufshc: ufshc@1da4000 {
1004                         compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1005                         reg = <0x01da4000 0x2500>;
1006                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1007                         phys = <&ufsphy_lanes>;
1008                         phy-names = "ufsphy";
1009                         lanes-per-direction = <2>;
1010                         power-domains = <&gcc UFS_GDSC>;
1011                         status = "disabled";
1012                         #reset-cells = <1>;
1013
1014                         clock-names =
1015                                 "core_clk",
1016                                 "bus_aggr_clk",
1017                                 "iface_clk",
1018                                 "core_clk_unipro",
1019                                 "ref_clk",
1020                                 "tx_lane0_sync_clk",
1021                                 "rx_lane0_sync_clk",
1022                                 "rx_lane1_sync_clk";
1023                         clocks =
1024                                 <&gcc GCC_UFS_AXI_CLK>,
1025                                 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1026                                 <&gcc GCC_UFS_AHB_CLK>,
1027                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1028                                 <&rpmcc RPM_SMD_LN_BB_CLK1>,
1029                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1030                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1031                                 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1032                         freq-table-hz =
1033                                 <50000000 200000000>,
1034                                 <0 0>,
1035                                 <0 0>,
1036                                 <37500000 150000000>,
1037                                 <0 0>,
1038                                 <0 0>,
1039                                 <0 0>,
1040                                 <0 0>;
1041
1042                         resets = <&gcc GCC_UFS_BCR>;
1043                         reset-names = "rst";
1044                 };
1045
1046                 ufsphy: phy@1da7000 {
1047                         compatible = "qcom,msm8998-qmp-ufs-phy";
1048                         reg = <0x01da7000 0x18c>;
1049                         #address-cells = <1>;
1050                         #size-cells = <1>;
1051                         status = "disabled";
1052                         ranges;
1053
1054                         clock-names =
1055                                 "ref",
1056                                 "ref_aux";
1057                         clocks =
1058                                 <&gcc GCC_UFS_CLKREF_CLK>,
1059                                 <&gcc GCC_UFS_PHY_AUX_CLK>;
1060
1061                         reset-names = "ufsphy";
1062                         resets = <&ufshc 0>;
1063
1064                         ufsphy_lanes: phy@1da7400 {
1065                                 reg = <0x01da7400 0x128>,
1066                                       <0x01da7600 0x1fc>,
1067                                       <0x01da7c00 0x1dc>,
1068                                       <0x01da7800 0x128>,
1069                                       <0x01da7a00 0x1fc>;
1070                                 #phy-cells = <0>;
1071                         };
1072                 };
1073
1074                 tcsr_mutex: hwlock@1f40000 {
1075                         compatible = "qcom,tcsr-mutex";
1076                         reg = <0x01f40000 0x20000>;
1077                         #hwlock-cells = <1>;
1078                 };
1079
1080                 tcsr_regs_1: syscon@1f60000 {
1081                         compatible = "qcom,msm8998-tcsr", "syscon";
1082                         reg = <0x01f60000 0x20000>;
1083                 };
1084
1085                 tlmm: pinctrl@3400000 {
1086                         compatible = "qcom,msm8998-pinctrl";
1087                         reg = <0x03400000 0xc00000>;
1088                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1089                         gpio-ranges = <&tlmm 0 0 150>;
1090                         gpio-controller;
1091                         #gpio-cells = <2>;
1092                         interrupt-controller;
1093                         #interrupt-cells = <2>;
1094
1095                         sdc2_on: sdc2-on-state {
1096                                 clk-pins {
1097                                         pins = "sdc2_clk";
1098                                         drive-strength = <16>;
1099                                         bias-disable;
1100                                 };
1101
1102                                 cmd-pins {
1103                                         pins = "sdc2_cmd";
1104                                         drive-strength = <10>;
1105                                         bias-pull-up;
1106                                 };
1107
1108                                 data-pins {
1109                                         pins = "sdc2_data";
1110                                         drive-strength = <10>;
1111                                         bias-pull-up;
1112                                 };
1113                         };
1114
1115                         sdc2_off: sdc2-off-state {
1116                                 clk-pins {
1117                                         pins = "sdc2_clk";
1118                                         drive-strength = <2>;
1119                                         bias-disable;
1120                                 };
1121
1122                                 cmd-pins {
1123                                         pins = "sdc2_cmd";
1124                                         drive-strength = <2>;
1125                                         bias-pull-up;
1126                                 };
1127
1128                                 data-pins {
1129                                         pins = "sdc2_data";
1130                                         drive-strength = <2>;
1131                                         bias-pull-up;
1132                                 };
1133                         };
1134
1135                         sdc2_cd: sdc2-cd-state {
1136                                 pins = "gpio95";
1137                                 function = "gpio";
1138                                 bias-pull-up;
1139                                 drive-strength = <2>;
1140                         };
1141
1142                         blsp1_uart3_on: blsp1-uart3-on-state {
1143                                 tx-pins {
1144                                         pins = "gpio45";
1145                                         function = "blsp_uart3_a";
1146                                         drive-strength = <2>;
1147                                         bias-disable;
1148                                 };
1149
1150                                 rx-pins {
1151                                         pins = "gpio46";
1152                                         function = "blsp_uart3_a";
1153                                         drive-strength = <2>;
1154                                         bias-disable;
1155                                 };
1156
1157                                 cts-pins {
1158                                         pins = "gpio47";
1159                                         function = "blsp_uart3_a";
1160                                         drive-strength = <2>;
1161                                         bias-disable;
1162                                 };
1163
1164                                 rfr-pins {
1165                                         pins = "gpio48";
1166                                         function = "blsp_uart3_a";
1167                                         drive-strength = <2>;
1168                                         bias-disable;
1169                                 };
1170                         };
1171
1172                         blsp1_i2c1_default: blsp1-i2c1-default-state {
1173                                 pins = "gpio2", "gpio3";
1174                                 function = "blsp_i2c1";
1175                                 drive-strength = <2>;
1176                                 bias-disable;
1177                         };
1178
1179                         blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1180                                 pins = "gpio2", "gpio3";
1181                                 function = "blsp_i2c1";
1182                                 drive-strength = <2>;
1183                                 bias-pull-up;
1184                         };
1185
1186                         blsp1_i2c2_default: blsp1-i2c2-default-state {
1187                                 pins = "gpio32", "gpio33";
1188                                 function = "blsp_i2c2";
1189                                 drive-strength = <2>;
1190                                 bias-disable;
1191                         };
1192
1193                         blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1194                                 pins = "gpio32", "gpio33";
1195                                 function = "blsp_i2c2";
1196                                 drive-strength = <2>;
1197                                 bias-pull-up;
1198                         };
1199
1200                         blsp1_i2c3_default: blsp1-i2c3-default-state {
1201                                 pins = "gpio47", "gpio48";
1202                                 function = "blsp_i2c3";
1203                                 drive-strength = <2>;
1204                                 bias-disable;
1205                         };
1206
1207                         blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1208                                 pins = "gpio47", "gpio48";
1209                                 function = "blsp_i2c3";
1210                                 drive-strength = <2>;
1211                                 bias-pull-up;
1212                         };
1213
1214                         blsp1_i2c4_default: blsp1-i2c4-default-state {
1215                                 pins = "gpio10", "gpio11";
1216                                 function = "blsp_i2c4";
1217                                 drive-strength = <2>;
1218                                 bias-disable;
1219                         };
1220
1221                         blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1222                                 pins = "gpio10", "gpio11";
1223                                 function = "blsp_i2c4";
1224                                 drive-strength = <2>;
1225                                 bias-pull-up;
1226                         };
1227
1228                         blsp1_i2c5_default: blsp1-i2c5-default-state {
1229                                 pins = "gpio87", "gpio88";
1230                                 function = "blsp_i2c5";
1231                                 drive-strength = <2>;
1232                                 bias-disable;
1233                         };
1234
1235                         blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1236                                 pins = "gpio87", "gpio88";
1237                                 function = "blsp_i2c5";
1238                                 drive-strength = <2>;
1239                                 bias-pull-up;
1240                         };
1241
1242                         blsp1_i2c6_default: blsp1-i2c6-default-state {
1243                                 pins = "gpio43", "gpio44";
1244                                 function = "blsp_i2c6";
1245                                 drive-strength = <2>;
1246                                 bias-disable;
1247                         };
1248
1249                         blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1250                                 pins = "gpio43", "gpio44";
1251                                 function = "blsp_i2c6";
1252                                 drive-strength = <2>;
1253                                 bias-pull-up;
1254                         };
1255
1256                         blsp1_spi_b_default: blsp1-spi-b-default-state {
1257                                 pins = "gpio23", "gpio28";
1258                                 function = "blsp1_spi_b";
1259                                 drive-strength = <6>;
1260                                 bias-disable;
1261                         };
1262
1263                         blsp1_spi1_default: blsp1-spi1-default-state {
1264                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1265                                 function = "blsp_spi1";
1266                                 drive-strength = <6>;
1267                                 bias-disable;
1268                         };
1269
1270                         blsp1_spi2_default: blsp1-spi2-default-state {
1271                                 pins = "gpio31", "gpio34", "gpio32", "gpio33";
1272                                 function = "blsp_spi2";
1273                                 drive-strength = <6>;
1274                                 bias-disable;
1275                         };
1276
1277                         blsp1_spi3_default: blsp1-spi3-default-state {
1278                                 pins = "gpio45", "gpio46", "gpio47", "gpio48";
1279                                 function = "blsp_spi2";
1280                                 drive-strength = <6>;
1281                                 bias-disable;
1282                         };
1283
1284                         blsp1_spi4_default: blsp1-spi4-default-state {
1285                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1286                                 function = "blsp_spi4";
1287                                 drive-strength = <6>;
1288                                 bias-disable;
1289                         };
1290
1291                         blsp1_spi5_default: blsp1-spi5-default-state {
1292                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1293                                 function = "blsp_spi5";
1294                                 drive-strength = <6>;
1295                                 bias-disable;
1296                         };
1297
1298                         blsp1_spi6_default: blsp1-spi6-default-state {
1299                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1300                                 function = "blsp_spi6";
1301                                 drive-strength = <6>;
1302                                 bias-disable;
1303                         };
1304
1305
1306                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1307                         blsp2_i2c1_default: blsp2-i2c1-default-state {
1308                                 pins = "gpio55", "gpio56";
1309                                 function = "blsp_i2c7";
1310                                 drive-strength = <2>;
1311                                 bias-disable;
1312                         };
1313
1314                         blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1315                                 pins = "gpio55", "gpio56";
1316                                 function = "blsp_i2c7";
1317                                 drive-strength = <2>;
1318                                 bias-pull-up;
1319                         };
1320
1321                         blsp2_i2c2_default: blsp2-i2c2-default-state {
1322                                 pins = "gpio6", "gpio7";
1323                                 function = "blsp_i2c8";
1324                                 drive-strength = <2>;
1325                                 bias-disable;
1326                         };
1327
1328                         blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1329                                 pins = "gpio6", "gpio7";
1330                                 function = "blsp_i2c8";
1331                                 drive-strength = <2>;
1332                                 bias-pull-up;
1333                         };
1334
1335                         blsp2_i2c3_default: blsp2-i2c3-default-state {
1336                                 pins = "gpio51", "gpio52";
1337                                 function = "blsp_i2c9";
1338                                 drive-strength = <2>;
1339                                 bias-disable;
1340                         };
1341
1342                         blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1343                                 pins = "gpio51", "gpio52";
1344                                 function = "blsp_i2c9";
1345                                 drive-strength = <2>;
1346                                 bias-pull-up;
1347                         };
1348
1349                         blsp2_i2c4_default: blsp2-i2c4-default-state {
1350                                 pins = "gpio67", "gpio68";
1351                                 function = "blsp_i2c10";
1352                                 drive-strength = <2>;
1353                                 bias-disable;
1354                         };
1355
1356                         blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1357                                 pins = "gpio67", "gpio68";
1358                                 function = "blsp_i2c10";
1359                                 drive-strength = <2>;
1360                                 bias-pull-up;
1361                         };
1362
1363                         blsp2_i2c5_default: blsp2-i2c5-default-state {
1364                                 pins = "gpio60", "gpio61";
1365                                 function = "blsp_i2c11";
1366                                 drive-strength = <2>;
1367                                 bias-disable;
1368                         };
1369
1370                         blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1371                                 pins = "gpio60", "gpio61";
1372                                 function = "blsp_i2c11";
1373                                 drive-strength = <2>;
1374                                 bias-pull-up;
1375                         };
1376
1377                         blsp2_i2c6_default: blsp2-i2c6-default-state {
1378                                 pins = "gpio83", "gpio84";
1379                                 function = "blsp_i2c12";
1380                                 drive-strength = <2>;
1381                                 bias-disable;
1382                         };
1383
1384                         blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1385                                 pins = "gpio83", "gpio84";
1386                                 function = "blsp_i2c12";
1387                                 drive-strength = <2>;
1388                                 bias-pull-up;
1389                         };
1390
1391                         blsp2_spi1_default: blsp2-spi1-default-state {
1392                                 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1393                                 function = "blsp_spi7";
1394                                 drive-strength = <6>;
1395                                 bias-disable;
1396                         };
1397
1398                         blsp2_spi2_default: blsp2-spi2-default-state {
1399                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1400                                 function = "blsp_spi8";
1401                                 drive-strength = <6>;
1402                                 bias-disable;
1403                         };
1404
1405                         blsp2_spi3_default: blsp2-spi3-default-state {
1406                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1407                                 function = "blsp_spi9";
1408                                 drive-strength = <6>;
1409                                 bias-disable;
1410                         };
1411
1412                         blsp2_spi4_default: blsp2-spi4-default-state {
1413                                 pins = "gpio65", "gpio66", "gpio67", "gpio68";
1414                                 function = "blsp_spi10";
1415                                 drive-strength = <6>;
1416                                 bias-disable;
1417                         };
1418
1419                         blsp2_spi5_default: blsp2-spi5-default-state {
1420                                 pins = "gpio58", "gpio59", "gpio60", "gpio61";
1421                                 function = "blsp_spi11";
1422                                 drive-strength = <6>;
1423                                 bias-disable;
1424                         };
1425
1426                         blsp2_spi6_default: blsp2-spi6-default-state {
1427                                 pins = "gpio81", "gpio82", "gpio83", "gpio84";
1428                                 function = "blsp_spi12";
1429                                 drive-strength = <6>;
1430                                 bias-disable;
1431                         };
1432                 };
1433
1434                 remoteproc_mss: remoteproc@4080000 {
1435                         compatible = "qcom,msm8998-mss-pil";
1436                         reg = <0x04080000 0x100>, <0x04180000 0x20>;
1437                         reg-names = "qdsp6", "rmb";
1438
1439                         interrupts-extended =
1440                                 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1441                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1442                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1443                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1444                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1445                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1446                         interrupt-names = "wdog", "fatal", "ready",
1447                                           "handover", "stop-ack",
1448                                           "shutdown-ack";
1449
1450                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1451                                  <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1452                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1453                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1454                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1455                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1456                                  <&rpmcc RPM_SMD_QDSS_CLK>,
1457                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1458                         clock-names = "iface", "bus", "mem", "gpll0_mss",
1459                                       "snoc_axi", "mnoc_axi", "qdss", "xo";
1460
1461                         qcom,smem-states = <&modem_smp2p_out 0>;
1462                         qcom,smem-state-names = "stop";
1463
1464                         resets = <&gcc GCC_MSS_RESTART>;
1465                         reset-names = "mss_restart";
1466
1467                         qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1468
1469                         power-domains = <&rpmpd MSM8998_VDDCX>,
1470                                         <&rpmpd MSM8998_VDDMX>;
1471                         power-domain-names = "cx", "mx";
1472
1473                         status = "disabled";
1474
1475                         mba {
1476                                 memory-region = <&mba_mem>;
1477                         };
1478
1479                         mpss {
1480                                 memory-region = <&mpss_mem>;
1481                         };
1482
1483                         metadata {
1484                                 memory-region = <&mdata_mem>;
1485                         };
1486
1487                         glink-edge {
1488                                 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1489                                 label = "modem";
1490                                 qcom,remote-pid = <1>;
1491                                 mboxes = <&apcs_glb 15>;
1492                         };
1493                 };
1494
1495                 adreno_gpu: gpu@5000000 {
1496                         compatible = "qcom,adreno-540.1", "qcom,adreno";
1497                         reg = <0x05000000 0x40000>;
1498                         reg-names = "kgsl_3d0_reg_memory";
1499
1500                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1501                                 <&gpucc RBBMTIMER_CLK>,
1502                                 <&gcc GCC_BIMC_GFX_CLK>,
1503                                 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1504                                 <&gpucc RBCPR_CLK>,
1505                                 <&gpucc GFX3D_CLK>;
1506                         clock-names = "iface",
1507                                 "rbbmtimer",
1508                                 "mem",
1509                                 "mem_iface",
1510                                 "rbcpr",
1511                                 "core";
1512
1513                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1514                         iommus = <&adreno_smmu 0>;
1515                         operating-points-v2 = <&gpu_opp_table>;
1516                         power-domains = <&rpmpd MSM8998_VDDMX>;
1517                         status = "disabled";
1518
1519                         gpu_opp_table: opp-table {
1520                                 compatible = "operating-points-v2";
1521                                 opp-710000097 {
1522                                         opp-hz = /bits/ 64 <710000097>;
1523                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
1524                                         opp-supported-hw = <0xff>;
1525                                 };
1526
1527                                 opp-670000048 {
1528                                         opp-hz = /bits/ 64 <670000048>;
1529                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1530                                         opp-supported-hw = <0xff>;
1531                                 };
1532
1533                                 opp-596000097 {
1534                                         opp-hz = /bits/ 64 <596000097>;
1535                                         opp-level = <RPM_SMD_LEVEL_NOM>;
1536                                         opp-supported-hw = <0xff>;
1537                                 };
1538
1539                                 opp-515000097 {
1540                                         opp-hz = /bits/ 64 <515000097>;
1541                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1542                                         opp-supported-hw = <0xff>;
1543                                 };
1544
1545                                 opp-414000000 {
1546                                         opp-hz = /bits/ 64 <414000000>;
1547                                         opp-level = <RPM_SMD_LEVEL_SVS>;
1548                                         opp-supported-hw = <0xff>;
1549                                 };
1550
1551                                 opp-342000000 {
1552                                         opp-hz = /bits/ 64 <342000000>;
1553                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1554                                         opp-supported-hw = <0xff>;
1555                                 };
1556
1557                                 opp-257000000 {
1558                                         opp-hz = /bits/ 64 <257000000>;
1559                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1560                                         opp-supported-hw = <0xff>;
1561                                 };
1562                         };
1563                 };
1564
1565                 adreno_smmu: iommu@5040000 {
1566                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1567                         reg = <0x05040000 0x10000>;
1568                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1569                                  <&gcc GCC_BIMC_GFX_CLK>,
1570                                  <&gcc GCC_GPU_BIMC_GFX_CLK>;
1571                         clock-names = "iface", "mem", "mem_iface";
1572
1573                         #global-interrupts = <0>;
1574                         #iommu-cells = <1>;
1575                         interrupts =
1576                                 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1577                                 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1578                                 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1579                         /*
1580                          * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1581                          * GPU-CX for SMMU but we need both of them up for Adreno.
1582                          * Contemporarily, we also need to manage the VDDMX rpmpd
1583                          * domain in the Adreno driver.
1584                          * Enable GPU CX/GX GDSCs here so that we can manage the
1585                          * SoC VDDMX RPM Power Domain in the Adreno driver.
1586                          */
1587                         power-domains = <&gpucc GPU_GX_GDSC>;
1588                         status = "disabled";
1589                 };
1590
1591                 gpucc: clock-controller@5065000 {
1592                         compatible = "qcom,msm8998-gpucc";
1593                         #clock-cells = <1>;
1594                         #reset-cells = <1>;
1595                         #power-domain-cells = <1>;
1596                         reg = <0x05065000 0x9000>;
1597
1598                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1599                                  <&gcc GCC_GPU_GPLL0_CLK>;
1600                         clock-names = "xo",
1601                                       "gpll0";
1602                 };
1603
1604                 remoteproc_slpi: remoteproc@5800000 {
1605                         compatible = "qcom,msm8998-slpi-pas";
1606                         reg = <0x05800000 0x4040>;
1607
1608                         interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1609                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1610                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1611                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1612                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1613                         interrupt-names = "wdog", "fatal", "ready",
1614                                           "handover", "stop-ack";
1615
1616                         px-supply = <&vreg_lvs2a_1p8>;
1617
1618                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1619                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1620                         clock-names = "xo", "aggre2";
1621
1622                         memory-region = <&slpi_mem>;
1623
1624                         qcom,smem-states = <&slpi_smp2p_out 0>;
1625                         qcom,smem-state-names = "stop";
1626
1627                         power-domains = <&rpmpd MSM8998_SSCCX>;
1628                         power-domain-names = "ssc_cx";
1629
1630                         status = "disabled";
1631
1632                         glink-edge {
1633                                 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1634                                 label = "dsps";
1635                                 qcom,remote-pid = <3>;
1636                                 mboxes = <&apcs_glb 27>;
1637                         };
1638                 };
1639
1640                 stm: stm@6002000 {
1641                         compatible = "arm,coresight-stm", "arm,primecell";
1642                         reg = <0x06002000 0x1000>,
1643                               <0x16280000 0x180000>;
1644                         reg-names = "stm-base", "stm-stimulus-base";
1645                         status = "disabled";
1646
1647                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1648                         clock-names = "apb_pclk", "atclk";
1649
1650                         out-ports {
1651                                 port {
1652                                         stm_out: endpoint {
1653                                                 remote-endpoint = <&funnel0_in7>;
1654                                         };
1655                                 };
1656                         };
1657                 };
1658
1659                 funnel1: funnel@6041000 {
1660                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1661                         reg = <0x06041000 0x1000>;
1662                         status = "disabled";
1663
1664                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1665                         clock-names = "apb_pclk", "atclk";
1666
1667                         out-ports {
1668                                 port {
1669                                         funnel0_out: endpoint {
1670                                                 remote-endpoint =
1671                                                   <&merge_funnel_in0>;
1672                                         };
1673                                 };
1674                         };
1675
1676                         in-ports {
1677                                 #address-cells = <1>;
1678                                 #size-cells = <0>;
1679
1680                                 port@7 {
1681                                         reg = <7>;
1682                                         funnel0_in7: endpoint {
1683                                                 remote-endpoint = <&stm_out>;
1684                                         };
1685                                 };
1686                         };
1687                 };
1688
1689                 funnel2: funnel@6042000 {
1690                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1691                         reg = <0x06042000 0x1000>;
1692                         status = "disabled";
1693
1694                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1695                         clock-names = "apb_pclk", "atclk";
1696
1697                         out-ports {
1698                                 port {
1699                                         funnel1_out: endpoint {
1700                                                 remote-endpoint =
1701                                                   <&merge_funnel_in1>;
1702                                         };
1703                                 };
1704                         };
1705
1706                         in-ports {
1707                                 #address-cells = <1>;
1708                                 #size-cells = <0>;
1709
1710                                 port@6 {
1711                                         reg = <6>;
1712                                         funnel1_in6: endpoint {
1713                                                 remote-endpoint =
1714                                                   <&apss_merge_funnel_out>;
1715                                         };
1716                                 };
1717                         };
1718                 };
1719
1720                 funnel3: funnel@6045000 {
1721                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1722                         reg = <0x06045000 0x1000>;
1723                         status = "disabled";
1724
1725                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1726                         clock-names = "apb_pclk", "atclk";
1727
1728                         out-ports {
1729                                 port {
1730                                         merge_funnel_out: endpoint {
1731                                                 remote-endpoint =
1732                                                   <&etf_in>;
1733                                         };
1734                                 };
1735                         };
1736
1737                         in-ports {
1738                                 #address-cells = <1>;
1739                                 #size-cells = <0>;
1740
1741                                 port@0 {
1742                                         reg = <0>;
1743                                         merge_funnel_in0: endpoint {
1744                                                 remote-endpoint =
1745                                                   <&funnel0_out>;
1746                                         };
1747                                 };
1748
1749                                 port@1 {
1750                                         reg = <1>;
1751                                         merge_funnel_in1: endpoint {
1752                                                 remote-endpoint =
1753                                                   <&funnel1_out>;
1754                                         };
1755                                 };
1756                         };
1757                 };
1758
1759                 replicator1: replicator@6046000 {
1760                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1761                         reg = <0x06046000 0x1000>;
1762                         status = "disabled";
1763
1764                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1765                         clock-names = "apb_pclk", "atclk";
1766
1767                         out-ports {
1768                                 port {
1769                                         replicator_out: endpoint {
1770                                                 remote-endpoint = <&etr_in>;
1771                                         };
1772                                 };
1773                         };
1774
1775                         in-ports {
1776                                 port {
1777                                         replicator_in: endpoint {
1778                                                 remote-endpoint = <&etf_out>;
1779                                         };
1780                                 };
1781                         };
1782                 };
1783
1784                 etf: etf@6047000 {
1785                         compatible = "arm,coresight-tmc", "arm,primecell";
1786                         reg = <0x06047000 0x1000>;
1787                         status = "disabled";
1788
1789                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1790                         clock-names = "apb_pclk", "atclk";
1791
1792                         out-ports {
1793                                 port {
1794                                         etf_out: endpoint {
1795                                                 remote-endpoint =
1796                                                   <&replicator_in>;
1797                                         };
1798                                 };
1799                         };
1800
1801                         in-ports {
1802                                 port {
1803                                         etf_in: endpoint {
1804                                                 remote-endpoint =
1805                                                   <&merge_funnel_out>;
1806                                         };
1807                                 };
1808                         };
1809                 };
1810
1811                 etr: etr@6048000 {
1812                         compatible = "arm,coresight-tmc", "arm,primecell";
1813                         reg = <0x06048000 0x1000>;
1814                         status = "disabled";
1815
1816                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1817                         clock-names = "apb_pclk", "atclk";
1818                         arm,scatter-gather;
1819
1820                         in-ports {
1821                                 port {
1822                                         etr_in: endpoint {
1823                                                 remote-endpoint =
1824                                                   <&replicator_out>;
1825                                         };
1826                                 };
1827                         };
1828                 };
1829
1830                 etm1: etm@7840000 {
1831                         compatible = "arm,coresight-etm4x", "arm,primecell";
1832                         reg = <0x07840000 0x1000>;
1833                         status = "disabled";
1834
1835                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1836                         clock-names = "apb_pclk", "atclk";
1837
1838                         cpu = <&CPU0>;
1839
1840                         out-ports {
1841                                 port {
1842                                         etm0_out: endpoint {
1843                                                 remote-endpoint =
1844                                                   <&apss_funnel_in0>;
1845                                         };
1846                                 };
1847                         };
1848                 };
1849
1850                 etm2: etm@7940000 {
1851                         compatible = "arm,coresight-etm4x", "arm,primecell";
1852                         reg = <0x07940000 0x1000>;
1853                         status = "disabled";
1854
1855                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1856                         clock-names = "apb_pclk", "atclk";
1857
1858                         cpu = <&CPU1>;
1859
1860                         out-ports {
1861                                 port {
1862                                         etm1_out: endpoint {
1863                                                 remote-endpoint =
1864                                                   <&apss_funnel_in1>;
1865                                         };
1866                                 };
1867                         };
1868                 };
1869
1870                 etm3: etm@7a40000 {
1871                         compatible = "arm,coresight-etm4x", "arm,primecell";
1872                         reg = <0x07a40000 0x1000>;
1873                         status = "disabled";
1874
1875                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1876                         clock-names = "apb_pclk", "atclk";
1877
1878                         cpu = <&CPU2>;
1879
1880                         out-ports {
1881                                 port {
1882                                         etm2_out: endpoint {
1883                                                 remote-endpoint =
1884                                                   <&apss_funnel_in2>;
1885                                         };
1886                                 };
1887                         };
1888                 };
1889
1890                 etm4: etm@7b40000 {
1891                         compatible = "arm,coresight-etm4x", "arm,primecell";
1892                         reg = <0x07b40000 0x1000>;
1893                         status = "disabled";
1894
1895                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1896                         clock-names = "apb_pclk", "atclk";
1897
1898                         cpu = <&CPU3>;
1899
1900                         out-ports {
1901                                 port {
1902                                         etm3_out: endpoint {
1903                                                 remote-endpoint =
1904                                                   <&apss_funnel_in3>;
1905                                         };
1906                                 };
1907                         };
1908                 };
1909
1910                 funnel4: funnel@7b60000 { /* APSS Funnel */
1911                         compatible = "arm,coresight-etm4x", "arm,primecell";
1912                         reg = <0x07b60000 0x1000>;
1913                         status = "disabled";
1914
1915                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1916                         clock-names = "apb_pclk", "atclk";
1917
1918                         out-ports {
1919                                 port {
1920                                         apss_funnel_out: endpoint {
1921                                                 remote-endpoint =
1922                                                   <&apss_merge_funnel_in>;
1923                                         };
1924                                 };
1925                         };
1926
1927                         in-ports {
1928                                 #address-cells = <1>;
1929                                 #size-cells = <0>;
1930
1931                                 port@0 {
1932                                         reg = <0>;
1933                                         apss_funnel_in0: endpoint {
1934                                                 remote-endpoint =
1935                                                   <&etm0_out>;
1936                                         };
1937                                 };
1938
1939                                 port@1 {
1940                                         reg = <1>;
1941                                         apss_funnel_in1: endpoint {
1942                                                 remote-endpoint =
1943                                                   <&etm1_out>;
1944                                         };
1945                                 };
1946
1947                                 port@2 {
1948                                         reg = <2>;
1949                                         apss_funnel_in2: endpoint {
1950                                                 remote-endpoint =
1951                                                   <&etm2_out>;
1952                                         };
1953                                 };
1954
1955                                 port@3 {
1956                                         reg = <3>;
1957                                         apss_funnel_in3: endpoint {
1958                                                 remote-endpoint =
1959                                                   <&etm3_out>;
1960                                         };
1961                                 };
1962
1963                                 port@4 {
1964                                         reg = <4>;
1965                                         apss_funnel_in4: endpoint {
1966                                                 remote-endpoint =
1967                                                   <&etm4_out>;
1968                                         };
1969                                 };
1970
1971                                 port@5 {
1972                                         reg = <5>;
1973                                         apss_funnel_in5: endpoint {
1974                                                 remote-endpoint =
1975                                                   <&etm5_out>;
1976                                         };
1977                                 };
1978
1979                                 port@6 {
1980                                         reg = <6>;
1981                                         apss_funnel_in6: endpoint {
1982                                                 remote-endpoint =
1983                                                   <&etm6_out>;
1984                                         };
1985                                 };
1986
1987                                 port@7 {
1988                                         reg = <7>;
1989                                         apss_funnel_in7: endpoint {
1990                                                 remote-endpoint =
1991                                                   <&etm7_out>;
1992                                         };
1993                                 };
1994                         };
1995                 };
1996
1997                 funnel5: funnel@7b70000 {
1998                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1999                         reg = <0x07b70000 0x1000>;
2000                         status = "disabled";
2001
2002                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2003                         clock-names = "apb_pclk", "atclk";
2004
2005                         out-ports {
2006                                 port {
2007                                         apss_merge_funnel_out: endpoint {
2008                                                 remote-endpoint =
2009                                                   <&funnel1_in6>;
2010                                         };
2011                                 };
2012                         };
2013
2014                         in-ports {
2015                                 port {
2016                                         apss_merge_funnel_in: endpoint {
2017                                                 remote-endpoint =
2018                                                   <&apss_funnel_out>;
2019                                         };
2020                                 };
2021                         };
2022                 };
2023
2024                 etm5: etm@7c40000 {
2025                         compatible = "arm,coresight-etm4x", "arm,primecell";
2026                         reg = <0x07c40000 0x1000>;
2027                         status = "disabled";
2028
2029                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2030                         clock-names = "apb_pclk", "atclk";
2031
2032                         cpu = <&CPU4>;
2033
2034                         port {
2035                                 etm4_out: endpoint {
2036                                         remote-endpoint = <&apss_funnel_in4>;
2037                                 };
2038                         };
2039                 };
2040
2041                 etm6: etm@7d40000 {
2042                         compatible = "arm,coresight-etm4x", "arm,primecell";
2043                         reg = <0x07d40000 0x1000>;
2044                         status = "disabled";
2045
2046                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2047                         clock-names = "apb_pclk", "atclk";
2048
2049                         cpu = <&CPU5>;
2050
2051                         port {
2052                                 etm5_out: endpoint {
2053                                         remote-endpoint = <&apss_funnel_in5>;
2054                                 };
2055                         };
2056                 };
2057
2058                 etm7: etm@7e40000 {
2059                         compatible = "arm,coresight-etm4x", "arm,primecell";
2060                         reg = <0x07e40000 0x1000>;
2061                         status = "disabled";
2062
2063                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2064                         clock-names = "apb_pclk", "atclk";
2065
2066                         cpu = <&CPU6>;
2067
2068                         port {
2069                                 etm6_out: endpoint {
2070                                         remote-endpoint = <&apss_funnel_in6>;
2071                                 };
2072                         };
2073                 };
2074
2075                 etm8: etm@7f40000 {
2076                         compatible = "arm,coresight-etm4x", "arm,primecell";
2077                         reg = <0x07f40000 0x1000>;
2078                         status = "disabled";
2079
2080                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2081                         clock-names = "apb_pclk", "atclk";
2082
2083                         cpu = <&CPU7>;
2084
2085                         port {
2086                                 etm7_out: endpoint {
2087                                         remote-endpoint = <&apss_funnel_in7>;
2088                                 };
2089                         };
2090                 };
2091
2092                 sram@290000 {
2093                         compatible = "qcom,rpm-stats";
2094                         reg = <0x00290000 0x10000>;
2095                 };
2096
2097                 spmi_bus: spmi@800f000 {
2098                         compatible = "qcom,spmi-pmic-arb";
2099                         reg = <0x0800f000 0x1000>,
2100                               <0x08400000 0x1000000>,
2101                               <0x09400000 0x1000000>,
2102                               <0x0a400000 0x220000>,
2103                               <0x0800a000 0x3000>;
2104                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2105                         interrupt-names = "periph_irq";
2106                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2107                         qcom,ee = <0>;
2108                         qcom,channel = <0>;
2109                         #address-cells = <2>;
2110                         #size-cells = <0>;
2111                         interrupt-controller;
2112                         #interrupt-cells = <4>;
2113                 };
2114
2115                 usb3: usb@a8f8800 {
2116                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2117                         reg = <0x0a8f8800 0x400>;
2118                         status = "disabled";
2119                         #address-cells = <1>;
2120                         #size-cells = <1>;
2121                         ranges;
2122
2123                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2124                                  <&gcc GCC_USB30_MASTER_CLK>,
2125                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2126                                  <&gcc GCC_USB30_SLEEP_CLK>,
2127                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2128                         clock-names = "cfg_noc",
2129                                       "core",
2130                                       "iface",
2131                                       "sleep",
2132                                       "mock_utmi";
2133
2134                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2135                                           <&gcc GCC_USB30_MASTER_CLK>;
2136                         assigned-clock-rates = <19200000>, <120000000>;
2137
2138                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2139                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2140                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2141
2142                         power-domains = <&gcc USB_30_GDSC>;
2143
2144                         resets = <&gcc GCC_USB_30_BCR>;
2145
2146                         usb3_dwc3: usb@a800000 {
2147                                 compatible = "snps,dwc3";
2148                                 reg = <0x0a800000 0xcd00>;
2149                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2150                                 snps,dis_u2_susphy_quirk;
2151                                 snps,dis_enblslpm_quirk;
2152                                 phys = <&qusb2phy>, <&usb1_ssphy>;
2153                                 phy-names = "usb2-phy", "usb3-phy";
2154                                 snps,has-lpm-erratum;
2155                                 snps,hird-threshold = /bits/ 8 <0x10>;
2156                         };
2157                 };
2158
2159                 usb3phy: phy@c010000 {
2160                         compatible = "qcom,msm8998-qmp-usb3-phy";
2161                         reg = <0x0c010000 0x18c>;
2162                         status = "disabled";
2163                         #address-cells = <1>;
2164                         #size-cells = <1>;
2165                         ranges;
2166
2167                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2168                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2169                                  <&gcc GCC_USB3_CLKREF_CLK>;
2170                         clock-names = "aux", "cfg_ahb", "ref";
2171
2172                         resets = <&gcc GCC_USB3_PHY_BCR>,
2173                                  <&gcc GCC_USB3PHY_PHY_BCR>;
2174                         reset-names = "phy", "common";
2175
2176                         usb1_ssphy: phy@c010200 {
2177                                 reg = <0xc010200 0x128>,
2178                                       <0xc010400 0x200>,
2179                                       <0xc010c00 0x20c>,
2180                                       <0xc010600 0x128>,
2181                                       <0xc010800 0x200>;
2182                                 #phy-cells = <0>;
2183                                 #clock-cells = <0>;
2184                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2185                                 clock-names = "pipe0";
2186                                 clock-output-names = "usb3_phy_pipe_clk_src";
2187                         };
2188                 };
2189
2190                 qusb2phy: phy@c012000 {
2191                         compatible = "qcom,msm8998-qusb2-phy";
2192                         reg = <0x0c012000 0x2a8>;
2193                         status = "disabled";
2194                         #phy-cells = <0>;
2195
2196                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2197                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2198                         clock-names = "cfg_ahb", "ref";
2199
2200                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2201
2202                         nvmem-cells = <&qusb2_hstx_trim>;
2203                 };
2204
2205                 sdhc2: mmc@c0a4900 {
2206                         compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2207                         reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2208                         reg-names = "hc", "core";
2209
2210                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2211                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2212                         interrupt-names = "hc_irq", "pwr_irq";
2213
2214                         clock-names = "iface", "core", "xo";
2215                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2216                                  <&gcc GCC_SDCC2_APPS_CLK>,
2217                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
2218                         bus-width = <4>;
2219                         status = "disabled";
2220                 };
2221
2222                 blsp1_dma: dma-controller@c144000 {
2223                         compatible = "qcom,bam-v1.7.0";
2224                         reg = <0x0c144000 0x25000>;
2225                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2226                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2227                         clock-names = "bam_clk";
2228                         #dma-cells = <1>;
2229                         qcom,ee = <0>;
2230                         qcom,controlled-remotely;
2231                         num-channels = <18>;
2232                         qcom,num-ees = <4>;
2233                 };
2234
2235                 blsp1_uart3: serial@c171000 {
2236                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2237                         reg = <0x0c171000 0x1000>;
2238                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2239                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2240                                  <&gcc GCC_BLSP1_AHB_CLK>;
2241                         clock-names = "core", "iface";
2242                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2243                         dma-names = "tx", "rx";
2244                         pinctrl-names = "default";
2245                         pinctrl-0 = <&blsp1_uart3_on>;
2246                         status = "disabled";
2247                 };
2248
2249                 blsp1_i2c1: i2c@c175000 {
2250                         compatible = "qcom,i2c-qup-v2.2.1";
2251                         reg = <0x0c175000 0x600>;
2252                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2253
2254                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2255                                  <&gcc GCC_BLSP1_AHB_CLK>;
2256                         clock-names = "core", "iface";
2257                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2258                         dma-names = "tx", "rx";
2259                         pinctrl-names = "default", "sleep";
2260                         pinctrl-0 = <&blsp1_i2c1_default>;
2261                         pinctrl-1 = <&blsp1_i2c1_sleep>;
2262                         clock-frequency = <400000>;
2263
2264                         status = "disabled";
2265                         #address-cells = <1>;
2266                         #size-cells = <0>;
2267                 };
2268
2269                 blsp1_i2c2: i2c@c176000 {
2270                         compatible = "qcom,i2c-qup-v2.2.1";
2271                         reg = <0x0c176000 0x600>;
2272                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2273
2274                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2275                                  <&gcc GCC_BLSP1_AHB_CLK>;
2276                         clock-names = "core", "iface";
2277                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2278                         dma-names = "tx", "rx";
2279                         pinctrl-names = "default", "sleep";
2280                         pinctrl-0 = <&blsp1_i2c2_default>;
2281                         pinctrl-1 = <&blsp1_i2c2_sleep>;
2282                         clock-frequency = <400000>;
2283
2284                         status = "disabled";
2285                         #address-cells = <1>;
2286                         #size-cells = <0>;
2287                 };
2288
2289                 blsp1_i2c3: i2c@c177000 {
2290                         compatible = "qcom,i2c-qup-v2.2.1";
2291                         reg = <0x0c177000 0x600>;
2292                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2293
2294                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2295                                  <&gcc GCC_BLSP1_AHB_CLK>;
2296                         clock-names = "core", "iface";
2297                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2298                         dma-names = "tx", "rx";
2299                         pinctrl-names = "default", "sleep";
2300                         pinctrl-0 = <&blsp1_i2c3_default>;
2301                         pinctrl-1 = <&blsp1_i2c3_sleep>;
2302                         clock-frequency = <400000>;
2303
2304                         status = "disabled";
2305                         #address-cells = <1>;
2306                         #size-cells = <0>;
2307                 };
2308
2309                 blsp1_i2c4: i2c@c178000 {
2310                         compatible = "qcom,i2c-qup-v2.2.1";
2311                         reg = <0x0c178000 0x600>;
2312                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2313
2314                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2315                                  <&gcc GCC_BLSP1_AHB_CLK>;
2316                         clock-names = "core", "iface";
2317                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2318                         dma-names = "tx", "rx";
2319                         pinctrl-names = "default", "sleep";
2320                         pinctrl-0 = <&blsp1_i2c4_default>;
2321                         pinctrl-1 = <&blsp1_i2c4_sleep>;
2322                         clock-frequency = <400000>;
2323
2324                         status = "disabled";
2325                         #address-cells = <1>;
2326                         #size-cells = <0>;
2327                 };
2328
2329                 blsp1_i2c5: i2c@c179000 {
2330                         compatible = "qcom,i2c-qup-v2.2.1";
2331                         reg = <0x0c179000 0x600>;
2332                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2333
2334                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2335                                  <&gcc GCC_BLSP1_AHB_CLK>;
2336                         clock-names = "core", "iface";
2337                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2338                         dma-names = "tx", "rx";
2339                         pinctrl-names = "default", "sleep";
2340                         pinctrl-0 = <&blsp1_i2c5_default>;
2341                         pinctrl-1 = <&blsp1_i2c5_sleep>;
2342                         clock-frequency = <400000>;
2343
2344                         status = "disabled";
2345                         #address-cells = <1>;
2346                         #size-cells = <0>;
2347                 };
2348
2349                 blsp1_i2c6: i2c@c17a000 {
2350                         compatible = "qcom,i2c-qup-v2.2.1";
2351                         reg = <0x0c17a000 0x600>;
2352                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2353
2354                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2355                                  <&gcc GCC_BLSP1_AHB_CLK>;
2356                         clock-names = "core", "iface";
2357                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2358                         dma-names = "tx", "rx";
2359                         pinctrl-names = "default", "sleep";
2360                         pinctrl-0 = <&blsp1_i2c6_default>;
2361                         pinctrl-1 = <&blsp1_i2c6_sleep>;
2362                         clock-frequency = <400000>;
2363
2364                         status = "disabled";
2365                         #address-cells = <1>;
2366                         #size-cells = <0>;
2367                 };
2368
2369                 blsp1_spi1: spi@c175000 {
2370                         compatible = "qcom,spi-qup-v2.2.1";
2371                         reg = <0x0c175000 0x600>;
2372                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2373
2374                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2375                                  <&gcc GCC_BLSP1_AHB_CLK>;
2376                         clock-names = "core", "iface";
2377                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2378                         dma-names = "tx", "rx";
2379                         pinctrl-names = "default";
2380                         pinctrl-0 = <&blsp1_spi1_default>;
2381
2382                         status = "disabled";
2383                         #address-cells = <1>;
2384                         #size-cells = <0>;
2385                 };
2386
2387                 blsp1_spi2: spi@c176000 {
2388                         compatible = "qcom,spi-qup-v2.2.1";
2389                         reg = <0x0c176000 0x600>;
2390                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2391
2392                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2393                                  <&gcc GCC_BLSP1_AHB_CLK>;
2394                         clock-names = "core", "iface";
2395                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2396                         dma-names = "tx", "rx";
2397                         pinctrl-names = "default";
2398                         pinctrl-0 = <&blsp1_spi2_default>;
2399
2400                         status = "disabled";
2401                         #address-cells = <1>;
2402                         #size-cells = <0>;
2403                 };
2404
2405                 blsp1_spi3: spi@c177000 {
2406                         compatible = "qcom,spi-qup-v2.2.1";
2407                         reg = <0x0c177000 0x600>;
2408                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2409
2410                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2411                                  <&gcc GCC_BLSP1_AHB_CLK>;
2412                         clock-names = "core", "iface";
2413                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2414                         dma-names = "tx", "rx";
2415                         pinctrl-names = "default";
2416                         pinctrl-0 = <&blsp1_spi3_default>;
2417
2418                         status = "disabled";
2419                         #address-cells = <1>;
2420                         #size-cells = <0>;
2421                 };
2422
2423                 blsp1_spi4: spi@c178000 {
2424                         compatible = "qcom,spi-qup-v2.2.1";
2425                         reg = <0x0c178000 0x600>;
2426                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2427
2428                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2429                                  <&gcc GCC_BLSP1_AHB_CLK>;
2430                         clock-names = "core", "iface";
2431                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2432                         dma-names = "tx", "rx";
2433                         pinctrl-names = "default";
2434                         pinctrl-0 = <&blsp1_spi4_default>;
2435
2436                         status = "disabled";
2437                         #address-cells = <1>;
2438                         #size-cells = <0>;
2439                 };
2440
2441                 blsp1_spi5: spi@c179000 {
2442                         compatible = "qcom,spi-qup-v2.2.1";
2443                         reg = <0x0c179000 0x600>;
2444                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2445
2446                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2447                                  <&gcc GCC_BLSP1_AHB_CLK>;
2448                         clock-names = "core", "iface";
2449                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2450                         dma-names = "tx", "rx";
2451                         pinctrl-names = "default";
2452                         pinctrl-0 = <&blsp1_spi5_default>;
2453
2454                         status = "disabled";
2455                         #address-cells = <1>;
2456                         #size-cells = <0>;
2457                 };
2458
2459                 blsp1_spi6: spi@c17a000 {
2460                         compatible = "qcom,spi-qup-v2.2.1";
2461                         reg = <0x0c17a000 0x600>;
2462                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2463
2464                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2465                                  <&gcc GCC_BLSP1_AHB_CLK>;
2466                         clock-names = "core", "iface";
2467                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2468                         dma-names = "tx", "rx";
2469                         pinctrl-names = "default";
2470                         pinctrl-0 = <&blsp1_spi6_default>;
2471
2472                         status = "disabled";
2473                         #address-cells = <1>;
2474                         #size-cells = <0>;
2475                 };
2476
2477                 blsp2_dma: dma-controller@c184000 {
2478                         compatible = "qcom,bam-v1.7.0";
2479                         reg = <0x0c184000 0x25000>;
2480                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2481                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2482                         clock-names = "bam_clk";
2483                         #dma-cells = <1>;
2484                         qcom,ee = <0>;
2485                         qcom,controlled-remotely;
2486                         num-channels = <18>;
2487                         qcom,num-ees = <4>;
2488                 };
2489
2490                 blsp2_uart1: serial@c1b0000 {
2491                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2492                         reg = <0x0c1b0000 0x1000>;
2493                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2494                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2495                                  <&gcc GCC_BLSP2_AHB_CLK>;
2496                         clock-names = "core", "iface";
2497                         status = "disabled";
2498                 };
2499
2500                 blsp2_i2c1: i2c@c1b5000 {
2501                         compatible = "qcom,i2c-qup-v2.2.1";
2502                         reg = <0x0c1b5000 0x600>;
2503                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2504
2505                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2506                                  <&gcc GCC_BLSP2_AHB_CLK>;
2507                         clock-names = "core", "iface";
2508                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2509                         dma-names = "tx", "rx";
2510                         pinctrl-names = "default", "sleep";
2511                         pinctrl-0 = <&blsp2_i2c1_default>;
2512                         pinctrl-1 = <&blsp2_i2c1_sleep>;
2513                         clock-frequency = <400000>;
2514
2515                         status = "disabled";
2516                         #address-cells = <1>;
2517                         #size-cells = <0>;
2518                 };
2519
2520                 blsp2_i2c2: i2c@c1b6000 {
2521                         compatible = "qcom,i2c-qup-v2.2.1";
2522                         reg = <0x0c1b6000 0x600>;
2523                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2524
2525                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2526                                  <&gcc GCC_BLSP2_AHB_CLK>;
2527                         clock-names = "core", "iface";
2528                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2529                         dma-names = "tx", "rx";
2530                         pinctrl-names = "default", "sleep";
2531                         pinctrl-0 = <&blsp2_i2c2_default>;
2532                         pinctrl-1 = <&blsp2_i2c2_sleep>;
2533                         clock-frequency = <400000>;
2534
2535                         status = "disabled";
2536                         #address-cells = <1>;
2537                         #size-cells = <0>;
2538                 };
2539
2540                 blsp2_i2c3: i2c@c1b7000 {
2541                         compatible = "qcom,i2c-qup-v2.2.1";
2542                         reg = <0x0c1b7000 0x600>;
2543                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2544
2545                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2546                                  <&gcc GCC_BLSP2_AHB_CLK>;
2547                         clock-names = "core", "iface";
2548                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2549                         dma-names = "tx", "rx";
2550                         pinctrl-names = "default", "sleep";
2551                         pinctrl-0 = <&blsp2_i2c3_default>;
2552                         pinctrl-1 = <&blsp2_i2c3_sleep>;
2553                         clock-frequency = <400000>;
2554
2555                         status = "disabled";
2556                         #address-cells = <1>;
2557                         #size-cells = <0>;
2558                 };
2559
2560                 blsp2_i2c4: i2c@c1b8000 {
2561                         compatible = "qcom,i2c-qup-v2.2.1";
2562                         reg = <0x0c1b8000 0x600>;
2563                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2564
2565                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2566                                  <&gcc GCC_BLSP2_AHB_CLK>;
2567                         clock-names = "core", "iface";
2568                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2569                         dma-names = "tx", "rx";
2570                         pinctrl-names = "default", "sleep";
2571                         pinctrl-0 = <&blsp2_i2c4_default>;
2572                         pinctrl-1 = <&blsp2_i2c4_sleep>;
2573                         clock-frequency = <400000>;
2574
2575                         status = "disabled";
2576                         #address-cells = <1>;
2577                         #size-cells = <0>;
2578                 };
2579
2580                 blsp2_i2c5: i2c@c1b9000 {
2581                         compatible = "qcom,i2c-qup-v2.2.1";
2582                         reg = <0x0c1b9000 0x600>;
2583                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2584
2585                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2586                                  <&gcc GCC_BLSP2_AHB_CLK>;
2587                         clock-names = "core", "iface";
2588                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2589                         dma-names = "tx", "rx";
2590                         pinctrl-names = "default", "sleep";
2591                         pinctrl-0 = <&blsp2_i2c5_default>;
2592                         pinctrl-1 = <&blsp2_i2c5_sleep>;
2593                         clock-frequency = <400000>;
2594
2595                         status = "disabled";
2596                         #address-cells = <1>;
2597                         #size-cells = <0>;
2598                 };
2599
2600                 blsp2_i2c6: i2c@c1ba000 {
2601                         compatible = "qcom,i2c-qup-v2.2.1";
2602                         reg = <0x0c1ba000 0x600>;
2603                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2604
2605                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2606                                  <&gcc GCC_BLSP2_AHB_CLK>;
2607                         clock-names = "core", "iface";
2608                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2609                         dma-names = "tx", "rx";
2610                         pinctrl-names = "default", "sleep";
2611                         pinctrl-0 = <&blsp2_i2c6_default>;
2612                         pinctrl-1 = <&blsp2_i2c6_sleep>;
2613                         clock-frequency = <400000>;
2614
2615                         status = "disabled";
2616                         #address-cells = <1>;
2617                         #size-cells = <0>;
2618                 };
2619
2620                 blsp2_spi1: spi@c1b5000 {
2621                         compatible = "qcom,spi-qup-v2.2.1";
2622                         reg = <0x0c1b5000 0x600>;
2623                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2624
2625                         clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2626                                  <&gcc GCC_BLSP2_AHB_CLK>;
2627                         clock-names = "core", "iface";
2628                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2629                         dma-names = "tx", "rx";
2630                         pinctrl-names = "default";
2631                         pinctrl-0 = <&blsp2_spi1_default>;
2632
2633                         status = "disabled";
2634                         #address-cells = <1>;
2635                         #size-cells = <0>;
2636                 };
2637
2638                 blsp2_spi2: spi@c1b6000 {
2639                         compatible = "qcom,spi-qup-v2.2.1";
2640                         reg = <0x0c1b6000 0x600>;
2641                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2642
2643                         clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2644                                  <&gcc GCC_BLSP2_AHB_CLK>;
2645                         clock-names = "core", "iface";
2646                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2647                         dma-names = "tx", "rx";
2648                         pinctrl-names = "default";
2649                         pinctrl-0 = <&blsp2_spi2_default>;
2650
2651                         status = "disabled";
2652                         #address-cells = <1>;
2653                         #size-cells = <0>;
2654                 };
2655
2656                 blsp2_spi3: spi@c1b7000 {
2657                         compatible = "qcom,spi-qup-v2.2.1";
2658                         reg = <0x0c1b7000 0x600>;
2659                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2660
2661                         clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2662                                  <&gcc GCC_BLSP2_AHB_CLK>;
2663                         clock-names = "core", "iface";
2664                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2665                         dma-names = "tx", "rx";
2666                         pinctrl-names = "default";
2667                         pinctrl-0 = <&blsp2_spi3_default>;
2668
2669                         status = "disabled";
2670                         #address-cells = <1>;
2671                         #size-cells = <0>;
2672                 };
2673
2674                 blsp2_spi4: spi@c1b8000 {
2675                         compatible = "qcom,spi-qup-v2.2.1";
2676                         reg = <0x0c1b8000 0x600>;
2677                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2678
2679                         clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2680                                  <&gcc GCC_BLSP2_AHB_CLK>;
2681                         clock-names = "core", "iface";
2682                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2683                         dma-names = "tx", "rx";
2684                         pinctrl-names = "default";
2685                         pinctrl-0 = <&blsp2_spi4_default>;
2686
2687                         status = "disabled";
2688                         #address-cells = <1>;
2689                         #size-cells = <0>;
2690                 };
2691
2692                 blsp2_spi5: spi@c1b9000 {
2693                         compatible = "qcom,spi-qup-v2.2.1";
2694                         reg = <0x0c1b9000 0x600>;
2695                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2696
2697                         clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2698                                  <&gcc GCC_BLSP2_AHB_CLK>;
2699                         clock-names = "core", "iface";
2700                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2701                         dma-names = "tx", "rx";
2702                         pinctrl-names = "default";
2703                         pinctrl-0 = <&blsp2_spi5_default>;
2704
2705                         status = "disabled";
2706                         #address-cells = <1>;
2707                         #size-cells = <0>;
2708                 };
2709
2710                 blsp2_spi6: spi@c1ba000 {
2711                         compatible = "qcom,spi-qup-v2.2.1";
2712                         reg = <0x0c1ba000 0x600>;
2713                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2714
2715                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2716                                  <&gcc GCC_BLSP2_AHB_CLK>;
2717                         clock-names = "core", "iface";
2718                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2719                         dma-names = "tx", "rx";
2720                         pinctrl-names = "default";
2721                         pinctrl-0 = <&blsp2_spi6_default>;
2722
2723                         status = "disabled";
2724                         #address-cells = <1>;
2725                         #size-cells = <0>;
2726                 };
2727
2728                 mmcc: clock-controller@c8c0000 {
2729                         compatible = "qcom,mmcc-msm8998";
2730                         #clock-cells = <1>;
2731                         #reset-cells = <1>;
2732                         #power-domain-cells = <1>;
2733                         reg = <0xc8c0000 0x40000>;
2734
2735                         clock-names = "xo",
2736                                       "gpll0",
2737                                       "dsi0dsi",
2738                                       "dsi0byte",
2739                                       "dsi1dsi",
2740                                       "dsi1byte",
2741                                       "hdmipll",
2742                                       "dplink",
2743                                       "dpvco",
2744                                       "gpll0_div";
2745                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2746                                  <&gcc GCC_MMSS_GPLL0_CLK>,
2747                                  <&mdss_dsi0_phy 1>,
2748                                  <&mdss_dsi0_phy 0>,
2749                                  <&mdss_dsi1_phy 1>,
2750                                  <&mdss_dsi1_phy 0>,
2751                                  <0>,
2752                                  <0>,
2753                                  <0>,
2754                                  <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2755                 };
2756
2757                 mdss: display-subsystem@c900000 {
2758                         compatible = "qcom,msm8998-mdss";
2759                         reg = <0x0c900000 0x1000>;
2760                         reg-names = "mdss";
2761
2762                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2763                         interrupt-controller;
2764                         #interrupt-cells = <1>;
2765
2766                         clocks = <&mmcc MDSS_AHB_CLK>,
2767                                  <&mmcc MDSS_AXI_CLK>,
2768                                  <&mmcc MDSS_MDP_CLK>;
2769                         clock-names = "iface",
2770                                       "bus",
2771                                       "core";
2772
2773                         power-domains = <&mmcc MDSS_GDSC>;
2774                         iommus = <&mmss_smmu 0>;
2775
2776                         #address-cells = <1>;
2777                         #size-cells = <1>;
2778                         ranges;
2779
2780                         status = "disabled";
2781
2782                         mdss_mdp: display-controller@c901000 {
2783                                 compatible = "qcom,msm8998-dpu";
2784                                 reg = <0x0c901000 0x8f000>,
2785                                       <0x0c9a8e00 0xf0>,
2786                                       <0x0c9b0000 0x2008>,
2787                                       <0x0c9b8000 0x1040>;
2788                                 reg-names = "mdp",
2789                                             "regdma",
2790                                             "vbif",
2791                                             "vbif_nrt";
2792
2793                                 interrupt-parent = <&mdss>;
2794                                 interrupts = <0>;
2795
2796                                 clocks = <&mmcc MDSS_AHB_CLK>,
2797                                          <&mmcc MDSS_AXI_CLK>,
2798                                          <&mmcc MNOC_AHB_CLK>,
2799                                          <&mmcc MDSS_MDP_CLK>,
2800                                          <&mmcc MDSS_VSYNC_CLK>;
2801                                 clock-names = "iface",
2802                                               "bus",
2803                                               "mnoc",
2804                                               "core",
2805                                               "vsync";
2806
2807                                 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2808                                 assigned-clock-rates = <19200000>;
2809
2810                                 operating-points-v2 = <&mdp_opp_table>;
2811                                 power-domains = <&rpmpd MSM8998_VDDMX>;
2812
2813                                 mdp_opp_table: opp-table {
2814                                         compatible = "operating-points-v2";
2815
2816                                         opp-171430000 {
2817                                                 opp-hz = /bits/ 64 <171430000>;
2818                                                 required-opps = <&rpmpd_opp_low_svs>;
2819                                         };
2820
2821                                         opp-275000000 {
2822                                                 opp-hz = /bits/ 64 <275000000>;
2823                                                 required-opps = <&rpmpd_opp_svs>;
2824                                         };
2825
2826                                         opp-330000000 {
2827                                                 opp-hz = /bits/ 64 <330000000>;
2828                                                 required-opps = <&rpmpd_opp_nom>;
2829                                         };
2830
2831                                         opp-412500000 {
2832                                                 opp-hz = /bits/ 64 <412500000>;
2833                                                 required-opps = <&rpmpd_opp_turbo>;
2834                                         };
2835                                 };
2836
2837                                 ports {
2838                                         #address-cells = <1>;
2839                                         #size-cells = <0>;
2840
2841                                         port@0 {
2842                                                 reg = <0>;
2843
2844                                                 dpu_intf1_out: endpoint {
2845                                                         remote-endpoint = <&mdss_dsi0_in>;
2846                                                 };
2847                                         };
2848
2849                                         port@1 {
2850                                                 reg = <1>;
2851
2852                                                 dpu_intf2_out: endpoint {
2853                                                         remote-endpoint = <&mdss_dsi1_in>;
2854                                                 };
2855                                         };
2856                                 };
2857                         };
2858
2859                         mdss_dsi0: dsi@c994000 {
2860                                 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2861                                 reg = <0x0c994000 0x400>;
2862                                 reg-names = "dsi_ctrl";
2863
2864                                 interrupt-parent = <&mdss>;
2865                                 interrupts = <4>;
2866
2867                                 clocks = <&mmcc MDSS_BYTE0_CLK>,
2868                                          <&mmcc MDSS_BYTE0_INTF_CLK>,
2869                                          <&mmcc MDSS_PCLK0_CLK>,
2870                                          <&mmcc MDSS_ESC0_CLK>,
2871                                          <&mmcc MDSS_AHB_CLK>,
2872                                          <&mmcc MDSS_AXI_CLK>;
2873                                 clock-names = "byte",
2874                                               "byte_intf",
2875                                               "pixel",
2876                                               "core",
2877                                               "iface",
2878                                               "bus";
2879                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2880                                                   <&mmcc PCLK0_CLK_SRC>;
2881                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2882                                                          <&mdss_dsi0_phy 1>;
2883
2884                                 operating-points-v2 = <&dsi_opp_table>;
2885                                 power-domains = <&rpmpd MSM8998_VDDCX>;
2886
2887                                 phys = <&mdss_dsi0_phy>;
2888                                 phy-names = "dsi";
2889
2890                                 #address-cells = <1>;
2891                                 #size-cells = <0>;
2892
2893                                 status = "disabled";
2894
2895                                 ports {
2896                                         #address-cells = <1>;
2897                                         #size-cells = <0>;
2898
2899                                         port@0 {
2900                                                 reg = <0>;
2901
2902                                                 mdss_dsi0_in: endpoint {
2903                                                         remote-endpoint = <&dpu_intf1_out>;
2904                                                 };
2905                                         };
2906
2907                                         port@1 {
2908                                                 reg = <1>;
2909
2910                                                 mdss_dsi0_out: endpoint {
2911                                                 };
2912                                         };
2913                                 };
2914                         };
2915
2916                         mdss_dsi0_phy: phy@c994400 {
2917                                 compatible = "qcom,dsi-phy-10nm-8998";
2918                                 reg = <0x0c994400 0x200>,
2919                                       <0x0c994600 0x280>,
2920                                       <0x0c994a00 0x1e0>;
2921                                 reg-names = "dsi_phy",
2922                                             "dsi_phy_lane",
2923                                             "dsi_pll";
2924
2925                                 clocks = <&mmcc MDSS_AHB_CLK>,
2926                                          <&rpmcc RPM_SMD_XO_CLK_SRC>;
2927                                 clock-names = "iface", "ref";
2928
2929                                 #clock-cells = <1>;
2930                                 #phy-cells = <0>;
2931
2932                                 status = "disabled";
2933                         };
2934
2935                         mdss_dsi1: dsi@c996000 {
2936                                 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2937                                 reg = <0x0c996000 0x400>;
2938                                 reg-names = "dsi_ctrl";
2939
2940                                 interrupt-parent = <&mdss>;
2941                                 interrupts = <5>;
2942
2943                                 clocks = <&mmcc MDSS_BYTE1_CLK>,
2944                                          <&mmcc MDSS_BYTE1_INTF_CLK>,
2945                                          <&mmcc MDSS_PCLK1_CLK>,
2946                                          <&mmcc MDSS_ESC1_CLK>,
2947                                          <&mmcc MDSS_AHB_CLK>,
2948                                          <&mmcc MDSS_AXI_CLK>;
2949                                 clock-names = "byte",
2950                                               "byte_intf",
2951                                               "pixel",
2952                                               "core",
2953                                               "iface",
2954                                               "bus";
2955                                 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2956                                                   <&mmcc PCLK1_CLK_SRC>;
2957                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2958                                                          <&mdss_dsi1_phy 1>;
2959
2960                                 operating-points-v2 = <&dsi_opp_table>;
2961                                 power-domains = <&rpmpd MSM8998_VDDCX>;
2962
2963                                 phys = <&mdss_dsi1_phy>;
2964                                 phy-names = "dsi";
2965
2966                                 #address-cells = <1>;
2967                                 #size-cells = <0>;
2968
2969                                 status = "disabled";
2970
2971                                 ports {
2972                                         #address-cells = <1>;
2973                                         #size-cells = <0>;
2974
2975                                         port@0 {
2976                                                 reg = <0>;
2977
2978                                                 mdss_dsi1_in: endpoint {
2979                                                         remote-endpoint = <&dpu_intf2_out>;
2980                                                 };
2981                                         };
2982
2983                                         port@1 {
2984                                                 reg = <1>;
2985
2986                                                 mdss_dsi1_out: endpoint {
2987                                                 };
2988                                         };
2989                                 };
2990                         };
2991
2992                         mdss_dsi1_phy: phy@c996400 {
2993                                 compatible = "qcom,dsi-phy-10nm-8998";
2994                                 reg = <0x0c996400 0x200>,
2995                                       <0x0c996600 0x280>,
2996                                       <0x0c996a00 0x10e>;
2997                                 reg-names = "dsi_phy",
2998                                             "dsi_phy_lane",
2999                                             "dsi_pll";
3000
3001                                 clocks = <&mmcc MDSS_AHB_CLK>,
3002                                          <&rpmcc RPM_SMD_XO_CLK_SRC>;
3003                                 clock-names = "iface",
3004                                               "ref";
3005
3006                                 #clock-cells = <1>;
3007                                 #phy-cells = <0>;
3008
3009                                 status = "disabled";
3010                         };
3011                 };
3012
3013                 mmss_smmu: iommu@cd00000 {
3014                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3015                         reg = <0x0cd00000 0x40000>;
3016                         #iommu-cells = <1>;
3017
3018                         clocks = <&mmcc MNOC_AHB_CLK>,
3019                                  <&mmcc BIMC_SMMU_AHB_CLK>,
3020                                  <&mmcc BIMC_SMMU_AXI_CLK>;
3021                         clock-names = "iface-mm",
3022                                       "iface-smmu",
3023                                       "bus-smmu";
3024
3025                         #global-interrupts = <0>;
3026                         interrupts =
3027                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3028                                 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3029                                 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3030                                 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3031                                 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3032                                 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3033                                 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3034                                 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3035                                 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3036                                 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3037                                 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3038                                 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3039                                 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3040                                 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3041                                 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3042                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3043                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3044                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3045                                 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3046                                 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3047
3048                         power-domains = <&mmcc BIMC_SMMU_GDSC>;
3049                 };
3050
3051                 remoteproc_adsp: remoteproc@17300000 {
3052                         compatible = "qcom,msm8998-adsp-pas";
3053                         reg = <0x17300000 0x4040>;
3054
3055                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3056                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3057                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3058                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3059                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3060                         interrupt-names = "wdog", "fatal", "ready",
3061                                           "handover", "stop-ack";
3062
3063                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3064                         clock-names = "xo";
3065
3066                         memory-region = <&adsp_mem>;
3067
3068                         qcom,smem-states = <&adsp_smp2p_out 0>;
3069                         qcom,smem-state-names = "stop";
3070
3071                         power-domains = <&rpmpd MSM8998_VDDCX>;
3072                         power-domain-names = "cx";
3073
3074                         status = "disabled";
3075
3076                         glink-edge {
3077                                 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3078                                 label = "lpass";
3079                                 qcom,remote-pid = <2>;
3080                                 mboxes = <&apcs_glb 9>;
3081                         };
3082                 };
3083
3084                 apcs_glb: mailbox@17911000 {
3085                         compatible = "qcom,msm8998-apcs-hmss-global",
3086                                      "qcom,msm8994-apcs-kpss-global";
3087                         reg = <0x17911000 0x1000>;
3088
3089                         #mbox-cells = <1>;
3090                 };
3091
3092                 timer@17920000 {
3093                         #address-cells = <1>;
3094                         #size-cells = <1>;
3095                         ranges;
3096                         compatible = "arm,armv7-timer-mem";
3097                         reg = <0x17920000 0x1000>;
3098
3099                         frame@17921000 {
3100                                 frame-number = <0>;
3101                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3102                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3103                                 reg = <0x17921000 0x1000>,
3104                                       <0x17922000 0x1000>;
3105                         };
3106
3107                         frame@17923000 {
3108                                 frame-number = <1>;
3109                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3110                                 reg = <0x17923000 0x1000>;
3111                                 status = "disabled";
3112                         };
3113
3114                         frame@17924000 {
3115                                 frame-number = <2>;
3116                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3117                                 reg = <0x17924000 0x1000>;
3118                                 status = "disabled";
3119                         };
3120
3121                         frame@17925000 {
3122                                 frame-number = <3>;
3123                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3124                                 reg = <0x17925000 0x1000>;
3125                                 status = "disabled";
3126                         };
3127
3128                         frame@17926000 {
3129                                 frame-number = <4>;
3130                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3131                                 reg = <0x17926000 0x1000>;
3132                                 status = "disabled";
3133                         };
3134
3135                         frame@17927000 {
3136                                 frame-number = <5>;
3137                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3138                                 reg = <0x17927000 0x1000>;
3139                                 status = "disabled";
3140                         };
3141
3142                         frame@17928000 {
3143                                 frame-number = <6>;
3144                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3145                                 reg = <0x17928000 0x1000>;
3146                                 status = "disabled";
3147                         };
3148                 };
3149
3150                 intc: interrupt-controller@17a00000 {
3151                         compatible = "arm,gic-v3";
3152                         reg = <0x17a00000 0x10000>,       /* GICD */
3153                               <0x17b00000 0x100000>;      /* GICR * 8 */
3154                         #interrupt-cells = <3>;
3155                         #address-cells = <1>;
3156                         #size-cells = <1>;
3157                         ranges;
3158                         interrupt-controller;
3159                         #redistributor-regions = <1>;
3160                         redistributor-stride = <0x0 0x20000>;
3161                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3162                 };
3163
3164                 wifi: wifi@18800000 {
3165                         compatible = "qcom,wcn3990-wifi";
3166                         status = "disabled";
3167                         reg = <0x18800000 0x800000>;
3168                         reg-names = "membase";
3169                         memory-region = <&wlan_msa_mem>;
3170                         clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3171                         clock-names = "cxo_ref_clk_pin";
3172                         interrupts =
3173                                 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3174                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3175                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3176                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3177                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3178                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3179                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3180                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3181                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3182                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3183                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3184                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3185                         iommus = <&anoc2_smmu 0x1900>,
3186                                  <&anoc2_smmu 0x1901>;
3187                         qcom,snoc-host-cap-8bit-quirk;
3188                 };
3189         };
3190 };