1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/gpio/gpio.h>
11 interrupt-parent = <&intc>;
13 qcom,msm-id = <292 0x0>;
21 device_type = "memory";
22 /* We expect the bootloader to fill in the reg */
32 reg = <0x0 0x85800000 0x0 0x800000>;
36 smem_mem: smem-mem@86000000 {
37 reg = <0x0 0x86000000 0x0 0x200000>;
42 reg = <0x0 0x86200000 0x0 0x2d00000>;
47 compatible = "qcom,rmtfs-mem";
49 size = <0x0 0x200000>;
50 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
60 compatible = "fixed-clock";
62 clock-frequency = <19200000>;
63 clock-output-names = "xo_board";
67 compatible = "fixed-clock";
69 clock-frequency = <32764>;
79 compatible = "arm,armv8";
81 enable-method = "psci";
82 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
83 next-level-cache = <&L2_0>;
85 compatible = "arm,arch-cache";
89 compatible = "arm,arch-cache";
92 compatible = "arm,arch-cache";
98 compatible = "arm,armv8";
100 enable-method = "psci";
101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
102 next-level-cache = <&L2_0>;
104 compatible = "arm,arch-cache";
107 compatible = "arm,arch-cache";
113 compatible = "arm,armv8";
115 enable-method = "psci";
116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
117 next-level-cache = <&L2_0>;
119 compatible = "arm,arch-cache";
122 compatible = "arm,arch-cache";
128 compatible = "arm,armv8";
130 enable-method = "psci";
131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
132 next-level-cache = <&L2_0>;
134 compatible = "arm,arch-cache";
137 compatible = "arm,arch-cache";
143 compatible = "arm,armv8";
145 enable-method = "psci";
146 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
147 next-level-cache = <&L2_1>;
149 compatible = "arm,arch-cache";
152 L1_I_100: l1-icache {
153 compatible = "arm,arch-cache";
155 L1_D_100: l1-dcache {
156 compatible = "arm,arch-cache";
162 compatible = "arm,armv8";
164 enable-method = "psci";
165 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
166 next-level-cache = <&L2_1>;
167 L1_I_101: l1-icache {
168 compatible = "arm,arch-cache";
170 L1_D_101: l1-dcache {
171 compatible = "arm,arch-cache";
177 compatible = "arm,armv8";
179 enable-method = "psci";
180 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
181 next-level-cache = <&L2_1>;
182 L1_I_102: l1-icache {
183 compatible = "arm,arch-cache";
185 L1_D_102: l1-dcache {
186 compatible = "arm,arch-cache";
192 compatible = "arm,armv8";
194 enable-method = "psci";
195 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
196 next-level-cache = <&L2_1>;
197 L1_I_103: l1-icache {
198 compatible = "arm,arch-cache";
200 L1_D_103: l1-dcache {
201 compatible = "arm,arch-cache";
244 entry-method = "psci";
246 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
247 compatible = "arm,idle-state";
248 idle-state-name = "little-retention";
249 /* CPU Retention (C2D), L2 Active */
250 arm,psci-suspend-param = <0x00000002>;
251 entry-latency-us = <81>;
252 exit-latency-us = <86>;
253 min-residency-us = <504>;
256 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
257 compatible = "arm,idle-state";
258 idle-state-name = "little-power-collapse";
259 /* CPU + L2 Power Collapse (C3, D4) */
260 arm,psci-suspend-param = <0x40000003>;
261 entry-latency-us = <814>;
262 exit-latency-us = <4562>;
263 min-residency-us = <9183>;
267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
268 compatible = "arm,idle-state";
269 idle-state-name = "big-retention";
270 /* CPU Retention (C2D), L2 Active */
271 arm,psci-suspend-param = <0x00000002>;
272 entry-latency-us = <79>;
273 exit-latency-us = <82>;
274 min-residency-us = <1302>;
277 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
278 compatible = "arm,idle-state";
279 idle-state-name = "big-power-collapse";
280 /* CPU + L2 Power Collapse (C3, D4) */
281 arm,psci-suspend-param = <0x40000003>;
282 entry-latency-us = <724>;
283 exit-latency-us = <2027>;
284 min-residency-us = <9419>;
292 compatible = "qcom,scm-msm8998", "qcom,scm";
297 compatible = "qcom,tcsr-mutex";
298 syscon = <&tcsr_mutex_regs 0 0x1000>;
303 compatible = "arm,psci-1.0";
308 compatible = "qcom,glink-rpm";
310 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
311 qcom,rpm-msg-ram = <&rpm_msg_ram>;
312 mboxes = <&apcs_glb 0>;
314 rpm_requests: rpm-requests {
315 compatible = "qcom,rpm-msm8998";
316 qcom,glink-channels = "rpm_requests";
318 rpmcc: clock-controller {
319 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
323 rpmpd: power-controller {
324 compatible = "qcom,msm8998-rpmpd";
325 #power-domain-cells = <1>;
326 operating-points-v2 = <&rpmpd_opp_table>;
328 rpmpd_opp_table: opp-table {
329 compatible = "operating-points-v2";
331 rpmpd_opp_ret: opp1 {
335 rpmpd_opp_ret_plus: opp2 {
339 rpmpd_opp_min_svs: opp3 {
343 rpmpd_opp_low_svs: opp4 {
347 rpmpd_opp_svs: opp5 {
351 rpmpd_opp_svs_plus: opp6 {
355 rpmpd_opp_nom: opp7 {
359 rpmpd_opp_nom_plus: opp8 {
363 rpmpd_opp_turbo: opp9 {
367 rpmpd_opp_turbo_plus: opp10 {
376 compatible = "qcom,smem";
377 memory-region = <&smem_mem>;
378 hwlocks = <&tcsr_mutex 3>;
382 compatible = "qcom,smp2p";
383 qcom,smem = <443>, <429>;
385 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
387 mboxes = <&apcs_glb 10>;
389 qcom,local-pid = <0>;
390 qcom,remote-pid = <2>;
392 adsp_smp2p_out: master-kernel {
393 qcom,entry-name = "master-kernel";
394 #qcom,smem-state-cells = <1>;
397 adsp_smp2p_in: slave-kernel {
398 qcom,entry-name = "slave-kernel";
400 interrupt-controller;
401 #interrupt-cells = <2>;
406 compatible = "qcom,smp2p";
407 qcom,smem = <435>, <428>;
408 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
409 mboxes = <&apcs_glb 14>;
410 qcom,local-pid = <0>;
411 qcom,remote-pid = <1>;
413 modem_smp2p_out: master-kernel {
414 qcom,entry-name = "master-kernel";
415 #qcom,smem-state-cells = <1>;
418 modem_smp2p_in: slave-kernel {
419 qcom,entry-name = "slave-kernel";
420 interrupt-controller;
421 #interrupt-cells = <2>;
426 compatible = "qcom,smp2p";
427 qcom,smem = <481>, <430>;
428 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
429 mboxes = <&apcs_glb 26>;
430 qcom,local-pid = <0>;
431 qcom,remote-pid = <3>;
433 slpi_smp2p_out: master-kernel {
434 qcom,entry-name = "master-kernel";
435 #qcom,smem-state-cells = <1>;
438 slpi_smp2p_in: slave-kernel {
439 qcom,entry-name = "slave-kernel";
440 interrupt-controller;
441 #interrupt-cells = <2>;
447 polling-delay-passive = <250>;
448 polling-delay = <1000>;
450 thermal-sensors = <&tsens0 1>;
453 cpu0_alert0: trip-point@0 {
454 temperature = <75000>;
459 cpu0_crit: cpu_crit {
460 temperature = <110000>;
468 polling-delay-passive = <250>;
469 polling-delay = <1000>;
471 thermal-sensors = <&tsens0 2>;
474 cpu1_alert0: trip-point@0 {
475 temperature = <75000>;
480 cpu1_crit: cpu_crit {
481 temperature = <110000>;
489 polling-delay-passive = <250>;
490 polling-delay = <1000>;
492 thermal-sensors = <&tsens0 3>;
495 cpu2_alert0: trip-point@0 {
496 temperature = <75000>;
501 cpu2_crit: cpu_crit {
502 temperature = <110000>;
510 polling-delay-passive = <250>;
511 polling-delay = <1000>;
513 thermal-sensors = <&tsens0 4>;
516 cpu3_alert0: trip-point@0 {
517 temperature = <75000>;
522 cpu3_crit: cpu_crit {
523 temperature = <110000>;
531 polling-delay-passive = <250>;
532 polling-delay = <1000>;
534 thermal-sensors = <&tsens0 7>;
537 cpu4_alert0: trip-point@0 {
538 temperature = <75000>;
543 cpu4_crit: cpu_crit {
544 temperature = <110000>;
552 polling-delay-passive = <250>;
553 polling-delay = <1000>;
555 thermal-sensors = <&tsens0 8>;
558 cpu5_alert0: trip-point@0 {
559 temperature = <75000>;
564 cpu5_crit: cpu_crit {
565 temperature = <110000>;
573 polling-delay-passive = <250>;
574 polling-delay = <1000>;
576 thermal-sensors = <&tsens0 9>;
579 cpu6_alert0: trip-point@0 {
580 temperature = <75000>;
585 cpu6_crit: cpu_crit {
586 temperature = <110000>;
594 polling-delay-passive = <250>;
595 polling-delay = <1000>;
597 thermal-sensors = <&tsens0 10>;
600 cpu7_alert0: trip-point@0 {
601 temperature = <75000>;
606 cpu7_crit: cpu_crit {
607 temperature = <110000>;
615 polling-delay-passive = <250>;
616 polling-delay = <1000>;
618 thermal-sensors = <&tsens0 12>;
621 gpu1_alert0: trip-point@0 {
622 temperature = <90000>;
630 polling-delay-passive = <250>;
631 polling-delay = <1000>;
633 thermal-sensors = <&tsens0 13>;
636 gpu2_alert0: trip-point@0 {
637 temperature = <90000>;
645 polling-delay-passive = <250>;
646 polling-delay = <1000>;
648 thermal-sensors = <&tsens0 5>;
651 cluster0_mhm_alert0: trip-point@0 {
652 temperature = <90000>;
660 polling-delay-passive = <250>;
661 polling-delay = <1000>;
663 thermal-sensors = <&tsens0 6>;
666 cluster1_mhm_alert0: trip-point@0 {
667 temperature = <90000>;
674 cluster1-l2-thermal {
675 polling-delay-passive = <250>;
676 polling-delay = <1000>;
678 thermal-sensors = <&tsens0 11>;
681 cluster1_l2_alert0: trip-point@0 {
682 temperature = <90000>;
690 polling-delay-passive = <250>;
691 polling-delay = <1000>;
693 thermal-sensors = <&tsens1 1>;
696 modem_alert0: trip-point@0 {
697 temperature = <90000>;
705 polling-delay-passive = <250>;
706 polling-delay = <1000>;
708 thermal-sensors = <&tsens1 2>;
711 mem_alert0: trip-point@0 {
712 temperature = <90000>;
720 polling-delay-passive = <250>;
721 polling-delay = <1000>;
723 thermal-sensors = <&tsens1 3>;
726 wlan_alert0: trip-point@0 {
727 temperature = <90000>;
735 polling-delay-passive = <250>;
736 polling-delay = <1000>;
738 thermal-sensors = <&tsens1 4>;
741 q6_dsp_alert0: trip-point@0 {
742 temperature = <90000>;
750 polling-delay-passive = <250>;
751 polling-delay = <1000>;
753 thermal-sensors = <&tsens1 5>;
756 camera_alert0: trip-point@0 {
757 temperature = <90000>;
765 polling-delay-passive = <250>;
766 polling-delay = <1000>;
768 thermal-sensors = <&tsens1 6>;
771 multimedia_alert0: trip-point@0 {
772 temperature = <90000>;
781 compatible = "arm,armv8-timer";
782 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
783 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
784 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
785 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
789 #address-cells = <1>;
791 ranges = <0 0 0 0xffffffff>;
792 compatible = "simple-bus";
794 gcc: clock-controller@100000 {
795 compatible = "qcom,gcc-msm8998";
798 #power-domain-cells = <1>;
799 reg = <0x00100000 0xb0000>;
802 rpm_msg_ram: memory@778000 {
803 compatible = "qcom,rpm-msg-ram";
804 reg = <0x00778000 0x7000>;
807 qfprom: qfprom@780000 {
808 compatible = "qcom,qfprom";
809 reg = <0x00780000 0x621c>;
810 #address-cells = <1>;
813 qusb2_hstx_trim: hstx-trim@423a {
819 tsens0: thermal@10ab000 {
820 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
821 reg = <0x010ab000 0x1000>, /* TM */
822 <0x010aa000 0x1000>; /* SROT */
824 #qcom,sensors = <14>;
825 #thermal-sensor-cells = <1>;
828 tsens1: thermal@10ae000 {
829 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
830 reg = <0x010ae000 0x1000>, /* TM */
831 <0x010ad000 0x1000>; /* SROT */
834 #thermal-sensor-cells = <1>;
837 anoc1_smmu: iommu@1680000 {
838 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
839 reg = <0x01680000 0x10000>;
842 #global-interrupts = <0>;
844 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
845 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
846 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
847 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
848 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
849 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
853 compatible = "qcom,pcie-msm8996";
854 reg = <0x01c00000 0x2000>,
857 <0x1b100000 0x100000>;
858 reg-names = "parf", "dbi", "elbi", "config";
860 linux,pci-domain = <0>;
861 bus-range = <0x00 0xff>;
862 #address-cells = <3>;
866 phy-names = "pciephy";
868 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
869 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
871 #interrupt-cells = <1>;
872 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
873 interrupt-names = "msi";
874 interrupt-map-mask = <0 0 0 0x7>;
875 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
876 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
877 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
878 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
881 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
882 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
883 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
884 <&gcc GCC_PCIE_0_AUX_CLK>;
885 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
887 power-domains = <&gcc PCIE_0_GDSC>;
888 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
889 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
893 compatible = "qcom,msm8998-qmp-pcie-phy";
894 reg = <0x01c06000 0x18c>;
895 #address-cells = <1>;
899 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
900 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
901 <&gcc GCC_PCIE_CLKREF_CLK>;
902 clock-names = "aux", "cfg_ahb", "ref";
904 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
905 reset-names = "phy", "common";
907 vdda-phy-supply = <&vreg_l1a_0p875>;
908 vdda-pll-supply = <&vreg_l2a_1p2>;
910 pciephy: lane@1c06800 {
911 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
914 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
915 clock-names = "pipe0";
916 clock-output-names = "pcie_0_pipe_clk_src";
921 ufshc: ufshc@1da4000 {
922 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
923 reg = <0x01da4000 0x2500>;
924 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
925 phys = <&ufsphy_lanes>;
926 phy-names = "ufsphy";
927 lanes-per-direction = <2>;
928 power-domains = <&gcc UFS_GDSC>;
941 <&gcc GCC_UFS_AXI_CLK>,
942 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
943 <&gcc GCC_UFS_AHB_CLK>,
944 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
945 <&rpmcc RPM_SMD_LN_BB_CLK1>,
946 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
947 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
948 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
950 <50000000 200000000>,
953 <37500000 150000000>,
959 resets = <&gcc GCC_UFS_BCR>;
963 ufsphy: phy@1da7000 {
964 compatible = "qcom,msm8998-qmp-ufs-phy";
965 reg = <0x01da7000 0x18c>;
966 #address-cells = <1>;
974 <&gcc GCC_UFS_CLKREF_CLK>,
975 <&gcc GCC_UFS_PHY_AUX_CLK>;
977 reset-names = "ufsphy";
980 ufsphy_lanes: lanes@1da7400 {
981 reg = <0x01da7400 0x128>,
990 tcsr_mutex_regs: syscon@1f40000 {
991 compatible = "syscon";
992 reg = <0x01f40000 0x40000>;
995 tlmm: pinctrl@3400000 {
996 compatible = "qcom,msm8998-pinctrl";
997 reg = <0x03400000 0xc00000>;
998 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1000 #gpio-cells = <0x2>;
1001 interrupt-controller;
1002 #interrupt-cells = <0x2>;
1006 compatible = "arm,coresight-stm", "arm,primecell";
1007 reg = <0x06002000 0x1000>,
1008 <0x16280000 0x180000>;
1009 reg-names = "stm-base", "stm-data-base";
1010 status = "disabled";
1012 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1013 clock-names = "apb_pclk", "atclk";
1018 remote-endpoint = <&funnel0_in7>;
1024 funnel1: funnel@6041000 {
1025 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1026 reg = <0x06041000 0x1000>;
1027 status = "disabled";
1029 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1030 clock-names = "apb_pclk", "atclk";
1034 funnel0_out: endpoint {
1036 <&merge_funnel_in0>;
1042 #address-cells = <1>;
1047 funnel0_in7: endpoint {
1048 remote-endpoint = <&stm_out>;
1054 funnel2: funnel@6042000 {
1055 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1056 reg = <0x06042000 0x1000>;
1057 status = "disabled";
1059 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1060 clock-names = "apb_pclk", "atclk";
1064 funnel1_out: endpoint {
1066 <&merge_funnel_in1>;
1072 #address-cells = <1>;
1077 funnel1_in6: endpoint {
1079 <&apss_merge_funnel_out>;
1085 funnel3: funnel@6045000 {
1086 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1087 reg = <0x06045000 0x1000>;
1088 status = "disabled";
1090 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1091 clock-names = "apb_pclk", "atclk";
1095 merge_funnel_out: endpoint {
1103 #address-cells = <1>;
1108 merge_funnel_in0: endpoint {
1116 merge_funnel_in1: endpoint {
1124 replicator1: replicator@6046000 {
1125 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1126 reg = <0x06046000 0x1000>;
1127 status = "disabled";
1129 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1130 clock-names = "apb_pclk", "atclk";
1134 replicator_out: endpoint {
1135 remote-endpoint = <&etr_in>;
1142 replicator_in: endpoint {
1143 remote-endpoint = <&etf_out>;
1150 compatible = "arm,coresight-tmc", "arm,primecell";
1151 reg = <0x06047000 0x1000>;
1152 status = "disabled";
1154 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1155 clock-names = "apb_pclk", "atclk";
1170 <&merge_funnel_out>;
1177 compatible = "arm,coresight-tmc", "arm,primecell";
1178 reg = <0x06048000 0x1000>;
1179 status = "disabled";
1181 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1182 clock-names = "apb_pclk", "atclk";
1196 compatible = "arm,coresight-etm4x", "arm,primecell";
1197 reg = <0x07840000 0x1000>;
1198 status = "disabled";
1200 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1201 clock-names = "apb_pclk", "atclk";
1207 etm0_out: endpoint {
1216 compatible = "arm,coresight-etm4x", "arm,primecell";
1217 reg = <0x07940000 0x1000>;
1218 status = "disabled";
1220 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1221 clock-names = "apb_pclk", "atclk";
1227 etm1_out: endpoint {
1236 compatible = "arm,coresight-etm4x", "arm,primecell";
1237 reg = <0x07a40000 0x1000>;
1238 status = "disabled";
1240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1241 clock-names = "apb_pclk", "atclk";
1247 etm2_out: endpoint {
1256 compatible = "arm,coresight-etm4x", "arm,primecell";
1257 reg = <0x07b40000 0x1000>;
1258 status = "disabled";
1260 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1261 clock-names = "apb_pclk", "atclk";
1267 etm3_out: endpoint {
1275 funnel4: funnel@7b60000 { /* APSS Funnel */
1276 compatible = "arm,coresight-etm4x", "arm,primecell";
1277 reg = <0x07b60000 0x1000>;
1278 status = "disabled";
1280 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1281 clock-names = "apb_pclk", "atclk";
1285 apss_funnel_out: endpoint {
1287 <&apss_merge_funnel_in>;
1293 #address-cells = <1>;
1298 apss_funnel_in0: endpoint {
1306 apss_funnel_in1: endpoint {
1314 apss_funnel_in2: endpoint {
1322 apss_funnel_in3: endpoint {
1330 apss_funnel_in4: endpoint {
1338 apss_funnel_in5: endpoint {
1346 apss_funnel_in6: endpoint {
1354 apss_funnel_in7: endpoint {
1362 funnel5: funnel@7b70000 {
1363 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1364 reg = <0x07b70000 0x1000>;
1365 status = "disabled";
1367 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1368 clock-names = "apb_pclk", "atclk";
1372 apss_merge_funnel_out: endpoint {
1381 apss_merge_funnel_in: endpoint {
1390 compatible = "arm,coresight-etm4x", "arm,primecell";
1391 reg = <0x07c40000 0x1000>;
1392 status = "disabled";
1394 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1395 clock-names = "apb_pclk", "atclk";
1401 etm4_out: endpoint {
1402 remote-endpoint = <&apss_funnel_in4>;
1409 compatible = "arm,coresight-etm4x", "arm,primecell";
1410 reg = <0x07d40000 0x1000>;
1411 status = "disabled";
1413 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1414 clock-names = "apb_pclk", "atclk";
1420 etm5_out: endpoint {
1421 remote-endpoint = <&apss_funnel_in5>;
1428 compatible = "arm,coresight-etm4x", "arm,primecell";
1429 reg = <0x07e40000 0x1000>;
1430 status = "disabled";
1432 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1433 clock-names = "apb_pclk", "atclk";
1439 etm6_out: endpoint {
1440 remote-endpoint = <&apss_funnel_in6>;
1447 compatible = "arm,coresight-etm4x", "arm,primecell";
1448 reg = <0x07f40000 0x1000>;
1449 status = "disabled";
1451 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1452 clock-names = "apb_pclk", "atclk";
1458 etm7_out: endpoint {
1459 remote-endpoint = <&apss_funnel_in7>;
1465 spmi_bus: spmi@800f000 {
1466 compatible = "qcom,spmi-pmic-arb";
1467 reg = <0x0800f000 0x1000>,
1468 <0x08400000 0x1000000>,
1469 <0x09400000 0x1000000>,
1470 <0x0a400000 0x220000>,
1471 <0x0800a000 0x3000>;
1472 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1473 interrupt-names = "periph_irq";
1474 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cells = <2>;
1479 interrupt-controller;
1480 #interrupt-cells = <4>;
1485 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1486 reg = <0x0a8f8800 0x400>;
1487 status = "disabled";
1488 #address-cells = <1>;
1492 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1493 <&gcc GCC_USB30_MASTER_CLK>,
1494 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
1495 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1496 <&gcc GCC_USB30_SLEEP_CLK>;
1497 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1500 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1501 <&gcc GCC_USB30_MASTER_CLK>;
1502 assigned-clock-rates = <19200000>, <120000000>;
1504 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1506 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1508 power-domains = <&gcc USB_30_GDSC>;
1510 resets = <&gcc GCC_USB_30_BCR>;
1512 usb3_dwc3: dwc3@a800000 {
1513 compatible = "snps,dwc3";
1514 reg = <0x0a800000 0xcd00>;
1515 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1516 snps,dis_u2_susphy_quirk;
1517 snps,dis_enblslpm_quirk;
1518 phys = <&qusb2phy>, <&usb1_ssphy>;
1519 phy-names = "usb2-phy", "usb3-phy";
1520 snps,has-lpm-erratum;
1521 snps,hird-threshold = /bits/ 8 <0x10>;
1525 usb3phy: phy@c010000 {
1526 compatible = "qcom,msm8998-qmp-usb3-phy";
1527 reg = <0x0c010000 0x18c>;
1528 status = "disabled";
1530 #address-cells = <1>;
1534 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1535 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1536 <&gcc GCC_USB3_CLKREF_CLK>;
1537 clock-names = "aux", "cfg_ahb", "ref";
1539 resets = <&gcc GCC_USB3_PHY_BCR>,
1540 <&gcc GCC_USB3PHY_PHY_BCR>;
1541 reset-names = "phy", "common";
1543 usb1_ssphy: lane@c010200 {
1544 reg = <0xc010200 0x128>,
1550 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1551 clock-names = "pipe0";
1552 clock-output-names = "usb3_phy_pipe_clk_src";
1556 qusb2phy: phy@c012000 {
1557 compatible = "qcom,msm8998-qusb2-phy";
1558 reg = <0x0c012000 0x2a8>;
1559 status = "disabled";
1562 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1563 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1564 clock-names = "cfg_ahb", "ref";
1566 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1568 nvmem-cells = <&qusb2_hstx_trim>;
1571 sdhc2: sdhci@c0a4900 {
1572 compatible = "qcom,sdhci-msm-v4";
1573 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
1574 reg-names = "hc_mem", "core_mem";
1576 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1578 interrupt-names = "hc_irq", "pwr_irq";
1580 clock-names = "iface", "core", "xo";
1581 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1582 <&gcc GCC_SDCC2_APPS_CLK>,
1585 status = "disabled";
1588 blsp1_i2c1: i2c@c175000 {
1589 compatible = "qcom,i2c-qup-v2.2.1";
1590 reg = <0x0c175000 0x600>;
1591 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1593 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1594 <&gcc GCC_BLSP1_AHB_CLK>;
1595 clock-names = "core", "iface";
1596 clock-frequency = <400000>;
1598 status = "disabled";
1599 #address-cells = <1>;
1603 blsp1_i2c2: i2c@c176000 {
1604 compatible = "qcom,i2c-qup-v2.2.1";
1605 reg = <0x0c176000 0x600>;
1606 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1608 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1609 <&gcc GCC_BLSP1_AHB_CLK>;
1610 clock-names = "core", "iface";
1611 clock-frequency = <400000>;
1613 status = "disabled";
1614 #address-cells = <1>;
1618 blsp1_i2c3: i2c@c177000 {
1619 compatible = "qcom,i2c-qup-v2.2.1";
1620 reg = <0x0c177000 0x600>;
1621 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1623 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1624 <&gcc GCC_BLSP1_AHB_CLK>;
1625 clock-names = "core", "iface";
1626 clock-frequency = <400000>;
1628 status = "disabled";
1629 #address-cells = <1>;
1633 blsp1_i2c4: i2c@c178000 {
1634 compatible = "qcom,i2c-qup-v2.2.1";
1635 reg = <0x0c178000 0x600>;
1636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1638 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1639 <&gcc GCC_BLSP1_AHB_CLK>;
1640 clock-names = "core", "iface";
1641 clock-frequency = <400000>;
1643 status = "disabled";
1644 #address-cells = <1>;
1648 blsp1_i2c5: i2c@c179000 {
1649 compatible = "qcom,i2c-qup-v2.2.1";
1650 reg = <0x0c179000 0x600>;
1651 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1653 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1654 <&gcc GCC_BLSP1_AHB_CLK>;
1655 clock-names = "core", "iface";
1656 clock-frequency = <400000>;
1658 status = "disabled";
1659 #address-cells = <1>;
1663 blsp1_i2c6: i2c@c17a000 {
1664 compatible = "qcom,i2c-qup-v2.2.1";
1665 reg = <0x0c17a000 0x600>;
1666 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1668 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1669 <&gcc GCC_BLSP1_AHB_CLK>;
1670 clock-names = "core", "iface";
1671 clock-frequency = <400000>;
1673 status = "disabled";
1674 #address-cells = <1>;
1678 blsp2_uart1: serial@c1b0000 {
1679 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1680 reg = <0x0c1b0000 0x1000>;
1681 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1682 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1683 <&gcc GCC_BLSP2_AHB_CLK>;
1684 clock-names = "core", "iface";
1685 status = "disabled";
1688 blsp2_i2c0: i2c@c1b5000 {
1689 compatible = "qcom,i2c-qup-v2.2.1";
1690 reg = <0x0c1b5000 0x600>;
1691 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1693 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1694 <&gcc GCC_BLSP2_AHB_CLK>;
1695 clock-names = "core", "iface";
1696 clock-frequency = <400000>;
1698 status = "disabled";
1699 #address-cells = <1>;
1703 blsp2_i2c1: i2c@c1b6000 {
1704 compatible = "qcom,i2c-qup-v2.2.1";
1705 reg = <0x0c1b6000 0x600>;
1706 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1708 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1709 <&gcc GCC_BLSP2_AHB_CLK>;
1710 clock-names = "core", "iface";
1711 clock-frequency = <400000>;
1713 status = "disabled";
1714 #address-cells = <1>;
1718 blsp2_i2c2: i2c@c1b7000 {
1719 compatible = "qcom,i2c-qup-v2.2.1";
1720 reg = <0x0c1b7000 0x600>;
1721 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1723 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1724 <&gcc GCC_BLSP2_AHB_CLK>;
1725 clock-names = "core", "iface";
1726 clock-frequency = <400000>;
1728 status = "disabled";
1729 #address-cells = <1>;
1733 blsp2_i2c3: i2c@c1b8000 {
1734 compatible = "qcom,i2c-qup-v2.2.1";
1735 reg = <0x0c1b8000 0x600>;
1736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1738 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1739 <&gcc GCC_BLSP2_AHB_CLK>;
1740 clock-names = "core", "iface";
1741 clock-frequency = <400000>;
1743 status = "disabled";
1744 #address-cells = <1>;
1748 blsp2_i2c4: i2c@c1b9000 {
1749 compatible = "qcom,i2c-qup-v2.2.1";
1750 reg = <0x0c1b9000 0x600>;
1751 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1753 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
1754 <&gcc GCC_BLSP2_AHB_CLK>;
1755 clock-names = "core", "iface";
1756 clock-frequency = <400000>;
1758 status = "disabled";
1759 #address-cells = <1>;
1763 blsp2_i2c5: i2c@c1ba000 {
1764 compatible = "qcom,i2c-qup-v2.2.1";
1765 reg = <0x0c1ba000 0x600>;
1766 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1768 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
1769 <&gcc GCC_BLSP2_AHB_CLK>;
1770 clock-names = "core", "iface";
1771 clock-frequency = <400000>;
1773 status = "disabled";
1774 #address-cells = <1>;
1778 apcs_glb: mailbox@17911000 {
1779 compatible = "qcom,msm8998-apcs-hmss-global";
1780 reg = <0x17911000 0x1000>;
1786 #address-cells = <1>;
1789 compatible = "arm,armv7-timer-mem";
1790 reg = <0x17920000 0x1000>;
1794 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1796 reg = <0x17921000 0x1000>,
1797 <0x17922000 0x1000>;
1802 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1803 reg = <0x17923000 0x1000>;
1804 status = "disabled";
1809 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1810 reg = <0x17924000 0x1000>;
1811 status = "disabled";
1816 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1817 reg = <0x17925000 0x1000>;
1818 status = "disabled";
1823 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1824 reg = <0x17926000 0x1000>;
1825 status = "disabled";
1830 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1831 reg = <0x17927000 0x1000>;
1832 status = "disabled";
1837 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1838 reg = <0x17928000 0x1000>;
1839 status = "disabled";
1843 intc: interrupt-controller@17a00000 {
1844 compatible = "arm,gic-v3";
1845 reg = <0x17a00000 0x10000>, /* GICD */
1846 <0x17b00000 0x100000>; /* GICR * 8 */
1847 #interrupt-cells = <3>;
1848 #address-cells = <1>;
1851 interrupt-controller;
1852 #redistributor-regions = <1>;
1853 redistributor-stride = <0x0 0x20000>;
1854 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1859 #include "msm8998-pins.dtsi"