1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
23 device_type = "memory";
24 /* We expect the bootloader to fill in the reg */
25 reg = <0x0 0x80000000 0x0 0x0>;
33 hyp_mem: memory@85800000 {
34 reg = <0x0 0x85800000 0x0 0x600000>;
38 xbl_mem: memory@85e00000 {
39 reg = <0x0 0x85e00000 0x0 0x100000>;
43 smem_mem: smem-mem@86000000 {
44 reg = <0x0 0x86000000 0x0 0x200000>;
48 tz_mem: memory@86200000 {
49 reg = <0x0 0x86200000 0x0 0x2d00000>;
53 rmtfs_mem: memory@88f00000 {
54 compatible = "qcom,rmtfs-mem";
55 reg = <0x0 0x88f00000 0x0 0x200000>;
62 spss_mem: memory@8ab00000 {
63 reg = <0x0 0x8ab00000 0x0 0x700000>;
67 adsp_mem: memory@8b200000 {
68 reg = <0x0 0x8b200000 0x0 0x1a00000>;
72 mpss_mem: memory@8cc00000 {
73 reg = <0x0 0x8cc00000 0x0 0x7000000>;
77 venus_mem: memory@93c00000 {
78 reg = <0x0 0x93c00000 0x0 0x500000>;
82 mba_mem: memory@94100000 {
83 reg = <0x0 0x94100000 0x0 0x200000>;
87 slpi_mem: memory@94300000 {
88 reg = <0x0 0x94300000 0x0 0xf00000>;
92 ipa_fw_mem: memory@95200000 {
93 reg = <0x0 0x95200000 0x0 0x10000>;
97 ipa_gsi_mem: memory@95210000 {
98 reg = <0x0 0x95210000 0x0 0x5000>;
102 gpu_mem: memory@95600000 {
103 reg = <0x0 0x95600000 0x0 0x100000>;
107 wlan_msa_mem: memory@95700000 {
108 reg = <0x0 0x95700000 0x0 0x100000>;
115 compatible = "fixed-clock";
117 clock-frequency = <19200000>;
118 clock-output-names = "xo_board";
121 sleep_clk: sleep-clk {
122 compatible = "fixed-clock";
124 clock-frequency = <32764>;
129 #address-cells = <2>;
134 compatible = "qcom,kryo280";
136 enable-method = "psci";
137 capacity-dmips-mhz = <1024>;
138 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
139 next-level-cache = <&L2_0>;
141 compatible = "cache";
148 compatible = "qcom,kryo280";
150 enable-method = "psci";
151 capacity-dmips-mhz = <1024>;
152 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
153 next-level-cache = <&L2_0>;
158 compatible = "qcom,kryo280";
160 enable-method = "psci";
161 capacity-dmips-mhz = <1024>;
162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
163 next-level-cache = <&L2_0>;
168 compatible = "qcom,kryo280";
170 enable-method = "psci";
171 capacity-dmips-mhz = <1024>;
172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
173 next-level-cache = <&L2_0>;
178 compatible = "qcom,kryo280";
180 enable-method = "psci";
181 capacity-dmips-mhz = <1536>;
182 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
183 next-level-cache = <&L2_1>;
185 compatible = "cache";
192 compatible = "qcom,kryo280";
194 enable-method = "psci";
195 capacity-dmips-mhz = <1536>;
196 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
197 next-level-cache = <&L2_1>;
202 compatible = "qcom,kryo280";
204 enable-method = "psci";
205 capacity-dmips-mhz = <1536>;
206 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
207 next-level-cache = <&L2_1>;
212 compatible = "qcom,kryo280";
214 enable-method = "psci";
215 capacity-dmips-mhz = <1536>;
216 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
217 next-level-cache = <&L2_1>;
259 entry-method = "psci";
261 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
262 compatible = "arm,idle-state";
263 idle-state-name = "little-retention";
264 /* CPU Retention (C2D), L2 Active */
265 arm,psci-suspend-param = <0x00000002>;
266 entry-latency-us = <81>;
267 exit-latency-us = <86>;
268 min-residency-us = <504>;
271 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
272 compatible = "arm,idle-state";
273 idle-state-name = "little-power-collapse";
274 /* CPU + L2 Power Collapse (C3, D4) */
275 arm,psci-suspend-param = <0x40000003>;
276 entry-latency-us = <814>;
277 exit-latency-us = <4562>;
278 min-residency-us = <9183>;
282 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "big-retention";
285 /* CPU Retention (C2D), L2 Active */
286 arm,psci-suspend-param = <0x00000002>;
287 entry-latency-us = <79>;
288 exit-latency-us = <82>;
289 min-residency-us = <1302>;
292 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
293 compatible = "arm,idle-state";
294 idle-state-name = "big-power-collapse";
295 /* CPU + L2 Power Collapse (C3, D4) */
296 arm,psci-suspend-param = <0x40000003>;
297 entry-latency-us = <724>;
298 exit-latency-us = <2027>;
299 min-residency-us = <9419>;
307 compatible = "qcom,scm-msm8998", "qcom,scm";
312 compatible = "arm,psci-1.0";
317 compatible = "qcom,glink-rpm";
319 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
320 qcom,rpm-msg-ram = <&rpm_msg_ram>;
321 mboxes = <&apcs_glb 0>;
323 rpm_requests: rpm-requests {
324 compatible = "qcom,rpm-msm8998";
325 qcom,glink-channels = "rpm_requests";
327 rpmcc: clock-controller {
328 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
332 rpmpd: power-controller {
333 compatible = "qcom,msm8998-rpmpd";
334 #power-domain-cells = <1>;
335 operating-points-v2 = <&rpmpd_opp_table>;
337 rpmpd_opp_table: opp-table {
338 compatible = "operating-points-v2";
340 rpmpd_opp_ret: opp1 {
341 opp-level = <RPM_SMD_LEVEL_RETENTION>;
344 rpmpd_opp_ret_plus: opp2 {
345 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
348 rpmpd_opp_min_svs: opp3 {
349 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
352 rpmpd_opp_low_svs: opp4 {
353 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
356 rpmpd_opp_svs: opp5 {
357 opp-level = <RPM_SMD_LEVEL_SVS>;
360 rpmpd_opp_svs_plus: opp6 {
361 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
364 rpmpd_opp_nom: opp7 {
365 opp-level = <RPM_SMD_LEVEL_NOM>;
368 rpmpd_opp_nom_plus: opp8 {
369 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
372 rpmpd_opp_turbo: opp9 {
373 opp-level = <RPM_SMD_LEVEL_TURBO>;
376 rpmpd_opp_turbo_plus: opp10 {
377 opp-level = <RPM_SMD_LEVEL_BINNING>;
385 compatible = "qcom,smem";
386 memory-region = <&smem_mem>;
387 hwlocks = <&tcsr_mutex 3>;
391 compatible = "qcom,smp2p";
392 qcom,smem = <443>, <429>;
394 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
396 mboxes = <&apcs_glb 10>;
398 qcom,local-pid = <0>;
399 qcom,remote-pid = <2>;
401 adsp_smp2p_out: master-kernel {
402 qcom,entry-name = "master-kernel";
403 #qcom,smem-state-cells = <1>;
406 adsp_smp2p_in: slave-kernel {
407 qcom,entry-name = "slave-kernel";
409 interrupt-controller;
410 #interrupt-cells = <2>;
415 compatible = "qcom,smp2p";
416 qcom,smem = <435>, <428>;
417 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
418 mboxes = <&apcs_glb 14>;
419 qcom,local-pid = <0>;
420 qcom,remote-pid = <1>;
422 modem_smp2p_out: master-kernel {
423 qcom,entry-name = "master-kernel";
424 #qcom,smem-state-cells = <1>;
427 modem_smp2p_in: slave-kernel {
428 qcom,entry-name = "slave-kernel";
429 interrupt-controller;
430 #interrupt-cells = <2>;
435 compatible = "qcom,smp2p";
436 qcom,smem = <481>, <430>;
437 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
438 mboxes = <&apcs_glb 26>;
439 qcom,local-pid = <0>;
440 qcom,remote-pid = <3>;
442 slpi_smp2p_out: master-kernel {
443 qcom,entry-name = "master-kernel";
444 #qcom,smem-state-cells = <1>;
447 slpi_smp2p_in: slave-kernel {
448 qcom,entry-name = "slave-kernel";
449 interrupt-controller;
450 #interrupt-cells = <2>;
456 polling-delay-passive = <250>;
457 polling-delay = <1000>;
459 thermal-sensors = <&tsens0 1>;
462 cpu0_alert0: trip-point0 {
463 temperature = <75000>;
468 cpu0_crit: cpu_crit {
469 temperature = <110000>;
477 polling-delay-passive = <250>;
478 polling-delay = <1000>;
480 thermal-sensors = <&tsens0 2>;
483 cpu1_alert0: trip-point0 {
484 temperature = <75000>;
489 cpu1_crit: cpu_crit {
490 temperature = <110000>;
498 polling-delay-passive = <250>;
499 polling-delay = <1000>;
501 thermal-sensors = <&tsens0 3>;
504 cpu2_alert0: trip-point0 {
505 temperature = <75000>;
510 cpu2_crit: cpu_crit {
511 temperature = <110000>;
519 polling-delay-passive = <250>;
520 polling-delay = <1000>;
522 thermal-sensors = <&tsens0 4>;
525 cpu3_alert0: trip-point0 {
526 temperature = <75000>;
531 cpu3_crit: cpu_crit {
532 temperature = <110000>;
540 polling-delay-passive = <250>;
541 polling-delay = <1000>;
543 thermal-sensors = <&tsens0 7>;
546 cpu4_alert0: trip-point0 {
547 temperature = <75000>;
552 cpu4_crit: cpu_crit {
553 temperature = <110000>;
561 polling-delay-passive = <250>;
562 polling-delay = <1000>;
564 thermal-sensors = <&tsens0 8>;
567 cpu5_alert0: trip-point0 {
568 temperature = <75000>;
573 cpu5_crit: cpu_crit {
574 temperature = <110000>;
582 polling-delay-passive = <250>;
583 polling-delay = <1000>;
585 thermal-sensors = <&tsens0 9>;
588 cpu6_alert0: trip-point0 {
589 temperature = <75000>;
594 cpu6_crit: cpu_crit {
595 temperature = <110000>;
603 polling-delay-passive = <250>;
604 polling-delay = <1000>;
606 thermal-sensors = <&tsens0 10>;
609 cpu7_alert0: trip-point0 {
610 temperature = <75000>;
615 cpu7_crit: cpu_crit {
616 temperature = <110000>;
624 polling-delay-passive = <250>;
625 polling-delay = <1000>;
627 thermal-sensors = <&tsens0 12>;
630 gpu1_alert0: trip-point0 {
631 temperature = <90000>;
639 polling-delay-passive = <250>;
640 polling-delay = <1000>;
642 thermal-sensors = <&tsens0 13>;
645 gpu2_alert0: trip-point0 {
646 temperature = <90000>;
654 polling-delay-passive = <250>;
655 polling-delay = <1000>;
657 thermal-sensors = <&tsens0 5>;
660 cluster0_mhm_alert0: trip-point0 {
661 temperature = <90000>;
669 polling-delay-passive = <250>;
670 polling-delay = <1000>;
672 thermal-sensors = <&tsens0 6>;
675 cluster1_mhm_alert0: trip-point0 {
676 temperature = <90000>;
683 cluster1-l2-thermal {
684 polling-delay-passive = <250>;
685 polling-delay = <1000>;
687 thermal-sensors = <&tsens0 11>;
690 cluster1_l2_alert0: trip-point0 {
691 temperature = <90000>;
699 polling-delay-passive = <250>;
700 polling-delay = <1000>;
702 thermal-sensors = <&tsens1 1>;
705 modem_alert0: trip-point0 {
706 temperature = <90000>;
714 polling-delay-passive = <250>;
715 polling-delay = <1000>;
717 thermal-sensors = <&tsens1 2>;
720 mem_alert0: trip-point0 {
721 temperature = <90000>;
729 polling-delay-passive = <250>;
730 polling-delay = <1000>;
732 thermal-sensors = <&tsens1 3>;
735 wlan_alert0: trip-point0 {
736 temperature = <90000>;
744 polling-delay-passive = <250>;
745 polling-delay = <1000>;
747 thermal-sensors = <&tsens1 4>;
750 q6_dsp_alert0: trip-point0 {
751 temperature = <90000>;
759 polling-delay-passive = <250>;
760 polling-delay = <1000>;
762 thermal-sensors = <&tsens1 5>;
765 camera_alert0: trip-point0 {
766 temperature = <90000>;
774 polling-delay-passive = <250>;
775 polling-delay = <1000>;
777 thermal-sensors = <&tsens1 6>;
780 multimedia_alert0: trip-point0 {
781 temperature = <90000>;
790 compatible = "arm,armv8-timer";
791 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
792 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
793 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
794 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
798 #address-cells = <1>;
800 ranges = <0 0 0 0xffffffff>;
801 compatible = "simple-bus";
803 gcc: clock-controller@100000 {
804 compatible = "qcom,gcc-msm8998";
807 #power-domain-cells = <1>;
808 reg = <0x00100000 0xb0000>;
810 clock-names = "xo", "sleep_clk";
811 clocks = <&xo>, <&sleep_clk>;
814 * The hypervisor typically configures the memory region where these clocks
815 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
816 * these clocks on a device with such configuration (e.g. because they are
817 * enabled but unused during boot-up), the device will most likely decide
819 * In light of that, we are conservative here and we list all such clocks
820 * as protected. The board dts (or a user-supplied dts) can override the
821 * list of protected clocks if it differs from the norm, and it is in fact
822 * desired for the HLOS to manage these clocks
824 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
829 rpm_msg_ram: sram@778000 {
830 compatible = "qcom,rpm-msg-ram";
831 reg = <0x00778000 0x7000>;
834 qfprom: qfprom@784000 {
835 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
836 reg = <0x00784000 0x621c>;
837 #address-cells = <1>;
840 qusb2_hstx_trim: hstx-trim@23a {
846 tsens0: thermal@10ab000 {
847 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
848 reg = <0x010ab000 0x1000>, /* TM */
849 <0x010aa000 0x1000>; /* SROT */
850 #qcom,sensors = <14>;
851 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
853 interrupt-names = "uplow", "critical";
854 #thermal-sensor-cells = <1>;
857 tsens1: thermal@10ae000 {
858 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
859 reg = <0x010ae000 0x1000>, /* TM */
860 <0x010ad000 0x1000>; /* SROT */
862 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
864 interrupt-names = "uplow", "critical";
865 #thermal-sensor-cells = <1>;
868 anoc1_smmu: iommu@1680000 {
869 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
870 reg = <0x01680000 0x10000>;
873 #global-interrupts = <0>;
875 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
876 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
877 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
878 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
879 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
880 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
883 anoc2_smmu: iommu@16c0000 {
884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885 reg = <0x016c0000 0x40000>;
888 #global-interrupts = <0>;
890 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
891 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
892 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
895 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
896 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
897 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
898 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
899 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
903 compatible = "qcom,pcie-msm8996";
904 reg = <0x01c00000 0x2000>,
907 <0x1b100000 0x100000>;
908 reg-names = "parf", "dbi", "elbi", "config";
910 linux,pci-domain = <0>;
911 bus-range = <0x00 0xff>;
912 #address-cells = <3>;
916 phy-names = "pciephy";
919 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
920 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
922 #interrupt-cells = <1>;
923 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
924 interrupt-names = "msi";
925 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
927 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
928 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
929 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
932 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
933 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
934 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
935 <&gcc GCC_PCIE_0_AUX_CLK>;
936 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
938 power-domains = <&gcc PCIE_0_GDSC>;
939 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
940 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
943 pcie_phy: phy@1c06000 {
944 compatible = "qcom,msm8998-qmp-pcie-phy";
945 reg = <0x01c06000 0x18c>;
946 #address-cells = <1>;
951 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
952 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
953 <&gcc GCC_PCIE_CLKREF_CLK>;
954 clock-names = "aux", "cfg_ahb", "ref";
956 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
957 reset-names = "phy", "common";
959 vdda-phy-supply = <&vreg_l1a_0p875>;
960 vdda-pll-supply = <&vreg_l2a_1p2>;
962 pciephy: phy@1c06800 {
963 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
966 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
967 clock-names = "pipe0";
968 clock-output-names = "pcie_0_pipe_clk_src";
973 ufshc: ufshc@1da4000 {
974 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
975 reg = <0x01da4000 0x2500>;
976 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
977 phys = <&ufsphy_lanes>;
978 phy-names = "ufsphy";
979 lanes-per-direction = <2>;
980 power-domains = <&gcc UFS_GDSC>;
994 <&gcc GCC_UFS_AXI_CLK>,
995 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
996 <&gcc GCC_UFS_AHB_CLK>,
997 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
998 <&rpmcc RPM_SMD_LN_BB_CLK1>,
999 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1000 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1001 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1003 <50000000 200000000>,
1006 <37500000 150000000>,
1012 resets = <&gcc GCC_UFS_BCR>;
1013 reset-names = "rst";
1016 ufsphy: phy@1da7000 {
1017 compatible = "qcom,msm8998-qmp-ufs-phy";
1018 reg = <0x01da7000 0x18c>;
1019 #address-cells = <1>;
1021 status = "disabled";
1028 <&gcc GCC_UFS_CLKREF_CLK>,
1029 <&gcc GCC_UFS_PHY_AUX_CLK>;
1031 reset-names = "ufsphy";
1032 resets = <&ufshc 0>;
1034 ufsphy_lanes: phy@1da7400 {
1035 reg = <0x01da7400 0x128>,
1044 tcsr_mutex: hwlock@1f40000 {
1045 compatible = "qcom,tcsr-mutex";
1046 reg = <0x01f40000 0x20000>;
1047 #hwlock-cells = <1>;
1050 tcsr_regs_1: syscon@1f60000 {
1051 compatible = "qcom,msm8998-tcsr", "syscon";
1052 reg = <0x01f60000 0x20000>;
1055 tlmm: pinctrl@3400000 {
1056 compatible = "qcom,msm8998-pinctrl";
1057 reg = <0x03400000 0xc00000>;
1058 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1061 interrupt-controller;
1062 #interrupt-cells = <2>;
1067 drive-strength = <16>;
1073 drive-strength = <10>;
1079 drive-strength = <10>;
1084 sdc2_off: sdc2-off {
1087 drive-strength = <2>;
1093 drive-strength = <2>;
1099 drive-strength = <2>;
1108 drive-strength = <2>;
1111 blsp1_uart3_on: blsp1-uart3-on {
1114 function = "blsp_uart3_a";
1115 drive-strength = <2>;
1121 function = "blsp_uart3_a";
1122 drive-strength = <2>;
1128 function = "blsp_uart3_a";
1129 drive-strength = <2>;
1135 function = "blsp_uart3_a";
1136 drive-strength = <2>;
1141 blsp1_i2c1_default: blsp1-i2c1-default {
1142 pins = "gpio2", "gpio3";
1143 function = "blsp_i2c1";
1144 drive-strength = <2>;
1148 blsp1_i2c1_sleep: blsp1-i2c1-sleep {
1149 pins = "gpio2", "gpio3";
1150 function = "blsp_i2c1";
1151 drive-strength = <2>;
1155 blsp1_i2c2_default: blsp1-i2c2-default {
1156 pins = "gpio32", "gpio33";
1157 function = "blsp_i2c2";
1158 drive-strength = <2>;
1162 blsp1_i2c2_sleep: blsp1-i2c2-sleep {
1163 pins = "gpio32", "gpio33";
1164 function = "blsp_i2c2";
1165 drive-strength = <2>;
1169 blsp1_i2c3_default: blsp1-i2c3-default {
1170 pins = "gpio47", "gpio48";
1171 function = "blsp_i2c3";
1172 drive-strength = <2>;
1176 blsp1_i2c3_sleep: blsp1-i2c3-sleep {
1177 pins = "gpio47", "gpio48";
1178 function = "blsp_i2c3";
1179 drive-strength = <2>;
1183 blsp1_i2c4_default: blsp1-i2c4-default {
1184 pins = "gpio10", "gpio11";
1185 function = "blsp_i2c4";
1186 drive-strength = <2>;
1190 blsp1_i2c4_sleep: blsp1-i2c4-sleep {
1191 pins = "gpio10", "gpio11";
1192 function = "blsp_i2c4";
1193 drive-strength = <2>;
1197 blsp1_i2c5_default: blsp1-i2c5-default {
1198 pins = "gpio87", "gpio88";
1199 function = "blsp_i2c5";
1200 drive-strength = <2>;
1204 blsp1_i2c5_sleep: blsp1-i2c5-sleep {
1205 pins = "gpio87", "gpio88";
1206 function = "blsp_i2c5";
1207 drive-strength = <2>;
1211 blsp1_i2c6_default: blsp1-i2c6-default {
1212 pins = "gpio43", "gpio44";
1213 function = "blsp_i2c6";
1214 drive-strength = <2>;
1218 blsp1_i2c6_sleep: blsp1-i2c6-sleep {
1219 pins = "gpio43", "gpio44";
1220 function = "blsp_i2c6";
1221 drive-strength = <2>;
1224 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1225 blsp2_i2c1_default: blsp2-i2c1-default {
1226 pins = "gpio55", "gpio56";
1227 function = "blsp_i2c7";
1228 drive-strength = <2>;
1232 blsp2_i2c1_sleep: blsp2-i2c1-sleep {
1233 pins = "gpio55", "gpio56";
1234 function = "blsp_i2c7";
1235 drive-strength = <2>;
1239 blsp2_i2c2_default: blsp2-i2c2-default {
1240 pins = "gpio6", "gpio7";
1241 function = "blsp_i2c8";
1242 drive-strength = <2>;
1246 blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1247 pins = "gpio6", "gpio7";
1248 function = "blsp_i2c8";
1249 drive-strength = <2>;
1253 blsp2_i2c3_default: blsp2-i2c3-default {
1254 pins = "gpio51", "gpio52";
1255 function = "blsp_i2c9";
1256 drive-strength = <2>;
1260 blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1261 pins = "gpio51", "gpio52";
1262 function = "blsp_i2c9";
1263 drive-strength = <2>;
1267 blsp2_i2c4_default: blsp2-i2c4-default {
1268 pins = "gpio67", "gpio68";
1269 function = "blsp_i2c10";
1270 drive-strength = <2>;
1274 blsp2_i2c4_sleep: blsp2-i2c4-sleep {
1275 pins = "gpio67", "gpio68";
1276 function = "blsp_i2c10";
1277 drive-strength = <2>;
1281 blsp2_i2c5_default: blsp2-i2c5-default {
1282 pins = "gpio60", "gpio61";
1283 function = "blsp_i2c11";
1284 drive-strength = <2>;
1288 blsp2_i2c5_sleep: blsp2-i2c5-sleep {
1289 pins = "gpio60", "gpio61";
1290 function = "blsp_i2c11";
1291 drive-strength = <2>;
1295 blsp2_i2c6_default: blsp2-i2c6-default {
1296 pins = "gpio83", "gpio84";
1297 function = "blsp_i2c12";
1298 drive-strength = <2>;
1302 blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1303 pins = "gpio83", "gpio84";
1304 function = "blsp_i2c12";
1305 drive-strength = <2>;
1310 remoteproc_mss: remoteproc@4080000 {
1311 compatible = "qcom,msm8998-mss-pil";
1312 reg = <0x04080000 0x100>, <0x04180000 0x20>;
1313 reg-names = "qdsp6", "rmb";
1315 interrupts-extended =
1316 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1317 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1318 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1319 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1320 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1321 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1322 interrupt-names = "wdog", "fatal", "ready",
1323 "handover", "stop-ack",
1326 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1327 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1328 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1329 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1330 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1331 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1332 <&rpmcc RPM_SMD_QDSS_CLK>,
1333 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1334 clock-names = "iface", "bus", "mem", "gpll0_mss",
1335 "snoc_axi", "mnoc_axi", "qdss", "xo";
1337 qcom,smem-states = <&modem_smp2p_out 0>;
1338 qcom,smem-state-names = "stop";
1340 resets = <&gcc GCC_MSS_RESTART>;
1341 reset-names = "mss_restart";
1343 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1345 power-domains = <&rpmpd MSM8998_VDDCX>,
1346 <&rpmpd MSM8998_VDDMX>;
1347 power-domain-names = "cx", "mx";
1349 status = "disabled";
1352 memory-region = <&mba_mem>;
1356 memory-region = <&mpss_mem>;
1360 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1362 qcom,remote-pid = <1>;
1363 mboxes = <&apcs_glb 15>;
1367 adreno_gpu: gpu@5000000 {
1368 compatible = "qcom,adreno-540.1", "qcom,adreno";
1369 reg = <0x05000000 0x40000>;
1370 reg-names = "kgsl_3d0_reg_memory";
1372 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1373 <&gpucc RBBMTIMER_CLK>,
1374 <&gcc GCC_BIMC_GFX_CLK>,
1375 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1378 clock-names = "iface",
1385 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1386 iommus = <&adreno_smmu 0>;
1387 operating-points-v2 = <&gpu_opp_table>;
1388 power-domains = <&rpmpd MSM8998_VDDMX>;
1389 status = "disabled";
1391 gpu_opp_table: opp-table {
1392 compatible = "operating-points-v2";
1394 opp-hz = /bits/ 64 <710000097>;
1395 opp-level = <RPM_SMD_LEVEL_TURBO>;
1396 opp-supported-hw = <0xFF>;
1400 opp-hz = /bits/ 64 <670000048>;
1401 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1402 opp-supported-hw = <0xFF>;
1406 opp-hz = /bits/ 64 <596000097>;
1407 opp-level = <RPM_SMD_LEVEL_NOM>;
1408 opp-supported-hw = <0xFF>;
1412 opp-hz = /bits/ 64 <515000097>;
1413 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1414 opp-supported-hw = <0xFF>;
1418 opp-hz = /bits/ 64 <414000000>;
1419 opp-level = <RPM_SMD_LEVEL_SVS>;
1420 opp-supported-hw = <0xFF>;
1424 opp-hz = /bits/ 64 <342000000>;
1425 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1426 opp-supported-hw = <0xFF>;
1430 opp-hz = /bits/ 64 <257000000>;
1431 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1432 opp-supported-hw = <0xFF>;
1437 adreno_smmu: iommu@5040000 {
1438 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1439 reg = <0x05040000 0x10000>;
1440 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1441 <&gcc GCC_BIMC_GFX_CLK>,
1442 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1443 clock-names = "iface", "mem", "mem_iface";
1445 #global-interrupts = <0>;
1448 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1452 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1453 * GPU-CX for SMMU but we need both of them up for Adreno.
1454 * Contemporarily, we also need to manage the VDDMX rpmpd
1455 * domain in the Adreno driver.
1456 * Enable GPU CX/GX GDSCs here so that we can manage the
1457 * SoC VDDMX RPM Power Domain in the Adreno driver.
1459 power-domains = <&gpucc GPU_GX_GDSC>;
1460 status = "disabled";
1463 gpucc: clock-controller@5065000 {
1464 compatible = "qcom,msm8998-gpucc";
1467 #power-domain-cells = <1>;
1468 reg = <0x05065000 0x9000>;
1470 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1471 <&gcc GPLL0_OUT_MAIN>;
1476 remoteproc_slpi: remoteproc@5800000 {
1477 compatible = "qcom,msm8998-slpi-pas";
1478 reg = <0x05800000 0x4040>;
1480 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1481 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1482 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1483 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1484 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1485 interrupt-names = "wdog", "fatal", "ready",
1486 "handover", "stop-ack";
1488 px-supply = <&vreg_lvs2a_1p8>;
1490 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1491 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1492 clock-names = "xo", "aggre2";
1494 memory-region = <&slpi_mem>;
1496 qcom,smem-states = <&slpi_smp2p_out 0>;
1497 qcom,smem-state-names = "stop";
1499 power-domains = <&rpmpd MSM8998_SSCCX>;
1500 power-domain-names = "ssc_cx";
1502 status = "disabled";
1505 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1507 qcom,remote-pid = <3>;
1508 mboxes = <&apcs_glb 27>;
1513 compatible = "arm,coresight-stm", "arm,primecell";
1514 reg = <0x06002000 0x1000>,
1515 <0x16280000 0x180000>;
1516 reg-names = "stm-base", "stm-stimulus-base";
1517 status = "disabled";
1519 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1520 clock-names = "apb_pclk", "atclk";
1525 remote-endpoint = <&funnel0_in7>;
1531 funnel1: funnel@6041000 {
1532 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1533 reg = <0x06041000 0x1000>;
1534 status = "disabled";
1536 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1537 clock-names = "apb_pclk", "atclk";
1541 funnel0_out: endpoint {
1543 <&merge_funnel_in0>;
1549 #address-cells = <1>;
1554 funnel0_in7: endpoint {
1555 remote-endpoint = <&stm_out>;
1561 funnel2: funnel@6042000 {
1562 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1563 reg = <0x06042000 0x1000>;
1564 status = "disabled";
1566 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1567 clock-names = "apb_pclk", "atclk";
1571 funnel1_out: endpoint {
1573 <&merge_funnel_in1>;
1579 #address-cells = <1>;
1584 funnel1_in6: endpoint {
1586 <&apss_merge_funnel_out>;
1592 funnel3: funnel@6045000 {
1593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1594 reg = <0x06045000 0x1000>;
1595 status = "disabled";
1597 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1598 clock-names = "apb_pclk", "atclk";
1602 merge_funnel_out: endpoint {
1610 #address-cells = <1>;
1615 merge_funnel_in0: endpoint {
1623 merge_funnel_in1: endpoint {
1631 replicator1: replicator@6046000 {
1632 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1633 reg = <0x06046000 0x1000>;
1634 status = "disabled";
1636 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1637 clock-names = "apb_pclk", "atclk";
1641 replicator_out: endpoint {
1642 remote-endpoint = <&etr_in>;
1649 replicator_in: endpoint {
1650 remote-endpoint = <&etf_out>;
1657 compatible = "arm,coresight-tmc", "arm,primecell";
1658 reg = <0x06047000 0x1000>;
1659 status = "disabled";
1661 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1662 clock-names = "apb_pclk", "atclk";
1677 <&merge_funnel_out>;
1684 compatible = "arm,coresight-tmc", "arm,primecell";
1685 reg = <0x06048000 0x1000>;
1686 status = "disabled";
1688 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1689 clock-names = "apb_pclk", "atclk";
1703 compatible = "arm,coresight-etm4x", "arm,primecell";
1704 reg = <0x07840000 0x1000>;
1705 status = "disabled";
1707 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1708 clock-names = "apb_pclk", "atclk";
1714 etm0_out: endpoint {
1723 compatible = "arm,coresight-etm4x", "arm,primecell";
1724 reg = <0x07940000 0x1000>;
1725 status = "disabled";
1727 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1728 clock-names = "apb_pclk", "atclk";
1734 etm1_out: endpoint {
1743 compatible = "arm,coresight-etm4x", "arm,primecell";
1744 reg = <0x07a40000 0x1000>;
1745 status = "disabled";
1747 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1748 clock-names = "apb_pclk", "atclk";
1754 etm2_out: endpoint {
1763 compatible = "arm,coresight-etm4x", "arm,primecell";
1764 reg = <0x07b40000 0x1000>;
1765 status = "disabled";
1767 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1768 clock-names = "apb_pclk", "atclk";
1774 etm3_out: endpoint {
1782 funnel4: funnel@7b60000 { /* APSS Funnel */
1783 compatible = "arm,coresight-etm4x", "arm,primecell";
1784 reg = <0x07b60000 0x1000>;
1785 status = "disabled";
1787 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1788 clock-names = "apb_pclk", "atclk";
1792 apss_funnel_out: endpoint {
1794 <&apss_merge_funnel_in>;
1800 #address-cells = <1>;
1805 apss_funnel_in0: endpoint {
1813 apss_funnel_in1: endpoint {
1821 apss_funnel_in2: endpoint {
1829 apss_funnel_in3: endpoint {
1837 apss_funnel_in4: endpoint {
1845 apss_funnel_in5: endpoint {
1853 apss_funnel_in6: endpoint {
1861 apss_funnel_in7: endpoint {
1869 funnel5: funnel@7b70000 {
1870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1871 reg = <0x07b70000 0x1000>;
1872 status = "disabled";
1874 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1875 clock-names = "apb_pclk", "atclk";
1879 apss_merge_funnel_out: endpoint {
1888 apss_merge_funnel_in: endpoint {
1897 compatible = "arm,coresight-etm4x", "arm,primecell";
1898 reg = <0x07c40000 0x1000>;
1899 status = "disabled";
1901 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1902 clock-names = "apb_pclk", "atclk";
1908 etm4_out: endpoint {
1909 remote-endpoint = <&apss_funnel_in4>;
1916 compatible = "arm,coresight-etm4x", "arm,primecell";
1917 reg = <0x07d40000 0x1000>;
1918 status = "disabled";
1920 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1921 clock-names = "apb_pclk", "atclk";
1927 etm5_out: endpoint {
1928 remote-endpoint = <&apss_funnel_in5>;
1935 compatible = "arm,coresight-etm4x", "arm,primecell";
1936 reg = <0x07e40000 0x1000>;
1937 status = "disabled";
1939 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1940 clock-names = "apb_pclk", "atclk";
1946 etm6_out: endpoint {
1947 remote-endpoint = <&apss_funnel_in6>;
1954 compatible = "arm,coresight-etm4x", "arm,primecell";
1955 reg = <0x07f40000 0x1000>;
1956 status = "disabled";
1958 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1959 clock-names = "apb_pclk", "atclk";
1965 etm7_out: endpoint {
1966 remote-endpoint = <&apss_funnel_in7>;
1973 compatible = "qcom,rpm-stats";
1974 reg = <0x00290000 0x10000>;
1977 spmi_bus: spmi@800f000 {
1978 compatible = "qcom,spmi-pmic-arb";
1979 reg = <0x0800f000 0x1000>,
1980 <0x08400000 0x1000000>,
1981 <0x09400000 0x1000000>,
1982 <0x0a400000 0x220000>,
1983 <0x0800a000 0x3000>;
1984 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1985 interrupt-names = "periph_irq";
1986 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1989 #address-cells = <2>;
1991 interrupt-controller;
1992 #interrupt-cells = <4>;
1997 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1998 reg = <0x0a8f8800 0x400>;
1999 status = "disabled";
2000 #address-cells = <1>;
2004 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2005 <&gcc GCC_USB30_MASTER_CLK>,
2006 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2007 <&gcc GCC_USB30_SLEEP_CLK>,
2008 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2009 clock-names = "cfg_noc",
2015 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2016 <&gcc GCC_USB30_MASTER_CLK>;
2017 assigned-clock-rates = <19200000>, <120000000>;
2019 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2021 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2023 power-domains = <&gcc USB_30_GDSC>;
2025 resets = <&gcc GCC_USB_30_BCR>;
2027 usb3_dwc3: usb@a800000 {
2028 compatible = "snps,dwc3";
2029 reg = <0x0a800000 0xcd00>;
2030 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2031 snps,dis_u2_susphy_quirk;
2032 snps,dis_enblslpm_quirk;
2033 phys = <&qusb2phy>, <&usb1_ssphy>;
2034 phy-names = "usb2-phy", "usb3-phy";
2035 snps,has-lpm-erratum;
2036 snps,hird-threshold = /bits/ 8 <0x10>;
2040 usb3phy: phy@c010000 {
2041 compatible = "qcom,msm8998-qmp-usb3-phy";
2042 reg = <0x0c010000 0x18c>;
2043 status = "disabled";
2044 #address-cells = <1>;
2048 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2049 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2050 <&gcc GCC_USB3_CLKREF_CLK>;
2051 clock-names = "aux", "cfg_ahb", "ref";
2053 resets = <&gcc GCC_USB3_PHY_BCR>,
2054 <&gcc GCC_USB3PHY_PHY_BCR>;
2055 reset-names = "phy", "common";
2057 usb1_ssphy: phy@c010200 {
2058 reg = <0xc010200 0x128>,
2065 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
2066 clock-names = "pipe0";
2067 clock-output-names = "usb3_phy_pipe_clk_src";
2071 qusb2phy: phy@c012000 {
2072 compatible = "qcom,msm8998-qusb2-phy";
2073 reg = <0x0c012000 0x2a8>;
2074 status = "disabled";
2077 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2078 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2079 clock-names = "cfg_ahb", "ref";
2081 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2083 nvmem-cells = <&qusb2_hstx_trim>;
2086 sdhc2: mmc@c0a4900 {
2087 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2088 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2089 reg-names = "hc", "core";
2091 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2093 interrupt-names = "hc_irq", "pwr_irq";
2095 clock-names = "iface", "core", "xo";
2096 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2097 <&gcc GCC_SDCC2_APPS_CLK>,
2100 status = "disabled";
2103 blsp1_dma: dma-controller@c144000 {
2104 compatible = "qcom,bam-v1.7.0";
2105 reg = <0x0c144000 0x25000>;
2106 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2107 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2108 clock-names = "bam_clk";
2111 qcom,controlled-remotely;
2112 num-channels = <18>;
2116 blsp1_uart3: serial@c171000 {
2117 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2118 reg = <0x0c171000 0x1000>;
2119 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2120 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2121 <&gcc GCC_BLSP1_AHB_CLK>;
2122 clock-names = "core", "iface";
2123 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2124 dma-names = "tx", "rx";
2125 pinctrl-names = "default";
2126 pinctrl-0 = <&blsp1_uart3_on>;
2127 status = "disabled";
2130 blsp1_i2c1: i2c@c175000 {
2131 compatible = "qcom,i2c-qup-v2.2.1";
2132 reg = <0x0c175000 0x600>;
2133 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2135 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2136 <&gcc GCC_BLSP1_AHB_CLK>;
2137 clock-names = "core", "iface";
2138 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2139 dma-names = "tx", "rx";
2140 pinctrl-names = "default", "sleep";
2141 pinctrl-0 = <&blsp1_i2c1_default>;
2142 pinctrl-1 = <&blsp1_i2c1_sleep>;
2143 clock-frequency = <400000>;
2145 status = "disabled";
2146 #address-cells = <1>;
2150 blsp1_i2c2: i2c@c176000 {
2151 compatible = "qcom,i2c-qup-v2.2.1";
2152 reg = <0x0c176000 0x600>;
2153 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2155 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2156 <&gcc GCC_BLSP1_AHB_CLK>;
2157 clock-names = "core", "iface";
2158 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2159 dma-names = "tx", "rx";
2160 pinctrl-names = "default", "sleep";
2161 pinctrl-0 = <&blsp1_i2c2_default>;
2162 pinctrl-1 = <&blsp1_i2c2_sleep>;
2163 clock-frequency = <400000>;
2165 status = "disabled";
2166 #address-cells = <1>;
2170 blsp1_i2c3: i2c@c177000 {
2171 compatible = "qcom,i2c-qup-v2.2.1";
2172 reg = <0x0c177000 0x600>;
2173 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2175 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2176 <&gcc GCC_BLSP1_AHB_CLK>;
2177 clock-names = "core", "iface";
2178 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2179 dma-names = "tx", "rx";
2180 pinctrl-names = "default", "sleep";
2181 pinctrl-0 = <&blsp1_i2c3_default>;
2182 pinctrl-1 = <&blsp1_i2c3_sleep>;
2183 clock-frequency = <400000>;
2185 status = "disabled";
2186 #address-cells = <1>;
2190 blsp1_i2c4: i2c@c178000 {
2191 compatible = "qcom,i2c-qup-v2.2.1";
2192 reg = <0x0c178000 0x600>;
2193 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2195 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2196 <&gcc GCC_BLSP1_AHB_CLK>;
2197 clock-names = "core", "iface";
2198 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2199 dma-names = "tx", "rx";
2200 pinctrl-names = "default", "sleep";
2201 pinctrl-0 = <&blsp1_i2c4_default>;
2202 pinctrl-1 = <&blsp1_i2c4_sleep>;
2203 clock-frequency = <400000>;
2205 status = "disabled";
2206 #address-cells = <1>;
2210 blsp1_i2c5: i2c@c179000 {
2211 compatible = "qcom,i2c-qup-v2.2.1";
2212 reg = <0x0c179000 0x600>;
2213 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2215 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2216 <&gcc GCC_BLSP1_AHB_CLK>;
2217 clock-names = "core", "iface";
2218 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2219 dma-names = "tx", "rx";
2220 pinctrl-names = "default", "sleep";
2221 pinctrl-0 = <&blsp1_i2c5_default>;
2222 pinctrl-1 = <&blsp1_i2c5_sleep>;
2223 clock-frequency = <400000>;
2225 status = "disabled";
2226 #address-cells = <1>;
2230 blsp1_i2c6: i2c@c17a000 {
2231 compatible = "qcom,i2c-qup-v2.2.1";
2232 reg = <0x0c17a000 0x600>;
2233 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2235 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2236 <&gcc GCC_BLSP1_AHB_CLK>;
2237 clock-names = "core", "iface";
2238 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2239 dma-names = "tx", "rx";
2240 pinctrl-names = "default", "sleep";
2241 pinctrl-0 = <&blsp1_i2c6_default>;
2242 pinctrl-1 = <&blsp1_i2c6_sleep>;
2243 clock-frequency = <400000>;
2245 status = "disabled";
2246 #address-cells = <1>;
2250 blsp2_dma: dma-controller@c184000 {
2251 compatible = "qcom,bam-v1.7.0";
2252 reg = <0x0c184000 0x25000>;
2253 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2254 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2255 clock-names = "bam_clk";
2258 qcom,controlled-remotely;
2259 num-channels = <18>;
2263 blsp2_uart1: serial@c1b0000 {
2264 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2265 reg = <0x0c1b0000 0x1000>;
2266 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2267 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2268 <&gcc GCC_BLSP2_AHB_CLK>;
2269 clock-names = "core", "iface";
2270 status = "disabled";
2273 blsp2_i2c1: i2c@c1b5000 {
2274 compatible = "qcom,i2c-qup-v2.2.1";
2275 reg = <0x0c1b5000 0x600>;
2276 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2278 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2279 <&gcc GCC_BLSP2_AHB_CLK>;
2280 clock-names = "core", "iface";
2281 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2282 dma-names = "tx", "rx";
2283 pinctrl-names = "default", "sleep";
2284 pinctrl-0 = <&blsp2_i2c1_default>;
2285 pinctrl-1 = <&blsp2_i2c1_sleep>;
2286 clock-frequency = <400000>;
2288 status = "disabled";
2289 #address-cells = <1>;
2293 blsp2_i2c2: i2c@c1b6000 {
2294 compatible = "qcom,i2c-qup-v2.2.1";
2295 reg = <0x0c1b6000 0x600>;
2296 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2298 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2299 <&gcc GCC_BLSP2_AHB_CLK>;
2300 clock-names = "core", "iface";
2301 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2302 dma-names = "tx", "rx";
2303 pinctrl-names = "default", "sleep";
2304 pinctrl-0 = <&blsp2_i2c2_default>;
2305 pinctrl-1 = <&blsp2_i2c2_sleep>;
2306 clock-frequency = <400000>;
2308 status = "disabled";
2309 #address-cells = <1>;
2313 blsp2_i2c3: i2c@c1b7000 {
2314 compatible = "qcom,i2c-qup-v2.2.1";
2315 reg = <0x0c1b7000 0x600>;
2316 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2318 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2319 <&gcc GCC_BLSP2_AHB_CLK>;
2320 clock-names = "core", "iface";
2321 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2322 dma-names = "tx", "rx";
2323 pinctrl-names = "default", "sleep";
2324 pinctrl-0 = <&blsp2_i2c3_default>;
2325 pinctrl-1 = <&blsp2_i2c3_sleep>;
2326 clock-frequency = <400000>;
2328 status = "disabled";
2329 #address-cells = <1>;
2333 blsp2_i2c4: i2c@c1b8000 {
2334 compatible = "qcom,i2c-qup-v2.2.1";
2335 reg = <0x0c1b8000 0x600>;
2336 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2338 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2339 <&gcc GCC_BLSP2_AHB_CLK>;
2340 clock-names = "core", "iface";
2341 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2342 dma-names = "tx", "rx";
2343 pinctrl-names = "default", "sleep";
2344 pinctrl-0 = <&blsp2_i2c4_default>;
2345 pinctrl-1 = <&blsp2_i2c4_sleep>;
2346 clock-frequency = <400000>;
2348 status = "disabled";
2349 #address-cells = <1>;
2353 blsp2_i2c5: i2c@c1b9000 {
2354 compatible = "qcom,i2c-qup-v2.2.1";
2355 reg = <0x0c1b9000 0x600>;
2356 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2358 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2359 <&gcc GCC_BLSP2_AHB_CLK>;
2360 clock-names = "core", "iface";
2361 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2362 dma-names = "tx", "rx";
2363 pinctrl-names = "default", "sleep";
2364 pinctrl-0 = <&blsp2_i2c5_default>;
2365 pinctrl-1 = <&blsp2_i2c5_sleep>;
2366 clock-frequency = <400000>;
2368 status = "disabled";
2369 #address-cells = <1>;
2373 blsp2_i2c6: i2c@c1ba000 {
2374 compatible = "qcom,i2c-qup-v2.2.1";
2375 reg = <0x0c1ba000 0x600>;
2376 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2378 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2379 <&gcc GCC_BLSP2_AHB_CLK>;
2380 clock-names = "core", "iface";
2381 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2382 dma-names = "tx", "rx";
2383 pinctrl-names = "default", "sleep";
2384 pinctrl-0 = <&blsp2_i2c6_default>;
2385 pinctrl-1 = <&blsp2_i2c6_sleep>;
2386 clock-frequency = <400000>;
2388 status = "disabled";
2389 #address-cells = <1>;
2393 mmcc: clock-controller@c8c0000 {
2394 compatible = "qcom,mmcc-msm8998";
2397 #power-domain-cells = <1>;
2398 reg = <0xc8c0000 0x40000>;
2409 "core_bi_pll_test_se";
2410 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2411 <&gcc GCC_MMSS_GPLL0_CLK>,
2422 mmss_smmu: iommu@cd00000 {
2423 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
2424 reg = <0x0cd00000 0x40000>;
2427 clocks = <&mmcc MNOC_AHB_CLK>,
2428 <&mmcc BIMC_SMMU_AHB_CLK>,
2429 <&mmcc BIMC_SMMU_AXI_CLK>;
2430 clock-names = "iface-mm",
2434 #global-interrupts = <0>;
2436 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2437 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2438 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2439 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2440 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2441 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2442 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2443 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2444 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2445 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2446 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2447 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2448 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2449 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2450 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2451 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2452 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2453 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2454 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2455 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2457 power-domains = <&mmcc BIMC_SMMU_GDSC>;
2460 remoteproc_adsp: remoteproc@17300000 {
2461 compatible = "qcom,msm8998-adsp-pas";
2462 reg = <0x17300000 0x4040>;
2464 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2465 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2466 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2467 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2468 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2469 interrupt-names = "wdog", "fatal", "ready",
2470 "handover", "stop-ack";
2472 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2475 memory-region = <&adsp_mem>;
2477 qcom,smem-states = <&adsp_smp2p_out 0>;
2478 qcom,smem-state-names = "stop";
2480 power-domains = <&rpmpd MSM8998_VDDCX>;
2481 power-domain-names = "cx";
2483 status = "disabled";
2486 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2488 qcom,remote-pid = <2>;
2489 mboxes = <&apcs_glb 9>;
2493 apcs_glb: mailbox@17911000 {
2494 compatible = "qcom,msm8998-apcs-hmss-global";
2495 reg = <0x17911000 0x1000>;
2501 #address-cells = <1>;
2504 compatible = "arm,armv7-timer-mem";
2505 reg = <0x17920000 0x1000>;
2509 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2510 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2511 reg = <0x17921000 0x1000>,
2512 <0x17922000 0x1000>;
2517 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2518 reg = <0x17923000 0x1000>;
2519 status = "disabled";
2524 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2525 reg = <0x17924000 0x1000>;
2526 status = "disabled";
2531 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2532 reg = <0x17925000 0x1000>;
2533 status = "disabled";
2538 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2539 reg = <0x17926000 0x1000>;
2540 status = "disabled";
2545 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2546 reg = <0x17927000 0x1000>;
2547 status = "disabled";
2552 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2553 reg = <0x17928000 0x1000>;
2554 status = "disabled";
2558 intc: interrupt-controller@17a00000 {
2559 compatible = "arm,gic-v3";
2560 reg = <0x17a00000 0x10000>, /* GICD */
2561 <0x17b00000 0x100000>; /* GICR * 8 */
2562 #interrupt-cells = <3>;
2563 #address-cells = <1>;
2566 interrupt-controller;
2567 #redistributor-regions = <1>;
2568 redistributor-stride = <0x0 0x20000>;
2569 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2572 wifi: wifi@18800000 {
2573 compatible = "qcom,wcn3990-wifi";
2574 status = "disabled";
2575 reg = <0x18800000 0x800000>;
2576 reg-names = "membase";
2577 memory-region = <&wlan_msa_mem>;
2578 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
2579 clock-names = "cxo_ref_clk_pin";
2581 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2582 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2583 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
2584 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
2585 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
2586 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2587 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2588 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2589 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2590 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2591 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2592 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
2593 iommus = <&anoc2_smmu 0x1900>,
2594 <&anoc2_smmu 0x1901>;
2595 qcom,snoc-host-cap-8bit-quirk;