arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * OnePlus 5(T) (cheeseburger / dumpling) common device tree source based on msm8998-mtp.dtsi
   4  *
   5  * Copyright (c) 2021, Jami Kettunen <jamipkettunen@gmail.com>
   6  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   7  */
   8
   9 /dts-v1/;
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
  13 #include "msm8998.dtsi"
  14 #include "pm8005.dtsi"
  15 #include "pm8998.dtsi"
  16 #include "pmi8998.dtsi"
  17
  18 / {
  19         /* Required for bootloader to select correct board */
  20         qcom,msm-id = <292 0x20001>; /* 8998 v2.1 */
  21
  22         chosen {
  23                 #address-cells = <2>;
  24                 #size-cells = <2>;
  25                 ranges;
  26
  27                 /* Use display framebuffer setup by the UEFI XBL bootloader for simplefb */
  28                 framebuffer0: framebuffer@9d400000 {
  29                         compatible = "simple-framebuffer";
  30                         reg = <0x0 0x9d400000 0x0 0x2400000>;
  31                         width = <1080>;
  32                         height = <1920>;
  33                         stride = <(1080 * 4)>;
  34                         format = "a8r8g8b8";
  35                         /*
  36                         * That's a lot of clocks, but it's necessary due
  37                         * to unused clk cleanup & no panel driver yet..
  38                         */
  39                         clocks = <&mmcc MDSS_AHB_CLK>,
  40                                  <&mmcc MDSS_AXI_CLK>,
  41                                  <&mmcc MDSS_VSYNC_CLK>,
  42                                  <&mmcc MDSS_MDP_CLK>,
  43                                  <&mmcc MDSS_BYTE0_CLK>,
  44                                  <&mmcc MDSS_BYTE0_INTF_CLK>,
  45                                  <&mmcc MDSS_PCLK0_CLK>,
  46                                  <&mmcc MDSS_ESC0_CLK>;
  47                         power-domains = <&mmcc MDSS_GDSC>;
  48                 };
  49         };
  50
  51         reserved-memory {
  52                 /* Bootloader display framebuffer region */
  53                 cont_splash_mem: memory@9d400000 {
  54                         reg = <0x0 0x9d400000 0x0 0x2400000>;
  55                         no-map;
  56                 };
  57
  58                 /* For getting crash logs using Android downstream kernels */
  59                 ramoops@ac000000 {
  60                         compatible = "ramoops";
  61                         reg = <0x0 0xac000000 0x0 0x200000>;
  62                         console-size = <0x80000>;
  63                         pmsg-size = <0x40000>;
  64                         record-size = <0x8000>;
  65                         ftrace-size = <0x20000>;
  66                 };
  67
  68                 /*
  69                  * The following memory regions on downstream are "dynamically allocated"
  70                  * but given the same addresses every time. Hard code them as these addresses
  71                  * are where the OnePlus signed firmware expects them to be.
  72                  */
  73                 ipa_fws_region: ipa@f6800000 {
  74                         compatible = "shared-dma-pool";
  75                         reg = <0x0 0xf6800000 0x0 0x5000>;
  76                         no-map;
  77                 };
  78                 zap_shader_region: gpu@f6900000 {
  79                         compatible = "shared-dma-pool";
  80                         reg = <0x0 0xf6900000 0x0 0x2000>;
  81                         no-map;
  82                 };
  83         };
  84
  85         gpio-keys {
  86                 compatible = "gpio-keys";
  87                 label = "Volume buttons";
  88                 autorepeat;
  89
  90                 pinctrl-names = "default";
  91                 pinctrl-0 = <&vol_keys_default>;
  92
  93                 button-vol-down {
  94                         label = "Volume down";
  95                         gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>;
  96                         linux,code = <KEY_VOLUMEDOWN>;
  97                         debounce-interval = <15>;
  98                         wakeup-source;
  99                 };
 100
 101                 button-vol-up {
 102                         label = "Volume up";
 103                         gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
 104                         linux,code = <KEY_VOLUMEUP>;
 105                         debounce-interval = <15>;
 106                         wakeup-source;
 107                 };
 108         };
 109
 110         gpio-hall-sensor {
 111                 compatible = "gpio-keys";
 112                 label = "Hall effect sensor";
 113
 114                 pinctrl-names = "default";
 115                 pinctrl-0 = <&hall_sensor_default>;
 116
 117                 event-hall-sensor {
 118                         label = "Hall Effect Sensor";
 119                         gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
 120                         linux,input-type = <EV_SW>;
 121                         linux,code = <SW_LID>;
 122                         linux,can-disable;
 123                         wakeup-source;
 124                 };
 125         };
 126
 127         vph_pwr: vph-pwr-regulator {
 128                 compatible = "regulator-fixed";
 129                 regulator-name = "vph_pwr";
 130                 regulator-always-on;
 131                 regulator-boot-on;
 132         };
 133 };
 134
 135 /*
 136  * OnePlus' ADSP firmware requires 30 MiB in total, so increase the adsp_mem
 137  * region by 4 MiB to account for this while relocating the other now
 138  * conflicting memory nodes accordingly.
 139  */
 140 &adsp_mem {
 141         reg = <0x0 0x8b200000 0x0 0x1e00000>;
 142 };
 143 &mpss_mem {
 144         reg = <0x0 0x8d000000 0x0 0x7000000>;
 145 };
 146 &venus_mem {
 147         reg = <0x0 0x94000000 0x0 0x500000>;
 148 };
 149 &mba_mem {
 150         reg = <0x0 0x94500000 0x0 0x200000>;
 151 };
 152 &slpi_mem {
 153         reg = <0x0 0x94700000 0x0 0xf00000>;
 154 };
 155 &ipa_fw_mem {
 156         reg = <0x0 0x95600000 0x0 0x10000>;
 157 };
 158 &ipa_gsi_mem {
 159         reg = <0x0 0x95610000 0x0 0x5000>;
 160 };
 161 &gpu_mem {
 162         reg = <0x0 0x95615000 0x0 0x100000>;
 163 };
 164 &wlan_msa_mem {
 165         reg = <0x0 0x95715000 0x0 0x100000>;
 166 };
 167
 168 &blsp1_i2c5 {
 169         status = "okay";
 170
 171         touchscreen@20 {
 172                 compatible = "syna,rmi4-i2c";
 173                 reg = <0x20>;
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176
 177                 interrupt-parent = <&tlmm>;
 178                 interrupts = <125 IRQ_TYPE_EDGE_FALLING>;
 179
 180                 pinctrl-names = "default";
 181                 pinctrl-0 = <&ts_int_active &ts_reset_active>;
 182
 183                 vdd-supply = <&vreg_l28_3p0>;
 184                 vio-supply = <&vreg_l6a_1p8>;
 185
 186                 syna,reset-delay-ms = <20>;
 187                 syna,startup-delay-ms = <20>;
 188
 189                 rmi4-f01@1 {
 190                         reg = <0x01>;
 191                         syna,nosleep-mode = <1>;
 192                 };
 193
 194                 rmi4_f12: rmi4-f12@12 {
 195                         reg = <0x12>;
 196                         syna,rezero-wait-ms = <20>;
 197                         syna,sensor-type = <1>;
 198                         touchscreen-x-mm = <68>;
 199                         touchscreen-y-mm = <122>;
 200                 };
 201         };
 202 };
 203
 204 &blsp1_i2c6 {
 205         status = "okay";
 206
 207         nfc@28 {
 208                 compatible = "nxp,nxp-nci-i2c";
 209                 reg = <0x28>;
 210
 211                 interrupt-parent = <&tlmm>;
 212                 interrupts = <92 IRQ_TYPE_LEVEL_HIGH>;
 213
 214                 enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>;
 215
 216                 pinctrl-names = "default";
 217                 pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
 218         };
 219 };
 220
 221 &blsp1_uart3 {
 222         status = "okay";
 223
 224         bluetooth {
 225                 compatible = "qcom,wcn3990-bt";
 226
 227                 vddio-supply = <&vreg_s4a_1p8>;
 228                 vddxo-supply = <&vreg_l7a_1p8>;
 229                 vddrf-supply = <&vreg_l17a_1p3>;
 230                 vddch0-supply = <&vreg_l25a_3p3>;
 231                 max-speed = <3200000>;
 232         };
 233 };
 234
 235 &blsp1_uart3_on {
 236         rx-pins {
 237                 /delete-property/ bias-disable;
 238                 /*
 239                  * Configure a pull-up on 46 (RX). This is needed to
 240                  * avoid garbage data when the TX pin of the Bluetooth
 241                  * module is in tri-state (module powered off or not
 242                  * driving the signal yet).
 243                  */
 244                 bias-pull-up;
 245         };
 246
 247         cts-pins {
 248                 /delete-property/ bias-disable;
 249                 /*
 250                  * Configure a pull-down on 47 (CTS) to match the pull
 251                  * of the Bluetooth module.
 252                  */
 253                 bias-pull-down;
 254         };
 255 };
 256
 257 &blsp2_uart1 {
 258         status = "okay";
 259 };
 260
 261 &pm8005_regulators {
 262         /* VDD_GFX supply */
 263         pm8005_s1: s1 {
 264                 regulator-min-microvolt = <524000>;
 265                 regulator-max-microvolt = <1100000>;
 266                 regulator-enable-ramp-delay = <500>;
 267                 /* Hack until we rig up the gpu consumer */
 268                 regulator-always-on;
 269         };
 270 };
 271
 272 &pm8998_gpios {
 273         vol_keys_default: vol-keys-state {
 274                 pins = "gpio5", "gpio6";
 275                 function = "normal";
 276                 bias-pull-up;
 277                 input-enable;
 278                 qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
 279         };
 280 };
 281
 282 &qusb2phy {
 283         status = "okay";
 284
 285         vdd-supply = <&vreg_l1a_0p875>;
 286         vdda-pll-supply = <&vreg_l12a_1p8>;
 287         vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
 288 };
 289
 290 &rpm_requests {
 291         regulators-0 {
 292                 compatible = "qcom,rpm-pm8998-regulators";
 293
 294                 vdd_s1-supply = <&vph_pwr>;
 295                 vdd_s2-supply = <&vph_pwr>;
 296                 vdd_s3-supply = <&vph_pwr>;
 297                 vdd_s4-supply = <&vph_pwr>;
 298                 vdd_s5-supply = <&vph_pwr>;
 299                 vdd_s6-supply = <&vph_pwr>;
 300                 vdd_s7-supply = <&vph_pwr>;
 301                 vdd_s8-supply = <&vph_pwr>;
 302                 vdd_s9-supply = <&vph_pwr>;
 303                 vdd_s10-supply = <&vph_pwr>;
 304                 vdd_s11-supply = <&vph_pwr>;
 305                 vdd_s12-supply = <&vph_pwr>;
 306                 vdd_s13-supply = <&vph_pwr>;
 307                 vdd_l1_l27-supply = <&vreg_s7a_1p025>;
 308                 vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
 309                 vdd_l3_l11-supply = <&vreg_s7a_1p025>;
 310                 vdd_l4_l5-supply = <&vreg_s7a_1p025>;
 311                 vdd_l6-supply = <&vreg_s5a_2p04>;
 312                 vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
 313                 vdd_l9-supply = <&vreg_bob>;
 314                 vdd_l10_l23_l25-supply = <&vreg_bob>;
 315                 vdd_l13_l19_l21-supply = <&vreg_bob>;
 316                 vdd_l16_l28-supply = <&vreg_bob>;
 317                 vdd_l18_l22-supply = <&vreg_bob>;
 318                 vdd_l20_l24-supply = <&vreg_bob>;
 319                 vdd_l26-supply = <&vreg_s3a_1p35>;
 320                 vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
 321
 322                 vreg_s3a_1p35: s3 {
 323                         regulator-min-microvolt = <1352000>;
 324                         regulator-max-microvolt = <1352000>;
 325                 };
 326
 327                 vreg_s4a_1p8: s4 {
 328                         regulator-min-microvolt = <1800000>;
 329                         regulator-max-microvolt = <1800000>;
 330                         regulator-allow-set-load;
 331                 };
 332
 333                 vreg_s5a_2p04: s5 {
 334                         regulator-min-microvolt = <1904000>;
 335                         regulator-max-microvolt = <2040000>;
 336                 };
 337
 338                 vreg_s7a_1p025: s7 {
 339                         regulator-min-microvolt = <900000>;
 340                         regulator-max-microvolt = <1028000>;
 341                 };
 342
 343                 vreg_l1a_0p875: l1 {
 344                         regulator-min-microvolt = <880000>;
 345                         regulator-max-microvolt = <880000>;
 346                 };
 347
 348                 vreg_l2a_1p2: l2 {
 349                         regulator-min-microvolt = <1200000>;
 350                         regulator-max-microvolt = <1200000>;
 351                 };
 352
 353                 vreg_l3a_1p0: l3 {
 354                         regulator-min-microvolt = <1000000>;
 355                         regulator-max-microvolt = <1000000>;
 356                 };
 357
 358                 vreg_l5a_0p8: l5 {
 359                         regulator-min-microvolt = <800000>;
 360                         regulator-max-microvolt = <800000>;
 361                 };
 362
 363                 vreg_l6a_1p8: l6 {
 364                         regulator-min-microvolt = <1808000>;
 365                         regulator-max-microvolt = <1808000>;
 366                 };
 367
 368                 vreg_l7a_1p8: l7 {
 369                         regulator-min-microvolt = <1800000>;
 370                         regulator-max-microvolt = <1800000>;
 371                 };
 372
 373                 vreg_l8a_1p2: l8 {
 374                         regulator-min-microvolt = <1200000>;
 375                         regulator-max-microvolt = <1200000>;
 376                 };
 377
 378                 vreg_l9a_1p8: l9 {
 379                         regulator-min-microvolt = <1808000>;
 380                         regulator-max-microvolt = <2960000>;
 381                 };
 382
 383                 vreg_l10a_1p8: l10 {
 384                         regulator-min-microvolt = <1808000>;
 385                         regulator-max-microvolt = <2960000>;
 386                 };
 387
 388                 vreg_l11a_1p0: l11 {
 389                         regulator-min-microvolt = <1000000>;
 390                         regulator-max-microvolt = <1000000>;
 391                 };
 392
 393                 vreg_l12a_1p8: l12 {
 394                         regulator-min-microvolt = <1800000>;
 395                         regulator-max-microvolt = <1800000>;
 396                 };
 397
 398                 vreg_l13a_2p95: l13 {
 399                         regulator-min-microvolt = <1808000>;
 400                         regulator-max-microvolt = <2960000>;
 401                 };
 402
 403                 vreg_l14a_1p88: l14 {
 404                         regulator-min-microvolt = <1880000>;
 405                         regulator-max-microvolt = <1880000>;
 406                 };
 407
 408                 vreg_l15a_1p8: l15 {
 409                         regulator-min-microvolt = <1800000>;
 410                         regulator-max-microvolt = <1800000>;
 411                 };
 412
 413                 vreg_l16a_2p7: l16 {
 414                         regulator-min-microvolt = <2704000>;
 415                         regulator-max-microvolt = <2704000>;
 416                 };
 417
 418                 vreg_l17a_1p3: l17 {
 419                         regulator-min-microvolt = <1304000>;
 420                         regulator-max-microvolt = <1304000>;
 421                 };
 422
 423                 vreg_l18a_2p7: l18 {
 424                         regulator-min-microvolt = <2704000>;
 425                         regulator-max-microvolt = <2704000>;
 426                 };
 427
 428                 vreg_l19a_3p0: l19 {
 429                         regulator-min-microvolt = <3008000>;
 430                         regulator-max-microvolt = <3008000>;
 431                 };
 432
 433                 vreg_l20a_2p95: l20 {
 434                         regulator-min-microvolt = <2960000>;
 435                         regulator-max-microvolt = <2960000>;
 436                         regulator-allow-set-load;
 437                 };
 438                 vreg_l21a_2p95: l21 {
 439                         regulator-min-microvolt = <2960000>;
 440                         regulator-max-microvolt = <2960000>;
 441                         regulator-system-load = <800000>;
 442                         regulator-allow-set-load;
 443                 };
 444
 445                 vreg_l22a_2p85: l22 {
 446                         regulator-min-microvolt = <2864000>;
 447                         regulator-max-microvolt = <2864000>;
 448                 };
 449
 450                 vreg_l23a_3p3: l23 {
 451                         regulator-min-microvolt = <3312000>;
 452                         regulator-max-microvolt = <3312000>;
 453                 };
 454
 455                 vreg_l24a_3p075: l24 {
 456                         regulator-min-microvolt = <3088000>;
 457                         regulator-max-microvolt = <3088000>;
 458                 };
 459
 460                 vreg_l25a_3p3: l25 {
 461                         regulator-min-microvolt = <3104000>;
 462                         regulator-max-microvolt = <3312000>;
 463                 };
 464
 465                 vreg_l26a_1p2: l26 {
 466                         regulator-min-microvolt = <1200000>;
 467                         regulator-max-microvolt = <1200000>;
 468                         regulator-allow-set-load;
 469                 };
 470
 471                 vreg_l28_3p0: l28 {
 472                         regulator-min-microvolt = <3008000>;
 473                         regulator-max-microvolt = <3008000>;
 474                 };
 475
 476                 vreg_lvs1a_1p8: lvs1 { };
 477                 vreg_lvs2a_1p8: lvs2 { };
 478         };
 479
 480         regulators-1 {
 481                 compatible = "qcom,rpm-pmi8998-regulators";
 482
 483                 vdd_bob-supply = <&vph_pwr>;
 484
 485                 vreg_bob: bob {
 486                         regulator-min-microvolt = <3312000>;
 487                         regulator-max-microvolt = <3600000>;
 488                 };
 489         };
 490 };
 491
 492 &tlmm {
 493         gpio-reserved-ranges = <0 4>, <81 4>;
 494
 495         hall_sensor_default: hall-sensor-default-state {
 496                 pins = "gpio124";
 497                 function = "gpio";
 498                 drive-strength = <2>;
 499                 bias-disable;
 500         };
 501
 502         ts_int_active: ts-int-active-state {
 503                 pins = "gpio125";
 504                 function = "gpio";
 505                 drive-strength = <8>;
 506                 bias-pull-up;
 507         };
 508
 509         ts_reset_active: ts-reset-active-state {
 510                 pins = "gpio89";
 511                 function = "gpio";
 512                 drive-strength = <8>;
 513                 bias-pull-up;
 514         };
 515
 516         nfc_int_active: nfc-int-active-state {
 517                 pins = "gpio92";
 518                 function = "gpio";
 519                 drive-strength = <6>;
 520                 bias-pull-up;
 521         };
 522
 523         nfc_enable_active: nfc-enable-active-state {
 524                 pins = "gpio12", "gpio116";
 525                 function = "gpio";
 526                 drive-strength = <6>;
 527                 bias-pull-up;
 528         };
 529 };
 530
 531 &ufshc {
 532         status = "okay";
 533
 534         vcc-supply = <&vreg_l20a_2p95>;
 535         vccq-supply = <&vreg_l26a_1p2>;
 536         vccq2-supply = <&vreg_s4a_1p8>;
 537         vdd-hba-supply = <&vreg_l26a_1p2>;
 538         vcc-max-microamp = <750000>;
 539         vccq-max-microamp = <560000>;
 540         vccq2-max-microamp = <750000>;
 541 };
 542
 543 &ufsphy {
 544         status = "okay";
 545
 546         vdda-phy-supply = <&vreg_l1a_0p875>;
 547         vdda-pll-supply = <&vreg_l2a_1p2>;
 548 };
 549
 550 &usb3 {
 551         status = "okay";
 552
 553         /* Disable USB3 clock requirement as the device only supports USB2 */
 554         qcom,select-utmi-as-pipe-clk;
 555 };
 556
 557 &usb3_dwc3 {
 558         /* Drop the unused USB 3 PHY */
 559         phys = <&qusb2phy>;
 560         phy-names = "usb2-phy";
 561
 562         /* Fastest mode for USB 2 */
 563         maximum-speed = "high-speed";
 564
 565         /* Force to peripheral until we can switch modes */
 566         dr_mode = "peripheral";
 567 };
 568
 569 &wifi {
 570         /* Leave disabled until MSS is functional */
 571         vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
 572         vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
 573         vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
 574         vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
 575 };