1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
18 model = "Qualcomm Technologies, Inc. MSM8996";
20 interrupt-parent = <&intc>;
28 device_type = "memory";
29 /* We expect the bootloader to fill in the reg */
39 compatible = "qcom,kryo";
41 enable-method = "psci";
42 next-level-cache = <&L2_0>;
51 compatible = "qcom,kryo";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
59 compatible = "qcom,kryo";
61 enable-method = "psci";
62 next-level-cache = <&L2_1>;
71 compatible = "qcom,kryo";
73 enable-method = "psci";
74 next-level-cache = <&L2_1>;
102 polling-delay-passive = <250>;
103 polling-delay = <1000>;
105 thermal-sensors = <&tsens0 3>;
109 temperature = <75000>;
115 temperature = <110000>;
123 polling-delay-passive = <250>;
124 polling-delay = <1000>;
126 thermal-sensors = <&tsens0 5>;
130 temperature = <75000>;
136 temperature = <110000>;
144 polling-delay-passive = <250>;
145 polling-delay = <1000>;
147 thermal-sensors = <&tsens0 8>;
151 temperature = <75000>;
157 temperature = <110000>;
165 polling-delay-passive = <250>;
166 polling-delay = <1000>;
168 thermal-sensors = <&tsens0 10>;
172 temperature = <75000>;
178 temperature = <110000>;
187 compatible = "arm,armv8-timer";
188 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
189 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
190 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
191 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
196 compatible = "fixed-clock";
198 clock-frequency = <19200000>;
199 clock-output-names = "xo_board";
203 compatible = "fixed-clock";
205 clock-frequency = <32764>;
206 clock-output-names = "sleep_clk";
211 compatible = "arm,psci-1.0";
216 #address-cells = <1>;
218 ranges = <0 0 0 0xffffffff>;
219 compatible = "simple-bus";
221 intc: interrupt-controller@9bc0000 {
222 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
223 #interrupt-cells = <3>;
224 interrupt-controller;
225 #redistributor-regions = <1>;
226 redistributor-stride = <0x0 0x40000>;
227 reg = <0x09bc0000 0x10000>,
228 <0x09c00000 0x100000>;
229 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
232 gcc: clock-controller@300000 {
233 compatible = "qcom,gcc-msm8996";
236 #power-domain-cells = <1>;
237 reg = <0x300000 0x90000>;
240 blsp1_spi0: spi@07575000 {
241 compatible = "qcom,spi-qup-v2.2.1";
242 reg = <0x07575000 0x600>;
243 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
245 <&gcc GCC_BLSP1_AHB_CLK>;
246 clock-names = "core", "iface";
247 pinctrl-names = "default", "sleep";
248 pinctrl-0 = <&blsp1_spi0_default>;
249 pinctrl-1 = <&blsp1_spi0_sleep>;
250 #address-cells = <1>;
255 blsp2_i2c0: i2c@075b5000 {
256 compatible = "qcom,i2c-qup-v2.2.1";
257 reg = <0x075b5000 0x1000>;
258 interrupts = <GIC_SPI 101 0>;
259 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
260 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
261 clock-names = "iface", "core";
262 pinctrl-names = "default", "sleep";
263 pinctrl-0 = <&blsp2_i2c0_default>;
264 pinctrl-1 = <&blsp2_i2c0_sleep>;
265 #address-cells = <1>;
270 tsens0: thermal-sensor@4a8000 {
271 compatible = "qcom,msm8996-tsens";
272 reg = <0x4a8000 0x2000>;
273 #thermal-sensor-cells = <1>;
276 blsp2_uart1: serial@75b0000 {
277 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
278 reg = <0x75b0000 0x1000>;
279 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
281 <&gcc GCC_BLSP2_AHB_CLK>;
282 clock-names = "core", "iface";
286 blsp2_i2c1: i2c@075b6000 {
287 compatible = "qcom,i2c-qup-v2.2.1";
288 reg = <0x075b6000 0x1000>;
289 interrupts = <GIC_SPI 102 0>;
290 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
291 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
292 clock-names = "iface", "core";
293 pinctrl-names = "default", "sleep";
294 pinctrl-0 = <&blsp2_i2c1_default>;
295 pinctrl-1 = <&blsp2_i2c1_sleep>;
296 #address-cells = <1>;
301 blsp2_uart2: serial@75b1000 {
302 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
303 reg = <0x075b1000 0x1000>;
304 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
306 <&gcc GCC_BLSP2_AHB_CLK>;
307 clock-names = "core", "iface";
311 blsp1_i2c2: i2c@07577000 {
312 compatible = "qcom,i2c-qup-v2.2.1";
313 reg = <0x07577000 0x1000>;
314 interrupts = <GIC_SPI 97 0>;
315 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
316 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
317 clock-names = "iface", "core";
318 pinctrl-names = "default", "sleep";
319 pinctrl-0 = <&blsp1_i2c2_default>;
320 pinctrl-1 = <&blsp1_i2c2_sleep>;
321 #address-cells = <1>;
326 blsp2_spi5: spi@075ba000{
327 compatible = "qcom,spi-qup-v2.2.1";
328 reg = <0x075ba000 0x600>;
329 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
331 <&gcc GCC_BLSP2_AHB_CLK>;
332 clock-names = "core", "iface";
333 pinctrl-names = "default", "sleep";
334 pinctrl-0 = <&blsp2_spi5_default>;
335 pinctrl-1 = <&blsp2_spi5_sleep>;
336 #address-cells = <1>;
341 sdhc2: sdhci@74a4900 {
343 compatible = "qcom,sdhci-msm-v4";
344 reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
345 reg-names = "hc_mem", "core_mem";
347 interrupts = <0 125 0>, <0 221 0>;
348 interrupt-names = "hc_irq", "pwr_irq";
350 clock-names = "iface", "core";
351 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
352 <&gcc GCC_SDCC2_APPS_CLK>;
356 msmgpio: pinctrl@1010000 {
357 compatible = "qcom,msm8996-pinctrl";
358 reg = <0x01010000 0x300000>;
359 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
367 #address-cells = <1>;
370 compatible = "arm,armv7-timer-mem";
371 reg = <0x09840000 0x1000>;
372 clock-frequency = <19200000>;
376 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
378 reg = <0x09850000 0x1000>,
384 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
385 reg = <0x09870000 0x1000>;
391 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
392 reg = <0x09880000 0x1000>;
398 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
399 reg = <0x09890000 0x1000>;
405 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
406 reg = <0x098a0000 0x1000>;
412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
413 reg = <0x098b0000 0x1000>;
419 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
420 reg = <0x098c0000 0x1000>;
425 spmi_bus: qcom,spmi@400f000 {
426 compatible = "qcom,spmi-pmic-arb";
427 reg = <0x400f000 0x1000>,
428 <0x4400000 0x800000>,
429 <0x4c00000 0x800000>,
430 <0x5800000 0x200000>,
431 <0x400a000 0x002100>;
432 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
433 interrupt-names = "periph_irq";
434 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
437 #address-cells = <2>;
439 interrupt-controller;
440 #interrupt-cells = <4>;
443 mmcc: clock-controller@8c0000 {
444 compatible = "qcom,mmcc-msm8996";
447 #power-domain-cells = <1>;
448 reg = <0x8c0000 0x40000>;
449 assigned-clocks = <&mmcc MMPLL9_PLL>,
454 assigned-clock-rates = <624000000>,
462 #include "msm8996-pins.dtsi"