1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,apr.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
28 compatible = "fixed-clock";
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
48 compatible = "qcom,kryo";
50 enable-method = "psci";
51 cpu-idle-states = <&CPU_SLEEP_0>;
52 capacity-dmips-mhz = <1024>;
54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
55 operating-points-v2 = <&cluster0_opp>;
57 next-level-cache = <&L2_0>;
67 compatible = "qcom,kryo";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
71 capacity-dmips-mhz = <1024>;
73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
74 operating-points-v2 = <&cluster0_opp>;
76 next-level-cache = <&L2_0>;
81 compatible = "qcom,kryo";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
85 capacity-dmips-mhz = <1024>;
87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
88 operating-points-v2 = <&cluster1_opp>;
90 next-level-cache = <&L2_1>;
100 compatible = "qcom,kryo";
102 enable-method = "psci";
103 cpu-idle-states = <&CPU_SLEEP_0>;
104 capacity-dmips-mhz = <1024>;
105 clocks = <&kryocc 1>;
106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>;
107 operating-points-v2 = <&cluster1_opp>;
108 #cooling-cells = <2>;
109 next-level-cache = <&L2_1>;
135 entry-method = "psci";
137 CPU_SLEEP_0: cpu-sleep-0 {
138 compatible = "arm,idle-state";
139 idle-state-name = "standalone-power-collapse";
140 arm,psci-suspend-param = <0x00000004>;
141 entry-latency-us = <130>;
142 exit-latency-us = <80>;
143 min-residency-us = <300>;
148 cluster0_opp: opp-table-cluster0 {
149 compatible = "operating-points-v2-kryo-cpu";
150 nvmem-cells = <&speedbin_efuse>;
153 /* Nominal fmax for now */
155 opp-hz = /bits/ 64 <307200000>;
156 opp-supported-hw = <0xf>;
157 clock-latency-ns = <200000>;
158 opp-peak-kBps = <307200>;
161 opp-hz = /bits/ 64 <422400000>;
162 opp-supported-hw = <0xf>;
163 clock-latency-ns = <200000>;
164 opp-peak-kBps = <307200>;
167 opp-hz = /bits/ 64 <480000000>;
168 opp-supported-hw = <0xf>;
169 clock-latency-ns = <200000>;
170 opp-peak-kBps = <307200>;
173 opp-hz = /bits/ 64 <556800000>;
174 opp-supported-hw = <0xf>;
175 clock-latency-ns = <200000>;
176 opp-peak-kBps = <307200>;
179 opp-hz = /bits/ 64 <652800000>;
180 opp-supported-hw = <0xf>;
181 clock-latency-ns = <200000>;
182 opp-peak-kBps = <384000>;
185 opp-hz = /bits/ 64 <729600000>;
186 opp-supported-hw = <0xf>;
187 clock-latency-ns = <200000>;
188 opp-peak-kBps = <460800>;
191 opp-hz = /bits/ 64 <844800000>;
192 opp-supported-hw = <0xf>;
193 clock-latency-ns = <200000>;
194 opp-peak-kBps = <537600>;
197 opp-hz = /bits/ 64 <960000000>;
198 opp-supported-hw = <0xf>;
199 clock-latency-ns = <200000>;
200 opp-peak-kBps = <672000>;
203 opp-hz = /bits/ 64 <1036800000>;
204 opp-supported-hw = <0xf>;
205 clock-latency-ns = <200000>;
206 opp-peak-kBps = <672000>;
209 opp-hz = /bits/ 64 <1113600000>;
210 opp-supported-hw = <0xf>;
211 clock-latency-ns = <200000>;
212 opp-peak-kBps = <825600>;
215 opp-hz = /bits/ 64 <1190400000>;
216 opp-supported-hw = <0xf>;
217 clock-latency-ns = <200000>;
218 opp-peak-kBps = <825600>;
221 opp-hz = /bits/ 64 <1228800000>;
222 opp-supported-hw = <0xf>;
223 clock-latency-ns = <200000>;
224 opp-peak-kBps = <902400>;
227 opp-hz = /bits/ 64 <1324800000>;
228 opp-supported-hw = <0xd>;
229 clock-latency-ns = <200000>;
230 opp-peak-kBps = <1056000>;
233 opp-hz = /bits/ 64 <1363200000>;
234 opp-supported-hw = <0x2>;
235 clock-latency-ns = <200000>;
236 opp-peak-kBps = <1132800>;
239 opp-hz = /bits/ 64 <1401600000>;
240 opp-supported-hw = <0xd>;
241 clock-latency-ns = <200000>;
242 opp-peak-kBps = <1132800>;
245 opp-hz = /bits/ 64 <1478400000>;
246 opp-supported-hw = <0x9>;
247 clock-latency-ns = <200000>;
248 opp-peak-kBps = <1190400>;
251 opp-hz = /bits/ 64 <1497600000>;
252 opp-supported-hw = <0x04>;
253 clock-latency-ns = <200000>;
254 opp-peak-kBps = <1305600>;
257 opp-hz = /bits/ 64 <1593600000>;
258 opp-supported-hw = <0x9>;
259 clock-latency-ns = <200000>;
260 opp-peak-kBps = <1382400>;
264 cluster1_opp: opp-table-cluster1 {
265 compatible = "operating-points-v2-kryo-cpu";
266 nvmem-cells = <&speedbin_efuse>;
269 /* Nominal fmax for now */
271 opp-hz = /bits/ 64 <307200000>;
272 opp-supported-hw = <0xf>;
273 clock-latency-ns = <200000>;
274 opp-peak-kBps = <307200>;
277 opp-hz = /bits/ 64 <403200000>;
278 opp-supported-hw = <0xf>;
279 clock-latency-ns = <200000>;
280 opp-peak-kBps = <307200>;
283 opp-hz = /bits/ 64 <480000000>;
284 opp-supported-hw = <0xf>;
285 clock-latency-ns = <200000>;
286 opp-peak-kBps = <307200>;
289 opp-hz = /bits/ 64 <556800000>;
290 opp-supported-hw = <0xf>;
291 clock-latency-ns = <200000>;
292 opp-peak-kBps = <307200>;
295 opp-hz = /bits/ 64 <652800000>;
296 opp-supported-hw = <0xf>;
297 clock-latency-ns = <200000>;
298 opp-peak-kBps = <307200>;
301 opp-hz = /bits/ 64 <729600000>;
302 opp-supported-hw = <0xf>;
303 clock-latency-ns = <200000>;
304 opp-peak-kBps = <307200>;
307 opp-hz = /bits/ 64 <806400000>;
308 opp-supported-hw = <0xf>;
309 clock-latency-ns = <200000>;
310 opp-peak-kBps = <384000>;
313 opp-hz = /bits/ 64 <883200000>;
314 opp-supported-hw = <0xf>;
315 clock-latency-ns = <200000>;
316 opp-peak-kBps = <460800>;
319 opp-hz = /bits/ 64 <940800000>;
320 opp-supported-hw = <0xf>;
321 clock-latency-ns = <200000>;
322 opp-peak-kBps = <537600>;
325 opp-hz = /bits/ 64 <1036800000>;
326 opp-supported-hw = <0xf>;
327 clock-latency-ns = <200000>;
328 opp-peak-kBps = <595200>;
331 opp-hz = /bits/ 64 <1113600000>;
332 opp-supported-hw = <0xf>;
333 clock-latency-ns = <200000>;
334 opp-peak-kBps = <672000>;
337 opp-hz = /bits/ 64 <1190400000>;
338 opp-supported-hw = <0xf>;
339 clock-latency-ns = <200000>;
340 opp-peak-kBps = <672000>;
343 opp-hz = /bits/ 64 <1248000000>;
344 opp-supported-hw = <0xf>;
345 clock-latency-ns = <200000>;
346 opp-peak-kBps = <748800>;
349 opp-hz = /bits/ 64 <1324800000>;
350 opp-supported-hw = <0xf>;
351 clock-latency-ns = <200000>;
352 opp-peak-kBps = <825600>;
355 opp-hz = /bits/ 64 <1401600000>;
356 opp-supported-hw = <0xf>;
357 clock-latency-ns = <200000>;
358 opp-peak-kBps = <902400>;
361 opp-hz = /bits/ 64 <1478400000>;
362 opp-supported-hw = <0xf>;
363 clock-latency-ns = <200000>;
364 opp-peak-kBps = <979200>;
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-supported-hw = <0xf>;
369 clock-latency-ns = <200000>;
370 opp-peak-kBps = <1056000>;
373 opp-hz = /bits/ 64 <1632000000>;
374 opp-supported-hw = <0xf>;
375 clock-latency-ns = <200000>;
376 opp-peak-kBps = <1190400>;
379 opp-hz = /bits/ 64 <1708800000>;
380 opp-supported-hw = <0xf>;
381 clock-latency-ns = <200000>;
382 opp-peak-kBps = <1228800>;
385 opp-hz = /bits/ 64 <1785600000>;
386 opp-supported-hw = <0xf>;
387 clock-latency-ns = <200000>;
388 opp-peak-kBps = <1305600>;
391 opp-hz = /bits/ 64 <1804800000>;
392 opp-supported-hw = <0xe>;
393 clock-latency-ns = <200000>;
394 opp-peak-kBps = <1305600>;
397 opp-hz = /bits/ 64 <1824000000>;
398 opp-supported-hw = <0x1>;
399 clock-latency-ns = <200000>;
400 opp-peak-kBps = <1382400>;
403 opp-hz = /bits/ 64 <1900800000>;
404 opp-supported-hw = <0x4>;
405 clock-latency-ns = <200000>;
406 opp-peak-kBps = <1305600>;
409 opp-hz = /bits/ 64 <1920000000>;
410 opp-supported-hw = <0x1>;
411 clock-latency-ns = <200000>;
412 opp-peak-kBps = <1459200>;
415 opp-hz = /bits/ 64 <1996800000>;
416 opp-supported-hw = <0x1>;
417 clock-latency-ns = <200000>;
418 opp-peak-kBps = <1593600>;
421 opp-hz = /bits/ 64 <2073600000>;
422 opp-supported-hw = <0x1>;
423 clock-latency-ns = <200000>;
424 opp-peak-kBps = <1593600>;
427 opp-hz = /bits/ 64 <2150400000>;
428 opp-supported-hw = <0x1>;
429 clock-latency-ns = <200000>;
430 opp-peak-kBps = <1593600>;
436 compatible = "qcom,scm-msm8996", "qcom,scm";
437 qcom,dload-mode = <&tcsr_2 0x13000>;
442 device_type = "memory";
443 /* We expect the bootloader to fill in the reg */
444 reg = <0x0 0x80000000 0x0 0x0>;
448 compatible = "arm,psci-1.0";
453 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
456 compatible = "qcom,glink-rpm";
457 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
458 qcom,rpm-msg-ram = <&rpm_msg_ram>;
459 mboxes = <&apcs_glb 0>;
461 rpm_requests: rpm-requests {
462 compatible = "qcom,rpm-msm8996";
463 qcom,glink-channels = "rpm_requests";
465 rpmcc: clock-controller {
466 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
468 clocks = <&xo_board>;
472 rpmpd: power-controller {
473 compatible = "qcom,msm8996-rpmpd";
474 #power-domain-cells = <1>;
475 operating-points-v2 = <&rpmpd_opp_table>;
477 rpmpd_opp_table: opp-table {
478 compatible = "operating-points-v2";
510 #address-cells = <2>;
514 hyp_mem: memory@85800000 {
515 reg = <0x0 0x85800000 0x0 0x600000>;
519 xbl_mem: memory@85e00000 {
520 reg = <0x0 0x85e00000 0x0 0x200000>;
524 smem_mem: smem-mem@86000000 {
525 reg = <0x0 0x86000000 0x0 0x200000>;
529 tz_mem: memory@86200000 {
530 reg = <0x0 0x86200000 0x0 0x2600000>;
535 compatible = "qcom,rmtfs-mem";
537 size = <0x0 0x200000>;
538 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
541 qcom,client-id = <1>;
542 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
545 mpss_mem: mpss@88800000 {
546 reg = <0x0 0x88800000 0x0 0x6200000>;
550 adsp_mem: adsp@8ea00000 {
551 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
555 slpi_mem: slpi@90500000 {
556 reg = <0x0 0x90500000 0x0 0xa00000>;
560 gpu_mem: gpu@90f00000 {
561 compatible = "shared-dma-pool";
562 reg = <0x0 0x90f00000 0x0 0x100000>;
566 venus_mem: venus@91000000 {
567 reg = <0x0 0x91000000 0x0 0x500000>;
571 mba_mem: mba@91500000 {
572 reg = <0x0 0x91500000 0x0 0x200000>;
576 mdata_mem: mpss-metadata {
577 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
584 compatible = "qcom,smem";
585 memory-region = <&smem_mem>;
586 hwlocks = <&tcsr_mutex 3>;
590 compatible = "qcom,smp2p";
591 qcom,smem = <443>, <429>;
593 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
595 mboxes = <&apcs_glb 10>;
597 qcom,local-pid = <0>;
598 qcom,remote-pid = <2>;
600 adsp_smp2p_out: master-kernel {
601 qcom,entry-name = "master-kernel";
602 #qcom,smem-state-cells = <1>;
605 adsp_smp2p_in: slave-kernel {
606 qcom,entry-name = "slave-kernel";
608 interrupt-controller;
609 #interrupt-cells = <2>;
614 compatible = "qcom,smp2p";
615 qcom,smem = <435>, <428>;
617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
619 mboxes = <&apcs_glb 14>;
621 qcom,local-pid = <0>;
622 qcom,remote-pid = <1>;
624 mpss_smp2p_out: master-kernel {
625 qcom,entry-name = "master-kernel";
626 #qcom,smem-state-cells = <1>;
629 mpss_smp2p_in: slave-kernel {
630 qcom,entry-name = "slave-kernel";
632 interrupt-controller;
633 #interrupt-cells = <2>;
638 compatible = "qcom,smp2p";
639 qcom,smem = <481>, <430>;
641 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
643 mboxes = <&apcs_glb 26>;
645 qcom,local-pid = <0>;
646 qcom,remote-pid = <3>;
648 slpi_smp2p_out: master-kernel {
649 qcom,entry-name = "master-kernel";
650 #qcom,smem-state-cells = <1>;
653 slpi_smp2p_in: slave-kernel {
654 qcom,entry-name = "slave-kernel";
656 interrupt-controller;
657 #interrupt-cells = <2>;
662 #address-cells = <1>;
664 ranges = <0 0 0 0xffffffff>;
665 compatible = "simple-bus";
667 pcie_phy: phy-wrapper@34000 {
668 compatible = "qcom,msm8996-qmp-pcie-phy";
669 reg = <0x00034000 0x488>;
670 #address-cells = <1>;
672 ranges = <0x0 0x00034000 0x4000>;
674 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
675 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
676 <&gcc GCC_PCIE_CLKREF_CLK>;
677 clock-names = "aux", "cfg_ahb", "ref";
679 resets = <&gcc GCC_PCIE_PHY_BCR>,
680 <&gcc GCC_PCIE_PHY_COM_BCR>,
681 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
682 reset-names = "phy", "common", "cfg";
686 pciephy_0: phy@1000 {
687 reg = <0x1000 0x130>,
691 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
692 clock-names = "pipe0";
693 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
694 reset-names = "lane0";
697 clock-output-names = "pcie_0_pipe_clk_src";
702 pciephy_1: phy@2000 {
703 reg = <0x2000 0x130>,
707 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
708 clock-names = "pipe1";
709 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
710 reset-names = "lane1";
713 clock-output-names = "pcie_1_pipe_clk_src";
718 pciephy_2: phy@3000 {
719 reg = <0x3000 0x130>,
723 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
724 clock-names = "pipe2";
725 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
726 reset-names = "lane2";
729 clock-output-names = "pcie_2_pipe_clk_src";
735 rpm_msg_ram: sram@68000 {
736 compatible = "qcom,rpm-msg-ram";
737 reg = <0x00068000 0x6000>;
741 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
742 reg = <0x00074000 0x8ff>;
743 #address-cells = <1>;
746 qusb2p_hstx_trim: hstx_trim@24e {
751 qusb2s_hstx_trim: hstx_trim@24f {
756 speedbin_efuse: speedbin@133 {
763 compatible = "qcom,prng-ee";
764 reg = <0x00083000 0x1000>;
765 clocks = <&gcc GCC_PRNG_AHB_CLK>;
766 clock-names = "core";
769 gcc: clock-controller@300000 {
770 compatible = "qcom,gcc-msm8996";
773 #power-domain-cells = <1>;
774 reg = <0x00300000 0x90000>;
776 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
777 <&rpmcc RPM_SMD_LN_BB_CLK>,
789 "pcie_0_pipe_clk_src",
790 "pcie_1_pipe_clk_src",
791 "pcie_2_pipe_clk_src",
792 "usb3_phy_pipe_clk_src",
793 "ufs_rx_symbol_0_clk_src",
794 "ufs_rx_symbol_1_clk_src",
795 "ufs_tx_symbol_0_clk_src";
798 bimc: interconnect@408000 {
799 compatible = "qcom,msm8996-bimc";
800 reg = <0x00408000 0x5a000>;
801 #interconnect-cells = <1>;
802 clock-names = "bus", "bus_a";
803 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
804 <&rpmcc RPM_SMD_BIMC_A_CLK>;
807 tsens0: thermal-sensor@4a9000 {
808 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
809 reg = <0x004a9000 0x1000>, /* TM */
810 <0x004a8000 0x1000>; /* SROT */
811 #qcom,sensors = <13>;
812 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
814 interrupt-names = "uplow", "critical";
815 #thermal-sensor-cells = <1>;
818 tsens1: thermal-sensor@4ad000 {
819 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
820 reg = <0x004ad000 0x1000>, /* TM */
821 <0x004ac000 0x1000>; /* SROT */
823 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "uplow", "critical";
826 #thermal-sensor-cells = <1>;
829 cryptobam: dma-controller@644000 {
830 compatible = "qcom,bam-v1.7.0";
831 reg = <0x00644000 0x24000>;
832 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&gcc GCC_CE1_CLK>;
834 clock-names = "bam_clk";
837 qcom,controlled-remotely;
840 crypto: crypto@67a000 {
841 compatible = "qcom,crypto-v5.4";
842 reg = <0x0067a000 0x6000>;
843 clocks = <&gcc GCC_CE1_AHB_CLK>,
844 <&gcc GCC_CE1_AXI_CLK>,
846 clock-names = "iface", "bus", "core";
847 dmas = <&cryptobam 6>, <&cryptobam 7>;
848 dma-names = "rx", "tx";
851 cnoc: interconnect@500000 {
852 compatible = "qcom,msm8996-cnoc";
853 reg = <0x00500000 0x1000>;
854 #interconnect-cells = <1>;
855 clock-names = "bus", "bus_a";
856 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
857 <&rpmcc RPM_SMD_CNOC_A_CLK>;
860 snoc: interconnect@524000 {
861 compatible = "qcom,msm8996-snoc";
862 reg = <0x00524000 0x1c000>;
863 #interconnect-cells = <1>;
864 clock-names = "bus", "bus_a";
865 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
866 <&rpmcc RPM_SMD_SNOC_A_CLK>;
869 a0noc: interconnect@543000 {
870 compatible = "qcom,msm8996-a0noc";
871 reg = <0x00543000 0x6000>;
872 #interconnect-cells = <1>;
873 clock-names = "aggre0_snoc_axi",
875 "aggre0_noc_mpu_cfg";
876 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
877 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
878 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
879 power-domains = <&gcc AGGRE0_NOC_GDSC>;
882 a1noc: interconnect@562000 {
883 compatible = "qcom,msm8996-a1noc";
884 reg = <0x00562000 0x5000>;
885 #interconnect-cells = <1>;
886 clock-names = "bus", "bus_a";
887 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
888 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
891 a2noc: interconnect@583000 {
892 compatible = "qcom,msm8996-a2noc";
893 reg = <0x00583000 0x7000>;
894 #interconnect-cells = <1>;
895 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
896 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
897 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
898 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
899 <&gcc GCC_UFS_AXI_CLK>;
902 mnoc: interconnect@5a4000 {
903 compatible = "qcom,msm8996-mnoc";
904 reg = <0x005a4000 0x1c000>;
905 #interconnect-cells = <1>;
906 clock-names = "bus", "bus_a", "iface";
907 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
908 <&rpmcc RPM_SMD_MMAXI_A_CLK>,
912 pnoc: interconnect@5c0000 {
913 compatible = "qcom,msm8996-pnoc";
914 reg = <0x005c0000 0x3000>;
915 #interconnect-cells = <1>;
916 clock-names = "bus", "bus_a";
917 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
918 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
921 tcsr_mutex: hwlock@740000 {
922 compatible = "qcom,tcsr-mutex";
923 reg = <0x00740000 0x20000>;
927 tcsr_1: syscon@760000 {
928 compatible = "qcom,tcsr-msm8996", "syscon";
929 reg = <0x00760000 0x20000>;
932 tcsr_2: syscon@7a0000 {
933 compatible = "qcom,tcsr-msm8996", "syscon";
934 reg = <0x007a0000 0x18000>;
937 mmcc: clock-controller@8c0000 {
938 compatible = "qcom,mmcc-msm8996";
941 #power-domain-cells = <1>;
942 reg = <0x008c0000 0x40000>;
943 clocks = <&xo_board>,
945 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
953 "gcc_mmss_noc_cfg_ahb_clk",
959 assigned-clocks = <&mmcc MMPLL9_PLL>,
964 assigned-clock-rates = <624000000>,
971 mdss: display-subsystem@900000 {
972 compatible = "qcom,mdss";
974 reg = <0x00900000 0x1000>,
977 reg-names = "mdss_phys",
981 power-domains = <&mmcc MDSS_GDSC>;
982 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
984 interrupt-controller;
985 #interrupt-cells = <1>;
987 clocks = <&mmcc MDSS_AHB_CLK>,
988 <&mmcc MDSS_MDP_CLK>;
989 clock-names = "iface", "core";
991 #address-cells = <1>;
997 mdp: display-controller@901000 {
998 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
999 reg = <0x00901000 0x90000>;
1000 reg-names = "mdp_phys";
1002 interrupt-parent = <&mdss>;
1005 clocks = <&mmcc MDSS_AHB_CLK>,
1006 <&mmcc MDSS_AXI_CLK>,
1007 <&mmcc MDSS_MDP_CLK>,
1008 <&mmcc SMMU_MDP_AXI_CLK>,
1009 <&mmcc MDSS_VSYNC_CLK>;
1010 clock-names = "iface",
1016 iommus = <&mdp_smmu 0>;
1018 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1019 <&mmcc MDSS_VSYNC_CLK>;
1020 assigned-clock-rates = <300000000>,
1023 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
1024 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
1025 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
1026 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1029 #address-cells = <1>;
1034 mdp5_intf3_out: endpoint {
1035 remote-endpoint = <&mdss_hdmi_in>;
1041 mdp5_intf1_out: endpoint {
1042 remote-endpoint = <&mdss_dsi0_in>;
1048 mdp5_intf2_out: endpoint {
1049 remote-endpoint = <&mdss_dsi1_in>;
1055 mdss_dsi0: dsi@994000 {
1056 compatible = "qcom,msm8996-dsi-ctrl",
1057 "qcom,mdss-dsi-ctrl";
1058 reg = <0x00994000 0x400>;
1059 reg-names = "dsi_ctrl";
1061 interrupt-parent = <&mdss>;
1064 clocks = <&mmcc MDSS_MDP_CLK>,
1065 <&mmcc MDSS_BYTE0_CLK>,
1066 <&mmcc MDSS_AHB_CLK>,
1067 <&mmcc MDSS_AXI_CLK>,
1068 <&mmcc MMSS_MISC_AHB_CLK>,
1069 <&mmcc MDSS_PCLK0_CLK>,
1070 <&mmcc MDSS_ESC0_CLK>;
1071 clock-names = "mdp_core",
1078 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1079 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1081 phys = <&mdss_dsi0_phy>;
1082 status = "disabled";
1084 #address-cells = <1>;
1088 #address-cells = <1>;
1093 mdss_dsi0_in: endpoint {
1094 remote-endpoint = <&mdp5_intf1_out>;
1100 mdss_dsi0_out: endpoint {
1106 mdss_dsi0_phy: phy@994400 {
1107 compatible = "qcom,dsi-phy-14nm";
1108 reg = <0x00994400 0x100>,
1111 reg-names = "dsi_phy",
1118 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1119 clock-names = "iface", "ref";
1120 status = "disabled";
1123 mdss_dsi1: dsi@996000 {
1124 compatible = "qcom,msm8996-dsi-ctrl",
1125 "qcom,mdss-dsi-ctrl";
1126 reg = <0x00996000 0x400>;
1127 reg-names = "dsi_ctrl";
1129 interrupt-parent = <&mdss>;
1132 clocks = <&mmcc MDSS_MDP_CLK>,
1133 <&mmcc MDSS_BYTE1_CLK>,
1134 <&mmcc MDSS_AHB_CLK>,
1135 <&mmcc MDSS_AXI_CLK>,
1136 <&mmcc MMSS_MISC_AHB_CLK>,
1137 <&mmcc MDSS_PCLK1_CLK>,
1138 <&mmcc MDSS_ESC1_CLK>;
1139 clock-names = "mdp_core",
1146 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1147 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1149 phys = <&mdss_dsi1_phy>;
1150 status = "disabled";
1152 #address-cells = <1>;
1156 #address-cells = <1>;
1161 mdss_dsi1_in: endpoint {
1162 remote-endpoint = <&mdp5_intf2_out>;
1168 mdss_dsi1_out: endpoint {
1174 mdss_dsi1_phy: phy@996400 {
1175 compatible = "qcom,dsi-phy-14nm";
1176 reg = <0x00996400 0x100>,
1179 reg-names = "dsi_phy",
1186 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1187 clock-names = "iface", "ref";
1188 status = "disabled";
1191 mdss_hdmi: hdmi-tx@9a0000 {
1192 compatible = "qcom,hdmi-tx-8996";
1193 reg = <0x009a0000 0x50c>,
1194 <0x00070000 0x6158>,
1196 reg-names = "core_physical",
1200 interrupt-parent = <&mdss>;
1203 clocks = <&mmcc MDSS_MDP_CLK>,
1204 <&mmcc MDSS_AHB_CLK>,
1205 <&mmcc MDSS_HDMI_CLK>,
1206 <&mmcc MDSS_HDMI_AHB_CLK>,
1207 <&mmcc MDSS_EXTPCLK_CLK>;
1215 phys = <&mdss_hdmi_phy>;
1216 #sound-dai-cells = <1>;
1218 status = "disabled";
1221 #address-cells = <1>;
1226 mdss_hdmi_in: endpoint {
1227 remote-endpoint = <&mdp5_intf3_out>;
1233 mdss_hdmi_phy: phy@9a0600 {
1235 compatible = "qcom,hdmi-phy-8996";
1236 reg = <0x009a0600 0x1c4>,
1242 reg-names = "hdmi_pll",
1249 clocks = <&mmcc MDSS_AHB_CLK>,
1250 <&gcc GCC_HDMI_CLKREF_CLK>,
1252 clock-names = "iface",
1258 status = "disabled";
1263 compatible = "qcom,adreno-530.2", "qcom,adreno";
1265 reg = <0x00b00000 0x3f000>;
1266 reg-names = "kgsl_3d0_reg_memory";
1268 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1271 <&mmcc GPU_AHB_CLK>,
1272 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1273 <&gcc GCC_BIMC_GFX_CLK>,
1274 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1276 clock-names = "core",
1282 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1283 interconnect-names = "gfx-mem";
1285 power-domains = <&mmcc GPU_GX_GDSC>;
1286 iommus = <&adreno_smmu 0>;
1288 nvmem-cells = <&speedbin_efuse>;
1289 nvmem-cell-names = "speed_bin";
1291 operating-points-v2 = <&gpu_opp_table>;
1293 status = "disabled";
1295 #cooling-cells = <2>;
1297 gpu_opp_table: opp-table {
1298 compatible = "operating-points-v2";
1301 * 624Mhz is only available on speed bins 0 and 3.
1302 * 560Mhz is only available on speed bins 0, 2 and 3.
1303 * All the rest are available on all bins of the hardware.
1306 opp-hz = /bits/ 64 <624000000>;
1307 opp-supported-hw = <0x09>;
1310 opp-hz = /bits/ 64 <560000000>;
1311 opp-supported-hw = <0x0d>;
1314 opp-hz = /bits/ 64 <510000000>;
1315 opp-supported-hw = <0xff>;
1318 opp-hz = /bits/ 64 <401800000>;
1319 opp-supported-hw = <0xff>;
1322 opp-hz = /bits/ 64 <315000000>;
1323 opp-supported-hw = <0xff>;
1326 opp-hz = /bits/ 64 <214000000>;
1327 opp-supported-hw = <0xff>;
1330 opp-hz = /bits/ 64 <133000000>;
1331 opp-supported-hw = <0xff>;
1336 memory-region = <&gpu_mem>;
1340 tlmm: pinctrl@1010000 {
1341 compatible = "qcom,msm8996-pinctrl";
1342 reg = <0x01010000 0x300000>;
1343 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1345 gpio-ranges = <&tlmm 0 0 150>;
1347 interrupt-controller;
1348 #interrupt-cells = <2>;
1350 blsp1_spi1_default: blsp1-spi1-default-state {
1352 pins = "gpio0", "gpio1", "gpio3";
1353 function = "blsp_spi1";
1354 drive-strength = <12>;
1361 drive-strength = <16>;
1367 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1368 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1370 drive-strength = <2>;
1374 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1375 pins = "gpio4", "gpio5";
1376 function = "blsp_uart8";
1377 drive-strength = <16>;
1381 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1382 pins = "gpio4", "gpio5";
1384 drive-strength = <2>;
1388 blsp2_i2c2_default: blsp2-i2c2-state {
1389 pins = "gpio6", "gpio7";
1390 function = "blsp_i2c8";
1391 drive-strength = <16>;
1395 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1396 pins = "gpio6", "gpio7";
1398 drive-strength = <2>;
1402 blsp1_i2c6_default: blsp1-i2c6-state {
1403 pins = "gpio27", "gpio28";
1404 function = "blsp_i2c6";
1405 drive-strength = <16>;
1409 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1410 pins = "gpio27", "gpio28";
1412 drive-strength = <2>;
1416 cci0_default: cci0-default-state {
1417 pins = "gpio17", "gpio18";
1418 function = "cci_i2c";
1419 drive-strength = <16>;
1424 camera_rear_default: camera-rear-default-state {
1425 camera0_mclk: mclk0-pins {
1427 function = "cam_mclk";
1428 drive-strength = <16>;
1432 camera0_rst: rst-pins {
1435 drive-strength = <16>;
1439 camera0_pwdn: pwdn-pins {
1442 drive-strength = <16>;
1447 cci1_default: cci1-default-state {
1448 pins = "gpio19", "gpio20";
1449 function = "cci_i2c";
1450 drive-strength = <16>;
1455 camera_board_default: camera-board-default-state {
1458 function = "cam_mclk";
1459 drive-strength = <16>;
1466 drive-strength = <16>;
1473 drive-strength = <16>;
1479 camera_front_default: camera-front-default-state {
1480 camera2_mclk: mclk2-pins {
1482 function = "cam_mclk";
1483 drive-strength = <16>;
1487 camera2_rst: rst-pins {
1490 drive-strength = <16>;
1497 drive-strength = <16>;
1502 pcie0_state_on: pcie0-state-on-state {
1506 drive-strength = <2>;
1512 function = "pci_e0";
1513 drive-strength = <2>;
1520 drive-strength = <2>;
1525 pcie0_state_off: pcie0-state-off-state {
1529 drive-strength = <2>;
1536 drive-strength = <2>;
1543 drive-strength = <2>;
1548 blsp1_uart2_default: blsp1-uart2-default-state {
1549 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1550 function = "blsp_uart2";
1551 drive-strength = <16>;
1555 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1556 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1558 drive-strength = <2>;
1562 blsp1_i2c3_default: blsp1-i2c3-default-state {
1563 pins = "gpio47", "gpio48";
1564 function = "blsp_i2c3";
1565 drive-strength = <16>;
1569 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1570 pins = "gpio47", "gpio48";
1572 drive-strength = <2>;
1576 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1577 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1578 function = "blsp_uart9";
1579 drive-strength = <16>;
1583 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1584 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1585 function = "blsp_uart9";
1586 drive-strength = <2>;
1590 blsp2_i2c3_default: blsp2-i2c3-state-state {
1591 pins = "gpio51", "gpio52";
1592 function = "blsp_i2c9";
1593 drive-strength = <16>;
1597 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1598 pins = "gpio51", "gpio52";
1600 drive-strength = <2>;
1604 wcd_intr_default: wcd-intr-default-state {
1607 drive-strength = <2>;
1611 blsp2_i2c1_default: blsp2-i2c1-state {
1612 pins = "gpio55", "gpio56";
1613 function = "blsp_i2c7";
1614 drive-strength = <16>;
1618 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1619 pins = "gpio55", "gpio56";
1621 drive-strength = <2>;
1625 blsp2_i2c5_default: blsp2-i2c5-state {
1626 pins = "gpio60", "gpio61";
1627 function = "blsp_i2c11";
1628 drive-strength = <2>;
1632 /* Sleep state for BLSP2_I2C5 is missing.. */
1634 cdc_reset_active: cdc-reset-active-state {
1637 drive-strength = <16>;
1642 cdc_reset_sleep: cdc-reset-sleep-state {
1645 drive-strength = <16>;
1650 blsp2_spi6_default: blsp2-spi6-default-state {
1652 pins = "gpio85", "gpio86", "gpio88";
1653 function = "blsp_spi12";
1654 drive-strength = <12>;
1661 drive-strength = <16>;
1667 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1668 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1670 drive-strength = <2>;
1674 blsp2_i2c6_default: blsp2-i2c6-state {
1675 pins = "gpio87", "gpio88";
1676 function = "blsp_i2c12";
1677 drive-strength = <16>;
1681 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1682 pins = "gpio87", "gpio88";
1684 drive-strength = <2>;
1688 pcie1_state_on: pcie1-on-state {
1692 drive-strength = <2>;
1698 function = "pci_e1";
1699 drive-strength = <2>;
1706 drive-strength = <2>;
1711 pcie1_state_off: pcie1-off-state {
1712 /* Perst is missing? */
1716 drive-strength = <2>;
1723 drive-strength = <2>;
1728 pcie2_state_on: pcie2-on-state {
1732 drive-strength = <2>;
1738 function = "pci_e2";
1739 drive-strength = <2>;
1746 drive-strength = <2>;
1751 pcie2_state_off: pcie2-off-state {
1752 /* Perst is missing? */
1756 drive-strength = <2>;
1763 drive-strength = <2>;
1768 sdc1_state_on: sdc1-on-state {
1772 drive-strength = <16>;
1778 drive-strength = <10>;
1784 drive-strength = <10>;
1793 sdc1_state_off: sdc1-off-state {
1797 drive-strength = <2>;
1803 drive-strength = <2>;
1809 drive-strength = <2>;
1818 sdc2_state_on: sdc2-on-state {
1822 drive-strength = <16>;
1828 drive-strength = <10>;
1834 drive-strength = <10>;
1838 sdc2_state_off: sdc2-off-state {
1842 drive-strength = <2>;
1848 drive-strength = <2>;
1854 drive-strength = <2>;
1860 compatible = "qcom,rpm-stats";
1861 reg = <0x00290000 0x10000>;
1864 spmi_bus: spmi@400f000 {
1865 compatible = "qcom,spmi-pmic-arb";
1866 reg = <0x0400f000 0x1000>,
1867 <0x04400000 0x800000>,
1868 <0x04c00000 0x800000>,
1869 <0x05800000 0x200000>,
1870 <0x0400a000 0x002100>;
1871 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1872 interrupt-names = "periph_irq";
1873 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1876 #address-cells = <2>;
1878 interrupt-controller;
1879 #interrupt-cells = <4>;
1883 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1884 compatible = "simple-pm-bus";
1885 #address-cells = <1>;
1887 ranges = <0x0 0x0 0xffffffff>;
1889 pcie0: pcie@600000 {
1890 compatible = "qcom,pcie-msm8996";
1891 status = "disabled";
1892 power-domains = <&gcc PCIE0_GDSC>;
1893 bus-range = <0x00 0xff>;
1896 reg = <0x00600000 0x2000>,
1899 <0x0c100000 0x100000>;
1900 reg-names = "parf", "dbi", "elbi","config";
1902 phys = <&pciephy_0>;
1903 phy-names = "pciephy";
1905 #address-cells = <3>;
1907 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1908 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1910 device_type = "pci";
1912 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1913 interrupt-names = "msi";
1914 #interrupt-cells = <1>;
1915 interrupt-map-mask = <0 0 0 0x7>;
1916 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1917 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1918 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1919 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1921 pinctrl-names = "default", "sleep";
1922 pinctrl-0 = <&pcie0_state_on>;
1923 pinctrl-1 = <&pcie0_state_off>;
1925 linux,pci-domain = <0>;
1927 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1928 <&gcc GCC_PCIE_0_AUX_CLK>,
1929 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1930 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1931 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1933 clock-names = "pipe",
1940 pcie1: pcie@608000 {
1941 compatible = "qcom,pcie-msm8996";
1942 power-domains = <&gcc PCIE1_GDSC>;
1943 bus-range = <0x00 0xff>;
1946 status = "disabled";
1948 reg = <0x00608000 0x2000>,
1951 <0x0d100000 0x100000>;
1953 reg-names = "parf", "dbi", "elbi","config";
1955 phys = <&pciephy_1>;
1956 phy-names = "pciephy";
1958 #address-cells = <3>;
1960 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1961 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1963 device_type = "pci";
1965 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1966 interrupt-names = "msi";
1967 #interrupt-cells = <1>;
1968 interrupt-map-mask = <0 0 0 0x7>;
1969 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1970 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1971 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1972 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1974 pinctrl-names = "default", "sleep";
1975 pinctrl-0 = <&pcie1_state_on>;
1976 pinctrl-1 = <&pcie1_state_off>;
1978 linux,pci-domain = <1>;
1980 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1981 <&gcc GCC_PCIE_1_AUX_CLK>,
1982 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1983 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1984 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1986 clock-names = "pipe",
1993 pcie2: pcie@610000 {
1994 compatible = "qcom,pcie-msm8996";
1995 power-domains = <&gcc PCIE2_GDSC>;
1996 bus-range = <0x00 0xff>;
1998 status = "disabled";
1999 reg = <0x00610000 0x2000>,
2002 <0x0e100000 0x100000>;
2004 reg-names = "parf", "dbi", "elbi","config";
2006 phys = <&pciephy_2>;
2007 phy-names = "pciephy";
2009 #address-cells = <3>;
2011 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2012 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2014 device_type = "pci";
2016 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
2017 interrupt-names = "msi";
2018 #interrupt-cells = <1>;
2019 interrupt-map-mask = <0 0 0 0x7>;
2020 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2021 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2022 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2023 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2025 pinctrl-names = "default", "sleep";
2026 pinctrl-0 = <&pcie2_state_on>;
2027 pinctrl-1 = <&pcie2_state_off>;
2029 linux,pci-domain = <2>;
2030 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2031 <&gcc GCC_PCIE_2_AUX_CLK>,
2032 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2033 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2034 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2036 clock-names = "pipe",
2044 ufshc: ufshc@624000 {
2045 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2047 reg = <0x00624000 0x2500>;
2048 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2050 phys = <&ufsphy_lane>;
2051 phy-names = "ufsphy";
2053 power-domains = <&gcc UFS_GDSC>;
2061 "core_clk_unipro_src",
2065 "tx_lane0_sync_clk",
2066 "rx_lane0_sync_clk";
2068 <&gcc UFS_AXI_CLK_SRC>,
2069 <&gcc GCC_UFS_AXI_CLK>,
2070 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2071 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2072 <&gcc GCC_UFS_AHB_CLK>,
2073 <&gcc UFS_ICE_CORE_CLK_SRC>,
2074 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2075 <&gcc GCC_UFS_ICE_CORE_CLK>,
2076 <&rpmcc RPM_SMD_LN_BB_CLK>,
2077 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2078 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2080 <100000000 200000000>,
2085 <150000000 300000000>,
2092 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>,
2093 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>;
2094 interconnect-names = "ufs-ddr", "cpu-ufs";
2096 lanes-per-direction = <1>;
2098 status = "disabled";
2101 ufsphy: phy@627000 {
2102 compatible = "qcom,msm8996-qmp-ufs-phy";
2103 reg = <0x00627000 0x1c4>;
2104 #address-cells = <1>;
2108 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2109 clock-names = "ref";
2111 resets = <&ufshc 0>;
2112 reset-names = "ufsphy";
2113 status = "disabled";
2115 ufsphy_lane: phy@627400 {
2116 reg = <0x627400 0x12c>,
2124 camss: camss@a34000 {
2125 compatible = "qcom,msm8996-camss";
2126 reg = <0x00a34000 0x1000>,
2128 <0x00a35000 0x1000>,
2130 <0x00a36000 0x1000>,
2138 <0x00a10000 0x1000>,
2139 <0x00a14000 0x1000>;
2140 reg-names = "csiphy0",
2154 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2155 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2156 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2157 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2158 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2159 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2160 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2161 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2162 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2163 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2164 interrupt-names = "csiphy0",
2174 power-domains = <&mmcc VFE0_GDSC>,
2176 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2177 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2178 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2179 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2180 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2181 <&mmcc CAMSS_CSI0_AHB_CLK>,
2182 <&mmcc CAMSS_CSI0_CLK>,
2183 <&mmcc CAMSS_CSI0PHY_CLK>,
2184 <&mmcc CAMSS_CSI0PIX_CLK>,
2185 <&mmcc CAMSS_CSI0RDI_CLK>,
2186 <&mmcc CAMSS_CSI1_AHB_CLK>,
2187 <&mmcc CAMSS_CSI1_CLK>,
2188 <&mmcc CAMSS_CSI1PHY_CLK>,
2189 <&mmcc CAMSS_CSI1PIX_CLK>,
2190 <&mmcc CAMSS_CSI1RDI_CLK>,
2191 <&mmcc CAMSS_CSI2_AHB_CLK>,
2192 <&mmcc CAMSS_CSI2_CLK>,
2193 <&mmcc CAMSS_CSI2PHY_CLK>,
2194 <&mmcc CAMSS_CSI2PIX_CLK>,
2195 <&mmcc CAMSS_CSI2RDI_CLK>,
2196 <&mmcc CAMSS_CSI3_AHB_CLK>,
2197 <&mmcc CAMSS_CSI3_CLK>,
2198 <&mmcc CAMSS_CSI3PHY_CLK>,
2199 <&mmcc CAMSS_CSI3PIX_CLK>,
2200 <&mmcc CAMSS_CSI3RDI_CLK>,
2201 <&mmcc CAMSS_AHB_CLK>,
2202 <&mmcc CAMSS_VFE0_CLK>,
2203 <&mmcc CAMSS_CSI_VFE0_CLK>,
2204 <&mmcc CAMSS_VFE0_AHB_CLK>,
2205 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2206 <&mmcc CAMSS_VFE1_CLK>,
2207 <&mmcc CAMSS_CSI_VFE1_CLK>,
2208 <&mmcc CAMSS_VFE1_AHB_CLK>,
2209 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2210 <&mmcc CAMSS_VFE_AHB_CLK>,
2211 <&mmcc CAMSS_VFE_AXI_CLK>;
2212 clock-names = "top_ahb",
2248 iommus = <&vfe_smmu 0>,
2252 status = "disabled";
2254 #address-cells = <1>;
2260 compatible = "qcom,msm8996-cci";
2261 #address-cells = <1>;
2263 reg = <0xa0c000 0x1000>;
2264 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2265 power-domains = <&mmcc CAMSS_GDSC>;
2266 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2267 <&mmcc CAMSS_CCI_AHB_CLK>,
2268 <&mmcc CAMSS_CCI_CLK>,
2269 <&mmcc CAMSS_AHB_CLK>;
2270 clock-names = "camss_top_ahb",
2274 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2275 <&mmcc CAMSS_CCI_CLK>;
2276 assigned-clock-rates = <80000000>, <37500000>;
2277 pinctrl-names = "default";
2278 pinctrl-0 = <&cci0_default &cci1_default>;
2279 status = "disabled";
2281 cci_i2c0: i2c-bus@0 {
2283 clock-frequency = <400000>;
2284 #address-cells = <1>;
2288 cci_i2c1: i2c-bus@1 {
2290 clock-frequency = <400000>;
2291 #address-cells = <1>;
2296 adreno_smmu: iommu@b40000 {
2297 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2298 reg = <0x00b40000 0x10000>;
2300 #global-interrupts = <1>;
2301 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2302 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2303 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2306 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>,
2307 <&mmcc GPU_AHB_CLK>;
2308 clock-names = "bus", "iface";
2310 power-domains = <&mmcc GPU_GDSC>;
2313 venus: video-codec@c00000 {
2314 compatible = "qcom,msm8996-venus";
2315 reg = <0x00c00000 0xff000>;
2316 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2317 power-domains = <&mmcc VENUS_GDSC>;
2318 clocks = <&mmcc VIDEO_CORE_CLK>,
2319 <&mmcc VIDEO_AHB_CLK>,
2320 <&mmcc VIDEO_AXI_CLK>,
2321 <&mmcc VIDEO_MAXI_CLK>;
2322 clock-names = "core", "iface", "bus", "mbus";
2323 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2324 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2325 interconnect-names = "video-mem", "cpu-cfg";
2326 iommus = <&venus_smmu 0x00>,
2346 memory-region = <&venus_mem>;
2347 status = "disabled";
2350 compatible = "venus-decoder";
2351 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2352 clock-names = "core";
2353 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2357 compatible = "venus-encoder";
2358 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2359 clock-names = "core";
2360 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2364 mdp_smmu: iommu@d00000 {
2365 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2366 reg = <0x00d00000 0x10000>;
2368 #global-interrupts = <1>;
2369 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2373 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2374 <&mmcc SMMU_MDP_AHB_CLK>;
2375 clock-names = "bus", "iface";
2377 power-domains = <&mmcc MDSS_GDSC>;
2380 venus_smmu: iommu@d40000 {
2381 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2382 reg = <0x00d40000 0x20000>;
2383 #global-interrupts = <1>;
2384 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2385 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2386 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2387 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2388 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2389 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2390 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2391 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2392 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2393 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2394 <&mmcc SMMU_VIDEO_AHB_CLK>;
2395 clock-names = "bus", "iface";
2400 vfe_smmu: iommu@da0000 {
2401 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2402 reg = <0x00da0000 0x10000>;
2404 #global-interrupts = <1>;
2405 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2406 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2407 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2408 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2409 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2410 <&mmcc SMMU_VFE_AHB_CLK>;
2411 clock-names = "bus", "iface";
2415 lpass_q6_smmu: iommu@1600000 {
2416 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2417 reg = <0x01600000 0x20000>;
2419 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2421 #global-interrupts = <1>;
2422 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2423 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2424 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2425 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2426 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2427 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2428 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2429 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2430 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2431 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2432 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2433 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2434 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2436 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>,
2437 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>;
2438 clock-names = "bus", "iface";
2441 slpi_pil: remoteproc@1c00000 {
2442 compatible = "qcom,msm8996-slpi-pil";
2443 reg = <0x01c00000 0x4000>;
2445 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2446 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2447 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2448 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2449 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2450 interrupt-names = "wdog",
2456 clocks = <&xo_board>,
2457 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
2458 clock-names = "xo", "aggre2";
2460 memory-region = <&slpi_mem>;
2462 qcom,smem-states = <&slpi_smp2p_out 0>;
2463 qcom,smem-state-names = "stop";
2465 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2466 power-domain-names = "ssc_cx";
2468 status = "disabled";
2471 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2474 mboxes = <&apcs_glb 25>;
2475 qcom,smd-edge = <3>;
2476 qcom,remote-pid = <3>;
2480 mss_pil: remoteproc@2080000 {
2481 compatible = "qcom,msm8996-mss-pil";
2482 reg = <0x2080000 0x100>,
2484 reg-names = "qdsp6", "rmb";
2486 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2487 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2488 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2489 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2490 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2491 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2492 interrupt-names = "wdog", "fatal", "ready",
2493 "handover", "stop-ack",
2496 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2497 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2498 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2500 <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2501 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2502 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2503 <&rpmcc RPM_SMD_PCNOC_CLK>,
2504 <&rpmcc RPM_SMD_QDSS_CLK>;
2505 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2506 "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2508 resets = <&gcc GCC_MSS_RESTART>;
2509 reset-names = "mss_restart";
2511 power-domains = <&rpmpd MSM8996_VDDCX>,
2512 <&rpmpd MSM8996_VDDMX>;
2513 power-domain-names = "cx", "mx";
2515 qcom,smem-states = <&mpss_smp2p_out 0>;
2516 qcom,smem-state-names = "stop";
2518 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2520 status = "disabled";
2523 memory-region = <&mba_mem>;
2527 memory-region = <&mpss_mem>;
2531 memory-region = <&mdata_mem>;
2535 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2538 mboxes = <&apcs_glb 12>;
2539 qcom,smd-edge = <0>;
2540 qcom,remote-pid = <1>;
2545 compatible = "arm,coresight-stm", "arm,primecell";
2546 reg = <0x3002000 0x1000>,
2547 <0x8280000 0x180000>;
2548 reg-names = "stm-base", "stm-stimulus-base";
2550 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2551 clock-names = "apb_pclk", "atclk";
2564 compatible = "arm,coresight-tpiu", "arm,primecell";
2565 reg = <0x3020000 0x1000>;
2567 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2568 clock-names = "apb_pclk", "atclk";
2581 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2582 reg = <0x3021000 0x1000>;
2584 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2585 clock-names = "apb_pclk", "atclk";
2588 #address-cells = <1>;
2593 funnel0_in: endpoint {
2602 funnel0_out: endpoint {
2604 <&merge_funnel_in0>;
2611 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2612 reg = <0x3022000 0x1000>;
2614 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2615 clock-names = "apb_pclk", "atclk";
2618 #address-cells = <1>;
2623 funnel1_in: endpoint {
2625 <&apss_merge_funnel_out>;
2632 funnel1_out: endpoint {
2634 <&merge_funnel_in1>;
2641 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2642 reg = <0x3023000 0x1000>;
2644 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2645 clock-names = "apb_pclk", "atclk";
2650 funnel2_out: endpoint {
2652 <&merge_funnel_in2>;
2659 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2660 reg = <0x3025000 0x1000>;
2662 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2663 clock-names = "apb_pclk", "atclk";
2666 #address-cells = <1>;
2671 merge_funnel_in0: endpoint {
2679 merge_funnel_in1: endpoint {
2687 merge_funnel_in2: endpoint {
2696 merge_funnel_out: endpoint {
2704 replicator@3026000 {
2705 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2706 reg = <0x3026000 0x1000>;
2708 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2709 clock-names = "apb_pclk", "atclk";
2713 replicator_in: endpoint {
2721 #address-cells = <1>;
2726 replicator_out0: endpoint {
2734 replicator_out1: endpoint {
2743 compatible = "arm,coresight-tmc", "arm,primecell";
2744 reg = <0x3027000 0x1000>;
2746 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2747 clock-names = "apb_pclk", "atclk";
2753 <&merge_funnel_out>;
2769 compatible = "arm,coresight-tmc", "arm,primecell";
2770 reg = <0x3028000 0x1000>;
2772 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2773 clock-names = "apb_pclk", "atclk";
2787 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2788 reg = <0x3810000 0x1000>;
2790 clocks = <&rpmcc RPM_QDSS_CLK>;
2791 clock-names = "apb_pclk";
2797 compatible = "arm,coresight-etm4x", "arm,primecell";
2798 reg = <0x3840000 0x1000>;
2800 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2801 clock-names = "apb_pclk", "atclk";
2807 etm0_out: endpoint {
2809 <&apss_funnel0_in0>;
2816 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2817 reg = <0x3910000 0x1000>;
2819 clocks = <&rpmcc RPM_QDSS_CLK>;
2820 clock-names = "apb_pclk";
2826 compatible = "arm,coresight-etm4x", "arm,primecell";
2827 reg = <0x3940000 0x1000>;
2829 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2830 clock-names = "apb_pclk", "atclk";
2836 etm1_out: endpoint {
2838 <&apss_funnel0_in1>;
2844 funnel@39b0000 { /* APSS Funnel 0 */
2845 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2846 reg = <0x39b0000 0x1000>;
2848 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2849 clock-names = "apb_pclk", "atclk";
2852 #address-cells = <1>;
2857 apss_funnel0_in0: endpoint {
2858 remote-endpoint = <&etm0_out>;
2864 apss_funnel0_in1: endpoint {
2865 remote-endpoint = <&etm1_out>;
2872 apss_funnel0_out: endpoint {
2874 <&apss_merge_funnel_in0>;
2881 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2882 reg = <0x3a10000 0x1000>;
2884 clocks = <&rpmcc RPM_QDSS_CLK>;
2885 clock-names = "apb_pclk";
2891 compatible = "arm,coresight-etm4x", "arm,primecell";
2892 reg = <0x3a40000 0x1000>;
2894 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2895 clock-names = "apb_pclk", "atclk";
2901 etm2_out: endpoint {
2903 <&apss_funnel1_in0>;
2910 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2911 reg = <0x3b10000 0x1000>;
2913 clocks = <&rpmcc RPM_QDSS_CLK>;
2914 clock-names = "apb_pclk";
2920 compatible = "arm,coresight-etm4x", "arm,primecell";
2921 reg = <0x3b40000 0x1000>;
2923 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2924 clock-names = "apb_pclk", "atclk";
2930 etm3_out: endpoint {
2932 <&apss_funnel1_in1>;
2938 funnel@3bb0000 { /* APSS Funnel 1 */
2939 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2940 reg = <0x3bb0000 0x1000>;
2942 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2943 clock-names = "apb_pclk", "atclk";
2946 #address-cells = <1>;
2951 apss_funnel1_in0: endpoint {
2952 remote-endpoint = <&etm2_out>;
2958 apss_funnel1_in1: endpoint {
2959 remote-endpoint = <&etm3_out>;
2966 apss_funnel1_out: endpoint {
2968 <&apss_merge_funnel_in1>;
2975 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2976 reg = <0x3bc0000 0x1000>;
2978 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2979 clock-names = "apb_pclk", "atclk";
2982 #address-cells = <1>;
2987 apss_merge_funnel_in0: endpoint {
2989 <&apss_funnel0_out>;
2995 apss_merge_funnel_in1: endpoint {
2997 <&apss_funnel1_out>;
3004 apss_merge_funnel_out: endpoint {
3012 kryocc: clock-controller@6400000 {
3013 compatible = "qcom,msm8996-apcc";
3014 reg = <0x06400000 0x90000>;
3016 clock-names = "xo", "sys_apcs_aux";
3017 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3023 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3024 reg = <0x06af8800 0x400>;
3025 #address-cells = <1>;
3029 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
3030 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
3031 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3033 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
3034 <&gcc GCC_USB30_MASTER_CLK>,
3035 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
3036 <&gcc GCC_USB30_SLEEP_CLK>,
3037 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
3038 clock-names = "cfg_noc",
3044 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3045 <&gcc GCC_USB30_MASTER_CLK>;
3046 assigned-clock-rates = <19200000>, <120000000>;
3048 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
3049 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
3050 interconnect-names = "usb-ddr", "apps-usb";
3052 power-domains = <&gcc USB30_GDSC>;
3053 status = "disabled";
3055 usb3_dwc3: usb@6a00000 {
3056 compatible = "snps,dwc3";
3057 reg = <0x06a00000 0xcc00>;
3058 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
3059 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3060 phy-names = "usb2-phy", "usb3-phy";
3061 snps,hird-threshold = /bits/ 8 <0>;
3062 snps,dis_u2_susphy_quirk;
3063 snps,dis_enblslpm_quirk;
3064 snps,is-utmi-l1-suspend;
3069 usb3phy: phy@7410000 {
3070 compatible = "qcom,msm8996-qmp-usb3-phy";
3071 reg = <0x07410000 0x1c4>;
3072 #address-cells = <1>;
3076 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3077 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3078 <&gcc GCC_USB3_CLKREF_CLK>;
3079 clock-names = "aux", "cfg_ahb", "ref";
3081 resets = <&gcc GCC_USB3_PHY_BCR>,
3082 <&gcc GCC_USB3PHY_PHY_BCR>;
3083 reset-names = "phy", "common";
3084 status = "disabled";
3086 ssusb_phy_0: phy@7410200 {
3087 reg = <0x07410200 0x200>,
3093 clock-output-names = "usb3_phy_pipe_clk_src";
3094 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
3095 clock-names = "pipe0";
3099 hsusb_phy1: phy@7411000 {
3100 compatible = "qcom,msm8996-qusb2-phy";
3101 reg = <0x07411000 0x180>;
3104 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3105 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3106 clock-names = "cfg_ahb", "ref";
3108 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3109 nvmem-cells = <&qusb2p_hstx_trim>;
3110 status = "disabled";
3113 hsusb_phy2: phy@7412000 {
3114 compatible = "qcom,msm8996-qusb2-phy";
3115 reg = <0x07412000 0x180>;
3118 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3119 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3120 clock-names = "cfg_ahb", "ref";
3122 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3123 nvmem-cells = <&qusb2s_hstx_trim>;
3124 status = "disabled";
3127 sdhc1: mmc@7464900 {
3128 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3129 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3130 reg-names = "hc", "core";
3132 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3133 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3134 interrupt-names = "hc_irq", "pwr_irq";
3136 clock-names = "iface", "core", "xo";
3137 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3138 <&gcc GCC_SDCC1_APPS_CLK>,
3139 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3140 resets = <&gcc GCC_SDCC1_BCR>;
3142 pinctrl-names = "default", "sleep";
3143 pinctrl-0 = <&sdc1_state_on>;
3144 pinctrl-1 = <&sdc1_state_off>;
3148 status = "disabled";
3151 sdhc2: mmc@74a4900 {
3152 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3153 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3154 reg-names = "hc", "core";
3156 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3157 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3158 interrupt-names = "hc_irq", "pwr_irq";
3160 clock-names = "iface", "core", "xo";
3161 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3162 <&gcc GCC_SDCC2_APPS_CLK>,
3163 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3164 resets = <&gcc GCC_SDCC2_BCR>;
3166 pinctrl-names = "default", "sleep";
3167 pinctrl-0 = <&sdc2_state_on>;
3168 pinctrl-1 = <&sdc2_state_off>;
3171 status = "disabled";
3174 blsp1_dma: dma-controller@7544000 {
3175 compatible = "qcom,bam-v1.7.0";
3176 reg = <0x07544000 0x2b000>;
3177 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3178 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3179 clock-names = "bam_clk";
3180 qcom,controlled-remotely;
3185 blsp1_uart2: serial@7570000 {
3186 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3187 reg = <0x07570000 0x1000>;
3188 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3189 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3190 <&gcc GCC_BLSP1_AHB_CLK>;
3191 clock-names = "core", "iface";
3192 pinctrl-names = "default", "sleep";
3193 pinctrl-0 = <&blsp1_uart2_default>;
3194 pinctrl-1 = <&blsp1_uart2_sleep>;
3195 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3196 dma-names = "tx", "rx";
3197 status = "disabled";
3200 blsp1_spi1: spi@7575000 {
3201 compatible = "qcom,spi-qup-v2.2.1";
3202 reg = <0x07575000 0x600>;
3203 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3204 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3205 <&gcc GCC_BLSP1_AHB_CLK>;
3206 clock-names = "core", "iface";
3207 pinctrl-names = "default", "sleep";
3208 pinctrl-0 = <&blsp1_spi1_default>;
3209 pinctrl-1 = <&blsp1_spi1_sleep>;
3210 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3211 dma-names = "tx", "rx";
3212 #address-cells = <1>;
3214 status = "disabled";
3217 blsp1_i2c3: i2c@7577000 {
3218 compatible = "qcom,i2c-qup-v2.2.1";
3219 reg = <0x07577000 0x1000>;
3220 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3221 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3222 <&gcc GCC_BLSP1_AHB_CLK>;
3223 clock-names = "core", "iface";
3224 pinctrl-names = "default", "sleep";
3225 pinctrl-0 = <&blsp1_i2c3_default>;
3226 pinctrl-1 = <&blsp1_i2c3_sleep>;
3227 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3228 dma-names = "tx", "rx";
3229 #address-cells = <1>;
3231 status = "disabled";
3234 blsp1_i2c6: i2c@757a000 {
3235 compatible = "qcom,i2c-qup-v2.2.1";
3236 reg = <0x757a000 0x1000>;
3237 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3238 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
3239 <&gcc GCC_BLSP1_AHB_CLK>;
3240 clock-names = "core", "iface";
3241 pinctrl-names = "default", "sleep";
3242 pinctrl-0 = <&blsp1_i2c6_default>;
3243 pinctrl-1 = <&blsp1_i2c6_sleep>;
3244 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
3245 dma-names = "tx", "rx";
3246 #address-cells = <1>;
3248 status = "disabled";
3251 blsp2_dma: dma-controller@7584000 {
3252 compatible = "qcom,bam-v1.7.0";
3253 reg = <0x07584000 0x2b000>;
3254 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3255 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3256 clock-names = "bam_clk";
3257 qcom,controlled-remotely;
3262 blsp2_uart2: serial@75b0000 {
3263 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3264 reg = <0x075b0000 0x1000>;
3265 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3266 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3267 <&gcc GCC_BLSP2_AHB_CLK>;
3268 clock-names = "core", "iface";
3269 status = "disabled";
3272 blsp2_uart3: serial@75b1000 {
3273 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3274 reg = <0x075b1000 0x1000>;
3275 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3276 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3277 <&gcc GCC_BLSP2_AHB_CLK>;
3278 clock-names = "core", "iface";
3279 status = "disabled";
3282 blsp2_i2c1: i2c@75b5000 {
3283 compatible = "qcom,i2c-qup-v2.2.1";
3284 reg = <0x075b5000 0x1000>;
3285 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3286 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3287 <&gcc GCC_BLSP2_AHB_CLK>;
3288 clock-names = "core", "iface";
3289 pinctrl-names = "default", "sleep";
3290 pinctrl-0 = <&blsp2_i2c1_default>;
3291 pinctrl-1 = <&blsp2_i2c1_sleep>;
3292 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3293 dma-names = "tx", "rx";
3294 #address-cells = <1>;
3296 status = "disabled";
3299 blsp2_i2c2: i2c@75b6000 {
3300 compatible = "qcom,i2c-qup-v2.2.1";
3301 reg = <0x075b6000 0x1000>;
3302 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3303 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3304 <&gcc GCC_BLSP2_AHB_CLK>;
3305 clock-names = "core", "iface";
3306 pinctrl-names = "default", "sleep";
3307 pinctrl-0 = <&blsp2_i2c2_default>;
3308 pinctrl-1 = <&blsp2_i2c2_sleep>;
3309 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3310 dma-names = "tx", "rx";
3311 #address-cells = <1>;
3313 status = "disabled";
3316 blsp2_i2c3: i2c@75b7000 {
3317 compatible = "qcom,i2c-qup-v2.2.1";
3318 reg = <0x075b7000 0x1000>;
3319 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3320 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3321 <&gcc GCC_BLSP2_AHB_CLK>;
3322 clock-names = "core", "iface";
3323 clock-frequency = <400000>;
3324 pinctrl-names = "default", "sleep";
3325 pinctrl-0 = <&blsp2_i2c3_default>;
3326 pinctrl-1 = <&blsp2_i2c3_sleep>;
3327 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3328 dma-names = "tx", "rx";
3329 #address-cells = <1>;
3331 status = "disabled";
3334 blsp2_i2c5: i2c@75b9000 {
3335 compatible = "qcom,i2c-qup-v2.2.1";
3336 reg = <0x75b9000 0x1000>;
3337 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3338 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3339 <&gcc GCC_BLSP2_AHB_CLK>;
3340 clock-names = "core", "iface";
3341 pinctrl-names = "default";
3342 pinctrl-0 = <&blsp2_i2c5_default>;
3343 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3344 dma-names = "tx", "rx";
3345 #address-cells = <1>;
3347 status = "disabled";
3350 blsp2_i2c6: i2c@75ba000 {
3351 compatible = "qcom,i2c-qup-v2.2.1";
3352 reg = <0x75ba000 0x1000>;
3353 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3354 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3355 <&gcc GCC_BLSP2_AHB_CLK>;
3356 clock-names = "core", "iface";
3357 pinctrl-names = "default", "sleep";
3358 pinctrl-0 = <&blsp2_i2c6_default>;
3359 pinctrl-1 = <&blsp2_i2c6_sleep>;
3360 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3361 dma-names = "tx", "rx";
3362 #address-cells = <1>;
3364 status = "disabled";
3367 blsp2_spi6: spi@75ba000 {
3368 compatible = "qcom,spi-qup-v2.2.1";
3369 reg = <0x075ba000 0x600>;
3370 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3371 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3372 <&gcc GCC_BLSP2_AHB_CLK>;
3373 clock-names = "core", "iface";
3374 pinctrl-names = "default", "sleep";
3375 pinctrl-0 = <&blsp2_spi6_default>;
3376 pinctrl-1 = <&blsp2_spi6_sleep>;
3377 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3378 dma-names = "tx", "rx";
3379 #address-cells = <1>;
3381 status = "disabled";
3385 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3386 reg = <0x076f8800 0x400>;
3387 #address-cells = <1>;
3391 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
3392 interrupt-names = "hs_phy_irq";
3394 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3395 <&gcc GCC_USB20_MASTER_CLK>,
3396 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3397 <&gcc GCC_USB20_SLEEP_CLK>,
3398 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3399 clock-names = "cfg_noc",
3405 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3406 <&gcc GCC_USB20_MASTER_CLK>;
3407 assigned-clock-rates = <19200000>, <60000000>;
3409 power-domains = <&gcc USB30_GDSC>;
3410 qcom,select-utmi-as-pipe-clk;
3411 status = "disabled";
3413 usb2_dwc3: usb@7600000 {
3414 compatible = "snps,dwc3";
3415 reg = <0x07600000 0xcc00>;
3416 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3417 phys = <&hsusb_phy2>;
3418 phy-names = "usb2-phy";
3419 maximum-speed = "high-speed";
3420 snps,dis_u2_susphy_quirk;
3421 snps,dis_enblslpm_quirk;
3425 slimbam: dma-controller@9184000 {
3426 compatible = "qcom,bam-v1.7.0";
3427 qcom,controlled-remotely;
3428 reg = <0x09184000 0x32000>;
3429 num-channels = <31>;
3430 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
3436 slim_msm: slim-ngd@91c0000 {
3437 compatible = "qcom,slim-ngd-v1.5.0";
3438 reg = <0x091c0000 0x2c000>;
3439 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3440 dmas = <&slimbam 3>, <&slimbam 4>;
3441 dma-names = "rx", "tx";
3442 #address-cells = <1>;
3445 status = "disabled";
3448 adsp_pil: remoteproc@9300000 {
3449 compatible = "qcom,msm8996-adsp-pil";
3450 reg = <0x09300000 0x80000>;
3452 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3453 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3454 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3455 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3456 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3457 interrupt-names = "wdog", "fatal", "ready",
3458 "handover", "stop-ack";
3460 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3463 memory-region = <&adsp_mem>;
3465 qcom,smem-states = <&adsp_smp2p_out 0>;
3466 qcom,smem-state-names = "stop";
3468 power-domains = <&rpmpd MSM8996_VDDCX>;
3469 power-domain-names = "cx";
3471 status = "disabled";
3474 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3477 mboxes = <&apcs_glb 8>;
3478 qcom,smd-edge = <1>;
3479 qcom,remote-pid = <2>;
3482 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3483 compatible = "qcom,apr-v2";
3484 qcom,smd-channels = "apr_audio_svc";
3485 qcom,domain = <APR_DOMAIN_ADSP>;
3486 #address-cells = <1>;
3490 reg = <APR_SVC_ADSP_CORE>;
3491 compatible = "qcom,q6core";
3495 compatible = "qcom,q6afe";
3496 reg = <APR_SVC_AFE>;
3498 compatible = "qcom,q6afe-dais";
3499 #address-cells = <1>;
3501 #sound-dai-cells = <1>;
3509 compatible = "qcom,q6asm";
3510 reg = <APR_SVC_ASM>;
3512 compatible = "qcom,q6asm-dais";
3513 #address-cells = <1>;
3515 #sound-dai-cells = <1>;
3516 iommus = <&lpass_q6_smmu 1>;
3521 compatible = "qcom,q6adm";
3522 reg = <APR_SVC_ADM>;
3523 q6routing: routing {
3524 compatible = "qcom,q6adm-routing";
3525 #sound-dai-cells = <0>;
3532 apcs_glb: mailbox@9820000 {
3533 compatible = "qcom,msm8996-apcs-hmss-global";
3534 reg = <0x09820000 0x1000>;
3541 #address-cells = <1>;
3544 compatible = "arm,armv7-timer-mem";
3545 reg = <0x09840000 0x1000>;
3546 clock-frequency = <19200000>;
3550 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3552 reg = <0x09850000 0x1000>,
3553 <0x09860000 0x1000>;
3558 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3559 reg = <0x09870000 0x1000>;
3560 status = "disabled";
3565 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3566 reg = <0x09880000 0x1000>;
3567 status = "disabled";
3572 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3573 reg = <0x09890000 0x1000>;
3574 status = "disabled";
3579 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3580 reg = <0x098a0000 0x1000>;
3581 status = "disabled";
3586 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3587 reg = <0x098b0000 0x1000>;
3588 status = "disabled";
3593 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3594 reg = <0x098c0000 0x1000>;
3595 status = "disabled";
3599 saw3: syscon@9a10000 {
3600 compatible = "syscon";
3601 reg = <0x09a10000 0x1000>;
3604 cbf: clock-controller@9a11000 {
3605 compatible = "qcom,msm8996-cbf";
3606 reg = <0x09a11000 0x10000>;
3607 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
3609 #interconnect-cells = <1>;
3612 intc: interrupt-controller@9bc0000 {
3613 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3614 #interrupt-cells = <3>;
3615 interrupt-controller;
3616 #redistributor-regions = <1>;
3617 redistributor-stride = <0x0 0x40000>;
3618 reg = <0x09bc0000 0x10000>,
3619 <0x09c00000 0x100000>;
3620 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3629 polling-delay-passive = <250>;
3630 polling-delay = <1000>;
3632 thermal-sensors = <&tsens0 3>;
3635 cpu0_alert0: trip-point0 {
3636 temperature = <75000>;
3637 hysteresis = <2000>;
3641 cpu0_crit: cpu-crit {
3642 temperature = <110000>;
3643 hysteresis = <2000>;
3650 polling-delay-passive = <250>;
3651 polling-delay = <1000>;
3653 thermal-sensors = <&tsens0 5>;
3656 cpu1_alert0: trip-point0 {
3657 temperature = <75000>;
3658 hysteresis = <2000>;
3662 cpu1_crit: cpu-crit {
3663 temperature = <110000>;
3664 hysteresis = <2000>;
3671 polling-delay-passive = <250>;
3672 polling-delay = <1000>;
3674 thermal-sensors = <&tsens0 8>;
3677 cpu2_alert0: trip-point0 {
3678 temperature = <75000>;
3679 hysteresis = <2000>;
3683 cpu2_crit: cpu-crit {
3684 temperature = <110000>;
3685 hysteresis = <2000>;
3692 polling-delay-passive = <250>;
3693 polling-delay = <1000>;
3695 thermal-sensors = <&tsens0 10>;
3698 cpu3_alert0: trip-point0 {
3699 temperature = <75000>;
3700 hysteresis = <2000>;
3704 cpu3_crit: cpu-crit {
3705 temperature = <110000>;
3706 hysteresis = <2000>;
3713 polling-delay-passive = <250>;
3714 polling-delay = <1000>;
3716 thermal-sensors = <&tsens1 6>;
3719 gpu1_alert0: trip-point0 {
3720 temperature = <90000>;
3721 hysteresis = <2000>;
3728 trip = <&gpu1_alert0>;
3729 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3734 gpu-bottom-thermal {
3735 polling-delay-passive = <250>;
3736 polling-delay = <1000>;
3738 thermal-sensors = <&tsens1 7>;
3741 gpu2_alert0: trip-point0 {
3742 temperature = <90000>;
3743 hysteresis = <2000>;
3750 trip = <&gpu2_alert0>;
3751 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3757 polling-delay-passive = <250>;
3758 polling-delay = <1000>;
3760 thermal-sensors = <&tsens0 1>;
3763 m4m_alert0: trip-point0 {
3764 temperature = <90000>;
3765 hysteresis = <2000>;
3771 l3-or-venus-thermal {
3772 polling-delay-passive = <250>;
3773 polling-delay = <1000>;
3775 thermal-sensors = <&tsens0 2>;
3778 l3_or_venus_alert0: trip-point0 {
3779 temperature = <90000>;
3780 hysteresis = <2000>;
3786 cluster0-l2-thermal {
3787 polling-delay-passive = <250>;
3788 polling-delay = <1000>;
3790 thermal-sensors = <&tsens0 7>;
3793 cluster0_l2_alert0: trip-point0 {
3794 temperature = <90000>;
3795 hysteresis = <2000>;
3801 cluster1-l2-thermal {
3802 polling-delay-passive = <250>;
3803 polling-delay = <1000>;
3805 thermal-sensors = <&tsens0 12>;
3808 cluster1_l2_alert0: trip-point0 {
3809 temperature = <90000>;
3810 hysteresis = <2000>;
3817 polling-delay-passive = <250>;
3818 polling-delay = <1000>;
3820 thermal-sensors = <&tsens1 1>;
3823 camera_alert0: trip-point0 {
3824 temperature = <90000>;
3825 hysteresis = <2000>;
3832 polling-delay-passive = <250>;
3833 polling-delay = <1000>;
3835 thermal-sensors = <&tsens1 2>;
3838 q6_dsp_alert0: trip-point0 {
3839 temperature = <90000>;
3840 hysteresis = <2000>;
3847 polling-delay-passive = <250>;
3848 polling-delay = <1000>;
3850 thermal-sensors = <&tsens1 3>;
3853 mem_alert0: trip-point0 {
3854 temperature = <90000>;
3855 hysteresis = <2000>;
3862 polling-delay-passive = <250>;
3863 polling-delay = <1000>;
3865 thermal-sensors = <&tsens1 4>;
3868 modemtx_alert0: trip-point0 {
3869 temperature = <90000>;
3870 hysteresis = <2000>;
3878 compatible = "arm,armv8-timer";
3879 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3880 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3881 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3882 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;