arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8996.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/soc/qcom,apr.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         clocks {
  24                 xo_board: xo-board {
  25                         compatible = "fixed-clock";
  26                         #clock-cells = <0>;
  27                         clock-frequency = <19200000>;
  28                         clock-output-names = "xo_board";
  29                 };
  30
  31                 sleep_clk: sleep-clk {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <32764>;
  35                         clock-output-names = "sleep_clk";
  36                 };
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 CPU0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "qcom,kryo";
  46                         reg = <0x0 0x0>;
  47                         enable-method = "psci";
  48                         cpu-idle-states = <&CPU_SLEEP_0>;
  49                         capacity-dmips-mhz = <1024>;
  50                         clocks = <&kryocc 0>;
  51                         operating-points-v2 = <&cluster0_opp>;
  52                         #cooling-cells = <2>;
  53                         next-level-cache = <&L2_0>;
  54                         L2_0: l2-cache {
  55                               compatible = "cache";
  56                               cache-level = <2>;
  57                         };
  58                 };
  59
  60                 CPU1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "qcom,kryo";
  63                         reg = <0x0 0x1>;
  64                         enable-method = "psci";
  65                         cpu-idle-states = <&CPU_SLEEP_0>;
  66                         capacity-dmips-mhz = <1024>;
  67                         clocks = <&kryocc 0>;
  68                         operating-points-v2 = <&cluster0_opp>;
  69                         #cooling-cells = <2>;
  70                         next-level-cache = <&L2_0>;
  71                 };
  72
  73                 CPU2: cpu@100 {
  74                         device_type = "cpu";
  75                         compatible = "qcom,kryo";
  76                         reg = <0x0 0x100>;
  77                         enable-method = "psci";
  78                         cpu-idle-states = <&CPU_SLEEP_0>;
  79                         capacity-dmips-mhz = <1024>;
  80                         clocks = <&kryocc 1>;
  81                         operating-points-v2 = <&cluster1_opp>;
  82                         #cooling-cells = <2>;
  83                         next-level-cache = <&L2_1>;
  84                         L2_1: l2-cache {
  85                               compatible = "cache";
  86                               cache-level = <2>;
  87                         };
  88                 };
  89
  90                 CPU3: cpu@101 {
  91                         device_type = "cpu";
  92                         compatible = "qcom,kryo";
  93                         reg = <0x0 0x101>;
  94                         enable-method = "psci";
  95                         cpu-idle-states = <&CPU_SLEEP_0>;
  96                         capacity-dmips-mhz = <1024>;
  97                         clocks = <&kryocc 1>;
  98                         operating-points-v2 = <&cluster1_opp>;
  99                         #cooling-cells = <2>;
 100                         next-level-cache = <&L2_1>;
 101                 };
 102
 103                 cpu-map {
 104                         cluster0 {
 105                                 core0 {
 106                                         cpu = <&CPU0>;
 107                                 };
 108
 109                                 core1 {
 110                                         cpu = <&CPU1>;
 111                                 };
 112                         };
 113
 114                         cluster1 {
 115                                 core0 {
 116                                         cpu = <&CPU2>;
 117                                 };
 118
 119                                 core1 {
 120                                         cpu = <&CPU3>;
 121                                 };
 122                         };
 123                 };
 124
 125                 idle-states {
 126                         entry-method = "psci";
 127
 128                         CPU_SLEEP_0: cpu-sleep-0 {
 129                                 compatible = "arm,idle-state";
 130                                 idle-state-name = "standalone-power-collapse";
 131                                 arm,psci-suspend-param = <0x00000004>;
 132                                 entry-latency-us = <130>;
 133                                 exit-latency-us = <80>;
 134                                 min-residency-us = <300>;
 135                         };
 136                 };
 137         };
 138
 139         cluster0_opp: opp-table-cluster0 {
 140                 compatible = "operating-points-v2-kryo-cpu";
 141                 nvmem-cells = <&speedbin_efuse>;
 142                 opp-shared;
 143
 144                 /* Nominal fmax for now */
 145                 opp-307200000 {
 146                         opp-hz = /bits/ 64 <307200000>;
 147                         opp-supported-hw = <0x7>;
 148                         clock-latency-ns = <200000>;
 149                 };
 150                 opp-422400000 {
 151                         opp-hz = /bits/ 64 <422400000>;
 152                         opp-supported-hw = <0x7>;
 153                         clock-latency-ns = <200000>;
 154                 };
 155                 opp-480000000 {
 156                         opp-hz = /bits/ 64 <480000000>;
 157                         opp-supported-hw = <0x7>;
 158                         clock-latency-ns = <200000>;
 159                 };
 160                 opp-556800000 {
 161                         opp-hz = /bits/ 64 <556800000>;
 162                         opp-supported-hw = <0x7>;
 163                         clock-latency-ns = <200000>;
 164                 };
 165                 opp-652800000 {
 166                         opp-hz = /bits/ 64 <652800000>;
 167                         opp-supported-hw = <0x7>;
 168                         clock-latency-ns = <200000>;
 169                 };
 170                 opp-729600000 {
 171                         opp-hz = /bits/ 64 <729600000>;
 172                         opp-supported-hw = <0x7>;
 173                         clock-latency-ns = <200000>;
 174                 };
 175                 opp-844800000 {
 176                         opp-hz = /bits/ 64 <844800000>;
 177                         opp-supported-hw = <0x7>;
 178                         clock-latency-ns = <200000>;
 179                 };
 180                 opp-960000000 {
 181                         opp-hz = /bits/ 64 <960000000>;
 182                         opp-supported-hw = <0x7>;
 183                         clock-latency-ns = <200000>;
 184                 };
 185                 opp-1036800000 {
 186                         opp-hz = /bits/ 64 <1036800000>;
 187                         opp-supported-hw = <0x7>;
 188                         clock-latency-ns = <200000>;
 189                 };
 190                 opp-1113600000 {
 191                         opp-hz = /bits/ 64 <1113600000>;
 192                         opp-supported-hw = <0x7>;
 193                         clock-latency-ns = <200000>;
 194                 };
 195                 opp-1190400000 {
 196                         opp-hz = /bits/ 64 <1190400000>;
 197                         opp-supported-hw = <0x7>;
 198                         clock-latency-ns = <200000>;
 199                 };
 200                 opp-1228800000 {
 201                         opp-hz = /bits/ 64 <1228800000>;
 202                         opp-supported-hw = <0x7>;
 203                         clock-latency-ns = <200000>;
 204                 };
 205                 opp-1324800000 {
 206                         opp-hz = /bits/ 64 <1324800000>;
 207                         opp-supported-hw = <0x5>;
 208                         clock-latency-ns = <200000>;
 209                 };
 210                 opp-1363200000 {
 211                         opp-hz = /bits/ 64 <1363200000>;
 212                         opp-supported-hw = <0x2>;
 213                         clock-latency-ns = <200000>;
 214                 };
 215                 opp-1401600000 {
 216                         opp-hz = /bits/ 64 <1401600000>;
 217                         opp-supported-hw = <0x5>;
 218                         clock-latency-ns = <200000>;
 219                 };
 220                 opp-1478400000 {
 221                         opp-hz = /bits/ 64 <1478400000>;
 222                         opp-supported-hw = <0x1>;
 223                         clock-latency-ns = <200000>;
 224                 };
 225                 opp-1497600000 {
 226                         opp-hz = /bits/ 64 <1497600000>;
 227                         opp-supported-hw = <0x04>;
 228                         clock-latency-ns = <200000>;
 229                 };
 230                 opp-1593600000 {
 231                         opp-hz = /bits/ 64 <1593600000>;
 232                         opp-supported-hw = <0x1>;
 233                         clock-latency-ns = <200000>;
 234                 };
 235         };
 236
 237         cluster1_opp: opp-table-cluster1 {
 238                 compatible = "operating-points-v2-kryo-cpu";
 239                 nvmem-cells = <&speedbin_efuse>;
 240                 opp-shared;
 241
 242                 /* Nominal fmax for now */
 243                 opp-307200000 {
 244                         opp-hz = /bits/ 64 <307200000>;
 245                         opp-supported-hw = <0x7>;
 246                         clock-latency-ns = <200000>;
 247                 };
 248                 opp-403200000 {
 249                         opp-hz = /bits/ 64 <403200000>;
 250                         opp-supported-hw = <0x7>;
 251                         clock-latency-ns = <200000>;
 252                 };
 253                 opp-480000000 {
 254                         opp-hz = /bits/ 64 <480000000>;
 255                         opp-supported-hw = <0x7>;
 256                         clock-latency-ns = <200000>;
 257                 };
 258                 opp-556800000 {
 259                         opp-hz = /bits/ 64 <556800000>;
 260                         opp-supported-hw = <0x7>;
 261                         clock-latency-ns = <200000>;
 262                 };
 263                 opp-652800000 {
 264                         opp-hz = /bits/ 64 <652800000>;
 265                         opp-supported-hw = <0x7>;
 266                         clock-latency-ns = <200000>;
 267                 };
 268                 opp-729600000 {
 269                         opp-hz = /bits/ 64 <729600000>;
 270                         opp-supported-hw = <0x7>;
 271                         clock-latency-ns = <200000>;
 272                 };
 273                 opp-806400000 {
 274                         opp-hz = /bits/ 64 <806400000>;
 275                         opp-supported-hw = <0x7>;
 276                         clock-latency-ns = <200000>;
 277                 };
 278                 opp-883200000 {
 279                         opp-hz = /bits/ 64 <883200000>;
 280                         opp-supported-hw = <0x7>;
 281                         clock-latency-ns = <200000>;
 282                 };
 283                 opp-940800000 {
 284                         opp-hz = /bits/ 64 <940800000>;
 285                         opp-supported-hw = <0x7>;
 286                         clock-latency-ns = <200000>;
 287                 };
 288                 opp-1036800000 {
 289                         opp-hz = /bits/ 64 <1036800000>;
 290                         opp-supported-hw = <0x7>;
 291                         clock-latency-ns = <200000>;
 292                 };
 293                 opp-1113600000 {
 294                         opp-hz = /bits/ 64 <1113600000>;
 295                         opp-supported-hw = <0x7>;
 296                         clock-latency-ns = <200000>;
 297                 };
 298                 opp-1190400000 {
 299                         opp-hz = /bits/ 64 <1190400000>;
 300                         opp-supported-hw = <0x7>;
 301                         clock-latency-ns = <200000>;
 302                 };
 303                 opp-1248000000 {
 304                         opp-hz = /bits/ 64 <1248000000>;
 305                         opp-supported-hw = <0x7>;
 306                         clock-latency-ns = <200000>;
 307                 };
 308                 opp-1324800000 {
 309                         opp-hz = /bits/ 64 <1324800000>;
 310                         opp-supported-hw = <0x7>;
 311                         clock-latency-ns = <200000>;
 312                 };
 313                 opp-1401600000 {
 314                         opp-hz = /bits/ 64 <1401600000>;
 315                         opp-supported-hw = <0x7>;
 316                         clock-latency-ns = <200000>;
 317                 };
 318                 opp-1478400000 {
 319                         opp-hz = /bits/ 64 <1478400000>;
 320                         opp-supported-hw = <0x7>;
 321                         clock-latency-ns = <200000>;
 322                 };
 323                 opp-1555200000 {
 324                         opp-hz = /bits/ 64 <1555200000>;
 325                         opp-supported-hw = <0x7>;
 326                         clock-latency-ns = <200000>;
 327                 };
 328                 opp-1632000000 {
 329                         opp-hz = /bits/ 64 <1632000000>;
 330                         opp-supported-hw = <0x7>;
 331                         clock-latency-ns = <200000>;
 332                 };
 333                 opp-1708800000 {
 334                         opp-hz = /bits/ 64 <1708800000>;
 335                         opp-supported-hw = <0x7>;
 336                         clock-latency-ns = <200000>;
 337                 };
 338                 opp-1785600000 {
 339                         opp-hz = /bits/ 64 <1785600000>;
 340                         opp-supported-hw = <0x7>;
 341                         clock-latency-ns = <200000>;
 342                 };
 343                 opp-1804800000 {
 344                         opp-hz = /bits/ 64 <1804800000>;
 345                         opp-supported-hw = <0x6>;
 346                         clock-latency-ns = <200000>;
 347                 };
 348                 opp-1824000000 {
 349                         opp-hz = /bits/ 64 <1824000000>;
 350                         opp-supported-hw = <0x1>;
 351                         clock-latency-ns = <200000>;
 352                 };
 353                 opp-1900800000 {
 354                         opp-hz = /bits/ 64 <1900800000>;
 355                         opp-supported-hw = <0x4>;
 356                         clock-latency-ns = <200000>;
 357                 };
 358                 opp-1920000000 {
 359                         opp-hz = /bits/ 64 <1920000000>;
 360                         opp-supported-hw = <0x1>;
 361                         clock-latency-ns = <200000>;
 362                 };
 363                 opp-1996800000 {
 364                         opp-hz = /bits/ 64 <1996800000>;
 365                         opp-supported-hw = <0x1>;
 366                         clock-latency-ns = <200000>;
 367                 };
 368                 opp-2073600000 {
 369                         opp-hz = /bits/ 64 <2073600000>;
 370                         opp-supported-hw = <0x1>;
 371                         clock-latency-ns = <200000>;
 372                 };
 373                 opp-2150400000 {
 374                         opp-hz = /bits/ 64 <2150400000>;
 375                         opp-supported-hw = <0x1>;
 376                         clock-latency-ns = <200000>;
 377                 };
 378         };
 379
 380         firmware {
 381                 scm {
 382                         compatible = "qcom,scm-msm8996", "qcom,scm";
 383                         qcom,dload-mode = <&tcsr_2 0x13000>;
 384                 };
 385         };
 386
 387         memory@80000000 {
 388                 device_type = "memory";
 389                 /* We expect the bootloader to fill in the reg */
 390                 reg = <0x0 0x80000000 0x0 0x0>;
 391         };
 392
 393         etm {
 394                 compatible = "qcom,coresight-remote-etm";
 395
 396                 out-ports {
 397                         port {
 398                                 modem_etm_out_funnel_in2: endpoint {
 399                                         remote-endpoint =
 400                                           <&funnel_in2_in_modem_etm>;
 401                                 };
 402                         };
 403                 };
 404         };
 405
 406         psci {
 407                 compatible = "arm,psci-1.0";
 408                 method = "smc";
 409         };
 410
 411         reserved-memory {
 412                 #address-cells = <2>;
 413                 #size-cells = <2>;
 414                 ranges;
 415
 416                 hyp_mem: memory@85800000 {
 417                         reg = <0x0 0x85800000 0x0 0x600000>;
 418                         no-map;
 419                 };
 420
 421                 xbl_mem: memory@85e00000 {
 422                         reg = <0x0 0x85e00000 0x0 0x200000>;
 423                         no-map;
 424                 };
 425
 426                 smem_mem: smem-mem@86000000 {
 427                         reg = <0x0 0x86000000 0x0 0x200000>;
 428                         no-map;
 429                 };
 430
 431                 tz_mem: memory@86200000 {
 432                         reg = <0x0 0x86200000 0x0 0x2600000>;
 433                         no-map;
 434                 };
 435
 436                 rmtfs_mem: rmtfs {
 437                         compatible = "qcom,rmtfs-mem";
 438
 439                         size = <0x0 0x200000>;
 440                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
 441                         no-map;
 442
 443                         qcom,client-id = <1>;
 444                         qcom,vmid = <15>;
 445                 };
 446
 447                 mpss_mem: mpss@88800000 {
 448                         reg = <0x0 0x88800000 0x0 0x6200000>;
 449                         no-map;
 450                 };
 451
 452                 adsp_mem: adsp@8ea00000 {
 453                         reg = <0x0 0x8ea00000 0x0 0x1b00000>;
 454                         no-map;
 455                 };
 456
 457                 slpi_mem: slpi@90500000 {
 458                         reg = <0x0 0x90500000 0x0 0xa00000>;
 459                         no-map;
 460                 };
 461
 462                 gpu_mem: gpu@90f00000 {
 463                         compatible = "shared-dma-pool";
 464                         reg = <0x0 0x90f00000 0x0 0x100000>;
 465                         no-map;
 466                 };
 467
 468                 venus_mem: venus@91000000 {
 469                         reg = <0x0 0x91000000 0x0 0x500000>;
 470                         no-map;
 471                 };
 472
 473                 mba_mem: mba@91500000 {
 474                         reg = <0x0 0x91500000 0x0 0x200000>;
 475                         no-map;
 476                 };
 477         };
 478
 479         rpm-glink {
 480                 compatible = "qcom,glink-rpm";
 481
 482                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 483
 484                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 485
 486                 mboxes = <&apcs_glb 0>;
 487
 488                 rpm_requests: rpm-requests {
 489                         compatible = "qcom,rpm-msm8996";
 490                         qcom,glink-channels = "rpm_requests";
 491
 492                         rpmcc: qcom,rpmcc {
 493                                 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
 494                                 #clock-cells = <1>;
 495                                 clocks = <&xo_board>;
 496                                 clock-names = "xo";
 497                         };
 498
 499                         rpmpd: power-controller {
 500                                 compatible = "qcom,msm8996-rpmpd";
 501                                 #power-domain-cells = <1>;
 502                                 operating-points-v2 = <&rpmpd_opp_table>;
 503
 504                                 rpmpd_opp_table: opp-table {
 505                                         compatible = "operating-points-v2";
 506
 507                                         rpmpd_opp1: opp1 {
 508                                                 opp-level = <1>;
 509                                         };
 510
 511                                         rpmpd_opp2: opp2 {
 512                                                 opp-level = <2>;
 513                                         };
 514
 515                                         rpmpd_opp3: opp3 {
 516                                                 opp-level = <3>;
 517                                         };
 518
 519                                         rpmpd_opp4: opp4 {
 520                                                 opp-level = <4>;
 521                                         };
 522
 523                                         rpmpd_opp5: opp5 {
 524                                                 opp-level = <5>;
 525                                         };
 526
 527                                         rpmpd_opp6: opp6 {
 528                                                 opp-level = <6>;
 529                                         };
 530                                 };
 531                         };
 532                 };
 533         };
 534
 535         smem {
 536                 compatible = "qcom,smem";
 537                 memory-region = <&smem_mem>;
 538                 hwlocks = <&tcsr_mutex 3>;
 539         };
 540
 541         smp2p-adsp {
 542                 compatible = "qcom,smp2p";
 543                 qcom,smem = <443>, <429>;
 544
 545                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 546
 547                 mboxes = <&apcs_glb 10>;
 548
 549                 qcom,local-pid = <0>;
 550                 qcom,remote-pid = <2>;
 551
 552                 adsp_smp2p_out: master-kernel {
 553                         qcom,entry-name = "master-kernel";
 554                         #qcom,smem-state-cells = <1>;
 555                 };
 556
 557                 adsp_smp2p_in: slave-kernel {
 558                         qcom,entry-name = "slave-kernel";
 559
 560                         interrupt-controller;
 561                         #interrupt-cells = <2>;
 562                 };
 563         };
 564
 565         smp2p-mpss {
 566                 compatible = "qcom,smp2p";
 567                 qcom,smem = <435>, <428>;
 568
 569                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 570
 571                 mboxes = <&apcs_glb 14>;
 572
 573                 qcom,local-pid = <0>;
 574                 qcom,remote-pid = <1>;
 575
 576                 mpss_smp2p_out: master-kernel {
 577                         qcom,entry-name = "master-kernel";
 578                         #qcom,smem-state-cells = <1>;
 579                 };
 580
 581                 mpss_smp2p_in: slave-kernel {
 582                         qcom,entry-name = "slave-kernel";
 583
 584                         interrupt-controller;
 585                         #interrupt-cells = <2>;
 586                 };
 587         };
 588
 589         smp2p-slpi {
 590                 compatible = "qcom,smp2p";
 591                 qcom,smem = <481>, <430>;
 592
 593                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 594
 595                 mboxes = <&apcs_glb 26>;
 596
 597                 qcom,local-pid = <0>;
 598                 qcom,remote-pid = <3>;
 599
 600                 slpi_smp2p_out: master-kernel {
 601                         qcom,entry-name = "master-kernel";
 602                         #qcom,smem-state-cells = <1>;
 603                 };
 604
 605                 slpi_smp2p_in: slave-kernel {
 606                         qcom,entry-name = "slave-kernel";
 607
 608                         interrupt-controller;
 609                         #interrupt-cells = <2>;
 610                 };
 611         };
 612
 613         soc: soc {
 614                 #address-cells = <1>;
 615                 #size-cells = <1>;
 616                 ranges = <0 0 0 0xffffffff>;
 617                 compatible = "simple-bus";
 618
 619                 pcie_phy: phy-wrapper@34000 {
 620                         compatible = "qcom,msm8996-qmp-pcie-phy";
 621                         reg = <0x00034000 0x488>;
 622                         #address-cells = <1>;
 623                         #size-cells = <1>;
 624                         ranges = <0x0 0x00034000 0x4000>;
 625
 626                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 627                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 628                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 629                         clock-names = "aux", "cfg_ahb", "ref";
 630
 631                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 632                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 633                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 634                         reset-names = "phy", "common", "cfg";
 635
 636                         status = "disabled";
 637
 638                         pciephy_0: phy@1000 {
 639                                 reg = <0x1000 0x130>,
 640                                       <0x1200 0x200>,
 641                                       <0x1400 0x1dc>;
 642
 643                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 644                                 clock-names = "pipe0";
 645                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 646                                 reset-names = "lane0";
 647
 648                                 #clock-cells = <0>;
 649                                 clock-output-names = "pcie_0_pipe_clk_src";
 650
 651                                 #phy-cells = <0>;
 652                         };
 653
 654                         pciephy_1: phy@2000 {
 655                                 reg = <0x2000 0x130>,
 656                                       <0x2200 0x200>,
 657                                       <0x2400 0x1dc>;
 658
 659                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 660                                 clock-names = "pipe1";
 661                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 662                                 reset-names = "lane1";
 663
 664                                 #clock-cells = <0>;
 665                                 clock-output-names = "pcie_1_pipe_clk_src";
 666
 667                                 #phy-cells = <0>;
 668                         };
 669
 670                         pciephy_2: phy@3000 {
 671                                 reg = <0x3000 0x130>,
 672                                       <0x3200 0x200>,
 673                                       <0x3400 0x1dc>;
 674
 675                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 676                                 clock-names = "pipe2";
 677                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 678                                 reset-names = "lane2";
 679
 680                                 #clock-cells = <0>;
 681                                 clock-output-names = "pcie_2_pipe_clk_src";
 682
 683                                 #phy-cells = <0>;
 684                         };
 685                 };
 686
 687                 rpm_msg_ram: sram@68000 {
 688                         compatible = "qcom,rpm-msg-ram";
 689                         reg = <0x00068000 0x6000>;
 690                 };
 691
 692                 qfprom@74000 {
 693                         compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
 694                         reg = <0x00074000 0x8ff>;
 695                         #address-cells = <1>;
 696                         #size-cells = <1>;
 697
 698                         qusb2p_hstx_trim: hstx_trim@24e {
 699                                 reg = <0x24e 0x2>;
 700                                 bits = <5 4>;
 701                         };
 702
 703                         qusb2s_hstx_trim: hstx_trim@24f {
 704                                 reg = <0x24f 0x1>;
 705                                 bits = <1 4>;
 706                         };
 707
 708                         speedbin_efuse: speedbin@133 {
 709                                 reg = <0x133 0x1>;
 710                                 bits = <5 3>;
 711                         };
 712                 };
 713
 714                 rng: rng@83000 {
 715                         compatible = "qcom,prng-ee";
 716                         reg = <0x00083000 0x1000>;
 717                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 718                         clock-names = "core";
 719                 };
 720
 721                 gcc: clock-controller@300000 {
 722                         compatible = "qcom,gcc-msm8996";
 723                         #clock-cells = <1>;
 724                         #reset-cells = <1>;
 725                         #power-domain-cells = <1>;
 726                         reg = <0x00300000 0x90000>;
 727
 728                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 729                                  <&rpmcc RPM_SMD_LN_BB_CLK>,
 730                                  <&sleep_clk>,
 731                                  <&pciephy_0>,
 732                                  <&pciephy_1>,
 733                                  <&pciephy_2>,
 734                                  <&ssusb_phy_0>,
 735                                  <0>, <0>, <0>;
 736                         clock-names = "cxo",
 737                                       "cxo2",
 738                                       "sleep_clk",
 739                                       "pcie_0_pipe_clk_src",
 740                                       "pcie_1_pipe_clk_src",
 741                                       "pcie_2_pipe_clk_src",
 742                                       "usb3_phy_pipe_clk_src",
 743                                       "ufs_rx_symbol_0_clk_src",
 744                                       "ufs_rx_symbol_1_clk_src",
 745                                       "ufs_tx_symbol_0_clk_src";
 746                 };
 747
 748                 bimc: interconnect@408000 {
 749                         compatible = "qcom,msm8996-bimc";
 750                         reg = <0x00408000 0x5a000>;
 751                         #interconnect-cells = <1>;
 752                         clock-names = "bus", "bus_a";
 753                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 754                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 755                 };
 756
 757                 tsens0: thermal-sensor@4a9000 {
 758                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 759                         reg = <0x004a9000 0x1000>, /* TM */
 760                               <0x004a8000 0x1000>; /* SROT */
 761                         #qcom,sensors = <13>;
 762                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 763                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 764                         interrupt-names = "uplow", "critical";
 765                         #thermal-sensor-cells = <1>;
 766                 };
 767
 768                 tsens1: thermal-sensor@4ad000 {
 769                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
 770                         reg = <0x004ad000 0x1000>, /* TM */
 771                               <0x004ac000 0x1000>; /* SROT */
 772                         #qcom,sensors = <8>;
 773                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 774                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 775                         interrupt-names = "uplow", "critical";
 776                         #thermal-sensor-cells = <1>;
 777                 };
 778
 779                 cryptobam: dma-controller@644000 {
 780                         compatible = "qcom,bam-v1.7.0";
 781                         reg = <0x00644000 0x24000>;
 782                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&gcc GCC_CE1_CLK>;
 784                         clock-names = "bam_clk";
 785                         #dma-cells = <1>;
 786                         qcom,ee = <0>;
 787                         qcom,controlled-remotely;
 788                 };
 789
 790                 crypto: crypto@67a000 {
 791                         compatible = "qcom,crypto-v5.4";
 792                         reg = <0x0067a000 0x6000>;
 793                         clocks = <&gcc GCC_CE1_AHB_CLK>,
 794                                  <&gcc GCC_CE1_AXI_CLK>,
 795                                  <&gcc GCC_CE1_CLK>;
 796                         clock-names = "iface", "bus", "core";
 797                         dmas = <&cryptobam 6>, <&cryptobam 7>;
 798                         dma-names = "rx", "tx";
 799                 };
 800
 801                 cnoc: interconnect@500000 {
 802                         compatible = "qcom,msm8996-cnoc";
 803                         reg = <0x00500000 0x1000>;
 804                         #interconnect-cells = <1>;
 805                         clock-names = "bus", "bus_a";
 806                         clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
 807                                  <&rpmcc RPM_SMD_CNOC_A_CLK>;
 808                 };
 809
 810                 snoc: interconnect@524000 {
 811                         compatible = "qcom,msm8996-snoc";
 812                         reg = <0x00524000 0x1c000>;
 813                         #interconnect-cells = <1>;
 814                         clock-names = "bus", "bus_a";
 815                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 816                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 817                 };
 818
 819                 a0noc: interconnect@543000 {
 820                         compatible = "qcom,msm8996-a0noc";
 821                         reg = <0x00543000 0x6000>;
 822                         #interconnect-cells = <1>;
 823                         clock-names = "aggre0_snoc_axi",
 824                                       "aggre0_cnoc_ahb",
 825                                       "aggre0_noc_mpu_cfg";
 826                         clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
 827                                  <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
 828                                  <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
 829                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
 830                 };
 831
 832                 a1noc: interconnect@562000 {
 833                         compatible = "qcom,msm8996-a1noc";
 834                         reg = <0x00562000 0x5000>;
 835                         #interconnect-cells = <1>;
 836                         clock-names = "bus", "bus_a";
 837                         clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
 838                                  <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
 839                 };
 840
 841                 a2noc: interconnect@583000 {
 842                         compatible = "qcom,msm8996-a2noc";
 843                         reg = <0x00583000 0x7000>;
 844                         #interconnect-cells = <1>;
 845                         clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
 846                         clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
 847                                  <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
 848                                  <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 849                                  <&gcc GCC_UFS_AXI_CLK>;
 850                 };
 851
 852                 mnoc: interconnect@5a4000 {
 853                         compatible = "qcom,msm8996-mnoc";
 854                         reg = <0x005a4000 0x1c000>;
 855                         #interconnect-cells = <1>;
 856                         clock-names = "bus", "bus_a", "iface";
 857                         clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
 858                                  <&rpmcc RPM_SMD_MMAXI_A_CLK>,
 859                                  <&mmcc AHB_CLK_SRC>;
 860                 };
 861
 862                 pnoc: interconnect@5c0000 {
 863                         compatible = "qcom,msm8996-pnoc";
 864                         reg = <0x005c0000 0x3000>;
 865                         #interconnect-cells = <1>;
 866                         clock-names = "bus", "bus_a";
 867                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
 868                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
 869                 };
 870
 871                 tcsr_mutex: hwlock@740000 {
 872                         compatible = "qcom,tcsr-mutex";
 873                         reg = <0x00740000 0x20000>;
 874                         #hwlock-cells = <1>;
 875                 };
 876
 877                 tcsr_1: syscon@760000 {
 878                         compatible = "qcom,tcsr-msm8996", "syscon";
 879                         reg = <0x00760000 0x20000>;
 880                 };
 881
 882                 tcsr_2: syscon@7a0000 {
 883                         compatible = "qcom,tcsr-msm8996", "syscon";
 884                         reg = <0x007a0000 0x18000>;
 885                 };
 886
 887                 mmcc: clock-controller@8c0000 {
 888                         compatible = "qcom,mmcc-msm8996";
 889                         #clock-cells = <1>;
 890                         #reset-cells = <1>;
 891                         #power-domain-cells = <1>;
 892                         reg = <0x008c0000 0x40000>;
 893                         clocks = <&xo_board>,
 894                                  <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
 895                                  <&gcc GPLL0>,
 896                                  <&dsi0_phy 1>,
 897                                  <&dsi0_phy 0>,
 898                                  <0>,
 899                                  <0>,
 900                                  <0>;
 901                         clock-names = "xo",
 902                                       "gcc_mmss_noc_cfg_ahb_clk",
 903                                       "gpll0",
 904                                       "dsi0pll",
 905                                       "dsi0pllbyte",
 906                                       "dsi1pll",
 907                                       "dsi1pllbyte",
 908                                       "hdmipll";
 909                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 910                                           <&mmcc MMPLL1_PLL>,
 911                                           <&mmcc MMPLL3_PLL>,
 912                                           <&mmcc MMPLL4_PLL>,
 913                                           <&mmcc MMPLL5_PLL>;
 914                         assigned-clock-rates = <624000000>,
 915                                                <810000000>,
 916                                                <980000000>,
 917                                                <960000000>,
 918                                                <825000000>;
 919                 };
 920
 921                 mdss: mdss@900000 {
 922                         compatible = "qcom,mdss";
 923
 924                         reg = <0x00900000 0x1000>,
 925                               <0x009b0000 0x1040>,
 926                               <0x009b8000 0x1040>;
 927                         reg-names = "mdss_phys",
 928                                     "vbif_phys",
 929                                     "vbif_nrt_phys";
 930
 931                         power-domains = <&mmcc MDSS_GDSC>;
 932                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 933
 934                         interrupt-controller;
 935                         #interrupt-cells = <1>;
 936
 937                         clocks = <&mmcc MDSS_AHB_CLK>,
 938                                  <&mmcc MDSS_MDP_CLK>;
 939                         clock-names = "iface", "core";
 940
 941                         #address-cells = <1>;
 942                         #size-cells = <1>;
 943                         ranges;
 944
 945                         status = "disabled";
 946
 947                         mdp: mdp@901000 {
 948                                 compatible = "qcom,mdp5";
 949                                 reg = <0x00901000 0x90000>;
 950                                 reg-names = "mdp_phys";
 951
 952                                 interrupt-parent = <&mdss>;
 953                                 interrupts = <0>;
 954
 955                                 clocks = <&mmcc MDSS_AHB_CLK>,
 956                                          <&mmcc MDSS_AXI_CLK>,
 957                                          <&mmcc MDSS_MDP_CLK>,
 958                                          <&mmcc SMMU_MDP_AXI_CLK>,
 959                                          <&mmcc MDSS_VSYNC_CLK>;
 960                                 clock-names = "iface",
 961                                               "bus",
 962                                               "core",
 963                                               "iommu",
 964                                               "vsync";
 965
 966                                 iommus = <&mdp_smmu 0>;
 967
 968                                 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
 969                                          <&mmcc MDSS_VSYNC_CLK>;
 970                                 assigned-clock-rates = <300000000>,
 971                                          <19200000>;
 972
 973                                 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
 974                                                 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
 975                                                 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
 976                                 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
 977
 978                                 ports {
 979                                         #address-cells = <1>;
 980                                         #size-cells = <0>;
 981
 982                                         port@0 {
 983                                                 reg = <0>;
 984                                                 mdp5_intf3_out: endpoint {
 985                                                         remote-endpoint = <&hdmi_in>;
 986                                                 };
 987                                         };
 988
 989                                         port@1 {
 990                                                 reg = <1>;
 991                                                 mdp5_intf1_out: endpoint {
 992                                                         remote-endpoint = <&dsi0_in>;
 993                                                 };
 994                                         };
 995
 996                                         port@2 {
 997                                                 reg = <2>;
 998                                                 mdp5_intf2_out: endpoint {
 999                                                         remote-endpoint = <&dsi1_in>;
1000                                                 };
1001                                         };
1002                                 };
1003                         };
1004
1005                         dsi0: dsi@994000 {
1006                                 compatible = "qcom,mdss-dsi-ctrl";
1007                                 reg = <0x00994000 0x400>;
1008                                 reg-names = "dsi_ctrl";
1009
1010                                 interrupt-parent = <&mdss>;
1011                                 interrupts = <4>;
1012
1013                                 clocks = <&mmcc MDSS_MDP_CLK>,
1014                                          <&mmcc MDSS_BYTE0_CLK>,
1015                                          <&mmcc MDSS_AHB_CLK>,
1016                                          <&mmcc MDSS_AXI_CLK>,
1017                                          <&mmcc MMSS_MISC_AHB_CLK>,
1018                                          <&mmcc MDSS_PCLK0_CLK>,
1019                                          <&mmcc MDSS_ESC0_CLK>;
1020                                 clock-names = "mdp_core",
1021                                               "byte",
1022                                               "iface",
1023                                               "bus",
1024                                               "core_mmss",
1025                                               "pixel",
1026                                               "core";
1027                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1028                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
1029
1030                                 phys = <&dsi0_phy>;
1031                                 phy-names = "dsi";
1032                                 status = "disabled";
1033
1034                                 #address-cells = <1>;
1035                                 #size-cells = <0>;
1036
1037                                 ports {
1038                                         #address-cells = <1>;
1039                                         #size-cells = <0>;
1040
1041                                         port@0 {
1042                                                 reg = <0>;
1043                                                 dsi0_in: endpoint {
1044                                                         remote-endpoint = <&mdp5_intf1_out>;
1045                                                 };
1046                                         };
1047
1048                                         port@1 {
1049                                                 reg = <1>;
1050                                                 dsi0_out: endpoint {
1051                                                 };
1052                                         };
1053                                 };
1054                         };
1055
1056                         dsi0_phy: dsi-phy@994400 {
1057                                 compatible = "qcom,dsi-phy-14nm";
1058                                 reg = <0x00994400 0x100>,
1059                                       <0x00994500 0x300>,
1060                                       <0x00994800 0x188>;
1061                                 reg-names = "dsi_phy",
1062                                             "dsi_phy_lane",
1063                                             "dsi_pll";
1064
1065                                 #clock-cells = <1>;
1066                                 #phy-cells = <0>;
1067
1068                                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1069                                 clock-names = "iface", "ref";
1070                                 status = "disabled";
1071                         };
1072
1073                         dsi1: dsi@996000 {
1074                                 compatible = "qcom,mdss-dsi-ctrl";
1075                                 reg = <0x00996000 0x400>;
1076                                 reg-names = "dsi_ctrl";
1077
1078                                 interrupt-parent = <&mdss>;
1079                                 interrupts = <5>;
1080
1081                                 clocks = <&mmcc MDSS_MDP_CLK>,
1082                                          <&mmcc MDSS_BYTE1_CLK>,
1083                                          <&mmcc MDSS_AHB_CLK>,
1084                                          <&mmcc MDSS_AXI_CLK>,
1085                                          <&mmcc MMSS_MISC_AHB_CLK>,
1086                                          <&mmcc MDSS_PCLK1_CLK>,
1087                                          <&mmcc MDSS_ESC1_CLK>;
1088                                 clock-names = "mdp_core",
1089                                               "byte",
1090                                               "iface",
1091                                               "bus",
1092                                               "core_mmss",
1093                                               "pixel",
1094                                               "core";
1095                                 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1096                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
1097
1098                                 phys = <&dsi1_phy>;
1099                                 phy-names = "dsi";
1100                                 status = "disabled";
1101
1102                                 #address-cells = <1>;
1103                                 #size-cells = <0>;
1104
1105                                 ports {
1106                                         #address-cells = <1>;
1107                                         #size-cells = <0>;
1108
1109                                         port@0 {
1110                                                 reg = <0>;
1111                                                 dsi1_in: endpoint {
1112                                                         remote-endpoint = <&mdp5_intf2_out>;
1113                                                 };
1114                                         };
1115
1116                                         port@1 {
1117                                                 reg = <1>;
1118                                                 dsi1_out: endpoint {
1119                                                 };
1120                                         };
1121                                 };
1122                         };
1123
1124                         dsi1_phy: dsi-phy@996400 {
1125                                 compatible = "qcom,dsi-phy-14nm";
1126                                 reg = <0x00996400 0x100>,
1127                                       <0x00996500 0x300>,
1128                                       <0x00996800 0x188>;
1129                                 reg-names = "dsi_phy",
1130                                             "dsi_phy_lane",
1131                                             "dsi_pll";
1132
1133                                 #clock-cells = <1>;
1134                                 #phy-cells = <0>;
1135
1136                                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1137                                 clock-names = "iface", "ref";
1138                                 status = "disabled";
1139                         };
1140
1141                         hdmi: hdmi-tx@9a0000 {
1142                                 compatible = "qcom,hdmi-tx-8996";
1143                                 reg =   <0x009a0000 0x50c>,
1144                                         <0x00070000 0x6158>,
1145                                         <0x009e0000 0xfff>;
1146                                 reg-names = "core_physical",
1147                                             "qfprom_physical",
1148                                             "hdcp_physical";
1149
1150                                 interrupt-parent = <&mdss>;
1151                                 interrupts = <8>;
1152
1153                                 clocks = <&mmcc MDSS_MDP_CLK>,
1154                                          <&mmcc MDSS_AHB_CLK>,
1155                                          <&mmcc MDSS_HDMI_CLK>,
1156                                          <&mmcc MDSS_HDMI_AHB_CLK>,
1157                                          <&mmcc MDSS_EXTPCLK_CLK>;
1158                                 clock-names =
1159                                         "mdp_core",
1160                                         "iface",
1161                                         "core",
1162                                         "alt_iface",
1163                                         "extp";
1164
1165                                 phys = <&hdmi_phy>;
1166                                 #sound-dai-cells = <1>;
1167
1168                                 status = "disabled";
1169
1170                                 ports {
1171                                         #address-cells = <1>;
1172                                         #size-cells = <0>;
1173
1174                                         port@0 {
1175                                                 reg = <0>;
1176                                                 hdmi_in: endpoint {
1177                                                         remote-endpoint = <&mdp5_intf3_out>;
1178                                                 };
1179                                         };
1180                                 };
1181                         };
1182
1183                         hdmi_phy: hdmi-phy@9a0600 {
1184                                 #phy-cells = <0>;
1185                                 compatible = "qcom,hdmi-phy-8996";
1186                                 reg = <0x009a0600 0x1c4>,
1187                                       <0x009a0a00 0x124>,
1188                                       <0x009a0c00 0x124>,
1189                                       <0x009a0e00 0x124>,
1190                                       <0x009a1000 0x124>,
1191                                       <0x009a1200 0x0c8>;
1192                                 reg-names = "hdmi_pll",
1193                                             "hdmi_tx_l0",
1194                                             "hdmi_tx_l1",
1195                                             "hdmi_tx_l2",
1196                                             "hdmi_tx_l3",
1197                                             "hdmi_phy";
1198
1199                                 clocks = <&mmcc MDSS_AHB_CLK>,
1200                                          <&gcc GCC_HDMI_CLKREF_CLK>,
1201                                          <&xo_board>;
1202                                 clock-names = "iface",
1203                                               "ref",
1204                                               "xo";
1205
1206                                 #clock-cells = <0>;
1207
1208                                 status = "disabled";
1209                         };
1210                 };
1211
1212                 gpu: gpu@b00000 {
1213                         compatible = "qcom,adreno-530.2", "qcom,adreno";
1214
1215                         reg = <0x00b00000 0x3f000>;
1216                         reg-names = "kgsl_3d0_reg_memory";
1217
1218                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1219
1220                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1221                                 <&mmcc GPU_AHB_CLK>,
1222                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1223                                 <&gcc GCC_BIMC_GFX_CLK>,
1224                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1225
1226                         clock-names = "core",
1227                                 "iface",
1228                                 "rbbmtimer",
1229                                 "mem",
1230                                 "mem_iface";
1231
1232                         interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
1233                         interconnect-names = "gfx-mem";
1234
1235                         power-domains = <&mmcc GPU_GX_GDSC>;
1236                         iommus = <&adreno_smmu 0>;
1237
1238                         nvmem-cells = <&speedbin_efuse>;
1239                         nvmem-cell-names = "speed_bin";
1240
1241                         operating-points-v2 = <&gpu_opp_table>;
1242
1243                         status = "disabled";
1244
1245                         #cooling-cells = <2>;
1246
1247                         gpu_opp_table: opp-table {
1248                                 compatible = "operating-points-v2";
1249
1250                                 /*
1251                                  * 624Mhz is only available on speed bins 0 and 3.
1252                                  * 560Mhz is only available on speed bins 0, 2 and 3.
1253                                  * All the rest are available on all bins of the hardware.
1254                                  */
1255                                 opp-624000000 {
1256                                         opp-hz = /bits/ 64 <624000000>;
1257                                         opp-supported-hw = <0x09>;
1258                                 };
1259                                 opp-560000000 {
1260                                         opp-hz = /bits/ 64 <560000000>;
1261                                         opp-supported-hw = <0x0d>;
1262                                 };
1263                                 opp-510000000 {
1264                                         opp-hz = /bits/ 64 <510000000>;
1265                                         opp-supported-hw = <0xFF>;
1266                                 };
1267                                 opp-401800000 {
1268                                         opp-hz = /bits/ 64 <401800000>;
1269                                         opp-supported-hw = <0xFF>;
1270                                 };
1271                                 opp-315000000 {
1272                                         opp-hz = /bits/ 64 <315000000>;
1273                                         opp-supported-hw = <0xFF>;
1274                                 };
1275                                 opp-214000000 {
1276                                         opp-hz = /bits/ 64 <214000000>;
1277                                         opp-supported-hw = <0xFF>;
1278                                 };
1279                                 opp-133000000 {
1280                                         opp-hz = /bits/ 64 <133000000>;
1281                                         opp-supported-hw = <0xFF>;
1282                                 };
1283                         };
1284
1285                         zap-shader {
1286                                 memory-region = <&gpu_mem>;
1287                         };
1288                 };
1289
1290                 tlmm: pinctrl@1010000 {
1291                         compatible = "qcom,msm8996-pinctrl";
1292                         reg = <0x01010000 0x300000>;
1293                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1294                         gpio-controller;
1295                         gpio-ranges = <&tlmm 0 0 150>;
1296                         #gpio-cells = <2>;
1297                         interrupt-controller;
1298                         #interrupt-cells = <2>;
1299
1300                         blsp1_spi1_default: blsp1-spi1-default {
1301                                 spi {
1302                                         pins = "gpio0", "gpio1", "gpio3";
1303                                         function = "blsp_spi1";
1304                                         drive-strength = <12>;
1305                                         bias-disable;
1306                                 };
1307
1308                                 cs {
1309                                         pins = "gpio2";
1310                                         function = "gpio";
1311                                         drive-strength = <16>;
1312                                         bias-disable;
1313                                         output-high;
1314                                 };
1315                         };
1316
1317                         blsp1_spi1_sleep: blsp1-spi1-sleep {
1318                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1319                                 function = "gpio";
1320                                 drive-strength = <2>;
1321                                 bias-pull-down;
1322                         };
1323
1324                         blsp2_uart2_2pins_default: blsp2-uart1-2pins {
1325                                 pins = "gpio4", "gpio5";
1326                                 function = "blsp_uart8";
1327                                 drive-strength = <16>;
1328                                 bias-disable;
1329                         };
1330
1331                         blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
1332                                 pins = "gpio4", "gpio5";
1333                                 function = "gpio";
1334                                 drive-strength = <2>;
1335                                 bias-disable;
1336                         };
1337
1338                         blsp2_i2c2_default: blsp2-i2c2 {
1339                                 pins = "gpio6", "gpio7";
1340                                 function = "blsp_i2c8";
1341                                 drive-strength = <16>;
1342                                 bias-disable;
1343                         };
1344
1345                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
1346                                 pins = "gpio6", "gpio7";
1347                                 function = "gpio";
1348                                 drive-strength = <2>;
1349                                 bias-disable;
1350                         };
1351
1352                         cci0_default: cci0-default {
1353                                 pins = "gpio17", "gpio18";
1354                                 function = "cci_i2c";
1355                                 drive-strength = <16>;
1356                                 bias-disable;
1357                         };
1358
1359                         camera0_state_on:
1360                         camera_rear_default: camera-rear-default {
1361                                 camera0_mclk: mclk0 {
1362                                         pins = "gpio13";
1363                                         function = "cam_mclk";
1364                                         drive-strength = <16>;
1365                                         bias-disable;
1366                                 };
1367
1368                                 camera0_rst: rst {
1369                                         pins = "gpio25";
1370                                         function = "gpio";
1371                                         drive-strength = <16>;
1372                                         bias-disable;
1373                                 };
1374
1375                                 camera0_pwdn: pwdn {
1376                                         pins = "gpio26";
1377                                         function = "gpio";
1378                                         drive-strength = <16>;
1379                                         bias-disable;
1380                                 };
1381                         };
1382
1383                         cci1_default: cci1-default {
1384                                 pins = "gpio19", "gpio20";
1385                                 function = "cci_i2c";
1386                                 drive-strength = <16>;
1387                                 bias-disable;
1388                         };
1389
1390                         camera1_state_on:
1391                         camera_board_default: camera-board-default {
1392                                 mclk1 {
1393                                         pins = "gpio14";
1394                                         function = "cam_mclk";
1395                                         drive-strength = <16>;
1396                                         bias-disable;
1397                                 };
1398
1399                                 pwdn {
1400                                         pins = "gpio98";
1401                                         function = "gpio";
1402                                         drive-strength = <16>;
1403                                         bias-disable;
1404                                 };
1405
1406                                 rst {
1407                                         pins = "gpio104";
1408                                         function = "gpio";
1409                                         drive-strength = <16>;
1410                                         bias-disable;
1411                                 };
1412                         };
1413
1414                         camera2_state_on:
1415                         camera_front_default: camera-front-default {
1416                                 camera2_mclk: mclk2 {
1417                                         pins = "gpio15";
1418                                         function = "cam_mclk";
1419                                         drive-strength = <16>;
1420                                         bias-disable;
1421                                 };
1422
1423                                 camera2_rst: rst {
1424                                         pins = "gpio23";
1425                                         function = "gpio";
1426                                         drive-strength = <16>;
1427                                         bias-disable;
1428                                 };
1429
1430                                 pwdn {
1431                                         pins = "gpio133";
1432                                         function = "gpio";
1433                                         drive-strength = <16>;
1434                                         bias-disable;
1435                                 };
1436                         };
1437
1438                         pcie0_state_on: pcie0-state-on {
1439                                 perst {
1440                                         pins = "gpio35";
1441                                         function = "gpio";
1442                                         drive-strength = <2>;
1443                                         bias-pull-down;
1444                                 };
1445
1446                                 clkreq {
1447                                         pins = "gpio36";
1448                                         function = "pci_e0";
1449                                         drive-strength = <2>;
1450                                         bias-pull-up;
1451                                 };
1452
1453                                 wake {
1454                                         pins = "gpio37";
1455                                         function = "gpio";
1456                                         drive-strength = <2>;
1457                                         bias-pull-up;
1458                                 };
1459                         };
1460
1461                         pcie0_state_off: pcie0-state-off {
1462                                 perst {
1463                                         pins = "gpio35";
1464                                         function = "gpio";
1465                                         drive-strength = <2>;
1466                                         bias-pull-down;
1467                                 };
1468
1469                                 clkreq {
1470                                         pins = "gpio36";
1471                                         function = "gpio";
1472                                         drive-strength = <2>;
1473                                         bias-disable;
1474                                 };
1475
1476                                 wake {
1477                                         pins = "gpio37";
1478                                         function = "gpio";
1479                                         drive-strength = <2>;
1480                                         bias-disable;
1481                                 };
1482                         };
1483
1484                         blsp1_uart2_default: blsp1-uart2-default {
1485                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1486                                 function = "blsp_uart2";
1487                                 drive-strength = <16>;
1488                                 bias-disable;
1489                         };
1490
1491                         blsp1_uart2_sleep: blsp1-uart2-sleep {
1492                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1493                                 function = "gpio";
1494                                 drive-strength = <2>;
1495                                 bias-disable;
1496                         };
1497
1498                         blsp1_i2c3_default: blsp1-i2c2-default {
1499                                 pins = "gpio47", "gpio48";
1500                                 function = "blsp_i2c3";
1501                                 drive-strength = <16>;
1502                                 bias-disable;
1503                         };
1504
1505                         blsp1_i2c3_sleep: blsp1-i2c2-sleep {
1506                                 pins = "gpio47", "gpio48";
1507                                 function = "gpio";
1508                                 drive-strength = <2>;
1509                                 bias-disable;
1510                         };
1511
1512                         blsp2_uart3_4pins_default: blsp2-uart2-4pins {
1513                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1514                                 function = "blsp_uart9";
1515                                 drive-strength = <16>;
1516                                 bias-disable;
1517                         };
1518
1519                         blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
1520                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
1521                                 function = "blsp_uart9";
1522                                 drive-strength = <2>;
1523                                 bias-disable;
1524                         };
1525
1526                         blsp2_i2c3_default: blsp2-i2c3 {
1527                                 pins = "gpio51", "gpio52";
1528                                 function = "blsp_i2c9";
1529                                 drive-strength = <16>;
1530                                 bias-disable;
1531                         };
1532
1533                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
1534                                 pins = "gpio51", "gpio52";
1535                                 function = "gpio";
1536                                 drive-strength = <2>;
1537                                 bias-disable;
1538                         };
1539
1540                         wcd_intr_default: wcd-intr-default{
1541                                 pins = "gpio54";
1542                                 function = "gpio";
1543                                 drive-strength = <2>;
1544                                 bias-pull-down;
1545                                 input-enable;
1546                         };
1547
1548                         blsp2_i2c1_default: blsp2-i2c1 {
1549                                 pins = "gpio55", "gpio56";
1550                                 function = "blsp_i2c7";
1551                                 drive-strength = <16>;
1552                                 bias-disable;
1553                         };
1554
1555                         blsp2_i2c1_sleep: blsp2-i2c0-sleep {
1556                                 pins = "gpio55", "gpio56";
1557                                 function = "gpio";
1558                                 drive-strength = <2>;
1559                                 bias-disable;
1560                         };
1561
1562                         blsp2_i2c5_default: blsp2-i2c5 {
1563                                 pins = "gpio60", "gpio61";
1564                                 function = "blsp_i2c11";
1565                                 drive-strength = <2>;
1566                                 bias-disable;
1567                         };
1568
1569                         /* Sleep state for BLSP2_I2C5 is missing.. */
1570
1571                         cdc_reset_active: cdc-reset-active {
1572                                 pins = "gpio64";
1573                                 function = "gpio";
1574                                 drive-strength = <16>;
1575                                 bias-pull-down;
1576                                 output-high;
1577                         };
1578
1579                         cdc_reset_sleep: cdc-reset-sleep {
1580                                 pins = "gpio64";
1581                                 function = "gpio";
1582                                 drive-strength = <16>;
1583                                 bias-disable;
1584                                 output-low;
1585                         };
1586
1587                         blsp2_spi6_default: blsp2-spi5-default {
1588                                 spi {
1589                                         pins = "gpio85", "gpio86", "gpio88";
1590                                         function = "blsp_spi12";
1591                                         drive-strength = <12>;
1592                                         bias-disable;
1593                                 };
1594
1595                                 cs {
1596                                         pins = "gpio87";
1597                                         function = "gpio";
1598                                         drive-strength = <16>;
1599                                         bias-disable;
1600                                         output-high;
1601                                 };
1602                         };
1603
1604                         blsp2_spi6_sleep: blsp2-spi5-sleep {
1605                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
1606                                 function = "gpio";
1607                                 drive-strength = <2>;
1608                                 bias-pull-down;
1609                         };
1610
1611                         blsp2_i2c6_default: blsp2-i2c6 {
1612                                 pins = "gpio87", "gpio88";
1613                                 function = "blsp_i2c12";
1614                                 drive-strength = <16>;
1615                                 bias-disable;
1616                         };
1617
1618                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
1619                                 pins = "gpio87", "gpio88";
1620                                 function = "gpio";
1621                                 drive-strength = <2>;
1622                                 bias-disable;
1623                         };
1624
1625                         pcie1_state_on: pcie1-state-on {
1626                                 perst {
1627                                         pins = "gpio130";
1628                                         function = "gpio";
1629                                         drive-strength = <2>;
1630                                         bias-pull-down;
1631                                 };
1632
1633                                 clkreq {
1634                                         pins = "gpio131";
1635                                         function = "pci_e1";
1636                                         drive-strength = <2>;
1637                                         bias-pull-up;
1638                                 };
1639
1640                                 wake {
1641                                         pins = "gpio132";
1642                                         function = "gpio";
1643                                         drive-strength = <2>;
1644                                         bias-pull-down;
1645                                 };
1646                         };
1647
1648                         pcie1_state_off: pcie1-state-off {
1649                                 /* Perst is missing? */
1650                                 clkreq {
1651                                         pins = "gpio131";
1652                                         function = "gpio";
1653                                         drive-strength = <2>;
1654                                         bias-disable;
1655                                 };
1656
1657                                 wake {
1658                                         pins = "gpio132";
1659                                         function = "gpio";
1660                                         drive-strength = <2>;
1661                                         bias-disable;
1662                                 };
1663                         };
1664
1665                         pcie2_state_on: pcie2-state-on {
1666                                 perst {
1667                                         pins = "gpio114";
1668                                         function = "gpio";
1669                                         drive-strength = <2>;
1670                                         bias-pull-down;
1671                                 };
1672
1673                                 clkreq {
1674                                         pins = "gpio115";
1675                                         function = "pci_e2";
1676                                         drive-strength = <2>;
1677                                         bias-pull-up;
1678                                 };
1679
1680                                 wake {
1681                                         pins = "gpio116";
1682                                         function = "gpio";
1683                                         drive-strength = <2>;
1684                                         bias-pull-down;
1685                                 };
1686                         };
1687
1688                         pcie2_state_off: pcie2-state-off {
1689                                 /* Perst is missing? */
1690                                 clkreq {
1691                                         pins = "gpio115";
1692                                         function = "gpio";
1693                                         drive-strength = <2>;
1694                                         bias-disable;
1695                                 };
1696
1697                                 wake {
1698                                         pins = "gpio116";
1699                                         function = "gpio";
1700                                         drive-strength = <2>;
1701                                         bias-disable;
1702                                 };
1703                         };
1704
1705                         sdc1_state_on: sdc1-state-on {
1706                                 clk {
1707                                         pins = "sdc1_clk";
1708                                         bias-disable;
1709                                         drive-strength = <16>;
1710                                 };
1711
1712                                 cmd {
1713                                         pins = "sdc1_cmd";
1714                                         bias-pull-up;
1715                                         drive-strength = <10>;
1716                                 };
1717
1718                                 data {
1719                                         pins = "sdc1_data";
1720                                         bias-pull-up;
1721                                         drive-strength = <10>;
1722                                 };
1723
1724                                 rclk {
1725                                         pins = "sdc1_rclk";
1726                                         bias-pull-down;
1727                                 };
1728                         };
1729
1730                         sdc1_state_off: sdc1-state-off {
1731                                 clk {
1732                                         pins = "sdc1_clk";
1733                                         bias-disable;
1734                                         drive-strength = <2>;
1735                                 };
1736
1737                                 cmd {
1738                                         pins = "sdc1_cmd";
1739                                         bias-pull-up;
1740                                         drive-strength = <2>;
1741                                 };
1742
1743                                 data {
1744                                         pins = "sdc1_data";
1745                                         bias-pull-up;
1746                                         drive-strength = <2>;
1747                                 };
1748
1749                                 rclk {
1750                                         pins = "sdc1_rclk";
1751                                         bias-pull-down;
1752                                 };
1753                         };
1754
1755                         sdc2_state_on: sdc2-clk-on {
1756                                 clk {
1757                                         pins = "sdc2_clk";
1758                                         bias-disable;
1759                                         drive-strength = <16>;
1760                                 };
1761
1762                                 cmd {
1763                                         pins = "sdc2_cmd";
1764                                         bias-pull-up;
1765                                         drive-strength = <10>;
1766                                 };
1767
1768                                 data {
1769                                         pins = "sdc2_data";
1770                                         bias-pull-up;
1771                                         drive-strength = <10>;
1772                                 };
1773                         };
1774
1775                         sdc2_state_off: sdc2-clk-off {
1776                                 clk {
1777                                         pins = "sdc2_clk";
1778                                         bias-disable;
1779                                         drive-strength = <2>;
1780                                 };
1781
1782                                 cmd {
1783                                         pins = "sdc2_cmd";
1784                                         bias-pull-up;
1785                                         drive-strength = <2>;
1786                                 };
1787
1788                                 data {
1789                                         pins = "sdc2_data";
1790                                         bias-pull-up;
1791                                         drive-strength = <2>;
1792                                 };
1793                         };
1794                 };
1795
1796                 sram@290000 {
1797                         compatible = "qcom,rpm-stats";
1798                         reg = <0x00290000 0x10000>;
1799                 };
1800
1801                 spmi_bus: spmi@400f000 {
1802                         compatible = "qcom,spmi-pmic-arb";
1803                         reg = <0x0400f000 0x1000>,
1804                               <0x04400000 0x800000>,
1805                               <0x04c00000 0x800000>,
1806                               <0x05800000 0x200000>,
1807                               <0x0400a000 0x002100>;
1808                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1809                         interrupt-names = "periph_irq";
1810                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1811                         qcom,ee = <0>;
1812                         qcom,channel = <0>;
1813                         #address-cells = <2>;
1814                         #size-cells = <0>;
1815                         interrupt-controller;
1816                         #interrupt-cells = <4>;
1817                 };
1818
1819                 agnoc@0 {
1820                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1821                         compatible = "simple-pm-bus";
1822                         #address-cells = <1>;
1823                         #size-cells = <1>;
1824                         ranges;
1825
1826                         pcie0: pcie@600000 {
1827                                 compatible = "qcom,pcie-msm8996";
1828                                 status = "disabled";
1829                                 power-domains = <&gcc PCIE0_GDSC>;
1830                                 bus-range = <0x00 0xff>;
1831                                 num-lanes = <1>;
1832
1833                                 reg = <0x00600000 0x2000>,
1834                                       <0x0c000000 0xf1d>,
1835                                       <0x0c000f20 0xa8>,
1836                                       <0x0c100000 0x100000>;
1837                                 reg-names = "parf", "dbi", "elbi","config";
1838
1839                                 phys = <&pciephy_0>;
1840                                 phy-names = "pciephy";
1841
1842                                 #address-cells = <3>;
1843                                 #size-cells = <2>;
1844                                 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1845                                          <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1846
1847                                 device_type = "pci";
1848
1849                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1850                                 interrupt-names = "msi";
1851                                 #interrupt-cells = <1>;
1852                                 interrupt-map-mask = <0 0 0 0x7>;
1853                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1854                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1855                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1856                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1857
1858                                 pinctrl-names = "default", "sleep";
1859                                 pinctrl-0 = <&pcie0_state_on>;
1860                                 pinctrl-1 = <&pcie0_state_off>;
1861
1862                                 linux,pci-domain = <0>;
1863
1864                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1865                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1866                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1867                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1868                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1869
1870                                 clock-names = "pipe",
1871                                                 "aux",
1872                                                 "cfg",
1873                                                 "bus_master",
1874                                                 "bus_slave";
1875
1876                         };
1877
1878                         pcie1: pcie@608000 {
1879                                 compatible = "qcom,pcie-msm8996";
1880                                 power-domains = <&gcc PCIE1_GDSC>;
1881                                 bus-range = <0x00 0xff>;
1882                                 num-lanes = <1>;
1883
1884                                 status = "disabled";
1885
1886                                 reg = <0x00608000 0x2000>,
1887                                       <0x0d000000 0xf1d>,
1888                                       <0x0d000f20 0xa8>,
1889                                       <0x0d100000 0x100000>;
1890
1891                                 reg-names = "parf", "dbi", "elbi","config";
1892
1893                                 phys = <&pciephy_1>;
1894                                 phy-names = "pciephy";
1895
1896                                 #address-cells = <3>;
1897                                 #size-cells = <2>;
1898                                 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1899                                          <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1900
1901                                 device_type = "pci";
1902
1903                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1904                                 interrupt-names = "msi";
1905                                 #interrupt-cells = <1>;
1906                                 interrupt-map-mask = <0 0 0 0x7>;
1907                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1908                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1909                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1910                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1911
1912                                 pinctrl-names = "default", "sleep";
1913                                 pinctrl-0 = <&pcie1_state_on>;
1914                                 pinctrl-1 = <&pcie1_state_off>;
1915
1916                                 linux,pci-domain = <1>;
1917
1918                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1919                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1920                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1921                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1922                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1923
1924                                 clock-names = "pipe",
1925                                                 "aux",
1926                                                 "cfg",
1927                                                 "bus_master",
1928                                                 "bus_slave";
1929                         };
1930
1931                         pcie2: pcie@610000 {
1932                                 compatible = "qcom,pcie-msm8996";
1933                                 power-domains = <&gcc PCIE2_GDSC>;
1934                                 bus-range = <0x00 0xff>;
1935                                 num-lanes = <1>;
1936                                 status = "disabled";
1937                                 reg = <0x00610000 0x2000>,
1938                                       <0x0e000000 0xf1d>,
1939                                       <0x0e000f20 0xa8>,
1940                                       <0x0e100000 0x100000>;
1941
1942                                 reg-names = "parf", "dbi", "elbi","config";
1943
1944                                 phys = <&pciephy_2>;
1945                                 phy-names = "pciephy";
1946
1947                                 #address-cells = <3>;
1948                                 #size-cells = <2>;
1949                                 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
1950                                          <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1951
1952                                 device_type = "pci";
1953
1954                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1955                                 interrupt-names = "msi";
1956                                 #interrupt-cells = <1>;
1957                                 interrupt-map-mask = <0 0 0 0x7>;
1958                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1959                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1960                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1961                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1962
1963                                 pinctrl-names = "default", "sleep";
1964                                 pinctrl-0 = <&pcie2_state_on>;
1965                                 pinctrl-1 = <&pcie2_state_off>;
1966
1967                                 linux,pci-domain = <2>;
1968                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1969                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1970                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1971                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1972                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1973
1974                                 clock-names = "pipe",
1975                                                 "aux",
1976                                                 "cfg",
1977                                                 "bus_master",
1978                                                 "bus_slave";
1979                         };
1980                 };
1981
1982                 ufshc: ufshc@624000 {
1983                         compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
1984                                      "jedec,ufs-2.0";
1985                         reg = <0x00624000 0x2500>;
1986                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1987
1988                         phys = <&ufsphy_lane>;
1989                         phy-names = "ufsphy";
1990
1991                         power-domains = <&gcc UFS_GDSC>;
1992
1993                         clock-names =
1994                                 "core_clk_src",
1995                                 "core_clk",
1996                                 "bus_clk",
1997                                 "bus_aggr_clk",
1998                                 "iface_clk",
1999                                 "core_clk_unipro_src",
2000                                 "core_clk_unipro",
2001                                 "core_clk_ice",
2002                                 "ref_clk",
2003                                 "tx_lane0_sync_clk",
2004                                 "rx_lane0_sync_clk";
2005                         clocks =
2006                                 <&gcc UFS_AXI_CLK_SRC>,
2007                                 <&gcc GCC_UFS_AXI_CLK>,
2008                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
2009                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
2010                                 <&gcc GCC_UFS_AHB_CLK>,
2011                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
2012                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
2013                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
2014                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
2015                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2016                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2017                         freq-table-hz =
2018                                 <100000000 200000000>,
2019                                 <0 0>,
2020                                 <0 0>,
2021                                 <0 0>,
2022                                 <0 0>,
2023                                 <150000000 300000000>,
2024                                 <0 0>,
2025                                 <0 0>,
2026                                 <0 0>,
2027                                 <0 0>,
2028                                 <0 0>;
2029
2030                         lanes-per-direction = <1>;
2031                         #reset-cells = <1>;
2032                         status = "disabled";
2033
2034                         ufs_variant {
2035                                 compatible = "qcom,ufs_variant";
2036                         };
2037                 };
2038
2039                 ufsphy: phy@627000 {
2040                         compatible = "qcom,msm8996-qmp-ufs-phy";
2041                         reg = <0x00627000 0x1c4>;
2042                         #address-cells = <1>;
2043                         #size-cells = <1>;
2044                         ranges;
2045
2046                         clocks = <&gcc GCC_UFS_CLKREF_CLK>;
2047                         clock-names = "ref";
2048
2049                         resets = <&ufshc 0>;
2050                         reset-names = "ufsphy";
2051                         status = "disabled";
2052
2053                         ufsphy_lane: phy@627400 {
2054                                 reg = <0x627400 0x12c>,
2055                                       <0x627600 0x200>,
2056                                       <0x627c00 0x1b4>;
2057                                 #phy-cells = <0>;
2058                         };
2059                 };
2060
2061                 camss: camss@a34000 {
2062                         compatible = "qcom,msm8996-camss";
2063                         reg = <0x00a34000 0x1000>,
2064                               <0x00a00030 0x4>,
2065                               <0x00a35000 0x1000>,
2066                               <0x00a00038 0x4>,
2067                               <0x00a36000 0x1000>,
2068                               <0x00a00040 0x4>,
2069                               <0x00a30000 0x100>,
2070                               <0x00a30400 0x100>,
2071                               <0x00a30800 0x100>,
2072                               <0x00a30c00 0x100>,
2073                               <0x00a31000 0x500>,
2074                               <0x00a00020 0x10>,
2075                               <0x00a10000 0x1000>,
2076                               <0x00a14000 0x1000>;
2077                         reg-names = "csiphy0",
2078                                 "csiphy0_clk_mux",
2079                                 "csiphy1",
2080                                 "csiphy1_clk_mux",
2081                                 "csiphy2",
2082                                 "csiphy2_clk_mux",
2083                                 "csid0",
2084                                 "csid1",
2085                                 "csid2",
2086                                 "csid3",
2087                                 "ispif",
2088                                 "csi_clk_mux",
2089                                 "vfe0",
2090                                 "vfe1";
2091                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2092                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2093                                 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2094                                 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2095                                 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2096                                 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2097                                 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2098                                 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2099                                 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2100                                 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2101                         interrupt-names = "csiphy0",
2102                                 "csiphy1",
2103                                 "csiphy2",
2104                                 "csid0",
2105                                 "csid1",
2106                                 "csid2",
2107                                 "csid3",
2108                                 "ispif",
2109                                 "vfe0",
2110                                 "vfe1";
2111                         power-domains = <&mmcc VFE0_GDSC>,
2112                                         <&mmcc VFE1_GDSC>;
2113                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2114                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2115                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2116                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2117                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2118                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
2119                                 <&mmcc CAMSS_CSI0_CLK>,
2120                                 <&mmcc CAMSS_CSI0PHY_CLK>,
2121                                 <&mmcc CAMSS_CSI0PIX_CLK>,
2122                                 <&mmcc CAMSS_CSI0RDI_CLK>,
2123                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
2124                                 <&mmcc CAMSS_CSI1_CLK>,
2125                                 <&mmcc CAMSS_CSI1PHY_CLK>,
2126                                 <&mmcc CAMSS_CSI1PIX_CLK>,
2127                                 <&mmcc CAMSS_CSI1RDI_CLK>,
2128                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
2129                                 <&mmcc CAMSS_CSI2_CLK>,
2130                                 <&mmcc CAMSS_CSI2PHY_CLK>,
2131                                 <&mmcc CAMSS_CSI2PIX_CLK>,
2132                                 <&mmcc CAMSS_CSI2RDI_CLK>,
2133                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
2134                                 <&mmcc CAMSS_CSI3_CLK>,
2135                                 <&mmcc CAMSS_CSI3PHY_CLK>,
2136                                 <&mmcc CAMSS_CSI3PIX_CLK>,
2137                                 <&mmcc CAMSS_CSI3RDI_CLK>,
2138                                 <&mmcc CAMSS_AHB_CLK>,
2139                                 <&mmcc CAMSS_VFE0_CLK>,
2140                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
2141                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
2142                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2143                                 <&mmcc CAMSS_VFE1_CLK>,
2144                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
2145                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
2146                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2147                                 <&mmcc CAMSS_VFE_AHB_CLK>,
2148                                 <&mmcc CAMSS_VFE_AXI_CLK>;
2149                         clock-names = "top_ahb",
2150                                 "ispif_ahb",
2151                                 "csiphy0_timer",
2152                                 "csiphy1_timer",
2153                                 "csiphy2_timer",
2154                                 "csi0_ahb",
2155                                 "csi0",
2156                                 "csi0_phy",
2157                                 "csi0_pix",
2158                                 "csi0_rdi",
2159                                 "csi1_ahb",
2160                                 "csi1",
2161                                 "csi1_phy",
2162                                 "csi1_pix",
2163                                 "csi1_rdi",
2164                                 "csi2_ahb",
2165                                 "csi2",
2166                                 "csi2_phy",
2167                                 "csi2_pix",
2168                                 "csi2_rdi",
2169                                 "csi3_ahb",
2170                                 "csi3",
2171                                 "csi3_phy",
2172                                 "csi3_pix",
2173                                 "csi3_rdi",
2174                                 "ahb",
2175                                 "vfe0",
2176                                 "csi_vfe0",
2177                                 "vfe0_ahb",
2178                                 "vfe0_stream",
2179                                 "vfe1",
2180                                 "csi_vfe1",
2181                                 "vfe1_ahb",
2182                                 "vfe1_stream",
2183                                 "vfe_ahb",
2184                                 "vfe_axi";
2185                         iommus = <&vfe_smmu 0>,
2186                                  <&vfe_smmu 1>,
2187                                  <&vfe_smmu 2>,
2188                                  <&vfe_smmu 3>;
2189                         status = "disabled";
2190                         ports {
2191                                 #address-cells = <1>;
2192                                 #size-cells = <0>;
2193                         };
2194                 };
2195
2196                 cci: cci@a0c000 {
2197                         compatible = "qcom,msm8996-cci";
2198                         #address-cells = <1>;
2199                         #size-cells = <0>;
2200                         reg = <0xa0c000 0x1000>;
2201                         interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2202                         power-domains = <&mmcc CAMSS_GDSC>;
2203                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2204                                  <&mmcc CAMSS_CCI_AHB_CLK>,
2205                                  <&mmcc CAMSS_CCI_CLK>,
2206                                  <&mmcc CAMSS_AHB_CLK>;
2207                         clock-names = "camss_top_ahb",
2208                                       "cci_ahb",
2209                                       "cci",
2210                                       "camss_ahb";
2211                         assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2212                                           <&mmcc CAMSS_CCI_CLK>;
2213                         assigned-clock-rates = <80000000>, <37500000>;
2214                         pinctrl-names = "default";
2215                         pinctrl-0 = <&cci0_default &cci1_default>;
2216                         status = "disabled";
2217
2218                         cci_i2c0: i2c-bus@0 {
2219                                 reg = <0>;
2220                                 clock-frequency = <400000>;
2221                                 #address-cells = <1>;
2222                                 #size-cells = <0>;
2223                         };
2224
2225                         cci_i2c1: i2c-bus@1 {
2226                                 reg = <1>;
2227                                 clock-frequency = <400000>;
2228                                 #address-cells = <1>;
2229                                 #size-cells = <0>;
2230                         };
2231                 };
2232
2233                 adreno_smmu: iommu@b40000 {
2234                         compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2235                         reg = <0x00b40000 0x10000>;
2236
2237                         #global-interrupts = <1>;
2238                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2239                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2240                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
2241                         #iommu-cells = <1>;
2242
2243                         clocks = <&mmcc GPU_AHB_CLK>,
2244                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2245                         clock-names = "iface", "bus";
2246
2247                         power-domains = <&mmcc GPU_GDSC>;
2248                 };
2249
2250                 venus: video-codec@c00000 {
2251                         compatible = "qcom,msm8996-venus";
2252                         reg = <0x00c00000 0xff000>;
2253                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2254                         power-domains = <&mmcc VENUS_GDSC>;
2255                         clocks = <&mmcc VIDEO_CORE_CLK>,
2256                                  <&mmcc VIDEO_AHB_CLK>,
2257                                  <&mmcc VIDEO_AXI_CLK>,
2258                                  <&mmcc VIDEO_MAXI_CLK>;
2259                         clock-names = "core", "iface", "bus", "mbus";
2260                         interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
2261                                         <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
2262                         interconnect-names = "video-mem", "cpu-cfg";
2263                         iommus = <&venus_smmu 0x00>,
2264                                  <&venus_smmu 0x01>,
2265                                  <&venus_smmu 0x0a>,
2266                                  <&venus_smmu 0x07>,
2267                                  <&venus_smmu 0x0e>,
2268                                  <&venus_smmu 0x0f>,
2269                                  <&venus_smmu 0x08>,
2270                                  <&venus_smmu 0x09>,
2271                                  <&venus_smmu 0x0b>,
2272                                  <&venus_smmu 0x0c>,
2273                                  <&venus_smmu 0x0d>,
2274                                  <&venus_smmu 0x10>,
2275                                  <&venus_smmu 0x11>,
2276                                  <&venus_smmu 0x21>,
2277                                  <&venus_smmu 0x28>,
2278                                  <&venus_smmu 0x29>,
2279                                  <&venus_smmu 0x2b>,
2280                                  <&venus_smmu 0x2c>,
2281                                  <&venus_smmu 0x2d>,
2282                                  <&venus_smmu 0x31>;
2283                         memory-region = <&venus_mem>;
2284                         status = "disabled";
2285
2286                         video-decoder {
2287                                 compatible = "venus-decoder";
2288                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2289                                 clock-names = "core";
2290                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2291                         };
2292
2293                         video-encoder {
2294                                 compatible = "venus-encoder";
2295                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2296                                 clock-names = "core";
2297                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2298                         };
2299                 };
2300
2301                 mdp_smmu: iommu@d00000 {
2302                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2303                         reg = <0x00d00000 0x10000>;
2304
2305                         #global-interrupts = <1>;
2306                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2307                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2308                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
2309                         #iommu-cells = <1>;
2310                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
2311                                  <&mmcc SMMU_MDP_AXI_CLK>;
2312                         clock-names = "iface", "bus";
2313
2314                         power-domains = <&mmcc MDSS_GDSC>;
2315                 };
2316
2317                 venus_smmu: iommu@d40000 {
2318                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2319                         reg = <0x00d40000 0x20000>;
2320                         #global-interrupts = <1>;
2321                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2322                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2323                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2324                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2325                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2326                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2327                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2328                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2329                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2330                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2331                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
2332                         clock-names = "iface", "bus";
2333                         #iommu-cells = <1>;
2334                         status = "okay";
2335                 };
2336
2337                 vfe_smmu: iommu@da0000 {
2338                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2339                         reg = <0x00da0000 0x10000>;
2340
2341                         #global-interrupts = <1>;
2342                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
2343                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2344                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
2345                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2346                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
2347                                  <&mmcc SMMU_VFE_AXI_CLK>;
2348                         clock-names = "iface",
2349                                       "bus";
2350                         #iommu-cells = <1>;
2351                 };
2352
2353                 lpass_q6_smmu: iommu@1600000 {
2354                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2355                         reg = <0x01600000 0x20000>;
2356                         #iommu-cells = <1>;
2357                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2358
2359                         #global-interrupts = <1>;
2360                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2361                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
2362                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
2363                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
2364                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
2365                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2366                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2367                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2368                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2369                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2370                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2371                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2372                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
2373
2374                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
2375                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
2376                         clock-names = "iface", "bus";
2377                 };
2378
2379                 slpi_pil: remoteproc@1c00000 {
2380                         compatible = "qcom,msm8996-slpi-pil";
2381                         reg = <0x01c00000 0x4000>;
2382
2383                         interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2384                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2385                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2386                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2387                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2388                         interrupt-names = "wdog",
2389                                           "fatal",
2390                                           "ready",
2391                                           "handover",
2392                                           "stop-ack";
2393
2394                         clocks = <&xo_board>,
2395                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
2396                         clock-names = "xo", "aggre2";
2397
2398                         memory-region = <&slpi_mem>;
2399
2400                         qcom,smem-states = <&slpi_smp2p_out 0>;
2401                         qcom,smem-state-names = "stop";
2402
2403                         power-domains = <&rpmpd MSM8996_VDDSSCX>;
2404                         power-domain-names = "ssc_cx";
2405
2406                         status = "disabled";
2407
2408                         smd-edge {
2409                                 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
2410
2411                                 label = "dsps";
2412                                 mboxes = <&apcs_glb 25>;
2413                                 qcom,smd-edge = <3>;
2414                                 qcom,remote-pid = <3>;
2415                         };
2416                 };
2417
2418                 mss_pil: remoteproc@2080000 {
2419                         compatible = "qcom,msm8996-mss-pil";
2420                         reg = <0x2080000 0x100>,
2421                               <0x2180000 0x020>;
2422                         reg-names = "qdsp6", "rmb";
2423
2424                         interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2425                                               <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2426                                               <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2427                                               <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2428                                               <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2429                                               <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2430                         interrupt-names = "wdog", "fatal", "ready",
2431                                           "handover", "stop-ack",
2432                                           "shutdown-ack";
2433
2434                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2435                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
2436                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
2437                                  <&xo_board>,
2438                                  <&gcc GCC_MSS_GPLL0_DIV_CLK>,
2439                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2440                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2441                                  <&rpmcc RPM_SMD_PCNOC_CLK>,
2442                                  <&rpmcc RPM_SMD_QDSS_CLK>;
2443                         clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2444                                       "snoc_axi", "mnoc_axi", "pnoc", "qdss";
2445
2446                         resets = <&gcc GCC_MSS_RESTART>;
2447                         reset-names = "mss_restart";
2448
2449                         power-domains = <&rpmpd MSM8996_VDDCX>,
2450                                         <&rpmpd MSM8996_VDDMX>;
2451                         power-domain-names = "cx", "mx";
2452
2453                         qcom,smem-states = <&mpss_smp2p_out 0>;
2454                         qcom,smem-state-names = "stop";
2455
2456                         qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2457
2458                         status = "disabled";
2459
2460                         mba {
2461                                 memory-region = <&mba_mem>;
2462                         };
2463
2464                         mpss {
2465                                 memory-region = <&mpss_mem>;
2466                         };
2467
2468                         smd-edge {
2469                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2470
2471                                 label = "mpss";
2472                                 mboxes = <&apcs_glb 12>;
2473                                 qcom,smd-edge = <0>;
2474                                 qcom,remote-pid = <1>;
2475                         };
2476                 };
2477
2478                 stm@3002000 {
2479                         compatible = "arm,coresight-stm", "arm,primecell";
2480                         reg = <0x3002000 0x1000>,
2481                               <0x8280000 0x180000>;
2482                         reg-names = "stm-base", "stm-stimulus-base";
2483
2484                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2485                         clock-names = "apb_pclk", "atclk";
2486
2487                         out-ports {
2488                                 port {
2489                                         stm_out: endpoint {
2490                                                 remote-endpoint =
2491                                                   <&funnel0_in>;
2492                                         };
2493                                 };
2494                         };
2495                 };
2496
2497                 tpiu@3020000 {
2498                         compatible = "arm,coresight-tpiu", "arm,primecell";
2499                         reg = <0x3020000 0x1000>;
2500
2501                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2502                         clock-names = "apb_pclk", "atclk";
2503
2504                         in-ports {
2505                                 port {
2506                                         tpiu_in: endpoint {
2507                                                 remote-endpoint =
2508                                                   <&replicator_out1>;
2509                                         };
2510                                 };
2511                         };
2512                 };
2513
2514                 funnel@3021000 {
2515                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2516                         reg = <0x3021000 0x1000>;
2517
2518                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2519                         clock-names = "apb_pclk", "atclk";
2520
2521                         in-ports {
2522                                 #address-cells = <1>;
2523                                 #size-cells = <0>;
2524
2525                                 port@7 {
2526                                         reg = <7>;
2527                                         funnel0_in: endpoint {
2528                                                 remote-endpoint =
2529                                                   <&stm_out>;
2530                                         };
2531                                 };
2532                         };
2533
2534                         out-ports {
2535                                 port {
2536                                         funnel0_out: endpoint {
2537                                                 remote-endpoint =
2538                                                   <&merge_funnel_in0>;
2539                                         };
2540                                 };
2541                         };
2542                 };
2543
2544                 funnel@3022000 {
2545                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2546                         reg = <0x3022000 0x1000>;
2547
2548                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2549                         clock-names = "apb_pclk", "atclk";
2550
2551                         in-ports {
2552                                 #address-cells = <1>;
2553                                 #size-cells = <0>;
2554
2555                                 port@6 {
2556                                         reg = <6>;
2557                                         funnel1_in: endpoint {
2558                                                 remote-endpoint =
2559                                                   <&apss_merge_funnel_out>;
2560                                         };
2561                                 };
2562                         };
2563
2564                         out-ports {
2565                                 port {
2566                                         funnel1_out: endpoint {
2567                                                 remote-endpoint =
2568                                                   <&merge_funnel_in1>;
2569                                         };
2570                                 };
2571                         };
2572                 };
2573
2574                 funnel@3023000 {
2575                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2576                         reg = <0x3023000 0x1000>;
2577
2578                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2579                         clock-names = "apb_pclk", "atclk";
2580
2581                         in-ports {
2582                                 port {
2583                                         funnel_in2_in_modem_etm: endpoint {
2584                                                 remote-endpoint =
2585                                                   <&modem_etm_out_funnel_in2>;
2586                                         };
2587                                 };
2588                         };
2589
2590                         out-ports {
2591                                 port {
2592                                         funnel2_out: endpoint {
2593                                                 remote-endpoint =
2594                                                   <&merge_funnel_in2>;
2595                                         };
2596                                 };
2597                         };
2598                 };
2599
2600                 funnel@3025000 {
2601                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2602                         reg = <0x3025000 0x1000>;
2603
2604                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2605                         clock-names = "apb_pclk", "atclk";
2606
2607                         in-ports {
2608                                 #address-cells = <1>;
2609                                 #size-cells = <0>;
2610
2611                                 port@0 {
2612                                         reg = <0>;
2613                                         merge_funnel_in0: endpoint {
2614                                                 remote-endpoint =
2615                                                   <&funnel0_out>;
2616                                         };
2617                                 };
2618
2619                                 port@1 {
2620                                         reg = <1>;
2621                                         merge_funnel_in1: endpoint {
2622                                                 remote-endpoint =
2623                                                   <&funnel1_out>;
2624                                         };
2625                                 };
2626
2627                                 port@2 {
2628                                         reg = <2>;
2629                                         merge_funnel_in2: endpoint {
2630                                                 remote-endpoint =
2631                                                   <&funnel2_out>;
2632                                         };
2633                                 };
2634                         };
2635
2636                         out-ports {
2637                                 port {
2638                                         merge_funnel_out: endpoint {
2639                                                 remote-endpoint =
2640                                                   <&etf_in>;
2641                                         };
2642                                 };
2643                         };
2644                 };
2645
2646                 replicator@3026000 {
2647                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2648                         reg = <0x3026000 0x1000>;
2649
2650                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2651                         clock-names = "apb_pclk", "atclk";
2652
2653                         in-ports {
2654                                 port {
2655                                         replicator_in: endpoint {
2656                                                 remote-endpoint =
2657                                                   <&etf_out>;
2658                                         };
2659                                 };
2660                         };
2661
2662                         out-ports {
2663                                 #address-cells = <1>;
2664                                 #size-cells = <0>;
2665
2666                                 port@0 {
2667                                         reg = <0>;
2668                                         replicator_out0: endpoint {
2669                                                 remote-endpoint =
2670                                                   <&etr_in>;
2671                                         };
2672                                 };
2673
2674                                 port@1 {
2675                                         reg = <1>;
2676                                         replicator_out1: endpoint {
2677                                                 remote-endpoint =
2678                                                   <&tpiu_in>;
2679                                         };
2680                                 };
2681                         };
2682                 };
2683
2684                 etf@3027000 {
2685                         compatible = "arm,coresight-tmc", "arm,primecell";
2686                         reg = <0x3027000 0x1000>;
2687
2688                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2689                         clock-names = "apb_pclk", "atclk";
2690
2691                         in-ports {
2692                                 port {
2693                                         etf_in: endpoint {
2694                                                 remote-endpoint =
2695                                                   <&merge_funnel_out>;
2696                                         };
2697                                 };
2698                         };
2699
2700                         out-ports {
2701                                 port {
2702                                         etf_out: endpoint {
2703                                                 remote-endpoint =
2704                                                   <&replicator_in>;
2705                                         };
2706                                 };
2707                         };
2708                 };
2709
2710                 etr@3028000 {
2711                         compatible = "arm,coresight-tmc", "arm,primecell";
2712                         reg = <0x3028000 0x1000>;
2713
2714                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2715                         clock-names = "apb_pclk", "atclk";
2716                         arm,scatter-gather;
2717
2718                         in-ports {
2719                                 port {
2720                                         etr_in: endpoint {
2721                                                 remote-endpoint =
2722                                                   <&replicator_out0>;
2723                                         };
2724                                 };
2725                         };
2726                 };
2727
2728                 debug@3810000 {
2729                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2730                         reg = <0x3810000 0x1000>;
2731
2732                         clocks = <&rpmcc RPM_QDSS_CLK>;
2733                         clock-names = "apb_pclk";
2734
2735                         cpu = <&CPU0>;
2736                 };
2737
2738                 etm@3840000 {
2739                         compatible = "arm,coresight-etm4x", "arm,primecell";
2740                         reg = <0x3840000 0x1000>;
2741
2742                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2743                         clock-names = "apb_pclk", "atclk";
2744
2745                         cpu = <&CPU0>;
2746
2747                         out-ports {
2748                                 port {
2749                                         etm0_out: endpoint {
2750                                                 remote-endpoint =
2751                                                   <&apss_funnel0_in0>;
2752                                         };
2753                                 };
2754                         };
2755                 };
2756
2757                 debug@3910000 {
2758                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2759                         reg = <0x3910000 0x1000>;
2760
2761                         clocks = <&rpmcc RPM_QDSS_CLK>;
2762                         clock-names = "apb_pclk";
2763
2764                         cpu = <&CPU1>;
2765                 };
2766
2767                 etm@3940000 {
2768                         compatible = "arm,coresight-etm4x", "arm,primecell";
2769                         reg = <0x3940000 0x1000>;
2770
2771                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2772                         clock-names = "apb_pclk", "atclk";
2773
2774                         cpu = <&CPU1>;
2775
2776                         out-ports {
2777                                 port {
2778                                         etm1_out: endpoint {
2779                                                 remote-endpoint =
2780                                                   <&apss_funnel0_in1>;
2781                                         };
2782                                 };
2783                         };
2784                 };
2785
2786                 funnel@39b0000 { /* APSS Funnel 0 */
2787                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788                         reg = <0x39b0000 0x1000>;
2789
2790                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2791                         clock-names = "apb_pclk", "atclk";
2792
2793                         in-ports {
2794                                 #address-cells = <1>;
2795                                 #size-cells = <0>;
2796
2797                                 port@0 {
2798                                         reg = <0>;
2799                                         apss_funnel0_in0: endpoint {
2800                                                 remote-endpoint = <&etm0_out>;
2801                                         };
2802                                 };
2803
2804                                 port@1 {
2805                                         reg = <1>;
2806                                         apss_funnel0_in1: endpoint {
2807                                                 remote-endpoint = <&etm1_out>;
2808                                         };
2809                                 };
2810                         };
2811
2812                         out-ports {
2813                                 port {
2814                                         apss_funnel0_out: endpoint {
2815                                                 remote-endpoint =
2816                                                   <&apss_merge_funnel_in0>;
2817                                         };
2818                                 };
2819                         };
2820                 };
2821
2822                 debug@3a10000 {
2823                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2824                         reg = <0x3a10000 0x1000>;
2825
2826                         clocks = <&rpmcc RPM_QDSS_CLK>;
2827                         clock-names = "apb_pclk";
2828
2829                         cpu = <&CPU2>;
2830                 };
2831
2832                 etm@3a40000 {
2833                         compatible = "arm,coresight-etm4x", "arm,primecell";
2834                         reg = <0x3a40000 0x1000>;
2835
2836                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2837                         clock-names = "apb_pclk", "atclk";
2838
2839                         cpu = <&CPU2>;
2840
2841                         out-ports {
2842                                 port {
2843                                         etm2_out: endpoint {
2844                                                 remote-endpoint =
2845                                                   <&apss_funnel1_in0>;
2846                                         };
2847                                 };
2848                         };
2849                 };
2850
2851                 debug@3b10000 {
2852                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
2853                         reg = <0x3b10000 0x1000>;
2854
2855                         clocks = <&rpmcc RPM_QDSS_CLK>;
2856                         clock-names = "apb_pclk";
2857
2858                         cpu = <&CPU3>;
2859                 };
2860
2861                 etm@3b40000 {
2862                         compatible = "arm,coresight-etm4x", "arm,primecell";
2863                         reg = <0x3b40000 0x1000>;
2864
2865                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2866                         clock-names = "apb_pclk", "atclk";
2867
2868                         cpu = <&CPU3>;
2869
2870                         out-ports {
2871                                 port {
2872                                         etm3_out: endpoint {
2873                                                 remote-endpoint =
2874                                                   <&apss_funnel1_in1>;
2875                                         };
2876                                 };
2877                         };
2878                 };
2879
2880                 funnel@3bb0000 { /* APSS Funnel 1 */
2881                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2882                         reg = <0x3bb0000 0x1000>;
2883
2884                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2885                         clock-names = "apb_pclk", "atclk";
2886
2887                         in-ports {
2888                                 #address-cells = <1>;
2889                                 #size-cells = <0>;
2890
2891                                 port@0 {
2892                                         reg = <0>;
2893                                         apss_funnel1_in0: endpoint {
2894                                                 remote-endpoint = <&etm2_out>;
2895                                         };
2896                                 };
2897
2898                                 port@1 {
2899                                         reg = <1>;
2900                                         apss_funnel1_in1: endpoint {
2901                                                 remote-endpoint = <&etm3_out>;
2902                                         };
2903                                 };
2904                         };
2905
2906                         out-ports {
2907                                 port {
2908                                         apss_funnel1_out: endpoint {
2909                                                 remote-endpoint =
2910                                                   <&apss_merge_funnel_in1>;
2911                                         };
2912                                 };
2913                         };
2914                 };
2915
2916                 funnel@3bc0000 {
2917                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2918                         reg = <0x3bc0000 0x1000>;
2919
2920                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
2921                         clock-names = "apb_pclk", "atclk";
2922
2923                         in-ports {
2924                                 #address-cells = <1>;
2925                                 #size-cells = <0>;
2926
2927                                 port@0 {
2928                                         reg = <0>;
2929                                         apss_merge_funnel_in0: endpoint {
2930                                                 remote-endpoint =
2931                                                   <&apss_funnel0_out>;
2932                                         };
2933                                 };
2934
2935                                 port@1 {
2936                                         reg = <1>;
2937                                         apss_merge_funnel_in1: endpoint {
2938                                                 remote-endpoint =
2939                                                   <&apss_funnel1_out>;
2940                                         };
2941                                 };
2942                         };
2943
2944                         out-ports {
2945                                 port {
2946                                         apss_merge_funnel_out: endpoint {
2947                                                 remote-endpoint =
2948                                                   <&funnel1_in>;
2949                                         };
2950                                 };
2951                         };
2952                 };
2953
2954                 kryocc: clock-controller@6400000 {
2955                         compatible = "qcom,msm8996-apcc";
2956                         reg = <0x06400000 0x90000>;
2957
2958                         clock-names = "xo", "sys_apcs_aux";
2959                         clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>;
2960
2961                         #clock-cells = <1>;
2962                 };
2963
2964                 usb3: usb@6af8800 {
2965                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
2966                         reg = <0x06af8800 0x400>;
2967                         #address-cells = <1>;
2968                         #size-cells = <1>;
2969                         ranges;
2970
2971                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2972                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2973                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
2974
2975                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
2976                                  <&gcc GCC_USB30_MASTER_CLK>,
2977                                  <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
2978                                  <&gcc GCC_USB30_SLEEP_CLK>,
2979                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2980                         clock-names = "cfg_noc",
2981                                       "core",
2982                                       "iface",
2983                                       "sleep",
2984                                       "mock_utmi";
2985
2986                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2987                                           <&gcc GCC_USB30_MASTER_CLK>;
2988                         assigned-clock-rates = <19200000>, <120000000>;
2989
2990                         interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
2991                                         <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
2992                         interconnect-names = "usb-ddr", "apps-usb";
2993
2994                         power-domains = <&gcc USB30_GDSC>;
2995                         status = "disabled";
2996
2997                         usb3_dwc3: usb@6a00000 {
2998                                 compatible = "snps,dwc3";
2999                                 reg = <0x06a00000 0xcc00>;
3000                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
3001                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
3002                                 phy-names = "usb2-phy", "usb3-phy";
3003                                 snps,hird-threshold = /bits/ 8 <0>;
3004                                 snps,dis_u2_susphy_quirk;
3005                                 snps,dis_enblslpm_quirk;
3006                                 snps,is-utmi-l1-suspend;
3007                                 tx-fifo-resize;
3008                         };
3009                 };
3010
3011                 usb3phy: phy@7410000 {
3012                         compatible = "qcom,msm8996-qmp-usb3-phy";
3013                         reg = <0x07410000 0x1c4>;
3014                         #address-cells = <1>;
3015                         #size-cells = <1>;
3016                         ranges;
3017
3018                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
3019                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3020                                 <&gcc GCC_USB3_CLKREF_CLK>;
3021                         clock-names = "aux", "cfg_ahb", "ref";
3022
3023                         resets = <&gcc GCC_USB3_PHY_BCR>,
3024                                 <&gcc GCC_USB3PHY_PHY_BCR>;
3025                         reset-names = "phy", "common";
3026                         status = "disabled";
3027
3028                         ssusb_phy_0: phy@7410200 {
3029                                 reg = <0x07410200 0x200>,
3030                                       <0x07410400 0x130>,
3031                                       <0x07410600 0x1a8>;
3032                                 #phy-cells = <0>;
3033
3034                                 #clock-cells = <0>;
3035                                 clock-output-names = "usb3_phy_pipe_clk_src";
3036                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
3037                                 clock-names = "pipe0";
3038                         };
3039                 };
3040
3041                 hsusb_phy1: phy@7411000 {
3042                         compatible = "qcom,msm8996-qusb2-phy";
3043                         reg = <0x07411000 0x180>;
3044                         #phy-cells = <0>;
3045
3046                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3047                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
3048                         clock-names = "cfg_ahb", "ref";
3049
3050                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3051                         nvmem-cells = <&qusb2p_hstx_trim>;
3052                         status = "disabled";
3053                 };
3054
3055                 hsusb_phy2: phy@7412000 {
3056                         compatible = "qcom,msm8996-qusb2-phy";
3057                         reg = <0x07412000 0x180>;
3058                         #phy-cells = <0>;
3059
3060                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3061                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
3062                         clock-names = "cfg_ahb", "ref";
3063
3064                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3065                         nvmem-cells = <&qusb2s_hstx_trim>;
3066                         status = "disabled";
3067                 };
3068
3069                 sdhc1: mmc@7464900 {
3070                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3071                         reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3072                         reg-names = "hc", "core";
3073
3074                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3075                                         <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
3076                         interrupt-names = "hc_irq", "pwr_irq";
3077
3078                         clock-names = "iface", "core", "xo";
3079                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
3080                                 <&gcc GCC_SDCC1_APPS_CLK>,
3081                                 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3082                         resets = <&gcc GCC_SDCC1_BCR>;
3083
3084                         pinctrl-names = "default", "sleep";
3085                         pinctrl-0 = <&sdc1_state_on>;
3086                         pinctrl-1 = <&sdc1_state_off>;
3087
3088                         bus-width = <8>;
3089                         non-removable;
3090                         status = "disabled";
3091                 };
3092
3093                 sdhc2: mmc@74a4900 {
3094                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3095                         reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3096                         reg-names = "hc", "core";
3097
3098                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
3099                                       <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
3100                         interrupt-names = "hc_irq", "pwr_irq";
3101
3102                         clock-names = "iface", "core", "xo";
3103                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3104                                 <&gcc GCC_SDCC2_APPS_CLK>,
3105                                 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3106                         resets = <&gcc GCC_SDCC2_BCR>;
3107
3108                         pinctrl-names = "default", "sleep";
3109                         pinctrl-0 = <&sdc2_state_on>;
3110                         pinctrl-1 = <&sdc2_state_off>;
3111
3112                         bus-width = <4>;
3113                         status = "disabled";
3114                  };
3115
3116                 blsp1_dma: dma-controller@7544000 {
3117                         compatible = "qcom,bam-v1.7.0";
3118                         reg = <0x07544000 0x2b000>;
3119                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3120                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
3121                         clock-names = "bam_clk";
3122                         qcom,controlled-remotely;
3123                         #dma-cells = <1>;
3124                         qcom,ee = <0>;
3125                 };
3126
3127                 blsp1_uart2: serial@7570000 {
3128                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3129                         reg = <0x07570000 0x1000>;
3130                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
3131                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
3132                                  <&gcc GCC_BLSP1_AHB_CLK>;
3133                         clock-names = "core", "iface";
3134                         pinctrl-names = "default", "sleep";
3135                         pinctrl-0 = <&blsp1_uart2_default>;
3136                         pinctrl-1 = <&blsp1_uart2_sleep>;
3137                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
3138                         dma-names = "tx", "rx";
3139                         status = "disabled";
3140                 };
3141
3142                 blsp1_spi1: spi@7575000 {
3143                         compatible = "qcom,spi-qup-v2.2.1";
3144                         reg = <0x07575000 0x600>;
3145                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
3146                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
3147                                  <&gcc GCC_BLSP1_AHB_CLK>;
3148                         clock-names = "core", "iface";
3149                         pinctrl-names = "default", "sleep";
3150                         pinctrl-0 = <&blsp1_spi1_default>;
3151                         pinctrl-1 = <&blsp1_spi1_sleep>;
3152                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
3153                         dma-names = "tx", "rx";
3154                         #address-cells = <1>;
3155                         #size-cells = <0>;
3156                         status = "disabled";
3157                 };
3158
3159                 blsp1_i2c3: i2c@7577000 {
3160                         compatible = "qcom,i2c-qup-v2.2.1";
3161                         reg = <0x07577000 0x1000>;
3162                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
3163                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
3164                                  <&gcc GCC_BLSP1_AHB_CLK>;
3165                         clock-names = "core", "iface";
3166                         pinctrl-names = "default", "sleep";
3167                         pinctrl-0 = <&blsp1_i2c3_default>;
3168                         pinctrl-1 = <&blsp1_i2c3_sleep>;
3169                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
3170                         dma-names = "tx", "rx";
3171                         #address-cells = <1>;
3172                         #size-cells = <0>;
3173                         status = "disabled";
3174                 };
3175
3176                 blsp2_dma: dma-controller@7584000 {
3177                         compatible = "qcom,bam-v1.7.0";
3178                         reg = <0x07584000 0x2b000>;
3179                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
3180                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
3181                         clock-names = "bam_clk";
3182                         qcom,controlled-remotely;
3183                         #dma-cells = <1>;
3184                         qcom,ee = <0>;
3185                 };
3186
3187                 blsp2_uart2: serial@75b0000 {
3188                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3189                         reg = <0x075b0000 0x1000>;
3190                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
3191                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
3192                                  <&gcc GCC_BLSP2_AHB_CLK>;
3193                         clock-names = "core", "iface";
3194                         status = "disabled";
3195                 };
3196
3197                 blsp2_uart3: serial@75b1000 {
3198                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3199                         reg = <0x075b1000 0x1000>;
3200                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
3201                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
3202                                  <&gcc GCC_BLSP2_AHB_CLK>;
3203                         clock-names = "core", "iface";
3204                         status = "disabled";
3205                 };
3206
3207                 blsp2_i2c1: i2c@75b5000 {
3208                         compatible = "qcom,i2c-qup-v2.2.1";
3209                         reg = <0x075b5000 0x1000>;
3210                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
3211                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
3212                                  <&gcc GCC_BLSP2_AHB_CLK>;
3213                         clock-names = "core", "iface";
3214                         pinctrl-names = "default", "sleep";
3215                         pinctrl-0 = <&blsp2_i2c1_default>;
3216                         pinctrl-1 = <&blsp2_i2c1_sleep>;
3217                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
3218                         dma-names = "tx", "rx";
3219                         #address-cells = <1>;
3220                         #size-cells = <0>;
3221                         status = "disabled";
3222                 };
3223
3224                 blsp2_i2c2: i2c@75b6000 {
3225                         compatible = "qcom,i2c-qup-v2.2.1";
3226                         reg = <0x075b6000 0x1000>;
3227                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
3228                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
3229                                  <&gcc GCC_BLSP2_AHB_CLK>;
3230                         clock-names = "core", "iface";
3231                         pinctrl-names = "default", "sleep";
3232                         pinctrl-0 = <&blsp2_i2c2_default>;
3233                         pinctrl-1 = <&blsp2_i2c2_sleep>;
3234                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
3235                         dma-names = "tx", "rx";
3236                         #address-cells = <1>;
3237                         #size-cells = <0>;
3238                         status = "disabled";
3239                 };
3240
3241                 blsp2_i2c3: i2c@75b7000 {
3242                         compatible = "qcom,i2c-qup-v2.2.1";
3243                         reg = <0x075b7000 0x1000>;
3244                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
3245                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
3246                                  <&gcc GCC_BLSP2_AHB_CLK>;
3247                         clock-names = "core", "iface";
3248                         clock-frequency = <400000>;
3249                         pinctrl-names = "default", "sleep";
3250                         pinctrl-0 = <&blsp2_i2c3_default>;
3251                         pinctrl-1 = <&blsp2_i2c3_sleep>;
3252                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
3253                         dma-names = "tx", "rx";
3254                         #address-cells = <1>;
3255                         #size-cells = <0>;
3256                         status = "disabled";
3257                 };
3258
3259                 blsp2_i2c5: i2c@75b9000 {
3260                         compatible = "qcom,i2c-qup-v2.2.1";
3261                         reg = <0x75b9000 0x1000>;
3262                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3263                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
3264                                  <&gcc GCC_BLSP2_AHB_CLK>;
3265                         clock-names = "core", "iface";
3266                         pinctrl-names = "default";
3267                         pinctrl-0 = <&blsp2_i2c5_default>;
3268                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
3269                         dma-names = "tx", "rx";
3270                         #address-cells = <1>;
3271                         #size-cells = <0>;
3272                         status = "disabled";
3273                 };
3274
3275                 blsp2_i2c6: i2c@75ba000 {
3276                         compatible = "qcom,i2c-qup-v2.2.1";
3277                         reg = <0x75ba000 0x1000>;
3278                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3279                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
3280                                  <&gcc GCC_BLSP2_AHB_CLK>;
3281                         clock-names = "core", "iface";
3282                         pinctrl-names = "default", "sleep";
3283                         pinctrl-0 = <&blsp2_i2c6_default>;
3284                         pinctrl-1 = <&blsp2_i2c6_sleep>;
3285                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3286                         dma-names = "tx", "rx";
3287                         #address-cells = <1>;
3288                         #size-cells = <0>;
3289                         status = "disabled";
3290                 };
3291
3292                 blsp2_spi6: spi@75ba000{
3293                         compatible = "qcom,spi-qup-v2.2.1";
3294                         reg = <0x075ba000 0x600>;
3295                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3296                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
3297                                  <&gcc GCC_BLSP2_AHB_CLK>;
3298                         clock-names = "core", "iface";
3299                         pinctrl-names = "default", "sleep";
3300                         pinctrl-0 = <&blsp2_spi6_default>;
3301                         pinctrl-1 = <&blsp2_spi6_sleep>;
3302                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
3303                         dma-names = "tx", "rx";
3304                         #address-cells = <1>;
3305                         #size-cells = <0>;
3306                         status = "disabled";
3307                 };
3308
3309                 usb2: usb@76f8800 {
3310                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3311                         reg = <0x076f8800 0x400>;
3312                         #address-cells = <1>;
3313                         #size-cells = <1>;
3314                         ranges;
3315
3316                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
3317                         interrupt-names = "hs_phy_irq";
3318
3319                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
3320                                 <&gcc GCC_USB20_MASTER_CLK>,
3321                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3322                                 <&gcc GCC_USB20_SLEEP_CLK>,
3323                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
3324                         clock-names = "cfg_noc",
3325                                       "core",
3326                                       "iface",
3327                                       "sleep",
3328                                       "mock_utmi";
3329
3330                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3331                                           <&gcc GCC_USB20_MASTER_CLK>;
3332                         assigned-clock-rates = <19200000>, <60000000>;
3333
3334                         power-domains = <&gcc USB30_GDSC>;
3335                         qcom,select-utmi-as-pipe-clk;
3336                         status = "disabled";
3337
3338                         usb2_dwc3: usb@7600000 {
3339                                 compatible = "snps,dwc3";
3340                                 reg = <0x07600000 0xcc00>;
3341                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
3342                                 phys = <&hsusb_phy2>;
3343                                 phy-names = "usb2-phy";
3344                                 maximum-speed = "high-speed";
3345                                 snps,dis_u2_susphy_quirk;
3346                                 snps,dis_enblslpm_quirk;
3347                         };
3348                 };
3349
3350                 slimbam: dma-controller@9184000 {
3351                         compatible = "qcom,bam-v1.7.0";
3352                         qcom,controlled-remotely;
3353                         reg = <0x09184000 0x32000>;
3354                         num-channels = <31>;
3355                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
3356                         #dma-cells = <1>;
3357                         qcom,ee = <1>;
3358                         qcom,num-ees = <2>;
3359                 };
3360
3361                 slim_msm: slim@91c0000 {
3362                         compatible = "qcom,slim-ngd-v1.5.0";
3363                         reg = <0x091c0000 0x2C000>;
3364                         reg-names = "ctrl";
3365                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
3366                         dmas = <&slimbam 3>, <&slimbam 4>,
3367                                 <&slimbam 5>, <&slimbam 6>;
3368                         dma-names = "rx", "tx", "tx2", "rx2";
3369                         #address-cells = <1>;
3370                         #size-cells = <0>;
3371                         ngd@1 {
3372                                 reg = <1>;
3373                                 #address-cells = <1>;
3374                                 #size-cells = <1>;
3375
3376                                 tasha_ifd: tas-ifd {
3377                                         compatible = "slim217,1a0";
3378                                         reg = <0 0>;
3379                                 };
3380
3381                                 wcd9335: codec@1{
3382                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
3383                                         pinctrl-names = "default";
3384
3385                                         compatible = "slim217,1a0";
3386                                         reg = <1 0>;
3387
3388                                         interrupt-parent = <&tlmm>;
3389                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
3390                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
3391                                         interrupt-names = "intr1", "intr2";
3392                                         interrupt-controller;
3393                                         #interrupt-cells = <1>;
3394                                         reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
3395
3396                                         slim-ifc-dev = <&tasha_ifd>;
3397
3398                                         #sound-dai-cells = <1>;
3399                                 };
3400                         };
3401                 };
3402
3403                 adsp_pil: remoteproc@9300000 {
3404                         compatible = "qcom,msm8996-adsp-pil";
3405                         reg = <0x09300000 0x80000>;
3406
3407                         interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3408                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3409                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3410                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3411                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3412                         interrupt-names = "wdog", "fatal", "ready",
3413                                           "handover", "stop-ack";
3414
3415                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3416                         clock-names = "xo";
3417
3418                         memory-region = <&adsp_mem>;
3419
3420                         qcom,smem-states = <&adsp_smp2p_out 0>;
3421                         qcom,smem-state-names = "stop";
3422
3423                         power-domains = <&rpmpd MSM8996_VDDCX>;
3424                         power-domain-names = "cx";
3425
3426                         status = "disabled";
3427
3428                         smd-edge {
3429                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3430
3431                                 label = "lpass";
3432                                 mboxes = <&apcs_glb 8>;
3433                                 qcom,smd-edge = <1>;
3434                                 qcom,remote-pid = <2>;
3435                                 #address-cells = <1>;
3436                                 #size-cells = <0>;
3437                                 apr {
3438                                         power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3439                                         compatible = "qcom,apr-v2";
3440                                         qcom,smd-channels = "apr_audio_svc";
3441                                         qcom,domain = <APR_DOMAIN_ADSP>;
3442                                         #address-cells = <1>;
3443                                         #size-cells = <0>;
3444
3445                                         q6core {
3446                                                 reg = <APR_SVC_ADSP_CORE>;
3447                                                 compatible = "qcom,q6core";
3448                                         };
3449
3450                                         q6afe: q6afe {
3451                                                 compatible = "qcom,q6afe";
3452                                                 reg = <APR_SVC_AFE>;
3453                                                 q6afedai: dais {
3454                                                         compatible = "qcom,q6afe-dais";
3455                                                         #address-cells = <1>;
3456                                                         #size-cells = <0>;
3457                                                         #sound-dai-cells = <1>;
3458                                                         hdmi@1 {
3459                                                                 reg = <1>;
3460                                                         };
3461                                                 };
3462                                         };
3463
3464                                         q6asm: q6asm {
3465                                                 compatible = "qcom,q6asm";
3466                                                 reg = <APR_SVC_ASM>;
3467                                                 q6asmdai: dais {
3468                                                         compatible = "qcom,q6asm-dais";
3469                                                         #address-cells = <1>;
3470                                                         #size-cells = <0>;
3471                                                         #sound-dai-cells = <1>;
3472                                                         iommus = <&lpass_q6_smmu 1>;
3473                                                 };
3474                                         };
3475
3476                                         q6adm: q6adm {
3477                                                 compatible = "qcom,q6adm";
3478                                                 reg = <APR_SVC_ADM>;
3479                                                 q6routing: routing {
3480                                                         compatible = "qcom,q6adm-routing";
3481                                                         #sound-dai-cells = <0>;
3482                                                 };
3483                                         };
3484                                 };
3485
3486                         };
3487                 };
3488
3489                 apcs_glb: mailbox@9820000 {
3490                         compatible = "qcom,msm8996-apcs-hmss-global";
3491                         reg = <0x09820000 0x1000>;
3492
3493                         #mbox-cells = <1>;
3494                 };
3495
3496                 timer@9840000 {
3497                         #address-cells = <1>;
3498                         #size-cells = <1>;
3499                         ranges;
3500                         compatible = "arm,armv7-timer-mem";
3501                         reg = <0x09840000 0x1000>;
3502                         clock-frequency = <19200000>;
3503
3504                         frame@9850000 {
3505                                 frame-number = <0>;
3506                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
3507                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
3508                                 reg = <0x09850000 0x1000>,
3509                                       <0x09860000 0x1000>;
3510                         };
3511
3512                         frame@9870000 {
3513                                 frame-number = <1>;
3514                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3515                                 reg = <0x09870000 0x1000>;
3516                                 status = "disabled";
3517                         };
3518
3519                         frame@9880000 {
3520                                 frame-number = <2>;
3521                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3522                                 reg = <0x09880000 0x1000>;
3523                                 status = "disabled";
3524                         };
3525
3526                         frame@9890000 {
3527                                 frame-number = <3>;
3528                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
3529                                 reg = <0x09890000 0x1000>;
3530                                 status = "disabled";
3531                         };
3532
3533                         frame@98a0000 {
3534                                 frame-number = <4>;
3535                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3536                                 reg = <0x098a0000 0x1000>;
3537                                 status = "disabled";
3538                         };
3539
3540                         frame@98b0000 {
3541                                 frame-number = <5>;
3542                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3543                                 reg = <0x098b0000 0x1000>;
3544                                 status = "disabled";
3545                         };
3546
3547                         frame@98c0000 {
3548                                 frame-number = <6>;
3549                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3550                                 reg = <0x098c0000 0x1000>;
3551                                 status = "disabled";
3552                         };
3553                 };
3554
3555                 saw3: syscon@9a10000 {
3556                         compatible = "syscon";
3557                         reg = <0x09a10000 0x1000>;
3558                 };
3559
3560                 intc: interrupt-controller@9bc0000 {
3561                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3562                         #interrupt-cells = <3>;
3563                         interrupt-controller;
3564                         #redistributor-regions = <1>;
3565                         redistributor-stride = <0x0 0x40000>;
3566                         reg = <0x09bc0000 0x10000>,
3567                               <0x09c00000 0x100000>;
3568                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3569                 };
3570         };
3571
3572         sound: sound {
3573         };
3574
3575         thermal-zones {
3576                 cpu0-thermal {
3577                         polling-delay-passive = <250>;
3578                         polling-delay = <1000>;
3579
3580                         thermal-sensors = <&tsens0 3>;
3581
3582                         trips {
3583                                 cpu0_alert0: trip-point0 {
3584                                         temperature = <75000>;
3585                                         hysteresis = <2000>;
3586                                         type = "passive";
3587                                 };
3588
3589                                 cpu0_crit: cpu_crit {
3590                                         temperature = <110000>;
3591                                         hysteresis = <2000>;
3592                                         type = "critical";
3593                                 };
3594                         };
3595                 };
3596
3597                 cpu1-thermal {
3598                         polling-delay-passive = <250>;
3599                         polling-delay = <1000>;
3600
3601                         thermal-sensors = <&tsens0 5>;
3602
3603                         trips {
3604                                 cpu1_alert0: trip-point0 {
3605                                         temperature = <75000>;
3606                                         hysteresis = <2000>;
3607                                         type = "passive";
3608                                 };
3609
3610                                 cpu1_crit: cpu_crit {
3611                                         temperature = <110000>;
3612                                         hysteresis = <2000>;
3613                                         type = "critical";
3614                                 };
3615                         };
3616                 };
3617
3618                 cpu2-thermal {
3619                         polling-delay-passive = <250>;
3620                         polling-delay = <1000>;
3621
3622                         thermal-sensors = <&tsens0 8>;
3623
3624                         trips {
3625                                 cpu2_alert0: trip-point0 {
3626                                         temperature = <75000>;
3627                                         hysteresis = <2000>;
3628                                         type = "passive";
3629                                 };
3630
3631                                 cpu2_crit: cpu_crit {
3632                                         temperature = <110000>;
3633                                         hysteresis = <2000>;
3634                                         type = "critical";
3635                                 };
3636                         };
3637                 };
3638
3639                 cpu3-thermal {
3640                         polling-delay-passive = <250>;
3641                         polling-delay = <1000>;
3642
3643                         thermal-sensors = <&tsens0 10>;
3644
3645                         trips {
3646                                 cpu3_alert0: trip-point0 {
3647                                         temperature = <75000>;
3648                                         hysteresis = <2000>;
3649                                         type = "passive";
3650                                 };
3651
3652                                 cpu3_crit: cpu_crit {
3653                                         temperature = <110000>;
3654                                         hysteresis = <2000>;
3655                                         type = "critical";
3656                                 };
3657                         };
3658                 };
3659
3660                 gpu-top-thermal {
3661                         polling-delay-passive = <250>;
3662                         polling-delay = <1000>;
3663
3664                         thermal-sensors = <&tsens1 6>;
3665
3666                         trips {
3667                                 gpu1_alert0: trip-point0 {
3668                                         temperature = <90000>;
3669                                         hysteresis = <2000>;
3670                                         type = "passive";
3671                                 };
3672                         };
3673
3674                         cooling-maps {
3675                                 map0 {
3676                                         trip = <&gpu1_alert0>;
3677                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3678                                 };
3679                         };
3680                 };
3681
3682                 gpu-bottom-thermal {
3683                         polling-delay-passive = <250>;
3684                         polling-delay = <1000>;
3685
3686                         thermal-sensors = <&tsens1 7>;
3687
3688                         trips {
3689                                 gpu2_alert0: trip-point0 {
3690                                         temperature = <90000>;
3691                                         hysteresis = <2000>;
3692                                         type = "passive";
3693                                 };
3694                         };
3695
3696                         cooling-maps {
3697                                 map0 {
3698                                         trip = <&gpu2_alert0>;
3699                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3700                                 };
3701                         };
3702                 };
3703
3704                 m4m-thermal {
3705                         polling-delay-passive = <250>;
3706                         polling-delay = <1000>;
3707
3708                         thermal-sensors = <&tsens0 1>;
3709
3710                         trips {
3711                                 m4m_alert0: trip-point0 {
3712                                         temperature = <90000>;
3713                                         hysteresis = <2000>;
3714                                         type = "hot";
3715                                 };
3716                         };
3717                 };
3718
3719                 l3-or-venus-thermal {
3720                         polling-delay-passive = <250>;
3721                         polling-delay = <1000>;
3722
3723                         thermal-sensors = <&tsens0 2>;
3724
3725                         trips {
3726                                 l3_or_venus_alert0: trip-point0 {
3727                                         temperature = <90000>;
3728                                         hysteresis = <2000>;
3729                                         type = "hot";
3730                                 };
3731                         };
3732                 };
3733
3734                 cluster0-l2-thermal {
3735                         polling-delay-passive = <250>;
3736                         polling-delay = <1000>;
3737
3738                         thermal-sensors = <&tsens0 7>;
3739
3740                         trips {
3741                                 cluster0_l2_alert0: trip-point0 {
3742                                         temperature = <90000>;
3743                                         hysteresis = <2000>;
3744                                         type = "hot";
3745                                 };
3746                         };
3747                 };
3748
3749                 cluster1-l2-thermal {
3750                         polling-delay-passive = <250>;
3751                         polling-delay = <1000>;
3752
3753                         thermal-sensors = <&tsens0 12>;
3754
3755                         trips {
3756                                 cluster1_l2_alert0: trip-point0 {
3757                                         temperature = <90000>;
3758                                         hysteresis = <2000>;
3759                                         type = "hot";
3760                                 };
3761                         };
3762                 };
3763
3764                 camera-thermal {
3765                         polling-delay-passive = <250>;
3766                         polling-delay = <1000>;
3767
3768                         thermal-sensors = <&tsens1 1>;
3769
3770                         trips {
3771                                 camera_alert0: trip-point0 {
3772                                         temperature = <90000>;
3773                                         hysteresis = <2000>;
3774                                         type = "hot";
3775                                 };
3776                         };
3777                 };
3778
3779                 q6-dsp-thermal {
3780                         polling-delay-passive = <250>;
3781                         polling-delay = <1000>;
3782
3783                         thermal-sensors = <&tsens1 2>;
3784
3785                         trips {
3786                                 q6_dsp_alert0: trip-point0 {
3787                                         temperature = <90000>;
3788                                         hysteresis = <2000>;
3789                                         type = "hot";
3790                                 };
3791                         };
3792                 };
3793
3794                 mem-thermal {
3795                         polling-delay-passive = <250>;
3796                         polling-delay = <1000>;
3797
3798                         thermal-sensors = <&tsens1 3>;
3799
3800                         trips {
3801                                 mem_alert0: trip-point0 {
3802                                         temperature = <90000>;
3803                                         hysteresis = <2000>;
3804                                         type = "hot";
3805                                 };
3806                         };
3807                 };
3808
3809                 modemtx-thermal {
3810                         polling-delay-passive = <250>;
3811                         polling-delay = <1000>;
3812
3813                         thermal-sensors = <&tsens1 4>;
3814
3815                         trips {
3816                                 modemtx_alert0: trip-point0 {
3817                                         temperature = <90000>;
3818                                         hysteresis = <2000>;
3819                                         type = "hot";
3820                                 };
3821                         };
3822                 };
3823         };
3824
3825         timer {
3826                 compatible = "arm,armv8-timer";
3827                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
3828                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
3829                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
3830                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
3831         };
3832 };