1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
17 model = "Qualcomm Technologies, Inc. MSM 8994";
18 compatible = "qcom,msm8994";
19 // msm-id and pmic-id are required by bootloader for
20 // proper selection of dt blob
21 qcom,msm-id = <207 0x20000>;
22 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
23 interrupt-parent = <&intc>;
43 compatible = "arm,cortex-a53", "arm,armv8";
45 next-level-cache = <&L2_0>;
54 compatible = "arm,armv8-timer";
55 interrupts = <1 2 0xff08>,
65 ranges = <0 0 0 0xffffffff>;
66 compatible = "simple-bus";
68 intc: interrupt-controller@f9000000 {
69 compatible = "qcom,msm-qgic2";
71 #interrupt-cells = <3>;
72 reg = <0xf9000000 0x1000>,
80 compatible = "arm,armv7-timer-mem";
81 reg = <0xf9020000 0x1000>;
85 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
87 reg = <0xf9021000 0x1000>,
93 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
94 reg = <0xf9023000 0x1000>;
100 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
101 reg = <0xf9024000 0x1000>;
107 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
108 reg = <0xf9025000 0x1000>;
114 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
115 reg = <0xf9026000 0x1000>;
121 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
122 reg = <0xf9027000 0x1000>;
128 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
129 reg = <0xf9028000 0x1000>;
135 compatible = "qcom,pshold";
136 reg = <0xfc4ab000 0x4>;
139 msmgpio: pinctrl@fd510000 {
140 compatible = "qcom,msm8994-pinctrl";
141 reg = <0xfd510000 0x4000>;
142 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
145 interrupt-controller;
146 #interrupt-cells = <2>;
149 blsp1_uart2: serial@f991e000 {
150 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
151 reg = <0xf991e000 0x1000>;
152 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
154 clock-names = "core", "iface";
155 clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
156 <&clock_gcc GCC_BLSP1_AHB_CLK>;
159 tcsr_mutex_regs: syscon@fd484000 {
160 compatible = "syscon";
161 reg = <0xfd484000 0x2000>;
164 clock_gcc: clock-controller@fc400000 {
165 compatible = "qcom,gcc-msm8994";
168 #power-domain-cells = <1>;
169 reg = <0xfc400000 0x2000>;
174 device_type = "memory";
175 // We expect the bootloader to fill in the reg
180 compatible = "fixed-clock";
182 clock-frequency = <19200000>;
185 sleep_clk: sleep_clk {
186 compatible = "fixed-clock";
188 clock-frequency = <32768>;
192 #address-cells = <2>;
196 smem_mem: smem_region@6a00000 {
197 reg = <0x0 0x6a00000 0x0 0x200000>;
203 compatible = "qcom,tcsr-mutex";
204 syscon = <&tcsr_mutex_regs 0 0x80>;
209 compatible = "qcom,smem";
210 memory-region = <&smem_mem>;
211 hwlocks = <&tcsr_mutex 3>;
216 #include "msm8994-pins.dtsi"